Link startup method for a storage device, storage device, host, and implementation system thereof

Abstract

A storage device capable of performing high-speed link startup and a storage system including the storage device are disclosed. A method for link startup of the storage device includes: receiving a line reset signal from a host through a line connected to an input signal pin of the storage device; comparing a duration of the received line reset signal with a first reference time; and performing a link startup operation between the storage device and the host in a high-speed mode or a low-speed mode according to a comparison result.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2020 - 0051055, filed on April 27, 2020, and Korean Patent Application No. 10 - 2020 - 0137077, filed on October 21, 2020, with the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a memory device, and more particularly, to a link startup method of a storage device configured to perform high - speed link startup, a storage device, a controller, and a system. Background art

[0004] A storage system may include a host and a storage device. The host may be connected to the storage device through various standard interfaces such as, for example, a Universal Flash Storage (UFS) interface, a Serial Advanced Technology Attachment (SATA) interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), and an Embedded Multimedia Card (eMMC) interface. When the storage system is used in a mobile device, high - speed operation between the host and the storage device may be very important, and a quick connection (linkup) between the host and the storage device may be desired. Summary of the invention

[0005] According to an aspect of the present inventive concept, there is provided a link startup method of a storage device, the link startup method including: receiving a line reset signal from a host through a line connected to an input signal pin of the storage device; comparing a duration of the received line reset signal with a first reference time; and in response to the comparison, performing a link startup operation in a high - speed mode or a low - speed mode, wherein the high - speed mode achieves a connection state between the host and the storage device faster than the low - speed mode.

[0006] According to another aspect of the present inventive concept, there is provided a link startup method of a storage device, the link startup method including: determining whether a line reset signal is received from a host through a line connected to an input signal pin of the storage device; and performing one of the following: in response to receiving the line reset signal from the host, performing a high - speed mode link startup operation between the storage device and the host; and when the line reset signal is not received from the host, performing a low - speed mode link startup operation between the storage device and the host, wherein the high - speed mode link startup operation achieves a connection state between the host and the storage device faster than the low - speed mode link startup operation.

[0007] According to another aspect of the inventive concept, there is provided a method for link startup of a storage device, the link startup method including: performing a high-speed mode link startup operation between the storage device and a host; determining whether the high-speed mode link startup operation is completed; when the high-speed mode link startup operation is completed, determining whether a connection between the storage device and the host as a result of the high-speed mode link startup operation is successful; and when it is determined that the connection is not successful, performing a low-speed mode link startup operation between the storage device and the host, wherein the high-speed mode link startup operation achieves a connection state between the host and the storage device faster than the low-speed mode link startup operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a storage system according to an embodiment;

[0010] Figure 2 shows an interconnection between a host and a storage device according to an embodiment;

[0011] Figure 3 is a timing diagram showing a line reset signal according to an embodiment;

[0012] Figure 4 is a table showing line reset parameters and line reset high-speed connection parameters according to an embodiment;

[0013] Figure 5 is a block diagram of a storage system according to an embodiment;

[0014] Figure 6 is a block diagram of a line reset detector according to an embodiment;

[0015] Figure 7 is a diagram showing an Figure 6 operation of a line reset detector according to an embodiment;

[0016] Figure 8 is a block diagram of a line reset detector according to an embodiment;

[0017] Figure 9 is a block diagram of a line reset detector according to an embodiment;

[0018] Figure 10 is a diagram showing an Figure 9 operation of a line reset detector according to an embodiment;

[0019] Figure 11 is a flowchart of an operation method of a storage device according to an embodiment;

[0020] Figure 12 is a flowchart of operations between a host and a storage device according to an embodiment;

[0021] Figure 13 is a flowchart of an operation method of a storage device according to an embodiment;

[0022] Figure 14 is a flowchart of a high-speed mode initialization sequence between a Universal Flash Storage (UFS) host and a UFS device according to an embodiment;

[0023] Figure 15 is a flowchart of a link startup operation between a host and a storage device according to an embodiment;

[0024] Figures 16 to 18 is a flowchart of a link startup method of a storage device according to respective embodiments;

[0025] Figure 19 is a flowchart of a link startup operation between a host and a storage device according to an embodiment;

[0026] Figures 20 to 21 is a flowchart of a link startup method of a storage device according to some embodiments;

[0027] Figure 22 is a flowchart of operations between a host and a storage device according to an embodiment;

[0028] Figure 23 and Figure 24 is a flowchart of a link startup method according to some embodiments;

[0029] Figure 25 is a diagram of a UFS system according to an embodiment;

[0030] Figures 26A to 26C is a diagram for describing the form factor of a UFS card;

[0031] Figure 27 is a block diagram of a memory system according to an embodiment;

[0032] Figure 28 is a diagram for describing a 3D vertical NAND (VNAND) structure applicable to a UFS device according to an embodiment; and

[0033] Figure 29 is a diagram for describing a bonded VNAND (B-VNAND) structure applicable to a UFS device according to an embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram of a storage system 10 according to an embodiment.

[0036] Referring Figure 1 , the storage system 10 includes a storage device 100 and a host 200. For example, the storage device 100 may be connected to the host 200 according to an interface protocol defined in the Universal Flash Storage (UFS) standard. Accordingly, the storage device 100 may include a UFS device and the host 200 may include a UFS host. However, the embodiment is not limited thereto, and the storage device 100 may be connected to the host 200 according to various standard interfaces.

[0037] The host 200 may include an interconnect circuit 210 and a host controller 220. The host 200 may control data processing operations (e.g., a data read operation or a data write operation) with respect to the storage device 100. The host 200 may be a data processing device that can process data, e.g., a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host 200 may be configured with an operating system (OS) and / or various applications, and execute the operating system (OS) and / or various applications. In an embodiment, the storage system 10 may be included in a mobile device and form a part of the mobile device, and the host 200 may be implemented as an AP. In an embodiment, the host 200 may be implemented as a system-on-chip (SoC) and included in an electronic device and form a part of the electronic device.

[0038] The storage device 100 may include an interconnect circuit 110, a device controller 120, and a non-volatile memory (NVM) 130. The device controller 120 may control access to the NVM 130, e.g., control the NVM 130 in response to a write request from the host 200 to write data to the NVM 130, or control the NVM 130 in response to a read request from the host 200 to read data from the NVM 130. The NVM 130 may include a plurality of memory cells, e.g., flash memory cells. In an embodiment, the memory cells may include NAND flash memory cells. However, the embodiment is not limited thereto. In some embodiments, the memory cells may include resistive memory cells, e.g., resistive random access memory (RRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0039] Although in Figure 1 the interconnect circuit 110 is shown as being separate from the device controller 120, the device controller 120 may be integrated with the interconnect circuit 110, which may be the case for other embodiments described herein. For example, when the device controller 120 is implemented as a single chip, the interconnect circuit 110 may also be implemented in the chip.

[0040] The host 200 may further include first pins P1a' and P1b', and the storage device 100 may further include: first pins P1a and P1b configured to be connected to the first pins P1a' and P1b' respectively. The storage device 100 may receive an input signal. Figure 1 It is shown that a differential signal sent from the host 200 to the storage device 100 as a pair of complementary input signals DIN_t and DIN_c (via the positive wire and the negative wire of the differential signal line forming the transmitted differential signal respectively), the storage device 100 receives the differential signal from the host 200 through the first pins P1a and P1b of the storage device 100. Therefore, the first pins P1a and P1b may be referred to as "input signal pins", and the signal lines transmitting the complementary input signals DIN_t and DIN_c may constitute a receiving path. For example, the first pin P1a may be referred to as the "positive input signal pin" and may be connected to the positive wire of the differential signal line transmitting DIN_t, and the first pin P1b may be referred to as the "negative input signal pin" and may be connected to the negative wire of the differential signal line transmitting DIN_c. It should be understood that the term "pin" as used herein is not limited to pin-type connections, but refers to any conventional terminal connection, for example, a pad (e.g., a chip pad, a package pad, etc.) or a bump (a solder bump, a solder ball, etc.). In addition, it should be understood that although Figure 1 it shows a single differential signal receiving path from the host 200 to the storage device 100, this differential signal receiving path is representative, and several such differential signal receiving paths may be provided between the host 200 and the storage device 100.

[0041] In addition, the host 200 may further include second pins P2a' and P2b', and the storage device 100 may further include: second pins P2a and P2b configured to be connected to the second pins P2a' and P2b' respectively. The storage device 100 may send an output signal. Figure 1 It is shown that a differential signal sent from the storage device 100 to the host 200 as a pair of complementary output signals DOUT_t and DOUT_c, the differential signal is sent from the storage device 100 to the host 200 through the second pins P2a and P2b. Therefore, the second pins P2a and P2b may be referred to as "output signal pins", and the signal lines transmitting the complementary output signals DOUT_t and DOUT_c may constitute a transmission path. For example, the second pin P2a may be referred to as the "positive output signal pin", and the second pin P2b may be referred to as the "negative output signal pin". It should be understood that although Figure 1A single differential signal transmission path from the storage device 100 to the host 200 is shown, but this differential signal transmission path is representative, and several such differential signal transmission paths can be provided between the storage device 100 and the host 200.

[0042] The storage device 100 may further include a line reset detector 140. Although shown that the device controller 120 includes the line reset detector 140, the embodiment is not limited thereto, and the line reset detector 140 may be separated from the device controller 140. The line reset detector 140 may receive a line reset signal LINE-RESET from the host 200 and detect the duration (persistence) of the received line reset signal LINE-RESET, that is, the duration (persistence) of the line reset time period. The device controller 120 may perform link startup in a high-speed mode or a low-speed mode (e.g., pulse width modulation (PWM) mode) based on the detected duration of the line reset signal LINE-RESET. The line reset signal LINE-RESET will be described in more detail with reference to Figure 1 and Figure 3 and Figure 4 The detailed operation of the line reset detector 140 will be described in more detail with reference to Figures 5 to 10

[0043] For example, the high-speed mode may be defined as a high-speed operation loop composed of STALL and HS-BURST. STALL may be defined as a power-saving state with a fast recovery time between HS-BURSTs. HS-BUSRT may be defined as a high-speed state including PREPARE, SYNC, MARKER, and data. PREPARE may be defined as the first part of the HOB after exiting STALL or SLEEP until but not including the SYNC sequence. SYNC may be defined as an 8b10b symbol sequence with a high edge density for fast phase alignment. MARKER may be defined as a non-data symbol for protocol-related control purposes. For example, the low-speed mode may be defined as a combination of SLEEP, PWM-BUSRT, INIT, and LINE-CFG states, or a combination of SLEEP and SYS-BURST states. SLEEP may be defined as a power-saving state used between LS-BURSTs. LS-BURST may be defined as a low-speed state including PREPARE, MARKER, and data.

[0044] Interconnection circuits 110 and 210 may be formed separately to provide an interface for communication (e.g., data exchange) between host 200 and storage device 100. In an embodiment, interconnection circuit 110 may include a physical layer (PL) 111 and a link layer (LL) 115, and PL 111 may be a circuit connected to first and second pins P1a, P1b, P2a, and P2b. Similarly, interconnection circuit 210 may also include PL 211 and LL 215, and physical layer 211 may be connected to first and second pins P1a′, P1b′, P2a′, and P2b′. Each of PL 111 and PL 211 may be a circuit for data exchange between host 200 and storage device 100. For example, each of PL 111 and PL 211 may include at least one transmitter and at least one receiver. Each of LL115 and LL 215 may include circuitry (e.g., hardware or firmware) to manage the transmission and construction of data and also manage data integrity and errors. It will be understood that the various protocol layers referred to herein may represent or be implemented by physical circuits (which may be dedicated circuits) or may be in the form of hardware or firmware (which may be configured by software) to provide specific functions associated with that layer (e.g., as defined according to a specification, e.g., as defined by the Unified Protocol (UniPro) specification).

[0045] In an embodiment, when storage system 10 is a mobile device, LL 115 and LL 215 may be defined by the Unified Protocol (UniPro) specification, and PL 111 and PL 211 may be defined by the M-PHY specification. As a non-limiting example, the UniPro specification may include UniPro specification version 1.8, and the M-PHY specification may include M-PHY specification version 4.1. UniPro and M-PHY are interface protocols introduced by the Mobile Industry Processor Interface (MIPI) Alliance. In this case, each of LL115 and LL 215 may include a physical adapter layer. The physical adapter layer may control PL 111 and PL 211 by managing the symbols and / or power of data. Hereinafter, reference will be made to Figure 2 The interface between host 200 and storage device 100 will be described in detail below.

[0046] Figure 2 Illustrates an interconnection 20 (a system connection or bus for communication of data or other information) between a host and a storage device according to an embodiment.

[0047] Reference Figure 2, the interconnection 20 may include a link 300 between the host controller 220 and the device controller 120. The link 300 may include a plurality of paths 310, 320, and 330. The link 300 may include at least one path corresponding to each direction, and the number of paths corresponding to different directions may not be symmetric. For example, the link 300 may include: two paths 310 and 320 corresponding to a first direction from the host controller 220 to the device controller 120; and, one path 330 corresponding to a second direction from the device controller 120 to the host controller 220, but the embodiments are not limited thereto. For example, the two paths 310 and 320 corresponding to the first direction may form a first sub-link, and the one path 330 corresponding to the second direction may form a second sub-link.

[0048] Each of the paths 310, 320, and 330 includes: a transmission channel that carries a single unidirectional differential signal (e.g., provides information in the form of a data frame formed by a plurality of data symbols). For example, the path 320 may include a transmitter TX1, a receiver RX1, and a line LINE that interconnects the transmitter TX1 to the receiver RX1 using a point-to-point link. For example, the transmitter TX1 may be connected to a pin TXDP corresponding to the positive node of the differential signal and a pin TXDN corresponding to the negative node of the differential signal, and the receiver RX1 may be connected to a pin RXDP corresponding to the positive node of the differential signal and a pin RXDN corresponding to the negative node of the differential signal. The line LINE may include: two differential pair wires that respectively connect the pins TXDP and TXDN of the transmitter TX1 to the pins RXDP and RXDN of the receiver RX1. The wires may correspond to the transmission lines.

[0049] The link 300 may further include path management circuits 340 and 350 that provide bidirectional data transmission. Although in Figure 2 the path management circuit 350 is separated from the host controller 220, the embodiments are not limited thereto. The path management circuit 350 may be included in the host controller 220. Similarly, in Figure 2 the path management circuit 340 is separated from the device controller 120, but the embodiments are not limited thereto. The path management circuit 340 may be included in the device controller 120.

[0050] Refer to Figure 1 and Figure 2 , the transmitter (e.g., Figure 1 ) included in the interconnection circuit 210 of the host 200 (see Figure 2 ) and the receiver (e.g., Figure 1 ) included in the interconnection circuit 110 of the storage device 100 (see Figure 2Either RX1 or RX2) can form a single path (e.g., Figure 2 One of paths 310 and 320). Similarly, the receiver included in the interconnect circuit 210 of host 200 (see Figure 1 ) (e.g., Figure 2 RX3) and the transmitter included in the interconnect circuit 110 of storage device 100 (see Figure 1 ) (e.g., Figure 2 TX3) can form a single path (e.g., Figure 2 Path 330). The number of transmitters and receivers included in the interconnect circuit 210 of the host can be different from the number of transmitters and receivers included in the interconnect circuit 110 of storage device 100. The capabilities of host 200 can be different from the capabilities of storage device 100.

[0051] Therefore, host 200 and storage device 100 identify the paths physically connected thereto and perform processing for receiving information from each other. Therefore, host 200 and storage device 100 perform link startup processing before exchanging data. Host 200 and storage device 100 can, by performing link startup processing, exchange and identify information about the number of transmitters and receivers, information about the paths physically connected to each other, information about their respective performances, etc. After the link startup processing is completed, host 200 and storage device 100 are set to a connected state in which host 200 and storage device 100 can stably exchange data with each other.

[0052] The link startup processing can be performed during initialization performed when storage system 10 is initially used or during startup of storage system 10. In addition, the link startup processing can also be performed during recovery from an error in the connected state. However, the link startup processing may take a long time because it requires exchanging a lot of information about host 200 and storage device 100. The link startup processing that takes a long time degrades the performance of storage system 10.

[0053] However, according to an embodiment, host 200 can provide a line reset signal LINE-RESET having a specific duration to storage device 100 via differential input signal lines, and send complementary input signals DIN_t and DIN_c via the differential input signal lines during initialization or startup of storage system 10, and storage device 100 can detect the duration of the received line reset signal LINE-RESET, thereby performing the link startup processing in high speed mode. Therefore, the time taken for link startup processing can be reduced, and thus, the performance of storage system 10 can be improved.

[0054] In addition, according to an embodiment, the storage device 100 may perform link startup processing in a high-speed mode or a low-speed mode based on the presence of the line reset signal LINE-RESET. In addition, according to an embodiment, after power-on or hardware reset, the storage device 100 may first perform link startup processing in a high-speed mode, and perform link startup processing in a low-speed mode when there is no connection between the host 200 and the storage device 100.

[0055] In addition, according to some embodiments, the conditions for determining the operation mode of the link startup processing are not limited to the duration or presence of the line reset signal LINE-RESET. For example, the link startup processing may be performed in a high-speed mode or a low-speed mode based on other characteristics, such as the number of transitions between logic low and logic high that occur in the line reset signal LINE-RESET.

[0056] In addition, according to some embodiments, the signal for determining the operation mode of the link startup processing is not limited to the line reset signal LINE-RESET. For example, other signals that can be sent between the host 200 and the storage device 100 before performing the link startup processing may be used instead of the line reset signal LINE-RESET, and the link startup processing may be performed in a high-speed mode or a low-speed mode based on the other signals.

[0057] In some embodiments, the storage device 100 may be implemented as a DRAM-less device, and the DRAM-less device may refer to a device that does not include a dynamic RAM (DRAM) cache. At this time, the device controller 120 may not include a DRAM controller. For example, the storage device 100 may use a portion of the NVM 130 as a buffer memory.

[0058] In some embodiments, the storage device 100 may include an internal memory embedded in an electronic device. For example, the storage device 100 may include an embedded Universal Flash Storage (UFS) memory device, an embedded multimedia card (eMMC), or a solid state drive (SSD). However, the embodiments are not limited thereto. The storage device 100 may include a non-volatile memory (NVM), such as a one-time programmable read-only memory (OTPROM), a programmable ROM (PROM), an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a mask ROM, or a flash ROM. In some embodiments, the storage device 100 may include an external memory that is detachable from the electronic device. For example, the storage device 100 may include at least one selected from the following: a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (XD) card, or a memory stick.

[0059] The storage system 10 can be implemented as an electronic device such as a personal computer (PC), a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), an MP3 player, a handheld game console, or an e-book. The storage system 10 can be implemented in various types of electronic devices including wearable devices (e.g., a watch or a head-mounted display (HMD)).

[0060] Figure 3 is a timing diagram showing the line reset signal LINE-RESET according to an embodiment.

[0061] Reference Figures 1 to 3 , the voltage 30 of the line LINE can be driven in a DIF-P state with a positive differential line voltage, a DIF-N state with a negative differential line voltage, or a DIF-Z state with a differential line voltage that is almost zero. Although not shown in the drawings, the line LINE can have a DIF-Q state indicating a high impedance state, or a DIF-X state other than the DIF-N or DIF-P state. In this case, the differential line voltage can be defined as the value obtained by subtracting the voltage level of the line connected to the negative node from the voltage level of the line connected to the positive node.

[0062] The line LINE can correspond to any line included in the interconnect 20. For example, the line LINE can correspond to a differential input signal line pair through which complementary input signals DIN_t and DIN_c are transmitted (e.g., a twisted pair wire pair). Figure 1 For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is higher than the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line LINE can be in the DIF-P state or the logic high state. For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is lower than the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line can be in the DIF-N state or in the logic low state. For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is substantially the same as the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line can be in the DIF-Z state or in the logic low state.

[0063] During the activation period T between t0 and t1 ACTIVATE , the line LINE can be driven to be in the DIF-N state. For example, during the activation period T ACTIVATEDuring this period, the host 200 may drive the signal (e.g., the activation signal) sent through the line LINE to be in the DIF-N state to indicate exiting from the power saving state (e.g., the hibernation state HIBERN8). The storage device 100 may respond to the activation signal and exit the power saving state (e.g., the hibernation state HIBERN8). The hibernation state HIBERN8 may be a low power state defined by the MIPI specification (e.g., the UniPro specification or the M-PHY specification). In an embodiment, the PL 111 or LL 115 of the interconnect circuit 110 of the storage device 100 may be preset based on the duration of the activation period T ACTIVATE The link startup operation between the host 200 and the storage device 100 may be performed in high speed mode or low speed mode based on the duration T of the activation period ACTIVATE .

[0064] During the line reset period T between t1 and t3 LINE-RESET , the line LINE may be driven to be in the DIF-P state. For example, during the line reset period T LINE-RESET , the host 200 may drive the signal (e.g., the line reset signal LINE-RESET) sent through the line LINE to be in the DIF-P state to indicate the line reset operation. The storage device 100 may perform a line reset for resetting the PL 111 of the interconnect circuit 110 in response to the line reset signal LINE-RESET. "Line reset" refers to a reset mechanism for resetting the PL 111 of the interconnect circuit 110 through the line LINE during a fault condition of the operation

[0065] "Line reset" may be defined as resetting through the line LINE by means of an abnormal signal condition of a long DIF-P. This is the lowest level of reset mechanism for resetting the M-PHY receive module (M-RX) through the line LINE in case of a fault during operation. The LINE-RESET condition is a long DIF-P time period that may never occur during normal operation. The M-CTRL-LINERESET.request primitive may be used to initiate LINE-RESET at the protocol layer on the M-PHY transmit module (M-TX) side of the LINK. This primitive requests the LINE-RESET action to be performed at the M-TX. All configuration settings (rate, amplitude, etc.) will be lost and reset to default values. The M-TX also asserts a signal on the line LINE so that the remote M-RX recognizes the LINE-RESET state

[0066] Before the protocol layer issues an M-CTRL-LINERESET.request with TActivateControl set to "ProtocolControlled", the protocol layer issues an M-LANE-BurstEnd.request and waits for T after M-TX has generated an M-LANE-SaveState.indication ACTIVATE This condition ensures that M-TX drives DIF-N for at least T ACTIVATE , thereby activating M-RX that may be in HIBERN8 before driving the LINE-RESET condition. For LINE-RESET, M-TX will drive DIF-P for T LINE-RESET .

[0067] After the protocol layer issues an M-CTRL-LINERESET.request that sets TActivateControl to "PhyControlled", M-TX drives DIF-N for T before driving the LINE-RESET condition ACTIVATE . When DIF-P is observed on the LINE for T LINE-RESET-DETECT , M-RX should be reset. The LINE-RESET timer should not rely on correct protocol operation. On transitioning to DIF-N, LINE-RESET exits to SLEEP. LINE-RESET should reset all configuration settings to their respective default values

[0068] The line reset high-speed connection time period T between t1 and t2 LINE-RESET-HS-LINKUP During this period, the line LINE can be driven to be in the DIF-P state. For example, during the line reset high-speed connection time period T LINE-RESET-HS-LINKUP During this period, the host 200 can drive the signal sent through the line LINE (e.g., the line reset signal LINE-RESET) to be in the DIF-P state to indicate the high-speed link startup sequence. The storage device 100 can respond to the line reset signal LINE-RESET and perform a link startup process in high-speed mode between the host 200 and the storage device 100 by executing the high-speed link startup sequence

[0069] Figure 4 Table 40 shows the line reset parameters and line reset high-speed connection parameters according to an embodiment

[0070] Reference Figure 1 , Figure 3 and Figure 4 , the line reset time period T for the host 200 to indicate the line reset operation of the storage device 100 LINE-REssET, can be defined as at least 3.1 milliseconds (ms). Thus, in order to reset the PL 111 of the interconnect circuit 110 of the storage device 100, the host 200 can drive the voltage of the line LINE to be in the DIF-P state for a period of 3.1 ms or longer. In other words, the line reset period T LINE-RESET can correspond to the line reset parameter of the transmitter.

[0071] The minimum and maximum values of the line reset detection period T of the storage device 100 for performing the line reset operation LINE-RESET-DETECT can be defined as approximately 1 ms and approximately 3 ms, respectively. Thus, when the duration of the period during which the voltage of the line LINE driven to be in the DIF-P state is between approximately 1 ms and approximately 3 ms, the storage device 100 can perform a line reset operation for resetting the PL 111 of the interconnect circuit 110. In other words, the line reset detection period T LINE-RESET-DETECT can correspond to the line reset parameter of the receiver.

[0072] The minimum and maximum values of the line reset high-speed connection period T of the host 200 for indicating the high-speed link start operation of the storage device 100 LINE-RESET-HS-LINKUP can be defined as approximately 300 μs and approximately 500 μs, respectively. Thus, the host 200 can drive the voltage of the line LINE to be in the DIF-P state for a time between 300 μs and 500 μs to perform the high-speed link start. In other words, the line reset high-speed connection period T LINE-RESET-HS-LINKUP can correspond to the line reset high-speed connection parameter of the transmitter.

[0073] The minimum and maximum values of the line reset high-speed connection detection period T of the storage device 100 for performing the high-speed link start operation LINE-RESET-HS-LINKUP-DETECT can be defined as approximately 200 μs and approximately 300 μs, respectively. Thus, when the duration of the period during which the voltage of the line LINE is driven to be in the DIF-P state is between approximately 200 μs and approximately 300 μs, the storage device 100 can perform a high-speed link start sequence. When the duration of the period during which the voltage of the line LINE is driven to be in the DIF-P state is greater than approximately 300 μs, the storage device 100 can perform a low-speed link start sequence. In other words, the line reset high-speed connection detection period T LINE-RESET-DETECT-HS-LINKUP-DETECT can correspond to the line reset high-speed connection parameter of the receiver.

[0074] Figure 5 is a block diagram of the storage system 10A according to an embodiment.

[0075] Reference Figure 5, the storage system 10A may include a storage device 100A and a host 200A. The storage device 100A may include an interconnect circuit 110a, a device controller 120a, and an NVM 130, and the host 200A may include an interconnect circuit 210a and a host controller 220a. The storage system 10A corresponds to a modification of the storage system 10 of Figure 1 and the description given above with reference to Figures 1 to 4 may also be applied to this embodiment. In this embodiment, the line reset detector 140 may be included in the interconnect circuit 110a. For example, the line reset detector 140 may be included in the PL (e.g., Figure 1 's PL 111) of the interconnect circuit 110a.

[0076] Figure 6 is a block diagram of a line reset detector 140a according to an embodiment. Figure 7 shows Figure 6 's line reset detector 140a's detection operation timing diagram according to an embodiment.

[0077] Referring to Figure 1 , Figure 6 and Figure 7 , the line reset detector 140a may include a comparator 141, a system clock counter 142, and a line reset duration determiner 143, and is Figure 1 's line reset detector 140 example. In this case, a positive input signal DIN_t may be received from the host 200 through the first pin P1a of the storage device 100, and a negative input signal DIN_c may be received from the host 200 through the first pin P1b of the storage device 100. The system clock SYS_CLK may be an internal clock signal generated by the storage device 100.

[0078] Comparator 141 can generate a differential line voltage DIF by comparing a positive input signal DIN_t with a negative input signal DIN_c. The system clock counter 142 can generate a system clock count value SYS_CNT by counting the number of clocks (i.e., counting the number of clock cycles, e.g., counting each transition (or clock edge) of the clock from high to low or from low to high) based on the system clock SYS_CLK. The line reset duration determiner 143 can determine a line reset duration based on the differential line voltage DIF and the system clock count value SYS_CNT. For example, the system clock SYS_CLK can transition at a first frequency, and during a period when the differential line voltage DIF remains logic high, i.e., during the period of the DIF-P state, a system clock count value SYS_CNT can be generated, e.g., as X. Thus, the line reset determiner 143 can determine the line reset duration based on the first frequency and the system clock count value SYS_CNT. For example, the system clock count values SYS_CNT at the start and end of the period when the differential line voltage DIF remains logic high (i.e., the start and end of the period of the DIF-P state) can be compared to determine the duration (length) of this period. Alternatively, the system clock count value SYS_CNT can initially be set to zero and operate to count the number of clock cycles only when the differential line voltage DIF remains logic high (e.g., during the period of the DIF-P state), and the system clock count value SYS_CNT at the termination of the differential line voltage DIF that remains logic high (e.g., at the end of the period of the DIF-P state) is used to determine the line reset duration (after which, the system clock count value SYS_CNT can be reset to zero for any subsequent line reset duration determination).

[0079] Figure 8 is a block diagram of a line reset detector 140b according to an embodiment.

[0080] Reference Figure 1 and Figure 8 and, the line reset detector 140b can include a comparator 141 and a resistor-capacitor (RC) filter 144, and can correspond to an example of the line reset detector 140 of Figure 1 In an embodiment, the RC filter 144 can be included in the PL_111 of the interconnect circuit 110. In an embodiment, the RC filter 144 can be included in the device controller 120.

[0081] Comparator 141 can generate a differential line voltage DIF by comparing a positive input signal DIN_t and a negative input signal DIN_c. The differential line voltage DIF can be a single-ended signal corresponding to the difference between the positive input signal DIN_t and the negative input signal DIN_c (e.g., corresponding to the positive input signal DIN_t minus the negative input signal DIN_c). The RC filter 144 can include a resistor R and a capacitor C, and can generate an output voltage Vout based on the differential line voltage DIF received as an input voltage Vin. The line reset detector 140b can detect the line reset duration based on the output voltage Vout1. Specifically, the differential line voltage DIF can be connected to the resistor R, and the RC filter 144 can detect an output voltage Vout corresponding to the differential line voltage DIF at a first time point (e.g., Figure 10 t1 in

[0082] Figure 9 is a block diagram of a line reset detector 140c according to an embodiment.

[0083] Reference Figure 9 , the line reset detector 140c can include a comparator 141, an RC filter 144, and a trigger signal generator 145. The line reset detector 140c can correspond to a modification of the line reset detector 140b of Figure 8 , and the descriptions given above with reference to Figure 1 and Figure 8 can also be applied to this embodiment. The trigger signal generator 145 can generate a trigger signal TS according to the output voltage Vout. For example, the trigger signal generator 145 can be implemented as a pulse generator, and the trigger signal TS can be generated as a pulse waveform. The line reset detector 140c can detect the line reset duration according to the trigger signal TS.

[0084] Figure 10 is a timing diagram showing the detection operation of the line reset detector 140c of Figure 9 according to an embodiment.

[0085] Reference Figure 9 and Figure 10, at t0, the differential line voltage DIF can transition from logic low to logic high, and thus, the voltage level of the output voltage Vout can increase. At t1, the RC filter 144 can detect the output voltage Vout corresponding to the differential line voltage DIF, and the trigger signal generator 145 can generate a trigger signal TS enabled according to the voltage level of the output voltage Vout. When the voltage level of the output voltage Vout is higher than the reference voltage level, the trigger signal generator 145 can generate a trigger signal, and when the voltage level of the output voltage Vout is lower than the reference voltage level, the trigger signal generator 145 can refrain from generating a trigger signal. In an embodiment, the RC filter 144 can include an internal switch, and when the trigger signal TS is generated, the internal switch of the RC filter 144 can be turned off. Thus, after t1, the differential line voltage DIF cannot be applied to the RC filter 144, and thus, the level of the output voltage Vout can decrease.

[0086] For example, a first reference time T1 from t0 to t1 can correspond to the maximum value of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT (e.g., about 300 μs). In this case, the time constant of the RC filter 144 can correspond to the first reference time T1. When the trigger signal TS is generated, the line reset detector 140c can determine that the duration of the line reset signal is greater than the maximum value of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT . In this case, the host 200 and the storage device 100 can perform link startup in the low-speed mode. On the other hand, when the trigger signal TS is not generated, the line reset detector 140c can determine that the duration of the line reset signal is less than the maximum value of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT . In this case, the host 200 and the storage device 100 can perform link startup in the high-speed mode.

[0087] In some embodiments, the line reset detector 140c can include a plurality of RC filters corresponding to the number of detection points. For example, the line reset detector 140c can include: four RC filters for detecting Figure 4 the minimum and maximum values of the line reset detection time period T shown in LINE-RESET-DETECT , as well as the minimum and maximum values of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT . In this case, the time constants of the four RC filters can respectively correspond to the minimum and maximum values of the line reset detection time period T LINE-RESET-DETECT , as well as the minimum and maximum values of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT .

[0088] Figure 11 is a flowchart of an operation method of a storage device according to an embodiment. Refer toFigure 11 , the operation method of the storage device according to this embodiment corresponds to the link startup operation method of the storage device, and may include, for example, operations performed in time series by the storage device 100 of Figure 1 or the storage device 100A of Figure 5 . The description given above with reference to Figures 1 to 10 can be applied to this embodiment, and redundant descriptions can be omitted.

[0089] In operation S110, the storage device 100 receives a line reset signal LINE-RESET. For example, the storage device 100 can receive the line reset signal LINE-RESET from the host 200 through the first pins P1a and P1b. For example, when power is applied to the storage system 10, the storage device 100 can receive the line reset signal LINE-RESET from the host 200.

[0090] In operation S130, the storage device 100 compares the line reset duration corresponding to the duration of the received line reset signal LINE-RESET with a first reference time. For example, the first reference time can correspond to Figure 4 the maximum value of the line reset high-speed connection detection period T of LINE-RESET-HS-LINKUP-DETECT (e.g., 300 μs). For example, the line reset detector 140a can detect the line reset duration (e.g., as described for Figure 6 and Figure 7 ) based on the DIF-P part of the differential line voltage DIF and the system clock count value SYS_CNT, and can compare the detected line reset duration with the first reference time. For example, the line reset detectors 140b or 140c can detect the line reset duration (e.g., as described for Figures 8 to 10 ) at a time corresponding to the first reference time based on the output voltage corresponding to the differential line voltage DIF, and can compare the detected line reset duration with the first reference time.

[0091] In operation S150, the storage device 100 performs link startup in high-speed mode or low-speed mode. In an embodiment, when the line reset duration is less than the first reference time, the storage device 100 can perform link startup in high-speed mode, and when the line reset duration is greater than the first reference time, the storage device 100 can perform link startup in low-speed mode. However, the embodiment is not limited thereto. In an embodiment, when the line reset duration is less than the first reference time, the storage device 100 can perform link startup in low-speed mode, and when the line reset duration is greater than the first reference time, the storage device 100 can perform link startup in high-speed mode.

[0092] Figure 12It is a flowchart of operations between the host 200 and the storage device 100 according to an embodiment.

[0093] Refer to Figure 12 , in operation S210, power can be applied to the storage system 10. In operation S210, the host 200 can send power to the storage device 100 and initiate the power-on operation of the storage device 100. In operation S220, the host 200 generates a line reset signal LINE-RESET. Specifically, in order to indicate the high-speed link start operation of the storage device 100, the host 200 can set the line LINE in the DIF-P state for a duration longer than a first predetermined duration and / or shorter than a second predetermined duration. For example, the line LINE is set in the DIF-P state for a time of about 300 μs to about 500 μs to set the duration of the line reset period.

[0094] In operation S230, the host 200 sends the line reset signal LINE-RESET to the storage device 100 through the differential input signal line, and the positive input signal DIN_t and the negative input signal DIN_c are sent through the differential input signal line. Specifically, the host 200 can drive the differential input signal line to be in the DIF-P state according to the duration of the line reset period set in operation S220. In operation S240, the storage device 100 detects the line reset signal LINE-RESET received from the host 200 and compares the duration of the line reset signal LINE-RESET with a first reference time. Operations S220 to S240 can correspond to the high-speed mode standby HS MODE STANDBY (HS_SB).

[0095] In operation S250, the host 200 performs a link start operation in the high-speed mode. In operation S260, the storage device 100 performs a link start operation in the high-speed mode. Operations S250 and S260 can be performed substantially at the same time. For example, operations S250 and S260 can correspond to Figure 11 operation S150. In an embodiment, the link start operation can include the initialization of PL111 and PL 211 and LL 115 and LL 215. The link start operation can also include: information exchange between the host 200 and the storage device 100. In operation S270, when the link start operation is completed, the host 200 and the storage device 100 can be set to the connected state and stably exchange data with each other. Operations S250 to S270 can be performed in the high-speed mode HS_MD.

[0096] Figure 13 It is a flowchart of an operation method of a storage device according to an embodiment. Refer to Figure 13, the operating method of the storage device according to this embodiment corresponds to the link startup operation method of the storage device, and can correspond to Figure 11 the modification of the operating method. The description referred to above Figure 11 can be applied to this embodiment, and the following description will focus on the differences from Figure 11 .

[0097] In operation S110, the storage device 100 receives a line reset signal LINE-RESET. In operation S130, the storage device 100 compares the line reset duration corresponding to the duration of the received line reset signal LINE-RESET with a first reference time. In operation S140, the storage device 100 sets the PL or LL of the interconnection layer according to the result of the comparison between the line reset duration and the first reference time. For example, the device controller 120 can set the PL 111 of the interconnection circuit 110 according to the result of the comparison between the line reset duration and the first reference time. For example, the device controller 120 can send the result information about the comparison between the line reset duration and the first reference time to the LL 115 of the interconnection circuit 110. For example, the storage device 100 can initialize the PL 111 and the LL 115 according to the result of the comparison between the line reset duration and the first reference time. In operation S150, the storage device 100 performs link startup in high-speed mode or low-speed mode.

[0098] Figure 14 is a flowchart showing the high-speed mode initialization sequence between the UFS host 200a and the UFS device 100a according to an embodiment.

[0099] Referring to Figure 14 , the UFS host 200a can be an example of the host 200 of Figure 1 , and the UFS device 100a can be Figure 1An example of the storage device 100. When power is applied to the UFS host 200a and the UFS device 100a, in the High-Speed Standby (HS_SB) operation, the UFS device 100a can receive the Line Reset signal LINE-RESET from the UFS host 200a and determine the duration of the received Line Reset signal LINE-RESET. When the duration of the Line Reset signal LINE-RESET is determined, the UFS host 200a and the UFS device 100a can perform a link startup operation in the high-speed mode. Specifically, the UFS host 200a and the UFS device 100a can perform M-PHY / UniPro initialization (operation S310), and can perform a link startup sequence (operation S320) by exchanging information. In this case, the UFS host 200a and the UFS device 100a can perform read operations and write operations in parallel simultaneously through a full-duplex Low-Voltage Differential Signaling (LVDS) serial interface.

[0100] Figure 15 is a flowchart of a link startup operation between the host 200 and the storage device 100 according to an embodiment.

[0101] Reference Figure 1 and Figure 15 In operation S410, the host 200 can generate the Line Reset signal LINE-RESET, reset the transmitter of the connected path, and send information indicating that the transmitter has been reset to the storage device 100. In addition, in operation S410, the storage device 100 can receive the Line Reset signal LINE-RESET, reset the receiver of the connected path, and send information indicating that the receiver has been reset to the host 200. Through this line reset operation, all attributes of the PL111 and 211 of the interconnection circuits 110 and 210 can be reset to default values. The host 200 and the storage device 100 can exchange line reset information with each other. Operation S410 can be referred to as a line reset operation. After performing the line reset operation, a link startup sequence including operations S420 to S460 can be started.

[0102] Operations S420 to S460 can correspond to a link startup sequence. The link startup sequence can be performed by a multi-stage handshake method that exchanges UniPro trigger events between the host 200 and the storage device 100 to establish initial link communication in both directions. The link startup sequence can be defined as specific stages, trigger events can be used for each of the stages, and each trigger event can be sent multiple times.

[0103] In the first operation S420 of the link startup sequence, the connected path between the host 200 and the storage device 100 can be detected. In the first operation S420, the host 200 can send the first trigger event TRG_UPR0 on all available transmit (TX) paths from the host 200 to the storage device 100. The host 200 can continue to send the first trigger event TRG_UPR0 until the host 200 receives the first trigger event message from the storage device 100. The first trigger event TRG_UPR0 sent from the host 200 can include the number of physical paths of the TX path of the host 200 that sends the trigger.

[0104] In addition, in the first operation S420, the storage device 100 can send the first trigger event TRG_UPR0 on all available TX paths from the storage device 100 to the host 200. The storage device 100 can continue to send the first trigger event TRG_UPR0 until the storage device 100 receives the first trigger event message from the host 200. The first trigger event TRG_UPR0 sent from the storage device 100 can include the number of physical paths of the TX path of the storage device 100 to which the trigger is sent.

[0105] In the second operation S430 of the link startup sequence, the path can be re-registered. In the second operation S430, the host 200 can send the second trigger event TRG_UPR1 on all available TX paths from the host 200 to the storage device 100. The host 200 can continue to send the second trigger event TRG_UPR1 until the host 200 receives the second trigger event message from the storage device 100. The second trigger event TRG_UPR1 sent from the host 200 can include information about the TX paths connected to the host 200.

[0106] In addition, in the second operation S430, the storage device 100 can send the second trigger event TRG_UPR1 on all available TX paths from the storage device 100 to the host 200. The storage device 100 can continue to send the second trigger event TRG_UPR1 until the storage device 100 receives the second trigger event message from the host 200. The second trigger event TRG_UPR1 sent from the storage device 100 can include information about the TX paths connected to the storage device 100.

[0107] In the third operation S440 of the link startup sequence, the physical layers of the interconnect circuits 110 and 210 can reflect in the attributes of the PLs 111 and 211 of the interconnect circuits 110 and 210 how many connected paths there are between the host 200 and the storage device 100, that is, how many available paths there are. In the third operation S440, the host 200 can send the third trigger event TRG_UPR2 on all available TX paths from the host 200 to the storage device 100. The host 200 can continue to send the third trigger event TRG_UPR2 until the host 200 receives a message corresponding to the third trigger event TRG_UPR2 from the storage device 100. The third trigger event TRG_UPR2 sent from the host 200 can include the number of logical paths for the TX paths connected to the host 200.

[0108] In addition, in the third operation S440, the storage device 100 can send the third trigger event TRG_UPR2 on all available TX paths from the storage device 100 to the host 200. The storage device 100 can continue to send the third trigger event TRG_UPR2 until the storage device 100 receives the third trigger event message corresponding to the third trigger event TRG_UPR2 from the host 200. The third trigger event TRG_UPR2 sent from the storage device 100 can include the number of logical paths for the TX paths connected to the storage device 100.

[0109] Because the third operation S430 of the link startup sequence is executed, the host 200 and the storage device 100 can have matching numbers of logical paths for the available paths. At this time, the host 200 and the storage device 100 can end the link startup sequence and perform a capabilities exchange.

[0110] In operation S450, the host 200 and the storage device 100 can exchange and identify CAP information (capability information) about each other's performance to mutually convey the construction requirements of the interconnect circuits 210 and 110. The construction requirements of the interconnect circuits 210 and 110 represented by the CAP information can include, for example, bandwidth, timer, speed level, termination / non-termination, scrambling, etc. Operation S450 can be referred to as a performance exchange operation. Because the performance exchange operation S450 is executed, information about each other's performance can be collected in the interconnect circuits 210 and 110, and the attributes of the PLs of the interconnect circuits 210 and 110 can be set according to the collected CAP information.

[0111] In operation S460, the host 200 and the storage device 100 may exchange control frames with each other, for example, an AFC control frame (acknowledgment flow control frame), to provide a reliable data link. To this end, the host 200 and the storage device 100 may send initial data frames to each other, and the device that receives the data frame among the host 200 and the storage device 100 may send the AFC control frame back to the device that sends the data frame among the host 200 and the storage device 100. The AFC control frame may be configured differently from the data frame and may be used to allow the sending device to recognize that the receiving device has correctly received the data frame and to notify the available buffer space in the data link layer. In operation S470, when the link startup operation is completed, the host 200 and the storage device 100 may be set to the connected state and may stably send and receive data from each other.

[0112] Figure 16 is a flowchart of a link startup method of a storage device according to an embodiment. Refer to Figure 16 , the link startup method of the storage device according to the present embodiment may correspond to an example implementation of the Figure 11 link startup method and may include operations performed in the storage device 100 according to a time series in Figure 1 . Hereinafter, reference will be made to Figure 1 , Figure 3 , Figure 4 and Figure 16 to describe the link startup method.

[0113] In operation S540, the storage device 100 determines whether the line reset duration is greater than a first reference time T1. For example, the first reference time T1 may correspond to the maximum value of the line reset high-speed connection detection time period T LINE-RESET-HS-LINKUP-DETECT (e.g., about 300 μs). In this case, the line reset duration may correspond to the duration of the line reset signal (e.g., the duration of the period during which the differential line voltage DIF is driven to be in the DIF-P state). For example, the differential line voltage DIF may correspond to the voltage level difference between the positive input signal DIN_t and the negative input signal DIN_c received from the first pins P1a and P1b of Figure 1 respectively. For example, operation S540 may correspond to Figure 15 operation S420.

[0114] As a result of the determination, when the line reset duration is not greater than the first reference time T1, in operation S560, the storage device 100 executes a high-speed mode link startup sequence. For example, Figure 15 operations S430 to S460 may be executed in high speed mode. On the other hand, when the line reset duration is greater than the first reference time T1, the storage device 100 executes a low-speed mode link startup sequence. For example,Figure 15 Operations S430 to S460 can be performed in a low-speed mode (i.e., PWM (pulse width modulation) mode).

[0115] In the start-up of the low-speed mode link performed by the PWM method, when exchanging the information required for link start-up between the storage device 100 and the host 200 through a path (e.g., a transmission path or a reception path), the bits indicating the information required for link start-up are represented by the pulse width of the signal transmitted through the path. In the start-up of the low-speed mode link performed by the PWM method, the return-to-zero (RZ) method in which the logical low time period of the signal transmitted through the path must be between the logical high time periods is used.

[0116] On the contrary, in the start-up of the high-speed mode link, the bits indicating the information required for link start-up are represented by the logical level of the signal transmitted through the path, and the non-return-to-zero (NRZ) method is used. In the non-return-to-zero (NRZ) method, even when the logical high time periods are continuous, there is no need for a logical low time period between the logical high time periods. Therefore, the start-up operation of the high-speed mode link can be performed at a higher speed and in less time than the start-up operation of the low-speed mode link to obtain the connection state between the host 200 and the storage device 100.

[0117] Figure 17 is a flowchart of a link start-up method of a storage device according to an embodiment. Refer to Figure 17 , the link start-up method of the storage device according to the present embodiment can correspond to Figure 16 modifications of the link start-up method, and redundant descriptions can be omitted.

[0118] In operation S530, the storage device 100 determines whether the line reset duration is greater than a second reference time T2. For example, the second reference time T2 can correspond to Figure 4 the minimum value of the line reset high connection detection time period T LINE-RESET-HS-LINKUP-DETECT (e.g., about 200 μs). As a result of the determination, when the line reset duration is greater than the second reference time T2, in operation S540, the storage device 100 determines whether the line reset duration is greater than a first reference time T1. According to the present embodiment, when the line reset duration is not greater than the second reference time T2, even when the line reset duration is less than the first reference time T1, the link start-up sequence may not be executed.

[0119] Figure 18 is a flowchart of a link start-up method of a storage device according to an embodiment. Refer to Figure 18 , the link start-up method of the storage device according to the present embodiment can correspond to Figure 16 modifications of the link start-up method, and redundant descriptions can be omitted.

[0120] In operation S510, the storage device 100 determines the activation period T ACTIVATE and checks if its duration is less than a third reference time T3. For example, the third reference time T3 may be about 0.9 ms. As a result of this determination, when the duration of the activation period T ACTIVATE is less than the third reference time T3, in operation S520 the storage device 100 sets the PL and / or LL of the interconnect layer to a default configuration, e.g., a configuration for performing a high-speed link startup sequence. For example, in operation 520, the device controller 120 may preset the PL 111 to the default configuration to perform a high-speed link startup sequence. For example, in operation 520, the device controller 120 may preset the LL 115 of the interconnect circuit 110 to the default configuration to perform a high-speed link startup sequence. For example, in operation 520, the storage device 100 may initialize the PL 111 and LL 115 to perform a high-speed link startup sequence. On the other hand, when the duration of the activation period T ACTIVATE is not less than the third reference time T3, operation S540 is immediately executed.

[0121] In operation S540, the storage device 100 determines if the line reset duration is greater than a first reference time T1. As a result of this determination, when the line reset duration is not greater than the first reference time T1, in operation S560 the storage device 100 performs a high-speed mode link startup sequence. On the other hand, when the line reset duration is greater than the first reference time T1, the storage device 100 performs a low-speed mode link startup sequence. As described above, according to this embodiment, to determine the operation mode for performing a link startup sequence, a two-step determination method can be used, in which the duration of the activation period T ACTIVATE is determined, and then the line reset duration is determined.

[0122] Figure 19 is a flowchart of the link startup operation between the host 200 and the storage device 100 according to an embodiment. Referring to Figure 19 , the link startup operation according to this embodiment can correspond to the modification of the link startup operation of Figure 15 , and redundant descriptions can be omitted. Operation S400 may correspond to exiting the hibernation state HIBERN8. In operation S400, the host 200 generates a signal (e.g., an activation signal) indicating an exit from the power-saving mode (e.g., exiting the hibernation state HIBERN8), and sends the generated signal to the storage device 100. Specifically, the host 200 may transition the line LINE to the DIF-N state and exit the hibernation state HIBERN8. Additionally, in operation S400, the storage device 100 may send information to the host 200 indicating that it has exited the hibernation state HIBERN8. It can be based on the above reference Figure 15The described operations perform operations S410 to S470, and redundant descriptions will be omitted.

[0123] Figure 20 is a flowchart of a link startup method for a storage device according to an embodiment.

[0124] Referring to Figure 1 、 Figure 3 and Figure 20 , in operation S500, the storage device 100 may exit the sleep state HIBERN8. For example, when the differential line voltage DIF changes from the DIF-Z state to the DIF-N state, the storage device 100 may determine that it has entered the activation period T ACTIVATE and exit the sleep state HIBERN8. In operation S540, the storage device 100 determines whether the line reset duration is greater than the first reference time T1. As a result of the determination, when the line reset duration is not greater than the first reference time T1, in operation S560 the storage device 100 executes a high-speed mode link startup sequence. On the other hand, when the line reset duration is greater than the first reference time T1, the storage device 100 executes a low-speed mode link startup sequence.

[0125] Figure 21 is a flowchart of a link startup method for a storage device according to an embodiment. Referring to Figure 21 , the link startup method of the storage device according to the present embodiment may correspond to an example implementation of the link startup method of Figure 11 and may include operations performed in time series in the storage device 100 of Figure 1 .

[0126] In operation S620, the storage controller 100 determines whether there is a line reset. Specifically, the storage device 100 determines whether it has received a line reset signal LINE-RESET from the host 200. In an embodiment, the storage device 100 may determine whether there is a line reset period during which the line LINE has a positive differential line voltage. In an embodiment, the storage device 100 may determine whether the line LINE changes from a negative differential line voltage to a positive differential line voltage. For example, Figure 6 's line reset detector 140a may detect whether the line reset signal LINE-RESET is received by using the system clock SYS_CLK. For example, Figure 8 's line reset detector 140b and Figure 9 's line reset detector 140c may detect whether the line reset signal LINE-RESET is received by using an RC filter. For example, the line reset detector 140a or the line reset detector 140b may detect a long DIF-P.

[0127] As a result of the determination, when there is a line reset signal LINE-RESET, the storage device 100 executes a high-speed mode link start-up sequence in operation S640. In this case, the storage device 100 may omit the line reset operation. When there is no line reset signal LINE-RESET, the storage device 100 executes a low-speed mode link start-up sequence.

[0128] Each of the embodiments described above with reference to Figures 11 to 20 can also be applied to this embodiment. In some embodiments, after operation S620, the storage device 100 may set the PL 111 or LL 115 of the interconnection circuit 110 to perform a high-speed mode link start-up operation or a low-speed mode link start-up operation. In addition, in some embodiments, before operation S620, the storage device 100 may compare the activation period during which the line LINE has a negative differential line voltage with a reference. When the activation period is less than the reference time, the storage device 100 may set the PL 111 or LL 115 of the interconnection circuit 110. In addition, in some embodiments, before operation S620, the storage device 100 may exit the sleep state HIBERN8 which is a power saving state.

[0129] Figure 22 is a flowchart of operations between the host 200 and the storage device 100 according to an embodiment.

[0130] Referring to Figure 22 , in operation S710, the host 200 generates a line reset signal LINE-RESET. In operation S720, the host 200 sends the line reset signal LINE-RESET to the storage device 100 through the differential input signal lines, and sends a positive input signal DIN_t and a negative input signal DIN_c through the differential input signal lines. Operations S710 and S720 may correspond to setting the storage device 100 to the high-speed mode standby HS_SB.

[0131] In operation S730, the host 200 performs a link start-up operation in high-speed mode. In operation S740, the storage device 100 performs a link start-up operation in high-speed mode. Operations S730 and S740 may be performed substantially at the same time. For example, operations S730 and S740 may correspond to Figure 12 operation S250 and operation S260 respectively. In operation S750, when the link start-up operation is completed, the connection state between the host 200 and the storage device 100 can be achieved, and the host 200 and the storage device 100 can stably exchange data with each other (for example, using the path / line on which the link start-up operation has been completed, for example, the path / line through which the positive input signal DIN_t and the negative input signal DIN_c are sent). Operations S250 to S270 may be performed in high-speed mode HS_MD.

[0132] The above reference Figures 11 to 20 The various embodiments described above can also be applied to this embodiment. In some embodiments, before operation S820, the storage device 100 may set the interconnect circuit 110 to perform a high-speed mode link startup operation. In addition, in some embodiments, before operation S880, the storage device 100 may set the interconnect circuit 110 to perform a low-speed mode link startup operation.

[0133] In addition, as Figure 23 represented in the method of, in some embodiments, in operation S820, a first trigger event for exchanging the number of physical paths of the transmission path and the reception path between the storage device 100 and the host 200, a second trigger event for exchanging information about the transmission path and information about the reception path between the storage device 100 and the host 200, and a third trigger event for exchanging logical path information about the transmission path and the reception path between the storage device 100 and the host 200 may be executed. In addition, in some embodiments, in operation S820, after executing the third trigger event, performance information may be exchanged and identified between the storage device 100 and the host 200, and a control frame indicating that the initially transmitted data frame has been correctly received may be exchanged and identified between the storage device 100 and the host 200.

[0134] Figure 23 is a flowchart of a link startup method of a storage system according to an embodiment. Refer to Figure 23 , according to the link startup method of the storage system of the present embodiment, it can correspond to an example implementation of the link startup method of Figure 11 and may include operations performed in the storage system 10 of Figure 1 in chronological order.

[0135] In operation S820, a high-speed mode link startup sequence is performed between the storage device 100 and the host 200 (for example, an operation for establishing a connection state by implementing a link startup operation in high-speed mode according to the embodiments described herein). In operation S840, the storage device 100 or the host 200 determines whether the high-speed mode link startup sequence of S820 is completed. As a result of the determination, when the high-speed connection operation is completed, the storage device 100 or the host 200 determines whether the connection is successful in operation S860. As a result of the determination, when the connection is successful, the link startup method ends. When the connection is not successful, in operation S880, a low-speed mode link startup sequence (i.e., for the path / line where the connection fails) is performed between the storage device 100 and the host 200.

[0136] In the initial stage, since the host 200 does not know whether the storage device 100 supports the high-speed mode, the host 200 may preferably execute the high-speed mode link startup sequence (as the default link startup sequence of the host 200) in S820. As a result of both the host 200 and the storage device 100 successfully executing the high-speed mode link startup sequence, when the connection is successful (for example, the connection state between the storage device 100 and the host 200 is achieved), the host 200 may determine that the storage device 100 supports the high-speed mode. On the other hand, when the connection is not successful after executing the high-speed mode link startup sequence, the host 200 may determine that the storage device 100 is a device that does not support the high-speed mode, and both the host 200 and the storage device 100 may execute the low-speed mode link startup sequence to provide the connection state between the storage device 100 and the host 200.

[0137] As described above, according to the present embodiment, when power is applied to the storage system 10, the host 200 may first attempt to establish a connection state with the storage device 100 by executing the high-speed mode link startup sequence with the storage device 100 first. Therefore, when the storage device 100 is a device that supports the high-speed mode, the storage device 100 may immediately execute the high-speed mode link startup sequence without performing operations such as detecting whether there is a line reset or detecting the line reset duration, and thus the time required for the link startup process can be further reduced.

[0138] Figure 24 is a flowchart of a link startup method of a storage system according to an embodiment. Refer to Figure 24 , according to the link startup method of the storage system according to the present embodiment, it may correspond to an example implementation of the link startup method of Figure 23 and may include operations performed in the storage system 10 of Figure 1 in time series.

[0139] In operation S820, a high-speed mode link startup sequence is executed between the storage device 100 and the host 200. In operation S840a, the storage device 100 or the host 200 determines whether the execution time t of the high-speed mode link startup sequence has exceeded a pre-determined threshold time Tth. Specifically, the storage device 100 may determine whether the threshold time Tth has elapsed after the initialization of the high-speed mode link startup sequence. The threshold time Tth may be defined as a link timeout value. For example, the threshold time Tth may be about 10 ms.

[0140] When the execution time t has exceeded the threshold time Tth, the host 200 determines in operation S840a whether performance information (e.g., PACP CAP ind) has been received from the storage device 100. When the host 200 has received performance information from the storage device 100, the host 200 may determine that the connection has been successful. When the host 200 has not received performance information from the storage device 100, the host 200 may determine that the connection has not been successful. Alternatively, when the execution time t has exceeded the threshold time Tth, in operation S840a, the storage device 100 determines whether performance information (e.g., PACP_CAP_ind) has been received from the host 200. When the storage device 100 has received performance information from the host 200, the storage device 100 may determine that the connection has been successful. When the storage device 100 has not received performance information from the host 200, the storage device 100 may determine that the connection has not been successful. When it is determined that the connection is not successful, in operation S880, a low-speed mode link startup sequence is executed between the storage device 100 and the host 200.

[0141] Figure 25 is a block diagram of a UFS system 1000 according to some example embodiments. The UFS system 1000 is compatible with the UFS standard released by the Joint Electron Device Engineering Council (JEDEC) and may include a UFS host 1100, a UFS device 1200, and a UFS interface 1300. Unless the description of Figure 1 and Figure 5 of the storage systems 10 and 10A conflicts with the description below with reference to Figure 25 the description may also apply to Figure 25 the UFS system 1000.

[0142] Reference Figure 25 , the UFS host 1100 and the UFS device 1200 may be interconnected via the UFS interface 1300. When Figure 1 the host 200 in Figure 1 is an AP, the UFS host 1100 may be implemented as part of the AP. The UFS host controller 1110 may correspond to Figure 1 the host controller 220 in Figure 1 The UFS device 1200 may correspond to

[0143] The UFS host 1100 may include a UFS host controller 1110, an application 1120, a UFS driver 1130, a host memory 1140, and a UFS interconnect (UIC) layer 1150. The UFS device 1200 may include a UFS device controller 1210, an NVM storage device 1220, a storage interface 1230, a device memory 1240, a UIC layer 1250, and a regulator 1260. The NVM storage device 1220 may include a plurality of memory cells 1221. The memory cells 1221 may include: vertical NAND (VNAND) flash memories of two-dimensional (2D) or three-dimensional (3D) structures or other types of NVM (e.g., PRAM and / or RRAM). The UFS device controller 1210 and the NVM storage device 1220 may be interconnected via the storage interface 1230. The storage interface 1230 may be implemented to comply with standard protocols (e.g., Toggle and / or ONFI).

[0144] The application 1120 may refer to a program for communicating with the UFS device 1200 to use the functions of the UFS device 1200. The application 1120 may send an input / output request (IOR) for the input / output of the UFS device 1200 to the UFS driver 1130. The IOR may include a data read request, a data write request, and / or a data discard request, but is not limited thereto.

[0145] The UFS driver 1130 may manage the UFS host controller 1110 via a UFS host controller interface (HCI). The UFS driver 1130 may convert the IOR generated by the application 1120 into a UFS command defined by the UFS standard, and may send the UFS command to the UFS host controller 1110. A single IOR may be converted into multiple UFS commands. The UFS command may be a command defined by the Small Computer System Interface (SCSI) standard or a command not included in the UFS standard.

[0146] The UFS host controller 1110 may send the UFS command from the UFS driver 1130 to the UIC layer 1250 of the UFS device 1200 via the UIC layer 1150 and the UFS interface 1300. In this process, the UFS host register of the UFS host controller 1110 may be used as and provide a command queue.

[0147] The UIC layer 1150 of the UFS host 1100 may include an MIPI M-PHY 1151 and an MIPI UniPro 1152, and the UIC layer 1250 of the UFS device 1200 may also include an MIPI M-PHY 1251 and an MIPI UniPro 1252.

[0148] The UFS interface 1300 may include: a line for transmitting a reference clock signal REF_CLK for the UFS device 1200, a line for transmitting a hardware reset signal RESET_n; a pair of wires for transmitting a complementary input signal pair DIN_T and DIN_C; and a pair of wires for transmitting a complementary output signal pair DOUT_T and DOUT_C.

[0149] The frequency value of the reference clock signal REF_CLK provided from the UFS host 1100 to the UFS device 1200 may be one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. Even while operating or exchanging data with the UFS device 1200, the UFS host 1100 may change the frequency value of the reference clock signal REF_CLK. The UFS device 1200 may generate a clock signal having a frequency different from that of the reference clock signal REF_CLK by using a phase-locked loop (PLL) or the like, and the reference clock signal REF_CLK is received from the UFS host 1100. The UFS host 1100 may use the frequency value of the reference clock signal REF_CLK to set the value of the data rate between the UFS host 1100 and the UFS device 1200. In other words, the value of the data rate may be determined according to the frequency value of the reference clock signal REF_CLK.

[0150] The UFS interface 1300 may support multiple channels, and each of the channels may be implemented as a differential pair. For example, the UFS interface 1300 may include at least one receiving channel and at least one transmitting channel. In Figure 25 this case, a pair of wires for transmitting a complementary input signal pair DIN_T and DIN_C may form a receiving channel, and a pair of wires for transmitting a complementary output signal pair DOUT_T and DOUT_C may form a transmitting channel. Although Figure 25 one transmitting channel and one receiving channel are shown in this case, the number of transmitting channels and receiving channels may be changed.

[0151] In the serial communication mode, the receive path and the transmit path can send data. Since the receive path is separated from the transmit path, the UFS host 1100 can communicate with the UFS device 1200 in full-duplex mode. In other words, even while receiving data from the UFS host 1100 through the receive path, the UFS device 1200 can send data to the UFS host 1100 through the transmit path. Control data (e.g., commands from the UFS host 1100 to the UFS device 1200) can be sent through the same path as the user data, and the UFS host 1100 writes or reads the user data to / from the NVM storage device 1220 of the UFS device 1200. Therefore, no additional path for data transmission other than the receive path and transmit path pair is required between the UFS host 1100 and the UFS device 1200.

[0152] The UFS device controller 1210 of the UFS device 1200 can overall control the operations of the UFS device 1200. The UFS device controller 1210 can manage the NVM storage device 1220 using logical units 1211 corresponding to logical data storage units. The number of logical units 1211 can be eight, but is not limited thereto. The UFS device controller 1210 can include a flash translation layer (FTL), and can convert the logical address data (e.g., logical block address (LBA)) received from the UFS host 1100 into physical data addresses (e.g., physical block address (PBA)) using the address mapping information of the FTL. The logical blocks for storing user data in the UFS system 1000 can have dimensions within a specific range. For example, the minimum size of a logical block can be set to 4K bytes.

[0153] When a command is input from the UFS host 1100 to the UFS device 1200 through the UIC layer 1250, the UFS device controller 1210 can execute the operation corresponding to the command, and send a completion response to the UFS host 1100 after the operation is completed.

[0154] For example, when the UFS host 1100 writes user data to the UFS device 1200, the UFS host 1100 can send a data write command to the UFS device 1200. When the UFS host 1100 receives a response corresponding to ready for transmission from the UFS device 1200, the UFS host 1100 can send the user data to the UFS device 1200. The UFS device controller 1210 can temporarily store the user data in the device memory 1240, and write the user data temporarily stored in the device memory 1240 to a selected location of the NVM storage device 1220.

[0155] In another example, when the UFS host 1100 reads user data from the UFS device 1200, the UFS host 1100 may send a data read command to the UFS device 1200. The UFS device controller 1210 may receive the data read command, read user data from the NVM storage device 1220 based on the data read command, and temporarily store the read user data in the device memory 1240. During the read operation, the UFS device controller 1210 may detect and correct errors in the read user data by using an embedded error correction code (ECC) engine (not shown). Specifically, the ECC engine may generate parity bits for the data to be written to the NVM storage device 1220 and may store the parity bits together with the data in the NVM storage device 1220. When reading data from the NVM storage device 1220, the ECC engine may use the parity bits to correct errors in the data, the parity bits being read from the NVM storage device 1220 together with the data, and may output the error-corrected read data.

[0156] The UFS device controller 1210 may send the user data that has been temporarily stored in the device memory 1240 to the UFS host 1100. The UFS device controller 1210 may also include an Advanced Encryption Standard (AES) engine (not shown). The AES engine may perform at least one selected from encryption and decryption of data input to the UFS device controller 1210 by using a symmetric key algorithm.

[0157] The UFS host 1100 may store commands to be sent to the UFS device 1200 in the UFS host register 1111. The UFS host register 1111 may be used as a sequential command queue and sequentially send the commands to the UFS device 1200. Currently, even while a command sent to the UFS device 1200 is being processed by the UFS device 1200, that is, even before the completion of processing of the command to be sent to the UFS device 1200 is notified to the UFS host 1100, the UFS host 1100 may send subsequent commands in the command queue to the UFS device 1200, and the UFS device 1200 may receive subsequent commands from the UFS host 1100 even while processing previously received commands. The queue depth (i.e., the maximum number of commands that can be stored in the command queue) may be 32. The command queue may be a circular queue, in which a head pointer and a tail pointer respectively indicate the start and end of the command sequence stored therein.

[0158] Each of the memory cells 1221 may include: a memory cell array (not shown); and a control circuit (not shown) that controls the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array includes a plurality of memory cells. Each of the memory cells may be configured as a single-level cell (SLC) or a cell that stores one bit of information, or a multi-level cell (MLC) (which may be a three-level cell (TLC) or a four-level cell (QLC)) that stores at least two bits of information. The 3D memory cell array may include vertically oriented NAND strings in which at least one memory cell is disposed on top of another memory cell.

[0159] Power supply voltages VCC, VCCQ, and VCCQ2 may be input to the UFS device 1200. The power supply voltage VCC may be the main power supply voltage of the UFS device 1200 and may have a value of approximately 2.4V to approximately 3.6V. The power supply voltage VCCQ may be used to supply voltages in the low voltage range and is mainly used for the UFS device controller 1210. The power supply voltage VCCQ may have a value of approximately 1.14V to approximately 1.26V. The power supply voltage VCCQ2 may be used to supply a voltage that is lower than the power supply voltage VCC and higher than the power supply voltage VCCQ, and is mainly used for the input / output interface (e.g., MIPI M-PHY 1251). The power supply voltage VCCQ2 may have a value of approximately 1.7V to approximately 1.95V. Each of the power supply voltages VCC, VCCQ, and VCCQ2 may be supplied to the corresponding elements of the UFS device 1200 through a regulator 1260. The regulator 1260 may be implemented as a group of regulator units respectively connected to the power supply voltages VCC, VCCQ, and VCCQ2.

[0160] Figures 26A to 26C is a diagram for describing the form factor of the UFS card. When the Figure 25 described UFS device 1200 is implemented in the form of a UFS card 2000, the external shape of the UFS card 2000 may be as Figures 26A to 26C shown.

[0161] Figure 26A shows a top view of the UFS card 2000. Referring to Figure 26A , it can be seen that the UFS card 2000 generally conforms to the design of a shark (e.g., having a protrusion in the shape of a shark fin ( Figure 26A on the right side) to facilitate the grasping by the user's finger or thumb). Regarding Figure 26A , the UFS card 2000 may have the dimensions shown in Table 1.

[0162] [Table 1]

[0163] Item Size (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

[0164] Figure 26B Shows a side view of the UFS card 2000. Regarding Figure 26B , the UFS card 2000 may have the dimensions shown in Table 2.

[0165] [Table 2]

[0166]

[0167]

[0168] Figure 26C Shows a bottom view of the UFS card 2000. Referring to Figure 26C , a plurality of pins electrically connected to the UFS slot may be formed in the bottom of the UFS card 2000, and the functions of each pin will be described below. Based on the symmetry between the top and bottom of the UFS card 2000, some details of the dimensions described with reference to Figure 26A and Table 1 (e.g., T1 to T5 and T9) may also be applied to the Figure 26C bottom view of the UFS card 2000.

[0169] A plurality of pins electrically connected to the UFS host may be formed in the bottom of the UFS card 2000. According to Figure 26C , the total number of pins may be 12. Each of the pins may have a rectangular shape, and the Figure 26C shows the signal names corresponding to each pin. General information about each pin may be referred to Table 3.

[0170] [Table 3]

[0171]

[0172]

[0173] Figure 27 Is a block diagram of a memory system 300 according to some example embodiments.

[0174] Referring to Figure 27 , the memory system 3000 may include a memory device 3200 and a memory controller 3100. The memory device 3200 may correspond to a non-volatile memory (NVM) device that communicates with the memory controller 3100 based on one of a plurality of channels. For example, the memory device 3200 may correspond to the NVM 130 in, and the memory controller 3100 may correspond to the Figure 1corresponds to the device controller 120 therein. The memory controller 3100 and the memory device 3200 can both be specifically implemented as a single semiconductor chip having pins corresponding to the chip pads of these semiconductor chips (described below). It should be understood that the NVM 130 can be formed as a single semiconductor chip (e.g., the same as the memory device 3200 when specifically implemented as a single semiconductor chip), and the NVM 130 can also be formed as multiple semiconductor chips (e.g., as a stack of memory chips in a semiconductor package that can also include the memory controller 3100 (e.g., when specifically implemented as a single semiconductor chip)).

[0175] The memory device 3200 can include first pins P11 to eighth pins P18, a memory interface circuit 3210, a control logic circuit 3220, and a memory cell array 3230. The memory interface circuit 3210 can receive a chip enable signal nCE from the memory controller 3100 through the first pin P11. The memory interface circuit 3210 can exchange signals with the memory controller 3100 through the second pin P12 to the eighth pin P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is enabled (e.g., at a certain level), the memory interface circuit 3210 can exchange signals with the memory controller 3100 through the second pin P12 to the eighth pin P18 according to the chip enable signal nCE.

[0176] The memory interface circuit 3210 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 3100 through the second pin P12 to the fourth pin P14, respectively. The memory interface circuit 3210 can receive a data signal DQ from the memory controller 3100 or send a data signal DQ to the memory controller 3100 through the seventh pin P17. A command CMD, an address ADDR, and data DATA can be sent through the data signal DQ. For example, the data signal DQ can be sent through multiple data signal lines. In this case, the seventh pin P17 can include multiple pins corresponding to the data signal lines, respectively.

[0177] The memory interface circuit 3210 can obtain the command CMD from the data signal DQ, which is received based on the transition timing of the write enable signal nWE during the enable period (e.g., high level state) of the command latch enable signal CLE. The memory interface circuit 3210 can obtain the address ADDR from the data signal DQ, which is received based on the transition timing of the write enable signal nWE during the enable period (e.g., high level state) of the command address enable signal CLE.

[0178] In an example embodiment, the write enable signal nWE may be maintained in a quiescent state (e.g., high level or low level) and transition between the high level and the low level. For example, the write enable signal nWE may transition during the period when the command CMD or the address ADDR is transmitted. Thus, the memory interface circuit 3210 may acquire the command CMD or the address ADDR based on the transition timing of the write enable signal nWE.

[0179] The memory interface circuit 3210 may receive the read enable signal nRE from the memory controller 3100 through the fifth pin P15. The memory interface circuit 3210 may receive or transmit the data strobe signal DQS to / from the memory controller 3100 through the sixth pin P16.

[0180] In the data output operation of the memory device 3200, the memory interface circuit 3210 may receive the transitioning read enable signal nRE through the fifth pin P15 before outputting the data DATA. The memory interface circuit 3210 may generate the transitioning data strobe signal DQS based on the transition of the read enable signal nRE. For example, the memory interface circuit 3210 may generate the data strobe signal DQS that starts to transition after a specific delay (e.g., tDQSRE) from the transition start time of the read enable signal nRE. The memory interface circuit 3210 may transmit the data signal DQ including the data DATA based on the transition timing of the data strobe signal DQS. Thus, the data DATA may be transmitted to the memory controller 3100 in synchronization with the transition timing of the data strobe signal DQS.

[0181] In the data input operation of the memory device 3200, when receiving the data signal DQ including the data DATA from the memory controller 3100, the memory interface circuit 3210 may receive the data DATA and the transitioning data strobe signal DQS from the memory controller 3100 together. The memory interface circuit 3210 may acquire the data DATA from the data signal DQ based on the transition timing of the data strobe signal DQS. For example, the memory interface circuit 3210 may acquire the data DATA by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

[0182] The memory interface circuit 3210 can send the ready / busy output signal nR / B to the memory controller 3100 through the eighth pin P18. The memory interface circuit 3210 can send the status information of the memory device 3200 to the memory controller 3100 through the ready / busy output signal nR / B. When the memory device 3200 is in the busy state (i.e., when the internal operation of the memory device 3200 is being executed), the memory interface circuit 3210 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 3100. When the memory device 3200 is in the ready state (i.e., when the internal operation of the memory device 3200 is not executed or completed), the memory interface circuit 3210 can send the ready / busy output signal nR / B indicating the ready state to the memory controller 3100. For example, when the memory device 3200 is reading data DATA from the memory cell array 3230 in response to a read command, the memory interface circuit 3210 can send the ready / busy output signal nR / B (e.g., low level) indicating the busy state to the memory controller 3100. For example, when the memory device 3200 is programming data DATA into the memory cell array 3230 in response to a program command, the memory interface circuit 3210 can send the ready / busy output signal nR / B indicating the busy state to the memory controller 3100.

[0183] The control logic circuit 3220 can generally control various operations of the memory device 3200. The control logic circuit 3220 can receive the command CMD and / or the address ADDR from the memory interface circuit 3210. The control logic circuit 3220 can generate control signals for controlling other components of the memory device 3200 according to the command CMD and / or the address ADDR. For example, the control logic circuit 3220 can generate various control signals for programming data DATA into the memory cell array 3230 or reading data DATA from the memory cell array 3230.

[0184] The memory cell array 3230 can store the data DATA from the memory interface circuit 3210 under the control of the control logic circuit 3220. The memory cell array 3230 can output the data DATA already stored therein to the memory interface circuit 3210 under the control of the control logic circuit 3220.

[0185] The memory cell array 3230 may include a plurality of memory cells. For example, the memory cells may include flash memory cells. However, the embodiments are not limited thereto. The memory cells may include at least one of RRAM cells, ferroelectric RAM (FRAM) cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, the embodiments will be described focusing on the case where the memory cells include NAND flash memory cells.

[0186] The memory controller 3100 may include first pins P21 to eighth pins P28 and a controller interface circuit 3110. The first pins P21 to eighth pins P28 may respectively correspond to the first pins P11 to eighth pins P18 of the memory device 3200. The controller interface circuit 3110 may send a chip enable signal nCE to the memory device 3200 through the first pin P21. The controller interface circuit 3110 may exchange signals with the memory device 3200 through the second pins P22 to eighth pins P28 according to the chip enable signal nCE.

[0187] The controller interface circuit 3110 may respectively send a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 3200 through the second pin P22 to the fourth pin P24. The controller interface circuit 3110 may send a data signal DQ to the memory device 3200 or receive a data signal DQ from the memory device 3200 through the seventh pin P27.

[0188] The controller interface circuit 3110 may send the data signal DQ including a command CMD or an address ADDR to the memory device 3200 together with the write enable signal nWE which is converted. The controller interface circuit 3110 may send the data signal DQ including the command CMD to the memory device 3200 by sending the command latch enable signal CLE in an enabled state, and may send the data signal DQ including the address ADDR to the memory device 3200 by sending the address latch enable signal ALE in an enabled state.

[0189] The controller interface circuit 3110 may send a read enable signal nRE to the memory device 3200 through the fifth pin P25. The controller interface circuit 3110 may receive or send a data strobe signal DQS to / from the memory device 3200 through the sixth pin P26.

[0190] During a data output operation of the memory device 3200, the controller interface circuit 3110 may generate a read enable signal nRE for transition and send it to the memory device 3200. For example, before outputting data DATA, the controller interface circuit 3110 may generate a read enable signal nRE that transitions from a quiescent state (e.g., high level or low level) to a transition state. Accordingly, the memory device 3200 may generate a data strobe signal DQS for transition based on the read enable signal nRE. The controller interface circuit 3110 may receive a data signal DQ including the data DATA and a transitioned data strobe signal DQS from the memory device 3200. The controller interface circuit 3110 may acquire the data DATA from the data signal DQ based on the transition timing of the data strobe signal DQS.

[0191] During a data input operation of the memory device 3200, the controller interface circuit 3110 may generate a transitioned data strobe signal DQS. For example, before sending data DATA, the controller interface circuit 3110 may generate a data strobe signal DQS that transitions from a quiescent state (e.g., high level or low level) to a transition state. The controller interface circuit 3110 may send a data signal DQ including the data DATA to the memory device 3200 based on the transition timing of the data strobe signal DQS.

[0192] The controller interface circuit 3110 may receive a ready / busy output signal nR / B from the memory device 3200 through the eighth pin P28. The controller interface circuit 3110 may determine status information of the memory device 3200 based on the ready / busy output signal nR / B.

[0193] Figure 28 is a diagram for describing a 3D VNAND structure that may be implemented in any UFS device described herein according to an embodiment. For example, Figure 1 the NVM130 of Figure 28 a 3D VNAND structure. When a storage module of a UFS device is implemented by a 3D VNAND type flash memory, each of a plurality of memory blocks of the storage module may be represented by an equivalent circuit as shown in Figure 28 FIG. Figure 28 The memory block BLKi shown in FIG. represents a 3D memory block having a 3D structure on a substrate (e.g., the substrate of a semiconductor chip (memory chip) of the NVM130). For example, a plurality of memory NAND strings of the storage block BLKi may be formed in a direction perpendicular to the substrate.

[0194] Reference Figure 28, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST. Although in Figure 28 each of the memory NAND strings NS11 to NS33 includes a first memory cell MC1 to an eighth memory cell MC8, the exemplary embodiments are not limited thereto.

[0195] The string select transistor SST may be connected to a corresponding one of the string select lines SSL1, SSL2, and SSL3. The memory cells MC1 to MC8 may be respectively connected to corresponding gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to a corresponding one of the ground select lines GSL1, GSL2, and GSL3. The string select transistor SST may be connected to a corresponding one of the bit lines BL1, BL2, and BL3, and the ground select transistor GST may be connected to the common source line CSL.

[0196] Gate lines at the same height (e.g., GTL1) may be commonly connected to each other, and the ground select lines GSL1, GSL2, and GSL3 and the string select lines SL1, SSL2, and SSL3 may be separated from each other. Although in Figure 28 the memory block BLKi is connected to eight gate lines GTL1 to GTL8 and three bit lines BL1, BL2, and BL3, the exemplary embodiments are not limited thereto.

[0197] Figure 29 is a diagram for describing a bonded VNAND (B-VNAND) structure applicable to a UFS device described herein according to an embodiment. When an NVM is included in a UFS device according to an embodiment described herein, the NVM may be implemented by a B-VNAND type flash memory, and the NVM may have Figure 28 the structure shown.

[0198] Refer to Figure 29, the memory device 4000 may have a chip - to - chip (C2C) structure. In the C2C structure, the upper chip including the cell region CELL may be formed on the first wafer, the lower chip including the peripheral circuit region PERI may be formed on a second wafer different from the first wafer, and the upper chip may be connected to the lower chip using a bonding method. For example, the bonding method may include a method of electrically connecting the bonding metal formed in the top - most metal layer of the upper chip to the bonding metal formed in the top - most metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may include a Cu - Cu bonding method. The bonding metal may include aluminum or tungsten.

[0199] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 4000 may include an external pad bonding region PA, a word - line bonding region WLBA, and a bit - line bonding region BLBA.

[0200] The peripheral circuit region PERI may include: a first substrate 4110; an inter - layer insulating layer 4115; a plurality of circuit devices 4120a, 4120b, and 4120c formed in the first substrate 4110; first metal layers 4130a, 4130b, and 4130c respectively connected to the circuit devices 4120a, 4120b, and 4120c; and second metal layers 4140a, 4140b, and 4140c respectively formed on the first metal layers 4130a, 4130b, and 4130c. In an embodiment, the first metal layers 4130a, 4130b, and 4130c may include tungsten having a relatively large resistance, and the second metal layers 4140a, 4140b, and 4140c may include copper having a relatively small resistance.

[0201] As described in this specification, only the first metal layers 4130a, 4130b, and 4130c and the second metal layers 4140a, 4140b, and 4140c are shown and described, but the embodiment is not limited thereto. At least one metal layer may also be formed on the second metal layers 4140a, 4140b, and 4140c. At least a part of the at least one metal layer formed on the second metal layers 4140a, 4140b, and 4140c may include aluminum having a lower resistance than the copper included in the second metal layers 4140a, 4140b, and 4140c.

[0202] The intermediate insulating layer 4115 may be disposed on the first substrate 4110 to cover the circuit devices 4120a, 4120b, and 4120c, the first metal layers 4130a, 4130b, and 4130c, and the second metal layers 4140a, 4140b, and 4140c, and may include an insulating material (e.g., silicon oxide or silicon nitride).

[0203] The lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b in the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4171b and 4172b in the cell area CELL using a bonding method. The lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may include aluminum, copper, or tungsten.

[0204] The cell area CELL may be provided with at least one memory block. The cell area CELL may include a second substrate 4210 and a common source line 4220. A plurality of word lines 4231 to 4238 (collectively represented by 4230) may be stacked on the second substrate 4210 in a direction perpendicular to the top surface of the second substrate 4210 (e.g., the Z-axis direction). The string selection line may be arranged above the word lines 4230, and the ground selection line may be arranged below the word lines 4230. The word lines 4230 may be arranged between the string selection line and the ground selection line.

[0205] In the bit line bonding area BLBA, the channel structure CHS may extend in a direction perpendicular to the top surface of the second substrate 4210 and pass through the word lines 4230, the string selection line, and the ground selection line. The channel structure CHS may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may correspond to a bit line contact, and the second metal layer 4260c may correspond to a bit line and may be hereinafter referred to as the bit line 4260c. In an embodiment, the bit line 4260c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 4210.

[0206] In Figure 29 it, the area where the channel structure CHS and the bit line 4260c are arranged may be defined as the bit line bonding area BLBA. The bit line 4260c may be electrically connected to the circuit device 4120c, and the circuit device 4120c provides a page buffer 4293 in the peripheral circuit area PERI and in the bit line bonding area BLBA. For example, the bit line 4260c may be connected to the upper bonding metals 4271c and 4272c in the bit line bonding area BLBA, and the upper bonding metals 4271c and 4272c may be connected to the lower bonding metals 4171c and 4172c, and the lower bonding metals 4171c and 4172c are connected to the circuit device 4120c of the page buffer 4293.

[0207] In the word line bonding area WLBA, the word line 4230 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 4210 and may be connected to a plurality of cell contact plugs 4241 to 4247 (collectively denoted by 4240). The word line 4230 may be connected to the cell contact plugs 4240 through pads provided by at least some of the word lines 4230 extending with different lengths in the second direction. The first metal layer 4250b and the second metal layer 4260b may be sequentially stacked on each of the cell contact plugs 4240 connected to the word line 4230. The cell contact plugs 4240 in the word line bonding area WLBA may be connected to the peripheral circuit area PERI through the upper bonding metals 4271b and 4272b of the cell area CELL and the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI.

[0208] The cell contact plugs 4240 may be electrically connected to a circuit device 4120b that provides a row decoder 4294 in the peripheral circuit area PERI. In an embodiment, the operating voltage of the circuit device 4120b that provides the row decoder 4294 may be different from the operating voltage of the circuit device 4120c that provides the page buffer 4293. For example, the operating voltage of the circuit device 4120c that provides the page buffer 4293 may be greater than the operating voltage of the circuit device 4120b that provides the row decoder 4294.

[0209] The common source line contact plug 4280 may be disposed in the external pad bonding area PA. The common source line contact plug 4280 may include a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to the common source line 4220. The first metal layer 4250a and the second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280. For example, the area where the common source line contact plug 4280, the first metal layer 4250a, and the second metal layer 4260a are disposed may be defined as the external pad bonding area PA.

[0210] The first input / output pad 4105 and the second input / output pad 4205 may be disposed in the external pad bonding area PA. Refer to Figure 29, an under-insulating film 4101 covering the bottom surface of the first substrate 4110 may be formed under the first substrate 4110, and a first input / output pad 4105 may be formed on the under-insulating film 4101. The first input / output pad 4105 may be connected to at least one of circuit devices 4120a, 4120b, and 4120c in the peripheral circuit region PERI through a first input / output contact plug 4103, and may be isolated from the first substrate 4110 through the under-insulating film 4101. A side-insulating film may be disposed between the first input / output contact plug 4103 and the first substrate 4110 to electrically isolate the first input / output contact plug 4103 from the first substrate 4110.

[0211] Reference Figure 29 , an upper-insulating film 4201 covering the top surface of the second substrate 4210 may be formed above the second substrate 4210, and a second input / output pad 4205 may be disposed on the upper-insulating film 4201. The second input / output pad 4205 may be connected to at least one of circuit devices 4120a, 4120b, and 4120c in the peripheral circuit region PERI through a second input / output contact plug 4203. For example, the second input / output contact plug 4203 may be connected to the circuit element 4120a through under-bonding metals 4171a and 4172a.

[0212] According to an embodiment, the second substrate 4210 and the common source line 4220 may not be disposed in the region where the second input / output contact plug 4203 is provided. The second input / output pad 4205 may not overlap the word line 4230 in a third direction (e.g., the Z-axis direction). Reference Figure 29 , the second input / output contact plug 4203 may be isolated from the top surface of the second substrate 4210 in a direction parallel to the top surface of the second substrate 4210, and may pass through the interlayer insulating layer 4215 of the cell region CELL to be connected to the second input / output pad 4205.

[0213] According to an embodiment, the first input / output pad 4105 and the second input / output pad 4205 may be selectively formed. For example, the memory device 400 may include: only the first input / output pad 4105 on the first substrate 4110 or only the second input / output pad 4205 on the second substrate 4210. Alternatively, the memory device 4000 may include both the first input / output pad 4105 and the second input / output pad 4205.

[0214] In the external pad bonding region PA of each of the cell region CELL and the peripheral circuit region PERI, the metal pattern of the topmost metal layer may be set as a dummy pattern, or the topmost metal layer may be empty.

[0215] Corresponding to the upper metal pattern 4272a in the uppermost metal layer of the cell region CELL, a lower metal pattern 4173a having the same shape as the upper metal pattern 4272a of the cell region CELL may be formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA. The lower metal pattern 4173a in the uppermost metal layer of the peripheral circuit region PERI may not be connected to the contact portion in the peripheral circuit region PERI. Similarly, corresponding to the lower metal pattern of the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed in the uppermost metal layer of the cell region CELL.

[0216] Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit region PERI may be electrically connected to the upper bonding metals 4171b and 4172b of the cell region CELL using a bonding method.

[0217] Corresponding to the lower metal pattern 4152 formed in the uppermost metal layer of the peripheral circuit region PERI, an upper metal pattern 4292 having the same shape as the lower metal pattern 4152 of the peripheral circuit region PERI may be formed in the bit line bonding region BLBA on the uppermost metal layer of the cell region CELL. A contact portion may not be formed on the upper metal pattern 4292 in the uppermost metal layer of the cell region CELL. For example, the lower metal pattern 4152 may be connected to the circuit element 4120c through the lower bonding metal 4151.

[0218] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method for starting a link of a storage device, the link starting method comprising: Receiving a line reset signal from a host via a line connected to an input signal pin of the storage device; Comparing the duration of the received line reset signal with a first reference time; And In response to the comparison, performing a link start operation between the storage device and the host in a high-speed mode or a low-speed mode, Wherein the high-speed mode achieves a connection state between the host and the storage device faster than the low-speed mode, and Wherein performing the link start operation comprises: In response to the duration of the line reset signal being less than the first reference time, performing the link start operation in the high-speed mode.

2. The link startup method according to claim 1, wherein, Comparing the duration of the line reset signal with the first reference time comprises: comparing the duration of the line reset time period during which the line has a positive differential line voltage with the first reference time.

3. The link startup method according to claim 2, wherein, The input signal pin includes: A positive input signal pin configured to receive a positive input signal and a negative input signal pin configured to receive a negative input signal, Wherein the line includes: a positive wire connected to the positive input signal pin and a negative wire connected to the negative input signal pin, and Wherein receiving the line reset signal comprises: receiving the line reset signal when the voltage level of the positive wire is higher than the voltage level of the negative wire.

4. The link startup method according to claim 3, wherein, Comparing the duration of the line reset signal with the first reference time comprises: Generating a differential line voltage by comparing the voltage level of the positive wire with the voltage level of the negative wire; Generating a system clock count value by counting the number of clocks of the system clock during a period when the differential line voltage has a first state; and Determining the duration of the line reset signal based on the differential line voltage and the system clock count value.

5. The link startup method according to claim 1, wherein, Comparing the duration of the line reset signal with the first reference time comprises: Sensing an output voltage corresponding to the differential line voltage of the line at a first time point by using a resistor-capacitor (RC) filter having a time constant corresponding to the first reference time; and Generating a trigger signal based on the sensed output voltage.

6. The link startup method according to claim 1, wherein, The first reference time is 300 μs.

7. The link startup method according to claim 1 further includes: Before comparing the duration of the line reset signal with the first reference time, comparing the duration of the received line reset signal with a second reference time that is less than the first reference time.

8. The link startup method according to claim 7, wherein, Performing the link start operation comprises: In response to the duration of the line reset signal being greater than the second reference time and less than the first reference time, performing the link start operation in the high-speed mode.

9. The link startup method according to claim 7, wherein The second reference time is 200 μs.

10. The link startup method according to claim 1, wherein, The storage device includes: an interconnect circuit configured to send data to and receive data from the host, and Wherein the link starting method further comprises: in response to the comparison, configuring at least one of a physical layer or a link layer of the interconnect circuit.

11. The link startup method according to claim 1, wherein, Receiving the line reset signal comprises: changing the line from a negative differential line voltage to a positive differential line voltage.

12. The link startup method according to claim 11, wherein, The storage device includes: an interconnection circuit configured to send data to and receive data from the host, and the link startup method further includes: Before comparing the duration of the line reset signal with the first reference time, comparing the activation period during which the line has a negative differential line voltage with a third reference time; and When the activation period is less than the third reference time, configuring at least one of the physical layer or the link layer of the interconnection circuit.

13. The link startup method according to claim 1 further includes: Before receiving the line reset signal, exiting the sleep state which is a power saving state.

14. The link startup method according to claim 1, wherein, The storage device is a UFS device interconnected with the host through the Universal Flash Storage UFS standard.

15. A link startup method for a storage device, the link startup method includes: Determining whether a line reset signal is received from the host through a line connected to an input signal pin of the storage device; And Performing one of the following: In response to receiving the line reset signal from the host, performing a high-speed mode link startup operation between the storage device and the host; And When the line reset signal is not received from the host, performing a low-speed mode link startup operation between the storage device and the host, wherein the high-speed mode link startup operation achieves the connection state between the host and the storage device faster than the low-speed mode link startup operation, and wherein the storage device includes an interconnection circuit configured to send data to and receive data from the host, and the link startup method further includes: after the determination, configuring at least one of the physical layer or the link layer of the interconnection circuit to perform the high-speed mode link startup operation or the low-speed mode link startup operation.

16. The link startup method according to claim 15, wherein, Determining whether the line reset signal is received includes: determining whether there is a line reset period during which the line has a positive differential line voltage.

17. A link startup method for a storage system including a storage device and a host, the link startup method includes: Performing a high-speed mode link startup operation between the storage device and the host; Determining whether the high-speed mode link startup operation is completed; When it is determined that the high-speed mode link startup operation is completed, determining whether the connection between the storage device and the host as a result of the high-speed mode link startup operation is successful; And When the connection is not successful, performing a low-speed mode link startup operation between the storage device and the host, wherein the high-speed mode link startup operation achieves the connection state between the host and the storage device faster than the low-speed mode link startup operation, and wherein determining whether the high-speed mode link startup operation is completed includes: determining whether a threshold time has elapsed since the start of the high-speed mode link startup operation.

18. The link startup method according to claim 17, wherein, Performing the high-speed mode link startup operation includes: Performing a first trigger event for exchanging the number of physical paths of the transmission path and the reception path between the storage device and the host; Performing a second trigger event for exchanging information about the transmission path and information about the reception path between the storage device and the host; and Execute a third trigger event for exchanging logical path information about the transmission path and the reception path between the storage device and the host.

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