Automatic Frequency Calibration Device

Abstract

The present invention discloses an automatic frequency calibration device, which includes a resampled 2n frequency divider, a frequency error detector, and a finite state machine. Among them, the resampled 2n frequency divider receives the output signal of the voltage-controlled oscillator and performs resampling and frequency division processing to generate 2n output clock signals with different phases and evenly distributed within 2π; the frequency error detector receives the output clock signals and performs counting and accumulation processing to obtain a counting and accumulation value, and compares it with the target count value to obtain a counting difference; the finite state machine searches for the minimum frequency error value according to the counting difference and transmits the corresponding capacitor array code to the capacitor array. The present invention greatly improves the calibration accuracy while ensuring the calibration time, and reduces the operating frequency of the counter, and can be applied to systems that require voltage-controlled oscillators with ultra-wide frequency tuning ranges, such as mobile phone radio frequency chips, IoT Internet of Things chips, millimeter-wave radar systems, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency calibration of voltage-controlled oscillators, and particularly relates to an automatic frequency calibration device. Background Art

[0002] In many application fields, especially in multi-standard and multi-band application fields, the voltage-controlled oscillator (VCO) in the phase-locked loop requires a wide frequency tuning range; in order to ensure the phase noise performance of the phase-locked loop, the analog tuning range of the voltage-controlled oscillator, that is, its gain value, should not be too large. Therefore, digital frequency tuning technology has become the only option to expand the frequency range of the voltage-controlled oscillator.

[0003] When the digital frequency tuning technology of the voltage-controlled oscillator (VCO) emerged, the automatic frequency calibration technology also developed accordingly, and technologies such as tuning voltage monitoring closed loop (V-tune Monitoring Closed Loop), relative frequency comparison open loop (Relative Frequency Comparison Open Loop), relative period comparison open loop (Relative Period Comparison Open Loop), and frequency error detector (Frequency Error Detector) have been developed successively.

[0004] However, the inventor has found through research that the tuning voltage closed-loop monitoring technology determines the sub-band movement direction of the voltage-controlled oscillator by monitoring the stable voltage value V after each phase-locked loop is locked. Since the locking time t of the phase-locked loop is usually in the order of dozens of microseconds or even hundreds of microseconds, even if the fastest binary search algorithm is used, for a voltage-controlled oscillator with a digital tuning bit width of w bits, it takes w·t time. It can be seen that this technical solution has the problems of long time and low efficiency. tune to judge the sub-band movement direction of the voltage-controlled oscillator. Since the locking time t of the phase-locked loop lock is usually in the order of dozens of microseconds or even hundreds of microseconds, so even if the fastest binary search algorithm is used, for a voltage-controlled oscillator with a digital tuning bit width of w bits, it takes w·t lock time. Thus, it can be seen that this technical solution has the problems of long time and low efficiency.

[0005] In the relative frequency comparison open-loop technology, within k cycle time periods of the reference clock frequency signal f ref the reference clock frequency signal f ref and the phase-locked loop loop calibration clock frequency signal f cal are respectively counted, and then the count values of the two are compared to obtain their difference, and the change of the digital control code of the voltage-controlled oscillator is judged according to the difference; since the count values of f ref and f cal are compared, it is necessary that the values of f ref and f cal are close to each other, then the calibration frequency division ratio N calEqual to the loop division ratio N = f vco / f ref ; In this technical solution, the frequency calibration accuracy is N·f ref / k, and the calibration time is w·k / f ref , and the calibration accuracy and calibration time need to be compromised through the count window k value. For example, when f ref = 100 MHz and N = 128, when the frequency calibration accuracy of 1 MHz is to be achieved, the value of the corresponding count window k is 12,800. For a voltage-controlled oscillator with a digital tuning bit width of w = 4 bits, its calibration time is as long as 512 μs. It can be seen that this technical solution also has the problems of long time and low efficiency;

[0006] The relative period comparison open-loop technology converts the reference clock frequency signal f ref and the phase-locked loop loop feedback clock frequency signal f b into corresponding voltage values through a time-voltage converter for comparison to obtain a difference, and judges the change of the digital control code of the voltage-controlled oscillator according to the difference; the relative period comparison open-loop technology has higher efficiency for integer phase-locked loops, while for fractional phase-locked loops, since it needs to turn on the ΔΣ modulator, the voltage stabilization time after the time-voltage converter performs voltage conversion is relatively long. As the calibration accuracy increases, its calibration time also becomes longer accordingly, and compromise processing is required;

[0007] Frequency Error Detection (FED) technology is the most widely used automatic frequency calibration technology for voltage-controlled oscillators at present. It consists of a frequency error detector (FED) and a finite state machine (Finite State Machine, abbreviated as FSM); when the phase-locked loop is in the open-loop state, within the specified k reference clock T ref time, the calibrated clock frequency signal f cal after dividing the frequency of the voltage-controlled oscillator is counted, and then compared with the target count value N target to obtain the difference between the two, and judge the sub-band movement direction of the voltage-controlled oscillator according to the difference. Among them, when the calibration division ratio N cal = 1, then f cal is equal to the voltage-controlled oscillator frequency f vco ; In this technical solution, the frequency calibration accuracy is N cal ·f ref / k, and the calibration time is w·k / f ref ; Different from the relative frequency comparison open-loop technology, the target count value N target is introduced in the frequency error detection technology, so N cal can be not equal to the loop division ratio N; when the value of N cal decreases, f calAs it increases, the calibration frequency accuracy is correspondingly improved; however, as the value of N cal decreases, the operating frequency of the counter in the calibration device also increases accordingly, thus greatly increasing the implementation difficulty of the counter.

[0008] In summary, in the prior art, the automatic frequency calibration technology has problems such as low frequency calibration accuracy or long calibration time, and the overall calibration efficiency is low. Although the frequency error detection technology can improve the frequency calibration accuracy and ensure that the calibration time remains unchanged by reducing the calibration frequency division ratio N cal , the operating frequency of the counter increases accordingly, and the implementation difficulty increases. Summary of the Invention

[0009] Based on this, in order to solve the technical problems in the prior art, an automatic frequency calibration device is specifically proposed, including a resampling 2 n frequency divider, a frequency error detector, and a finite state machine;

[0010] Among them, the resampling 2 n frequency divider receives the output signal of the voltage-controlled oscillator and performs resampling and frequency division processing to generate 2 n output clock signals with different phases and evenly distributed within 2π, where n is an integer greater than or equal to 2; the resampling 2 n frequency divider inputs the 2 n output clock signals to the connected frequency error detector;

[0011] Among them, the frequency error detector receives the 2 n output clock signals and performs counting and accumulation processing to obtain a counting accumulation value, compares the counting accumulation value with a target count value to obtain a counting difference; the frequency error detector inputs the counting difference to the connected finite state machine;

[0012] Among them, the finite state machine searches for the minimum frequency error value according to the received counting difference and transmits the capacitance array code corresponding to the minimum frequency error value to the capacitance array of the voltage-controlled oscillator.

[0013] In one embodiment, the resampling 2 n frequency divider includes a prescaler and a resampling uniform phase frequency divider; the prescaler is connected to the resampling uniform phase frequency divider;

[0014] Among them, the prescaler is a 2-frequency divider; the prescaler receives the output signal of the voltage-controlled oscillator and performs 2-frequency division processing to generate two differential output signals; the prescaler outputs the two differential output signals to the resampling uniform phase frequency divider;

[0015] Among them, the resampling uniform phase divider is 2 n-1 divider; the resampling uniform phase divider receives two differential output signals of the prescaler and performs resampling and 2 n-1 frequency division processing to generate 2 n output clock signals with different phases and evenly distributed within 2π range.

[0016] In one embodiment, the resampling uniform phase divider includes 2 n-1 serially connected resampling frequency division units; each resampling frequency division unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first flip-flop, and a second flip-flop; wherein, the first flip-flop and the second flip-flop are D flip-flops.

[0017] In one embodiment, for the m-th resampling frequency division unit in the resampling uniform phase divider, where m = 1, 2,... 2 n-1 :

[0018] The two differential output signals generated by the prescaler include a first differential output signal and a second differential output signal;

[0019] When m is odd, the positive enable terminals of the first inverter and the second inverter receive the second differential output signal, and the negative enable terminals of the first inverter and the second inverter receive the first differential output signal;

[0020] When m is even, the positive enable terminals of the first inverter and the second inverter receive the first differential output signal, and the negative enable terminals of the first inverter and the second inverter receive the second differential output signal;

[0021] The output terminal of the first inverter is connected to the data input terminal of the first flip-flop and to the input terminal of the fourth inverter; the output terminal of the second inverter is connected to the data input terminal of the second flip-flop and to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the input terminal of the third inverter;

[0022] The clock input terminals of the first flip-flop and the second flip-flop receive the output signal of the voltage-controlled oscillator; the output terminal of the first flip-flop outputs the first output clock signal clk m of the m-th resampling frequency division unit, and the output terminal of the second flip-flop outputs the second output clock signal of the m-th resampling frequency division unit where m = 1, 2,... 2 n-1 , and n is an integer greater than or equal to 2;

[0023] The output terminal of the first inverter of the m-th resampling frequency division unit is connected to the input terminal of the second inverter of the next resampling frequency division unit in series therewith, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2 n-1 - 1; the output terminal of the second inverter of the m-th resampling frequency division unit is connected to the input terminal of the first inverter of the next resampling frequency division unit in series therewith, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2 n-1 - 1;

[0024] When m = 2 n-1 i.e., the output terminal of the first inverter of the second n-1 resampling frequency division unit is connected to the input terminal of the first inverter of the first resampling frequency division unit, and the output terminal of the second inverter of the second n-1 resampling frequency division unit is connected to the input terminal of the second inverter of the first resampling frequency division unit.

[0025] In one embodiment, the frequency error detector includes two n counters, an accumulator, and a comparator; the two n counters respectively count the two n output clock signals output by the resampling two n frequency dividers within k reference clock cycles to obtain two n count values, where k is the number of counting reference clock cycles; the two n counters are connected to the accumulator, and the accumulator accumulates the two n count values to obtain a counting accumulation value; the accumulator is connected to the comparator, and the accumulator inputs the counting accumulation value to the comparator;

[0026] The comparator has a first input terminal and a second input terminal; the first input terminal of the comparator receives the counting accumulation value, and the second input terminal of the comparator receives the target count value N target = k·N.f, where N.f is the loop fractional division ratio; the comparator obtains the difference between the counting accumulation value and the target count value to obtain a counting difference; the counting difference includes a sign bit and an absolute value, and the absolute value of the counting difference is the frequency error value; the frequency error detector inputs the counting difference to the finite state machine.

[0027] In one embodiment, the automatic frequency calibration device further includes a counting clock controller; the counting clock controller receives a reference clock signal; the counting clock controller generates a control signal according to the reference clock signal and sends it to the frequency error detector connected thereto, and the control signal is used to control the counter, the accumulator, and the counting comparator to perform counting, accumulation, and comparison processes respectively.

[0028] In one embodiment, the finite state machine includes a search unit, a minimum error code lookup unit, and an output code selection unit; the search unit is connected to the output code selection unit; the minimum error code lookup unit is connected to the output code selection unit;

[0029] The search unit receives the sign bit of the count difference; the search unit determines the sub-band movement search direction of the voltage-controlled oscillator according to the sign bit of the count difference;

[0030] The minimum error code lookup unit receives the absolute value of the count difference; the minimum error code lookup unit stores a minimum frequency error value, and the minimum error code lookup unit compares the absolute value of the count difference it receives with the currently stored minimum error value. When the absolute value of the received count difference is less than the currently stored minimum error value, the minimum frequency error lookup unit updates and stores the absolute value of the count difference as the current minimum frequency error value, and at the same time updates the corresponding capacitor array code, and the capacitor array code corresponds to the sub-band number of the voltage-controlled oscillator;

[0031] The minimum error code lookup unit always stores the capacitor array code with the minimum frequency error value until the search ends during the search process; after the search ends, the output code selection unit transmits the capacitor array code corresponding to the minimum frequency error value stored in the minimum error code lookup unit to the capacitor array of the voltage-controlled oscillator.

[0032] In one embodiment, the search unit determines the sub-band movement search direction of the voltage-controlled oscillator according to the sign bit of the count difference, specifically including:

[0033] When the sign bit of the count difference is negative, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of higher frequency; when the sign bit of the count difference is positive, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of lower frequency.

[0034] In one embodiment, the finite state machine uses a binary search algorithm to search for the minimum frequency error value and the corresponding capacitor array code.

[0035] Implementing the embodiments of the present invention will have the following beneficial effects:

[0036] In the automatic frequency calibration device of the present invention, by introducing a n frequency divider to obtain a nAn output clock signal with uniform phase greatly reduces the operating frequency of the counter. For example, when n is 4, the operating frequency of the counter is only 1 / 16 of the output signal frequency of the voltage-controlled oscillator. To overcome the defect that the phase uniformity in the prior art is susceptible to process influence, by introducing a clock resampling technique, that is, using the output signal of the voltage-controlled oscillator to resample the output clock signal after division by 2 n to ensure that the phases of the 2 n output clock signals are evenly distributed within the range of 2π (360°), greatly reducing the counting error caused by the deterioration of phase uniformity, making the counting error of this counting scheme infinitely close to the error value generated by directly counting the output signal of the voltage-controlled oscillator. The solution of the present invention can be widely applied to various systems that require a voltage-controlled oscillator with an ultra-wide frequency tuning range, such as 2G / 3G / 4G mobile phone multi-mode multi-band RF chips, IoT Internet of Things chips, millimeter-wave radar systems, especially in voltage-controlled oscillator systems with high oscillation frequencies such as millimeter-wave radar systems, which has obvious advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Among them:

[0039] Figure 1 is a schematic diagram of the automatic frequency calibration device in the present invention;

[0040] Figure 2 is a circuit schematic diagram of the resampling uniform phase frequency divider in the present invention;

[0041] Figure 3.1 is a counting waveform diagram of the output clock signal of the 4-frequency divider;

[0042] Figure 3.2 is a counting waveform diagram when the phases of the output clock signals of the 4-frequency divider are uneven. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] Such asFigure 1 As shown, the present invention discloses an automatic frequency calibration device, including a resampling 2 n frequency divider, a frequency error detector, and a finite state machine;

[0045] The resampling 2 n frequency divider is connected to the frequency error detector; the frequency error detector is connected to the finite state machine;

[0046] Among them, the resampling 2 n frequency divider receives the output signal of the voltage-controlled oscillator and performs resampling and frequency division processing to generate 2 n output clock signals with different phases and evenly distributed within 2π; the resampling 2 n frequency divider inputs the 2 n output clock signals to the frequency error detector connected thereto;

[0047] Specifically, the resampling 2 n frequency divider includes a prescaler and a resampling uniform phase frequency divider, where n is an integer greater than or equal to 2; the prescaler is connected to the resampling uniform phase frequency divider;

[0048] Among them, the prescaler is a 2-frequency divider; the prescaler receives the output signal f of the voltage-controlled oscillator vco and performs 2-frequency division processing to generate two differential output signals; the two differential output signals include a first differential output signal ckip and a second differential output signal ckin; the prescaler outputs the two differential output signals to the resampling uniform phase frequency divider;

[0049] Among them, the resampling uniform phase frequency divider is a 2 n-1 frequency divider; the resampling uniform phase frequency divider receives the two differential output signals of the prescaler and performs resampling and 2 n-1 frequency division processing to generate 2 n output clock signals with different phases and evenly distributed within the 2π range (360° range), where i = 1, 2,... 2 i , and n is an integer greater than or equal to 2; n Specifically, the resampling uniform phase frequency divider includes 2

[0050] serially connected resampling frequency division units; each resampling frequency division unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first flip-flop, and a second flip-flop; among them, the first flip-flop and the second flip-flop are D flip-flops; n-1 Among them, the first flip-flop and the second flip-flop are D flip-flops;

[0051] Among them, the D flip-flop has a data input terminal, i.e., the D input terminal, a clock input terminal, i.e., the CLK input terminal, and a positive-phase output terminal, i.e., the Q output terminal;

[0052] Such as Figure 2 As shown, for the m-th resampling frequency division unit in the resampling uniform phase frequency divider, where m = 1, 2,... 2 n-1 , n is an integer greater than or equal to 2:

[0053] The two differential output signals generated by the prescaler include a first differential output signal ckip and a second differential output signal ckin;

[0054] When m is odd, the positive-phase enable terminals of the first inverter and the second inverter receive the second differential output signal ckin, and the inverted enable terminals of the first inverter and the second inverter receive the first differential output signal ckip;

[0055] When m is even, the positive-phase enable terminals of the first inverter and the second inverter receive the first differential output signal ckip, and the inverted enable terminals of the first inverter and the second inverter receive the second differential output signal ckin;

[0056] The output terminal of the first inverter is connected to the data input terminal (D input terminal) of the first flip-flop and is also connected to the input terminal of the fourth inverter; the output terminal of the second inverter is connected to the data input terminal (D input terminal) of the second flip-flop and is also connected to the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the input terminal of the third inverter;

[0057] The clock input terminals (CLK input terminals) of the first flip-flop and the second flip-flop receive the output signal f of the voltage-controlled oscillator vco ; the output terminal of the first flip-flop outputs the first output clock signal clk of this resampling frequency division unit m , and the output terminal of the second flip-flop outputs the second output clock signal of this resampling frequency division unit where m = 1, 2,... 2 n-1 , n is an integer greater than or equal to 2;

[0058] The output terminal of the first inverter of the m-th resampling frequency division unit is connected to the input terminal of the second inverter of the next resampling frequency division unit in series with it, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2 n-1 -1; the output terminal of the second inverter of the m-th resampling frequency division unit is connected to the input terminal of the first inverter of the next resampling frequency division unit in series with it, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2n-1 -1;

[0059] When m=2 n-1 At that time, that is, the 2nd n-1 The output end of the first inverter of the first resampling frequency division unit is connected to the input end of the first inverter of the first resampling frequency division unit, and the output end of the first inverter of the second resampling frequency division unit is connected to the input end of the first inverter of the first resampling frequency division unit. n-1 The output end of the second inverter of the first resampling frequency division unit is connected to the input end of the second inverter of the first resampling frequency division unit;

[0060] As can be seen from the above, the trigger in the resampling frequency division unit uses the voltage-controlled oscillator output signal to resample its output clock signal, thereby ensuring that the 2 n Output clock signal clk i The phase is evenly distributed within the range of 2π (360°);

[0061] The resampling frequency division unit improves 2 n Output clock signal clk i The phase uniformity is improved, and the additional counting error caused by the deterioration of phase uniformity is reduced, thereby improving the frequency calibration accuracy; wherein, the output clock signal frequency The output signal frequency f of the voltage controlled oscillator vco The relationship between them is:

[0062]

[0063] The resampling 2 n The frequency divider is connected to the frequency error detector; the resampling 2 n The divider will 2 n Output clock signal clk i input to the frequency error detector;

[0064] Wherein, the frequency error detector receives 2 n output clock signals and perform count accumulation processing to obtain a count accumulation value, compare the count accumulation value with the target count value to obtain a count difference value; the frequency error detector inputs the count difference value into the finite state machine connected thereto;

[0065] In particular, the frequency error detector (FED) comprises 2 n counter, accumulator, comparator; the 2 n The counter is in k reference clock cycles T ref Resample in time 2 n The divider output is 2 n Output clock signal clk i Count them separately and get 2 na count value, where k is the number of counting reference clock cycles; the 2 n counters are connected to the accumulator, and the accumulator accumulates the 2 n count values to obtain a count accumulation value; the accumulator is connected to the comparator, and the accumulator inputs the count accumulation value to the comparator;

[0066] The comparator has a first input terminal and a second input terminal; the first input terminal of the comparator receives the count accumulation value, and the second input terminal of the comparator receives the set target count value N target = k·N.f, where k is the number of counting reference clock cycles and N.f is the loop fractional division ratio; the comparator compares the count accumulation value with the target count value to obtain the difference between the count accumulation value and the target count value, resulting in a count difference. The count difference includes a sign bit and an absolute value, and the absolute value of the count difference is the frequency error value; the frequency error detector inputs the count difference to the finite state machine;

[0067] wherein, the finite state machine searches for the minimum frequency error value according to the received count difference and transmits the capacitance array code corresponding to the minimum frequency error value to the capacitance array of the voltage-controlled oscillator;

[0068] Specifically, the finite state machine (FSM) includes a search unit, a minimum error code search unit, and an output code selection unit; the search unit is connected to the output code selection unit; the minimum error code search unit is connected to the output code selection unit;

[0069] The search unit receives the sign bit of the count difference; the search unit determines the sub-band movement search direction of the voltage-controlled oscillator according to the sign bit of the count difference;

[0070] Specifically, when the sign bit of the count difference is negative, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of higher frequency; when the sign bit of the count difference is positive, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of lower frequency;

[0071] The minimum error code search unit receives the absolute value σ of the count difference; the minimum error code search unit stores the minimum frequency error value σ min and the minimum error code search unit compares the absolute value σ of the count difference it receives with the currently stored minimum error value σ min When the absolute value σ of the received count difference is less than the currently stored minimum error value σ min then the minimum frequency error search unit updates and stores the absolute value σ of the count difference as the current minimum frequency error value σ min, while updating the corresponding capacitance array code, where the capacitance array code corresponds to the sub-band number of the voltage-controlled oscillator;

[0072] During the search process, the minimum error code search unit always stores the capacitance array code with the minimum frequency error value until the search ends, that is, until the last capacitance array code is searched; after the search ends, the output code selection unit transfers the capacitance array code corresponding to the minimum frequency error value stored in the minimum error code search unit to the capacitance array of the voltage-controlled oscillator;

[0073] Specifically, the finite state machine uses a binary search algorithm to search for the minimum frequency error value and the corresponding capacitance array code; the finite state machine is not limited to using a binary search algorithm for search processing;

[0074] Specifically, the automatic frequency calibration device further includes a counting clock controller; the counting clock controller receives the reference clock signal f ref and generates a corresponding control signal; the counting clock controller is connected to the frequency error detector;

[0075] Specifically, the counting clock controller receives the reference clock signal f ref ; the counting clock controller generates a control signal according to the reference clock signal f ref and sends it to the frequency error detector connected thereto, and the control signal is used to control the counter, accumulator, and counting comparator to perform counting, accumulation, and comparison processing respectively.

[0076] In the present invention, the frequency calibration accuracy of the automatic frequency calibration device is:

[0077]

[0078] wherein, f ref is the frequency of the reference clock signal; k is the number of reference clock cycles for counting, that is, the count value of the reference clock cycle T ref for counting the voltage-controlled oscillator signal;

[0079] It can be seen that the calibration accuracy is the same as the accuracy of directly counting the output clock of the voltage-controlled oscillator;

[0080] In the present invention, the frequency calibration time of the automatic frequency calibration device is:

[0081] t cal = w·k·T ref

[0082] wherein, T ref is the reference clock cycle; k is the number of reference clock cycles for counting, that is, the count value of the reference clock cycle for counting the voltage-controlled oscillator signal; w is the digital tuning bit width of the voltage-controlled oscillator;

[0083] It can be seen that the calibration time is the same as the duration of directly counting the output signal of the voltage-controlled oscillator.

[0084] The operating frequency of the counter of the frequency calibration device is:

[0085]

[0086] where f vco is the output signal frequency of the voltage-controlled oscillator, and n is an integer greater than or equal to 2; the operating frequency of the calibration counter is 1 / 2 of the operating frequency of the counter that directly counts the output signal of the voltage-controlled oscillator n .

[0087] Implementing the embodiments of the present invention will have the following beneficial effects:

[0088] For example, when n = 2, the output signal of the voltage-controlled oscillator passes through the frequency division processing of a resampling 4-divider to obtain 4 output clock signals with phases evenly distributed within 360°. These 4 output clock signals are respectively counted and the sum is accumulated. The obtained count accumulation value is compared with the target count value N target ; Counting and accumulating the 4 output clock signals with evenly distributed phases is equivalent to directly counting the output of the voltage-controlled oscillator, that is, equivalent to calibrating the division ratio N cal = 1, and the calibration accuracy is increased by 4 times. At the same time, the operating frequency of the counter is 1 / 4 of the voltage-controlled oscillator frequency, and the implementation difficulty is greatly reduced;

[0089] As Figure 3.1 shown, the technical solution of counting and accumulating the 4 output clock signals (clk1, clk2, clk3, clk4) with phases evenly distributed within 360° is very different from the technical solution of counting and accumulating a single output clock signal and then performing a 4-fold multiplication; assuming the counting window k = 1, f vco = 10f ref , then directly counting and accumulating f vco results in 10; the results obtained by counting a single output clock signal and then multiplying by 4 are different. The results of multiplying the corresponding count values 2, 3, 3, 2 of clk1, clk2, clk3, clk4 by 4 are 8, 12, 12, 8 respectively. It can be seen that no matter which value is taken and compared with the accumulated value 10, an additional counting error of 2 will be introduced, thus affecting the frequency calibration accuracy, and this counting error value will further deteriorate as the division ratio of the divider increases; while using the technical solution of the present invention to count and accumulate the 4 output clock signals with evenly distributed phases still results in 2 + 3 + 3 + 2 = 10, which can ensure that no additional error value is introduced;

[0090] In addition, if the phases of the four output clock signals are not uniform, that is, the frequency divider does not have a resampling frequency division unit to ensure the phase uniformity of the output clock signals, when the phase of the output clock signal is not in the ideal position, such as Figure 3.2 shown, the phase of clk3 is not in the ideal position but has a certain delay, then the count value of clk3 is 2 instead of 3. At this time, the count accumulation value (2 + 3 + 2 + 2 = 9) and the direct counting of f vco The additional counting error value generated between the count accumulation values (10) is not 0, and this counting error value will also deteriorate as the frequency division ratio of the frequency divider increases. It can be seen that in the technical solution of the present invention, using a resampling frequency division unit to ensure the phase uniformity of the output clock signals is the key to ensuring no additional counting errors.

[0091] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An automatic frequency calibration device, characterized in that, Including resampling 2 n Divider, frequency error detector, finite state machine; Among them, the resampling 2 n The frequency divider receives the output signal of the voltage-controlled oscillator and performs resampling and frequency division processing to generate 2 n output clock signals with different phases and evenly distributed within the range, where n is an integer greater than or equal to 2; the resampling 2 n The frequency divider inputs 2 n output clock signals to the frequency error detector connected thereto; Wherein, the frequency error detector receives 2 n output clock signals and performs counting and accumulation processing to obtain a counting and accumulation value, compares the counting and accumulation value with a target count value to obtain a counting difference; the frequency error detector inputs the counting difference to the finite state machine connected thereto; Among them, the finite state machine searches for the minimum frequency error value according to the received counting difference, and transmits the capacitance array code corresponding to the minimum frequency error value to the capacitance array of the voltage-controlled oscillator; Among them, the frequency error detector includes 2 n counters, an accumulator, and a comparator; the 2 n counters respectively count the 2 n output clock signals output by the resampling 2 n -divider within k reference clock cycles to obtain 2 n count values, where k is the number of counting reference clock cycles; the 2 n counters are connected to the accumulator, and the accumulator accumulates the 2 n count values to obtain a count accumulation value; the accumulator is connected to the comparator, and the accumulator inputs the count accumulation value to the comparator; The comparator has a first input terminal and a second input terminal; the first input terminal of the comparator receives a counted accumulation value, and the second input terminal of the comparator receives a target count value , where N.f is the loop fractional division ratio; the comparator obtains a difference between the counted accumulation value and the target count value to obtain a counting difference; the counting difference includes a sign bit and an absolute value, and the absolute value of the counting difference is a frequency error value; the frequency error detector inputs the counting difference to the finite state machine.

2. The automatic frequency calibration device according to claim 1, wherein: Among them, The resampling 2 n The frequency divider includes a prescaler and a resampling uniform phase frequency divider; the prescaler is connected to the resampling uniform phase frequency divider; Among them, the prescaler is a divide-by-2 prescaler; the prescaler receives the output signal of the voltage-controlled oscillator and performs a divide-by-2 process to generate two differential output signals; the prescaler outputs the two differential output signals to the resampling uniform phase divider; Among them, the resampling uniform phase divider is a 2 n-1 divider; the resampling uniform phase divider receives the two-way differential output signals of the prescaler and performs resampling and 2 n-1 division processing to generate 2 n output clock signals with different phases and evenly distributed within the range.

3. The automatic frequency calibration device according to claim 2, wherein: Among them, The resampling uniform phase frequency divider includes 2 n-1 serially connected resampling frequency division units; each resampling frequency division unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first flip-flop, and a second flip-flop; wherein, the first flip-flop and the second flip-flop are D flip-flops.

4. The automatic frequency calibration device according to claim 3, wherein: Among them, for the m-th resampling frequency division unit in the resampling uniform phase frequency divider, where m = 1, 2,... 2 n-1 : The two differential output signals generated by the prescaler include a first differential output signal and a second differential output signal; When m is odd, the positive enable terminal of the first inverter and the positive enable terminal of the second inverter receive the second differential output signal, and the negative enable terminal of the first inverter and the negative enable terminal of the second inverter receive the first differential output signal; When m is even, the positive enable terminal of the first inverter and the positive enable terminal of the second inverter receive the first differential output signal, and the negative enable terminal of the first inverter and the negative enable terminal of the second inverter receive the second differential output signal; The output terminal of the first inverter is connected to the data input terminal of the first flip-flop and the input terminal of the fourth inverter; the output terminal of the second inverter is connected to the data input terminal of the second flip-flop and the input terminal of the third inverter; the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the input terminal of the third inverter; The clock input terminals of the first flip-flop and the second flip-flop receive the output signal of the voltage-controlled oscillator; the output terminal of the first flip-flop outputs the first output clock signal of the m-th resampling frequency division unit , and the output terminal of the second flip-flop outputs the second output clock signal of the m-th resampling frequency division unit , where m = 1, 2,... 2 n-1 , and n is an integer greater than or equal to 2; The output terminal of the first inverter of the m-th resampling frequency division unit is connected to the input terminal of the second inverter of the next resampling frequency division unit in series therewith, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2 n-1 -1; the output terminal of the second inverter of the m-th resampling frequency division unit is connected to the input terminal of the first inverter of the next resampling frequency division unit in series therewith, i.e., the (m + 1)-th resampling frequency division unit, where m = 1, 2,... 2 n-1 -1; When m = 2 n-1 , that is, the output terminal of the first inverter of the second resampling frequency division unit is connected to the input terminal of the first inverter of the first resampling frequency division unit, and the output terminal of the second inverter of the second resampling frequency division unit is connected to the input terminal of the second inverter of the first resampling frequency division unit. n-1 When it comes to the second n-1 resampling frequency division unit, the output of the first inverter is connected to the input of the first inverter of the first resampling frequency division unit, and the output of the second inverter of the second resampling frequency division unit is connected to the input of the second inverter of the first resampling frequency division unit.

5. The automatic frequency calibration device according to claim 1, wherein: The automatic frequency calibration device further includes a counting clock controller; the counting clock controller receives a reference clock signal; the counting clock controller generates a control signal according to the reference clock signal and sends it to the frequency error detector connected thereto, and the control signal is used to control the counter, accumulator, and counting comparator to perform counting, accumulation, and comparison processes respectively.

6. The automatic frequency calibration device according to claim 1, wherein: Among them, The finite state machine includes a search unit, a minimum error code search unit, and an output code selection unit; the search unit is connected to the output code selection unit; the minimum error code search unit is connected to the output code selection unit; The search unit receives the sign bit of the counting difference; the search unit determines the sub-band movement search direction of the voltage-controlled oscillator according to the sign bit of the counting difference; The minimum error code search unit receives the absolute value of the counting difference; the minimum error code search unit stores the minimum frequency error value, and the minimum error code search unit compares the absolute value of the counting difference it receives with the currently stored minimum error value. When the absolute value of the received counting difference is less than the currently stored minimum error value, the minimum frequency error search unit updates and stores the absolute value of the counting difference as the current minimum frequency error value, and at the same time updates the corresponding capacitance array code, and the capacitance array code corresponds to the sub-band number of the voltage-controlled oscillator; The minimum error code search unit always saves the capacitor array code with the minimum frequency error value during the search process until the search ends; after the search ends, the output code selection unit transfers the capacitor array code corresponding to the minimum frequency error value stored in the minimum error code search unit to the capacitor array of the voltage-controlled oscillator.

7. The automatic frequency calibration device according to claim 6, wherein Among them, the search unit determines the sub-band moving search direction of the voltage-controlled oscillator according to the sign bit of the count difference, specifically including: when the sign bit of the count difference is negative, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of higher frequency; when the sign bit of the count difference is positive, the search unit instructs the sub-band of the voltage-controlled oscillator to move and search in the direction of lower frequency.

8. The automatic frequency calibration device according to claim 6, wherein the finite state machine uses a binary search algorithm to search for the minimum frequency error value and the corresponding capacitor array code.

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