Processor random instruction verification method, device, electronic device and storage medium

Abstract

The present disclosure provides a random instruction verification method, device, electronic device and storage medium for a processor, which relates to the field of computer technology, and specifically to the field of artificial intelligence technology such as natural language processing and deep learning. The specific implementation plan is: generate a random instruction verification file set, the random instruction verification file set includes a random instruction stream file, a register stack initialization file of the processor and a data memory initialization file of the processor; perform simulation operation according to the random instruction stream file, the register stack initialization file and the data memory initialization file, generate simulation operation data and simulation operation results; if the simulation operation result meets the preset conditions, run the random instruction stream file through the processor and according to the register stack initialization file and the data memory initialization file, generate operation data; verify the random instruction stream file according to the operation data and the simulated operation data. In this way, the efficiency and accuracy of random instruction verification of the processor can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, specifically to the field of artificial intelligence technology such as natural language processing and deep learning, and in particular to a random instruction verification method, device, electronic device and storage medium for a processor. Background Art

[0002] Today, AI processors are designed to be increasingly complex to meet the almost stringent requirements of AI models and algorithms for accuracy and performance. The increase in chip scale and process has led to a multiple increase in R&D and tape-out costs, and very high requirements for chip quality, requiring complete and accurate verification strategies and methods.

[0003] In related technologies, verification methods for AI processors usually include instruction function-oriented testing, instruction consistency testing, benchmark testing, large-scale software testing, and random verification that relies on the tool chain. Summary of the invention

[0004] The present disclosure provides a random instruction verification method, device, electronic device and storage medium for a processor.

[0005] According to one aspect of the present disclosure, a random instruction verification method for a processor is provided, comprising:

[0006] Generate a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a register file initialization file of a processor, and a data memory initialization file of the processor;

[0007] Perform simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results;

[0008] If the simulation operation result meets the preset condition, the random instruction stream file is executed by the processor according to the register file initialization file and the data memory initialization file to generate operation data; and

[0009] The random instruction stream file is verified according to the operation data and the simulated operation data.

[0010] According to another aspect of the present disclosure, a random instruction verification device for a processor is provided, comprising:

[0011] A generating module, used for generating a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a register stack initialization file of a processor, and a data memory initialization file of the processor;

[0012] A simulation operation module, used for performing simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results;

[0013] an operation module, configured to, if the simulation operation result satisfies a preset condition, execute the random instruction stream file through the processor and according to the register file initialization file and the data memory initialization file to generate operation data; and

[0014] A verification module is used to verify the random instruction stream file according to the operation data and the simulated operation data.

[0015] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the random instruction verification method of the processor described in the above-mentioned embodiment.

[0019] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, on which a computer program is stored. The computer instructions are used to enable the computer to execute the random instruction verification method of the processor described in the above-mentioned embodiment.

[0020] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the random instruction verification method of the processor described in the above-mentioned first embodiment is implemented.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0023] Figure 1 A flowchart of a random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0024] Figure 2A timing diagram of a random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram of an environment framework of a random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0026] Figure 4 A flowchart of another random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0027] Figure 5 A flowchart of another random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0028] Figure 6 A flowchart of another random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0029] Figure 7 A flowchart of another random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0030] Figure 8 A flowchart of another random instruction verification method for a processor provided by an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of the structure of a random instruction verification device for a processor provided by an embodiment of the present disclosure;

[0032] Fig.10 The present invention is a block diagram of an electronic device for implementing a random instruction verification method of a processor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0034] The following describes a random instruction verification method, device, and electronic device for a processor according to an embodiment of the present disclosure with reference to the accompanying drawings.

[0035] Artificial intelligence is a discipline that studies the use of computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level technical fields and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies include computer vision technology, speech recognition technology, natural language processing technology, as well as deep learning, big data processing technology, knowledge graph technology, and other major directions.

[0036] Natural language processing is an important direction in the fields of computer science and artificial intelligence. It studies various theories and methods that can achieve effective communication between humans and computers using natural language. Natural language processing is a science that integrates linguistics, computer science, and mathematics.

[0037] Deep learning is a new research direction in the field of machine learning. Deep learning is the study of the inherent laws and representation levels of sample data. The information obtained in the learning process is of great help in the interpretation of data such as text, images and sounds. Its ultimate goal is to enable machines to have analytical learning capabilities like humans and to be able to recognize data such as text, images and sounds. Deep learning is a complex machine learning algorithm that has achieved results in speech and image recognition that far exceed previous related technologies.

[0038] The random instruction verification method of the processor provided in the embodiment of the present disclosure can be executed by an electronic device, and the electronic device can be a PC (Personal Computer), a tablet computer, a server, etc., without any limitation here.

[0039] In the embodiment of the present disclosure, a processing component, a storage component and a drive component may be provided in the electronic device. Optionally, the drive component and the processing component may be integrated, the storage component may store an operating system, an application program or other program modules, and the processing component implements the random instruction verification method of the processor provided in the embodiment of the present disclosure by executing the application program stored in the storage component.

[0040] Figure 1 A flowchart of a random instruction verification method for a processor provided in an embodiment of the present disclosure is provided.

[0041] The random instruction verification method of the processor of the embodiment of the present disclosure can also be executed by the random instruction verification device of the processor provided by the embodiment of the present disclosure. The device can be configured in an electronic device to generate a random instruction verification file set, and perform simulation operation according to the random instruction stream file, the register stack initialization file and the data storage memory initialization file to generate simulation operation data and simulation operation results. If the simulation operation result meets the preset conditions, the random instruction stream file is run by the processor and according to the register stack initialization file and the data storage memory initialization file to generate operation data, and the random instruction stream file is verified according to the operation data and the simulated operation data, thereby improving the efficiency and accuracy of the random instruction verification of the processor.

[0042] As a possible scenario, the random instruction verification method of the processor of the embodiment of the present disclosure may also be executed on the server side, and the server may be a cloud server, and the random instruction verification method of the processor may be executed on the cloud.

[0043] like Figure 1 As shown, the random instruction verification method of the processor may include:

[0044] Step 101, generating a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a processor register stack initialization file, and a processor data memory initialization file.

[0045] It should be noted that the random instruction stream file, the processor register stack initialization file and the processor data memory initialization file described in this embodiment can all be .dat (DATA) files, wherein .dat is not a standard file. Many files can use this extension, but the file meanings are different.

[0046] In the embodiments of the present disclosure, Figure 2 and Figure 3 As shown, a random instruction verification file set can be generated by a random instruction generator. It should be noted that the random instruction generator described in this embodiment can be a software program (ie, a random instruction generation program).

[0047] Specifically, see Figure 2 and Figure 3 , the electronic device can randomly select instructions from the instruction set through a built-in random instruction generator to generate a random instruction stream file, and at the same time generate a processor register stack initialization file and a data memory initialization file.

[0048] It should be noted that the instruction set described in this embodiment can be generated in advance by relevant personnel according to verification requirements, and preset in the storage space of the electronic device for use. Among them, the storage space is not limited to physical storage space, such as a hard disk, and the above storage space can also be a cloud storage space connected to a server.

[0049] For example, see Figure 3 , assuming that the above-mentioned random instruction stream file is instruction.dat, the processor register stack initialization file is reg_init.dat, the processor register stack initialization file is mem_init.dat, and the data in the random instruction stream file, the processor register stack initialization file and the processor data memory initialization file are all hexadecimal, then the specific description of instruction.dat, reg_init.dat and mem_init.dat is as follows:

[0050] ①, instruction.dat: random instruction stream file, which can be used to initialize the instruction memory. Each line in the random instruction stream file can represent 1 instruction, which can be arranged in ascending order by pointer value: 02003000

[0052] …

[0053] 7ff1111b

[0054] ②, reg_init.dat: processor register stack initialization file, each line in the register stack initialization file can represent the initialization data of a register, which can be arranged in ascending order by register number:

[0055] f323bad1

[0056] …

[0057] 23dc0ab8

[0058] ③, mem_init.dat: the processor's data memory initialization file. Each line of data in the data memory initialization file can represent the initialization data of a row of memory and can be arranged in ascending order according to the memory address:

[0059] 1030f0bc

[0060] …

[0061] 049a0dc1

[0062] Step 102, perform simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results. It should be noted that the simulation operation described in this embodiment can be completed based on the program.

[0063] In the disclosed embodiment, a simulation operation can be performed based on a preset simulation operation strategy and according to a random instruction stream file, a register file initialization file, and a data memory initialization file to generate simulation operation data and simulation operation results. The preset simulation operation strategy can be calibrated according to actual conditions, and the preset simulation operation strategy can be preset in the storage space of the electronic device for easy call when used.

[0064] Specifically, after generating a random instruction verification file set, the electronic device can call out a preset simulation operation strategy from its own storage space, and perform simulation operation based on the preset simulation operation strategy and according to the random instruction stream file, register stack initialization file and data storage initialization file to generate simulation operation data and simulation operation results.

[0065] It should be noted that the simulation operation data described in this embodiment may include the pointer value and the corresponding instruction stream file during the simulation operation (program execution), the result data file of the register stack after the simulation operation is completed, and the result data file of the data storage after the simulation operation is completed. The simulation operation result described in this embodiment may be a simulation operation success or a simulation operation failure.

[0066] For example, see Figure 3 , assuming that the data in the above random instruction stream file, the processor register stack initialization file and the processor data memory initialization file are all hexadecimal, the pointer value and the corresponding instruction stream file are instr_dump.dat, the result data file of the register stack is reg_dump.dat, and the result data file of the data memory is mem_dump.dat, then the specific descriptions of instr_dump.dat, reg_dump.dat and mem_dump.dat are as follows:

[0067] ①, instr_dump.dat, this file may include pointer values ​​and instruction streams during the simulation run. Each line in this file may represent a pointer value and a corresponding instruction, and may be arranged according to the simulation run process: 00000000:02003000

[0069] …

[0070] 000007fc:7ff1111b

[0071] ②, reg_dump.dat, this file may include the result data of the register stack after the simulation run is completed. Each line in this file may represent the data of a register and may be arranged in ascending order by register number:

[0072] 4f3eba17

[0073] …

[0074] 19efdc80

[0075] ③, mem_dump.dat, this file may include the result data of the data memory after the simulation run is completed. Each line of data in this file may represent the result data of one line of memory, and may be arranged in ascending order according to the memory address:

[0076] 429a13fc

[0077] …

[0078] b92a8d12

[0079] As a possible situation, the simulation running data described in this embodiment may also only include the result data file of the register file after the simulation running is completed and the result data file of the data memory after the simulation running is completed.

[0080] Step 103, if the simulation operation result meets the preset condition, the random instruction stream file is run by the processor according to the register file initialization file and the data memory initialization file to generate operation data. The preset condition can be calibrated according to the actual situation, for example, the preset condition can be that the simulation operation is successful.

[0081] It should be noted that the processor described in the above embodiment may be an AI processor, wherein the AI ​​processor may be an AI chip, see Figure 3 , the AI ​​chip may include registers and data memory.

[0082] In an embodiment of the present disclosure, the above-mentioned random instruction stream file, the processor's register stack initialization file and the processor's data memory initialization file can be input into the processor, so that the random instruction stream file is executed by the processor and according to the register stack initialization file and the data memory initialization file to generate operation data.

[0083] Specifically, see Figure 2After obtaining the simulation operation data and simulation operation results, the electronic device can first determine whether the simulation operation results meet the preset conditions, for example, whether the simulation operation is successful. If yes, it means that the simulation operation is successful. At this time, the electronic device can input the above-mentioned random instruction stream file, the processor's register stack initialization file, and the processor's data storage initialization file into the processor. Then the processor can sequentially execute the instructions in the random instruction stream file to generate operation data, wherein, in the process of the processor sequentially executing the instructions in the random instruction stream file, it is necessary to call the data in the register stack initialization file and the data storage initialization file.

[0084] Furthermore, participating Figure 3 After receiving the above-mentioned random instruction stream file, the processor's register stack initialization file and the processor's data memory initialization file, the processor can place the register stack initialization file into the register and the data memory initialization file into the data memory, and then execute the instructions in the random instruction stream file in sequence, and in the process of executing the instructions, call the files (data) placed in the register and the data memory to generate running data.

[0085] It should be noted that the operating data described in this embodiment may include the pointer value and corresponding instruction stream file during the processor running (program execution) instructions, the result data file of the register stack after the processor finishes running the instructions, and the result data file of the data storage device after the processor finishes running the instructions.

[0086] As a possible situation, the operation data described in this embodiment may also only include the result data file of the register file after the processor finishes running the instruction and the result data file of the data memory after the processor finishes running the instruction.

[0087] Step 104, verifying the random instruction stream file according to the operation data and the simulated operation data.

[0088] In the disclosed embodiment, the random instruction stream file can be verified based on the preset verification strategy and according to the operation data and the simulated operation data. The preset verification strategy can be calibrated according to the actual situation, and the preset verification strategy can be preset in the storage space of the electronic device for easy call when used.

[0089] Specifically, see Figure 2 and Figure 3After obtaining the above-mentioned operation data, the electronic device can call out the preset verification strategy from the storage space of the electronic device through the comparison unit, and verify the random instruction stream file based on the preset verification strategy and the operation data and the simulated operation data, thereby verifying the quality of the above-mentioned processor. The comparison unit can be set in the electronic device or in the above-mentioned processor, and no limitation is made here.

[0090] In the disclosed embodiment, a random instruction verification file set is first generated, and a simulation operation is performed according to the random instruction stream file, the register file initialization file, and the data memory initialization file to generate simulation operation data and simulation operation results. If the simulation operation result meets the preset conditions, the random instruction stream file is run by the processor according to the register file initialization file and the data memory initialization file to generate operation data, and then the random instruction stream file is verified according to the operation data and the simulation operation data. Thus, the efficiency and accuracy of the random instruction verification of the processor can be improved.

[0091] In order to clearly explain the above embodiment, in one embodiment of the present disclosure, as Figure 4 As shown, generating a random instruction verification file set may include:

[0092] Step 401, calling a random instruction generator to randomly select instructions from an instruction set to generate a random instruction stream file.

[0093] Step 402, generating a register file initialization file and a data memory initialization file according to the random instruction stream file.

[0094] Specifically, see Figure 2 and Figure 3 The electronic device can randomly select instructions from an instruction set through a built-in random instruction generator to generate a random instruction stream file, and generate a register stack initialization file and a data memory initialization file based on the random instruction stream file.

[0095] As a possible scenario, the random instruction stream file may also be processed according to the generation model to generate a register file initialization file and a data memory initialization file.

[0096] It should be noted that the generation model described in this embodiment may be trained in advance and pre-stored in the storage space of the server to facilitate retrieval and application.

[0097] The training and generation of the generation model can be performed by a related training server, which can be a cloud server or a computer host. A communication connection is established between the training server and an electronic device that can execute the random instruction verification method of the processor provided in the embodiment of the present disclosure, and the communication connection can be at least one of a wireless network connection and a wired network connection. The training server can send the trained generation model to the electronic device so that the electronic device can call it when needed, thereby greatly reducing the computing pressure of the electronic device.

[0098] Specifically, see Figure 2 and Figure 3 After the electronic device generates a random instruction stream file through a built-in random instruction generator, it can call out a generation model from its own storage space and input the random instruction stream file into the generation model, thereby processing the random instruction stream file through the generation model to obtain a register stack initialization file and a data storage initialization file output by the generation model.

[0099] As another possible situation, the electronic device may also generate a register file initialization file and a data memory initialization file according to a preset generation algorithm and a random instruction stream file, wherein the preset generation algorithm may be calibrated according to actual conditions.

[0100] Step 403, generating a random instruction verification file set according to the random instruction stream file, the register stack initialization file and the data memory initialization file.

[0101] Specifically, after obtaining the register file initialization file and the data memory initialization file, the electronic device can integrate the random instruction stream file, the register file initialization file and the data memory initialization file into a file set, namely, the random instruction verification file set, thereby providing high-quality data guarantee for the random instruction verification of the processor.

[0102] In order to clearly explain the above embodiment, in one embodiment of the present disclosure, as Figure 5 As shown, calling a random instruction generator to randomly select instructions from an instruction set to generate a random instruction stream file may include:

[0103] Step 501, calling a random instruction generator to randomly select instructions from an instruction set to generate a random instruction stream, wherein the random instruction stream includes at least one instruction sequence. It should be noted that the random instruction generator described in this embodiment can be pre-stored in the storage space of the electronic device so as to be called when used.

[0104] In the embodiment of the present disclosure, when the electronic device calls the random instruction generator to randomly select instructions from the instruction set, it can also impose corresponding constraints according to the type of the selected instructions, so that the selected instructions can be executed.

[0105] Step 502: When the length of the random instruction stream reaches a length threshold, the random instruction stream is converted into a random instruction stream file. The length threshold can be calibrated according to actual conditions, for example, the length threshold can be 100.

[0106] It should be noted that the length of the random instruction stream described in this embodiment may be the number of instructions in the random instruction stream.

[0107] Specifically, see Figure 2 and Figure 3 , the electronic device can call out a random instruction generator from its own storage space, and randomly select instructions from the instruction set through the random instruction generator, and when the number of selected instructions reaches a length threshold, generate a random instruction stream, and convert the random instruction stream into a random instruction stream file. Therefore, by limiting the number of instructions in the random instruction stream file, the efficiency and accuracy of the processor random instruction verification can be further improved.

[0108] In one embodiment of the present disclosure, Figure 6 As shown, performing simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results may include:

[0109] Step 601, obtain a simulator.

[0110] It should be noted that the simulator described in this embodiment may be a software program (ie, a simulator program), and the simulator may be pre-stored in the storage space of the electronic device to facilitate the retrieval of the application, wherein, see Figure 3 The simulator may include simulated registers and data memory to emulate the instruction execution environment of the processor.

[0111] Step 602, inputting the random instruction stream file, the register file initialization file and the data memory initialization file into the simulator.

[0112] Step 603, using a simulator and based on the register file initialization file and the data memory initialization file, simulate running the random instruction stream file to generate simulation running data and simulation running results.

[0113] Specifically, see Figure 2 and Figure 3After obtaining the random instruction verification file set, the electronic device can call out (acquire) the simulator from its own storage space, and input the random instruction stream file, the processor's register stack initialization file, and the processor's data memory initialization file in the random instruction verification file set into the simulator, and then the simulator can sequentially run the instructions in the random instruction stream file to generate simulation running data, wherein, in the process of the simulator sequentially running the instructions in the random instruction stream file, the data in the register stack initialization file and the data memory initialization file need to be called. Thus, the verification environment of the simulator and the processor is the same.

[0114] In one embodiment of the present disclosure, Figure 7 As shown, the random instruction verification method may further include:

[0115] Step 701: If the simulation running result does not meet the preset conditions, a random instruction verification file set is regenerated.

[0116] Step 702, performing simulation operation according to the regenerated random instruction verification file set to regenerate simulation operation data and simulation operation results, until the regenerated simulation operation results meet preset conditions.

[0117] Specifically, see Figure 2 When the electronic device determines that the above-mentioned simulation operation result does not meet the preset conditions, it means that the simulation operation has failed (for example, the simulation operation is stopped midway). At this time, the electronic device can call out the random instruction generator from its own storage space again, and use the random instruction generator to randomly select instructions from the instruction set to generate a random instruction stream file. Then the electronic device can perform a simulation operation according to the regenerated random instruction verification file set to regenerate the simulation operation data and simulation operation results, and continue to determine whether the simulation operation result meets the preset conditions. If not, the random instruction verification file set is regenerated again until the random instruction verification file set is regenerated. In this way, the correct simulation operation result can be obtained to ensure the accuracy of the final verification result.

[0118] In the embodiments of the present disclosure, see Figure 3 If the simulation result does not meet the preset conditions, the electronic device can first receive the debugging or modification of the simulator and / or random instruction generator by the relevant personnel through the built-in debugging tool, and then regenerate the random instruction verification file set, thereby further improving the accuracy of the random instruction verification of the processor. Among them, the debugging tool can be pre-installed in the storage space of the electronic device for easy access when in use.

[0119] In one embodiment of the present disclosure, Figure 8As shown, verifying the random instruction stream file according to the operation data and the simulated operation data may include:

[0120] Step 801 : compare the operation data with the simulated operation data to generate a comparison result.

[0121] Specifically, after obtaining the above-mentioned operation data, the electronic device can parse the operation data and the simulation operation data respectively, so as to obtain the result data file of the register stack after the processor operation instruction is completed and the result data file of the data storage device after the processor operation instruction is completed in the operation data, as well as the result data file of the register stack after the simulation operation is completed and the result data file of the data storage device after the simulation operation is completed in the simulation operation data. Then, the electronic device can compare the data in the result data file of the register stack after the processor operation instruction is completed and the result data file of the register stack after the simulation operation is completed, as well as the result data file of the data storage device after the processor operation instruction is completed and the result data file of the data storage device after the simulation operation is completed, and generate corresponding comparison results.

[0122] For example, see Figure 3 The comparison between the running data and the simulated running data can be a comparison between the reg_dump.dat file and the mem_dump.dat file output by the simulator and the reg_dump.dat file and the mem_dump.dat file output by the runner.

[0123] Step 802, verify the random instruction stream file according to the comparison result.

[0124] Specifically, after obtaining the comparison result, the electronic device can verify the random instruction stream file according to the comparison result. For example, if the comparison result shows that the running data and the simulated running data are 100% identical, it can be determined that the execution function of the random instruction of the processor is normal.

[0125] As a feasible method, in order to avoid errors caused by the operating environment, when the comparison results show that the operating data and the simulated operating data are more than 95% identical, it can be determined that the execution function of the random instructions of the processor is normal, otherwise, it can be determined that the execution function of the random instructions of the processor is abnormal.

[0126] In this way, register-level comparison can be achieved with high verification accuracy, and changes in the instruction set have little impact on the verification environment, allowing for rapid deployment.

[0127] In the embodiments of the present disclosure, see Figure 3If it is determined that the random instruction execution function of the processor is abnormal, the processor, simulator and / or random instruction generator can be debugged or modified through the above-mentioned debugging tools, and the next round of verification can be re-performed, so as to optimize the random instruction execution function of the processor in a targeted manner.

[0128] According to the random instruction verification method of the processor of the embodiment of the present disclosure, a random instruction verification file set is first generated, and a simulation operation is performed according to the random instruction stream file, the register stack initialization file and the data memory initialization file to generate simulation operation data and simulation operation results. If the simulation operation result meets the preset conditions, the random instruction stream file is run by the processor according to the register stack initialization file and the data memory initialization file to generate operation data, and then the random instruction stream file is verified according to the operation data and the simulation operation data. Thus, the efficiency and accuracy of the random instruction verification of the processor can be improved.

[0129] Fig. 9 A schematic diagram of the structure of a random instruction verification device for a processor provided in an embodiment of the present disclosure.

[0130] The random instruction verification device of the processor of the embodiment of the present disclosure can be configured in an electronic device to generate a random instruction verification file set, and perform simulation operation according to the random instruction stream file, the register stack initialization file and the data storage memory initialization file to generate simulation operation data and simulation operation results. If the simulation operation result meets the preset conditions, the random instruction stream file is run by the processor and according to the register stack initialization file and the data storage memory initialization file to generate operation data, and the random instruction stream file is verified according to the operation data and the simulated operation data, thereby improving the efficiency and accuracy of the random instruction verification of the processor.

[0131] like Fig. 9 As shown, the random instruction verification device 900 of the processor may include: a generation module 910, a simulation operation module 920, an operation module 930, and a verification module 940.

[0132] The generating module 910 is used to generate a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a processor register stack initialization file, and a processor data memory initialization file.

[0133] It should be noted that the random instruction stream file, the processor register stack initialization file and the processor data memory initialization file described in this embodiment can all be .dat (DATA) files, wherein .dat is not a standard file. Many files can use this extension, but the file meanings are different.

[0134] In the embodiment of the present disclosure, the generation module 910 can generate a random instruction verification file set by calling a random instruction generator. It should be noted that the random instruction generator described in this embodiment can be a software program (ie, a random instruction generation program).

[0135] Specifically, the generation module 910 can randomly select instructions from the instruction set by calling a random instruction generator to generate a random instruction stream file, and at the same time generate a register file initialization file and a data memory initialization file of the processor.

[0136] It should be noted that the instruction set described in this embodiment can be generated in advance by relevant personnel according to verification requirements, and preset in the storage space of the electronic device so as to be called when the generation module 910 is used. Among them, the storage space is not limited to a physical storage space, such as a hard disk, and the above storage space can also be a cloud storage space connected to a server.

[0137] For example, assuming that the random instruction stream file is instruction.dat, the processor register stack initialization file is reg_init.dat, the processor register stack initialization file is mem_init.dat, and the data in the random instruction stream file, the processor register stack initialization file and the processor data memory initialization file are all in hexadecimal, then the specific descriptions of instruction.dat, reg_init.dat and mem_init.dat are as follows:

[0138] ①, instruction.dat: random instruction stream file, which can be used to initialize the instruction memory. Each line in the random instruction stream file can represent 1 instruction, which can be arranged in ascending order by pointer value: 02003000

[0140] …

[0141] 7ff1111b

[0142] ②, reg_init.dat: processor register stack initialization file, each line in the register stack initialization file can represent the initialization data of a register, which can be arranged in ascending order by register number:

[0143] f323bad1

[0144] …

[0145] 23dc0ab8

[0146] ③, mem_init.dat: the processor's data memory initialization file. Each line of data in the data memory initialization file can represent the initialization data of a row of memory and can be arranged in ascending order according to the memory address:

[0147] 1030f0bc

[0148] …

[0149] 049a0dc1

[0150] The simulation operation module 920 is used to perform simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results. It should be noted that the simulation operation described in this embodiment can be completed based on the program.

[0151] In the disclosed embodiment, the simulation operation module 920 can perform simulation operation based on a preset simulation operation strategy and according to a random instruction stream file, a register file initialization file, and a data memory initialization file to generate simulation operation data and simulation operation results. Among them, the preset simulation operation strategy can be calibrated according to actual conditions, and the preset simulation operation strategy can be preset in the storage space of the electronic device so that the simulation operation module 920 can be called when used.

[0152] Specifically, after the generation module 910 generates a random instruction verification file set, the simulation operation module 920 can call out a preset simulation operation strategy from the storage space of the electronic device, and perform a simulation operation based on the preset simulation operation strategy and according to the random instruction stream file, the register stack initialization file and the data storage initialization file to generate simulation operation data and simulation operation results.

[0153] It should be noted that the simulation operation data described in this embodiment may include the pointer value and the corresponding instruction stream file during the simulation operation (program execution), the result data file of the register stack after the simulation operation is completed, and the result data file of the data storage after the simulation operation is completed. The simulation operation result described in this embodiment may be a simulation operation success or a simulation operation failure.

[0154] For example, assuming that the data in the above-mentioned random instruction stream file, the processor register stack initialization file and the processor data memory initialization file are all in hexadecimal, the pointer value and the corresponding instruction stream file are instr_dump.dat, the result data file of the register stack is reg_dump.dat, and the result data file of the data memory is mem_dump.dat, then the specific descriptions of instr_dump.dat, reg_dump.dat and mem_dump.dat are as follows:

[0155] ①, instr_dump.dat, this file may include pointer values ​​and instruction streams during the simulation run. Each line in this file may represent a pointer value and a corresponding instruction, and may be arranged according to the simulation run process: 00000000:02003000

[0157] …

[0158] 000007fc:7ff1111b

[0159] ②, reg_dump.dat, this file may include the result data of the register stack after the simulation run is completed. Each line in this file may represent the data of a register and may be arranged in ascending order by register number:

[0160] 4f3eba17

[0161] …

[0162] 19efdc80

[0163] ③, mem_dump.dat, this file may include the result data of the data memory after the simulation run is completed. Each line of data in this file may represent the result data of one line of memory, and may be arranged in ascending order according to the memory address:

[0164] 429a13fc

[0165] …

[0166] b92a8d12

[0167] As a possible situation, the simulation running data described in this embodiment may also only include the result data file of the register file after the simulation running is completed and the result data file of the data memory after the simulation running is completed.

[0168] The operation module 930 is used to run the random instruction stream file through the processor and according to the register file initialization file and the data memory initialization file to generate operation data if the simulation operation result meets the preset condition. Among them, the preset condition can be calibrated according to the actual situation, for example, the preset condition can be that the simulation operation is successful.

[0169] It should be noted that the processor described in this embodiment may be an AI processor.

[0170] In an embodiment of the present disclosure, the operation module 930 can input the above-mentioned random instruction stream file, the processor's register stack initialization file and the processor's data memory initialization file into the processor, thereby running the random instruction stream file through the processor and according to the register stack initialization file and the data memory initialization file to generate operation data.

[0171] Specifically, after the simulation operation module 920 obtains the simulation operation data and the simulation operation result, the operation module 930 may first determine whether the simulation operation result meets the preset conditions, for example, whether the simulation operation is successful. If yes, it means that the simulation operation is successful. At this time, the operation module 930 may input the above-mentioned random instruction stream file, the processor's register stack initialization file, and the processor's data storage initialization file into the processor. Then the processor may sequentially execute the instructions in the random instruction stream file to generate operation data, wherein, in the process of the processor sequentially executing the instructions in the random instruction stream file, the data in the register stack initialization file and the data storage initialization file need to be called.

[0172] It should be noted that the operating data described in this embodiment may include the pointer value and corresponding instruction stream file during the processor running (program execution) instructions, the result data file of the register stack after the processor finishes running the instructions, and the result data file of the data storage device after the processor finishes running the instructions.

[0173] As a possible situation, the operation data described in this embodiment may also only include the result data file of the register file after the processor finishes running the instruction and the result data file of the data memory after the processor finishes running the instruction.

[0174] The verification module 940 is used to verify the random instruction stream file according to the operation data and the simulated operation data.

[0175] In the disclosed embodiment, the verification module 940 can verify the random instruction stream file based on the preset verification strategy and the operation data and the simulated operation data. The preset verification strategy can be calibrated according to the actual situation, and the preset verification strategy can be preset in the storage space of the electronic device so that the verification module 940 can be called when in use.

[0176] Specifically, after the operation module 930 obtains the above-mentioned operation data, the verification module 940 can call out a preset verification strategy from the storage space of the electronic device through the comparison unit, and verify the random instruction stream file based on the preset verification strategy and the operation data and the simulated operation data, thereby verifying the quality of the above-mentioned processor. Among them, the comparison unit can be set in the electronic device, and can also be set in the above-mentioned processor, which is not limited here.

[0177] In the disclosed embodiment, a random instruction verification file set is generated by a generation module, and a simulation operation is performed according to a random instruction stream file, a register file initialization file, and a data memory initialization file through a simulation operation module to generate simulation operation data and simulation operation results. If the simulation operation result meets a preset condition, the operation module is made to run the random instruction stream file through a processor and according to the register file initialization file and the data memory initialization file to generate operation data, and then the random instruction stream file is verified according to the operation data and the simulation operation data through a verification module. Thus, the efficiency and accuracy of random instruction verification of the processor can be improved.

[0178] In one embodiment of the present disclosure, Fig. 9 As shown, the generating module 910 may include: a first generating unit 911 , a second generating unit 912 and a third generating unit 913 .

[0179] Among them, the first generating unit 911 is used to call the random instruction generator to randomly select instructions from the instruction set to generate a random instruction stream file.

[0180] The second generating unit 912 is used to generate a register file initialization file and a data memory initialization file according to the random instruction stream file.

[0181] The third generating unit 913 is used to generate a random instruction verification file set according to the random instruction stream file, the register stack initialization file and the data memory initialization file.

[0182] In one embodiment of the present disclosure, the first generation unit 911 is specifically used to: call a random instruction generator to randomly select instructions from an instruction set to generate a random instruction stream, wherein the random instruction stream includes at least one instruction sequence; when the length of the random instruction stream reaches a length threshold, convert the random instruction stream into a random instruction stream file.

[0183] In one embodiment of the present disclosure, the simulation operation module 920 is specifically used to: obtain a simulator; input a random instruction stream file, a register stack initialization file, and a data memory initialization file into the simulator; and simulate the operation of the random instruction stream file through the simulator and according to the register stack initialization file and the data memory initialization file to generate simulation operation data and simulation operation results.

[0184] In one embodiment of the present disclosure, the operation module 930 is also used to: regenerate a random instruction verification file set if the simulation operation result does not meet the preset conditions; perform a simulation operation according to the regenerated random instruction verification file set to regenerate the simulation operation data and the simulation operation result until the regenerated simulation operation result meets the preset conditions.

[0185] In one embodiment of the present disclosure, the verification module 940 is specifically used to: compare the running data with the simulated running data to generate a comparison result; and verify the random instruction stream file according to the comparison result.

[0186] It should be noted that the above explanation of the embodiment of the random instruction verification method for a processor is also applicable to the random instruction verification device for the processor of this embodiment, and will not be repeated here.

[0187] The random instruction verification device of the processor of the embodiment of the present disclosure generates a random instruction verification file set through a generation module, and performs simulation operation according to the random instruction stream file, the register stack initialization file and the data memory initialization file through a simulation operation module to generate simulation operation data and simulation operation results. If the simulation operation result meets the preset conditions, the operation module runs the random instruction stream file through the processor and according to the register stack initialization file and the data memory initialization file to generate operation data, and then verifies the random instruction stream file according to the operation data and the simulation operation data through the verification module. In this way, the efficiency and accuracy of the random instruction verification of the processor can be improved.

[0188] In the technical solution disclosed herein, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0189] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0190] Fig.10 A schematic block diagram of an example electronic device 1000 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0191] like Fig.10As shown, the device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1002 or a computer program loaded from a storage unit 1006 to a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0192] A number of components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006 such as a keyboard, a mouse, etc.; an output unit 1007 such as various types of displays, speakers, etc.; a storage unit 1008 such as a disk, an optical disk, etc.; and a communication unit 1009 such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0193] The computing unit 1001 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1001 performs the various methods and processes described above, such as the random instruction verification method of the processor. For example, in some embodiments, the random instruction verification method of the processor may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 1006. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded into the RAM 1003 and executed by the computing unit 1001, one or more steps of the random instruction verification method of the processor described above may be executed. Alternatively, in other embodiments, the computing unit 1001 may be configured to execute the random instruction verification method of the processor in any other appropriate manner (eg, by means of firmware).

[0194] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0195] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0196] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0197] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0198] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

[0199] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0200] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in the disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in the disclosure can be achieved, and this document does not limit them here.

[0201] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A random instruction verification method for a processor, comprising: Generate a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a register file initialization file of a processor, and a data memory initialization file of the processor; Perform simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results; If the simulation operation result meets the preset condition, the random instruction stream file is executed by the processor according to the register file initialization file and the data memory initialization file to generate operation data; and Verifying the random instruction stream file according to the operation data and the simulated operation data; The method further comprises: If the simulation operation result does not meet the preset condition, regenerate the random instruction verification file set; A simulation run is performed according to the regenerated random instruction verification file set to regenerate the simulation run data and the simulation run result, until the regenerated simulation run result meets the preset condition.

2. The method according to claim 1, wherein: The generating of the random instruction verification file set includes: Calling a random instruction generator to randomly select instructions from an instruction set to generate the random instruction stream file; Generate the register file initialization file and the data memory initialization file according to the random instruction stream file; The random instruction verification file set is generated according to the random instruction stream file, the register file initialization file and the data memory initialization file.

3. The method according to claim 2, wherein: The calling random instruction generator randomly selects instructions from the instruction set to generate the random instruction stream file, including: calling the random instruction generator to randomly select instructions from the instruction set to generate a random instruction stream, wherein the random instruction stream includes at least one instruction sequence; When the length of the random instruction stream reaches a length threshold, the random instruction stream is converted into the random instruction stream file.

4. The method according to claim 1, wherein: The performing simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results includes: Get the simulator; inputting the random instruction stream file, the register file initialization file and the data memory initialization file into the simulator; The simulator is used to simulate and run the random instruction stream file according to the register file initialization file and the data memory initialization file to generate the simulation running data and the simulation running result.

5. The method according to claim 1, wherein: The verifying the random instruction stream file according to the operation data and the simulated operation data includes: Comparing the operation data with the simulated operation data to generate a comparison result; The random instruction stream file is verified according to the comparison result.

6. A random instruction verification device for a processor, comprising: A generating module, used for generating a random instruction verification file set, wherein the random instruction verification file set includes a random instruction stream file, a register stack initialization file of a processor, and a data memory initialization file of the processor; A simulation operation module, used for performing simulation operation according to the random instruction stream file, the register file initialization file and the data memory initialization file to generate simulation operation data and simulation operation results; an operation module, configured to, if the simulation operation result satisfies a preset condition, execute the random instruction stream file through the processor and according to the register file initialization file and the data memory initialization file to generate operation data; and A verification module, used for verifying the random instruction stream file according to the operation data and the simulated operation data; Wherein, the operation module is also used for: If the simulation operation result does not meet the preset condition, regenerate the random instruction verification file set; A simulation run is performed according to the regenerated random instruction verification file set to regenerate the simulation run data and the simulation run result, until the regenerated simulation run result meets the preset condition.

7. The device according to claim 6, wherein: The generating module comprises: A first generating unit, used for calling a random instruction generator to randomly select instructions from an instruction set to generate the random instruction stream file; A second generating unit, configured to generate the register file initialization file and the data memory initialization file according to the random instruction stream file; The third generating unit is used to generate the random instruction verification file set according to the random instruction stream file, the register stack initialization file and the data storage initialization file.

8. The device according to claim 7, wherein: The first generating unit is specifically configured to: calling the random instruction generator to randomly select instructions from the instruction set to generate a random instruction stream, wherein the random instruction stream includes at least one instruction sequence; When the length of the random instruction stream reaches a length threshold, the random instruction stream is converted into the random instruction stream file.

9. The device according to claim 6, wherein: The simulation operation module is specifically used for: Get the simulator; inputting the random instruction stream file, the register file initialization file and the data memory initialization file into the simulator; The random instruction stream file is simulated and run through the simulator according to the register file initialization file and the data memory initialization file to generate the simulation running data and the simulation running result.

10. The device according to claim 6, wherein: The verification module is specifically used for: Comparing the operation data with the simulated operation data to generate a comparison result; The random instruction stream file is verified according to the comparison result.

11. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the random instruction verification method of the processor according to any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the random instruction verification method for a processor according to any one of claims 1 to 5.

13. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the random instruction verification method for a processor according to any one of claims 1 to 5.

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