Optoelectronic component

Abstract

The present invention discloses an optoelectronic device, comprising a semiconductor stack including a first semiconductor layer, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer; a current blocking region formed on the second semiconductor layer and including a first pad portion; a first opening formed in the first pad portion; a transparent conductive layer formed on the current blocking region and on the surface of the semiconductor stack, and the transparent conductive layer includes a second opening exposing the first opening; and a first electrode formed on the transparent conductive layer, including a first pad electrode located on the first pad portion; wherein the first pad electrode contacts the second semiconductor layer through the first opening and the second opening, wherein the width of the first pad electrode is smaller than the width of the second opening, and the first pad electrode contacts the first pad portion but does not contact the transparent conductive layer.

Description

[0001] This application is a divisional application of a Chinese invention patent application (Application No.: 201810144931.7, Application Date: February 12, 2018, Invention Title: Optoelectronic Element). Technical Field

[0002] The present invention relates to an optoelectronic element, and more particularly, to a light-emitting element having uniform current diffusion and improved brightness. Background Art

[0003] Light-emitting diodes (LEDs) in solid-state light-emitting elements have good optoelectronic characteristics such as low power consumption, low heat generation, long lifespan, shock resistance, small size, fast response speed, and stable emission wavelength, so they have been widely used in household devices, indicator lights, and optoelectronic products, etc. With the development of optoelectronic technology, solid-state light-emitting elements have made considerable progress in luminous efficiency, operating lifespan, and brightness. Light-emitting diodes are expected to become the mainstream of future lighting devices.

[0004] Existing light-emitting diodes include a substrate, an n-type semiconductor layer formed on the substrate, an active layer, and a p-type semiconductor layer, as well as p and n electrodes respectively formed on the p-type / n-type semiconductor layers. When a specific value of operating voltage is input to the light-emitting diode via the electrodes, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer combine in the active layer to emit light. Improving the brightness and operating voltage are important issues for light-emitting diodes. Summary of the Invention

[0005] To solve the above problems, the present invention provides an optoelectronic element, including a semiconductor stack including a first semiconductor layer, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer; a current blocking region formed on the second semiconductor layer and including a first pad portion; a first opening formed in the first pad portion; a transparent conductive layer formed on the current blocking region and on the surface of the semiconductor stack, and the transparent conductive layer includes a second opening exposing the first opening; and a first electrode formed on the transparent conductive layer, including a first pad electrode located on the first pad portion; wherein the first pad electrode contacts the second semiconductor layer through the first opening and the second opening, wherein the width of the first pad electrode is smaller than the width of the second opening, and the first pad electrode contacts the first pad portion but does not contact the transparent conductive layer. Description of the Drawings

[0006] Figures 1A to 1C Optoelectronic element diagram of an embodiment of the present invention;

[0007] Figures 2A to 2H Top views of different embodiments of the present invention, viewing the current blocking region through the openings of the transparent conductive layer;

[0008] Figures 3A to 3E Partial cross-sectional views of the current blocking region and the transparent conductive layer of different embodiments of the present invention;

[0009] Figure 4 Top view of an optoelectronic element according to an embodiment of the present invention;

[0010] Figure 5 Top view of an optoelectronic element according to an embodiment of the present invention;

[0011] Figure 6 A table, which is a test data graph of two optoelectronic elements of the embodiments of the present invention and an optoelectronic element as a control example;

[0012] Figure 7 Optoelectronic device diagram according to an embodiment of the present invention; and

[0013] Figure 8 Optoelectronic device diagram according to an embodiment of the present invention.

[0014] Symbol description

[0015] 1, 2, 3 Optoelectronic elements

[0016] 4, 5 Light-emitting devices

[0017] 10 Substrate

[0018] 12 Semiconductor stack

[0019] 121 First semiconductor layer

[0020] 122 Second semiconductor layer

[0021] 123 Active layer

[0022] 14 Second electrode

[0023] 141 Second pad electrode

[0024] 142 Second finger electrode

[0025] 16 First electrode

[0026] 161 First pad electrode

[0027] 162 First finger electrode

[0028] 20 Protective layer

[0029] 201, 202 Openings

[0030] 21 Current blocking region

[0031] 211 First pad portion

[0032] 212 First finger-like part

[0033] 2120 Opening

[0034] 2120A, 2120B, 2120C, 2120D Opening branches

[0035] 2120E Opening area

[0036] 213 Second cushion part

[0037] 214 Second finger-like part

[0038] 2141 Island

[0039] 22 Transparent conductive layer

[0040] 220 Opening

[0041] 41 Carrier

[0042] 411 First conductive pad

[0043] 412 Second conductive pad

[0044] 43 Insulating part

[0045] 44 Reflective structure

[0046] 502 Lamp housing

[0047] 504 Reflector

[0048] 506 Bearing part

[0049] 508 Light-emitting unit

[0050] 510 Light-emitting module

[0051] 512 Lamp socket

[0052] 514 Radiator

[0053] 516 Connecting part

[0054] 518 Electrical connection component

[0055] A1, A2 Area

[0056] A3 Total area

[0057] d Width

[0058] Po Power

[0059] Vf Operating voltage

[0060] W1, W2, W4 Width

[0061] W3 Outer edge width Detailed Embodiments

[0062] For a better and more concise explanation of the present invention, once a name or element symbol has been defined anywhere in the present invention, the same name or the same element symbol given or appearing in different paragraphs of the specification or in the drawings shall have the same or equivalent meaning.

[0063] Throughout the description, the substrate of the present invention is considered to be placed horizontally. A thin film stack is formed on the substrate. The expressions "upper" and "lower", "above" and "below", or "lower" and "upper" shall be construed in terms of this placement direction. Unless otherwise specified, the expressions "upper" and "lower", "above" and "below" do not necessarily mean that the upper and lower layers are in direct contact with each other. In addition, the expression "layer" means a region of material having a thickness and its composition is used to provide the desired properties. Unless otherwise specified, the expression "layer" may mean a single layer or include multiple sub-layers.

[0064] Although the optoelectronic element disclosed in the present invention includes a light emitting diode. Optoelectronic elements such as laser diodes, solar cells, light sensors, etc. are also within the scope of the present invention. The following embodiments, either alone or in combination, are within the scope of the present invention. The embodiments of the present invention will be described below with reference to the drawings.

[0065] Figure 1A FIG. is a top view of an optoelectronic element 1 according to a first embodiment of the present invention. Figure 1B is Figure 1A a cross-sectional view of the optoelectronic element 1 taken along line A-A'.

[0066] Referring to Figure 1A and Figure 1B , the optoelectronic element 1 includes a substrate 10, a semiconductor stack 12 on the substrate 10, a current blocking region 21 on the semiconductor stack 12, a transparent conductive layer 22 on the semiconductor stack 12, a first electrode 16, a second electrode 14, and a protective layer 20. The second electrode 14 includes a second pad electrode 141 and a second finger electrode 142 extending from the second pad electrode 141. The first electrode 16 includes a first pad electrode 161 and two first finger electrodes 162 extending from the first pad electrode 161. The protective layer 20 includes openings 201 and 202 to expose the second pad electrode 141 and the first pad electrode 161. The number of finger electrodes of the first electrode 16 and the second electrode 14 is not limited to the above, and can be designed according to the characteristics of the optoelectronic element, such as the size of the optoelectronic element, the quality of the semiconductor stack, and its optoelectronic characteristics, such as brightness or current diffusion.

[0067] In Figure 1AIn the top view shown, the second finger electrode 142 extends from the second pad electrode 141 towards the first pad electrode 161. In one embodiment, the second finger electrode 142 extends along a direction of a short side of the optoelectronic element 1 towards the opposite side of the second pad electrode 141. In one embodiment, the second finger electrode 142 is parallel to a long side of the optoelectronic element 1. The first finger electrode 162 extends from the first pad electrode 161 towards the second pad electrode 141. In one embodiment, the first finger electrode 162 extends along a direction of the other short side of the optoelectronic element 1 towards the opposite side of the first pad electrode 161. In one embodiment, the first finger electrode 162 is parallel to the long side of the optoelectronic element 1. In the present embodiment, the second electrode 14 and the first electrode 16 are formed on the same side of the substrate 10. In another embodiment, the second electrode 14 and the first electrode 16 may be formed on opposite sides of the substrate 10, and the current blocking region 21 may be formed correspondingly under the second electrode 14 and the first electrode 16.

[0068] Referring to Figure 1B , the substrate 10 may be a growth substrate, which includes a gallium arsenide (GaAs) substrate, a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate for growing aluminum gallium indium phosphide (AlGaInP), or an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 may be a patterned substrate, that is, an upper surface of the substrate 10 for epitaxially growing the semiconductor stack 12 may include a patterned structure. The light emitted from the semiconductor stack 12 can be refracted through the patterned structure of the substrate 10, thereby increasing the brightness of the optoelectronic element. In addition, the patterned structure slows down or suppresses the dislocation caused by the lattice mismatch between the substrate 10 and the semiconductor stack 12, thereby improving the epitaxial quality of the semiconductor stack 12.

[0069] In one embodiment of the present invention, the semiconductor stack 12 may be formed on the substrate 10 by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0070] The semiconductor stack 12 includes a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122 that are sequentially formed on a substrate 10. In an embodiment of the present invention, the first semiconductor layer 121 and the second semiconductor layer 122, such as a cladding layer or a confinement layer, have different conduction types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. The active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Under current drive, electrons and holes combine in the active layer 123 to convert electrical energy into light energy to emit light. The wavelength of the light emitted by the optoelectronic element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical compositions of one or more layers in the semiconductor stack 12.

[0071] The material of the semiconductor stack 12 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P of group III-V semiconductor materials, where 0 ≤ x, y ≤ 1; (x + y) ≤ 1. According to the material of the active layer 123, when the material of the semiconductor stack 12 is of the AlInGaP series, red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack 12 is of the InGaN series, blue light or deep blue light with a wavelength between 400 nm and 490 nm, or green light with a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack 12 is of the AlGaN series, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 123 can be an i-type, p-type, or n-type semiconductor.

[0072] In addition, before forming the semiconductor stack 12, a buffer layer (not shown) may be formed on the upper surface of the substrate 10. The buffer layer can also reduce the above-mentioned lattice mismatch and suppress dislocations, thereby improving the epitaxial quality. The material of the buffer layer includes GaN, AlGaN or AlN. In one embodiment, the buffer layer includes a plurality of sub-layers (not shown). These sub-layers include the same material or different materials. In one embodiment, the buffer layer includes two sub-layers. These two sub-layers include the same material AlN. The growth mode of the first sub-layer is sputtering, while the growth mode of the second sub-layer is MOCVD. In one embodiment, the buffer layer further includes a third sub-layer. The growth mode of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is higher or lower than that of the third sub-layer.

[0073] As Figure 1B shown, an exposed area is formed by etching downward and removing a part of the second semiconductor layer 122 and the active layer 123 until an upper surface of the first semiconductor layer 121 is exposed. At the exposed area, the sidewalls of the second semiconductor layer 122 and the active layer 123 and the upper surface of the first semiconductor layer 121 are exposed. The second electrode 14 is disposed on the exposed upper surface of the first semiconductor layer 121 and forms an electrical connection with the first semiconductor layer 121. The first electrode 16 is disposed on the second semiconductor layer 122 and forms an electrical connection with the second semiconductor layer 122.

[0074] The materials of the second pad electrode 141, the second finger electrode 142, the first pad electrode 161 and the first finger electrode 162 are selected from metals such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), rhodium (Rh), alloys or laminates of the above materials.

[0075] A current blocking region 21 is correspondingly formed under the second electrode 14 and the first electrode 16 and above the first semiconductor layer 121 and the second semiconductor layer 122. In this embodiment, the current blocking region 21 includes a first pad portion 211, a first finger portion 212, a second pad portion 213, and a second finger portion 214. The second pad portion 213 and the second finger portion 214 are correspondingly and respectively formed under the second pad electrode 141 and the second finger electrode 142 and above the first semiconductor layer 121. The first pad portion 211 and the first finger portion 212 are correspondingly and respectively formed under the first pad electrode 161 and the first finger electrode 162 and above the second semiconductor layer 122. When current (electrons or holes) is injected into the optoelectronic device 1 through the second pad electrode 141 and the first pad electrode 161, the current spreads out through the second finger electrode 142 and the first finger electrode 162, and then flows into the first semiconductor layer 121 and the second semiconductor layer 122. The current blocking region 21 prevents most of the current from directly flowing into the active layer 123 under the electrodes, thereby avoiding the current congestion problem.

[0076] In this embodiment, as Figure 1A with 1B shown, the first pad portion 211 of the current blocking region 21 is formed under the first pad electrode 161, and the first finger portion 212 of the current blocking region 21 extends from the first pad portion 211 and is formed under the first finger electrode 162. At the first pad electrode 161, part or all of the current is blocked from flowing downward through the first pad portion 211, and then the current diffuses outward through a transparent conductive layer 22 and the first finger electrode 162. At the first finger electrode 162, the current is blocked from flowing downward through the first finger portion 212. The current spreads laterally in the transparent conductive layer 22 and then uniformly flows into the second conductor layer 122. In addition, the second pad portion 213 of the current blocking region 21 is formed under the second pad electrode 141 and under the second finger electrode 142. The second finger portion 214 of the current blocking region 21 includes a plurality of separated islands 2141. The locations of the plurality of separated islands 2141 block the current diffused by the second finger electrode 142 from flowing downward. The current flows downward into the first semiconductor layer 121 through the second finger electrode 142 between two adjacent islands 2141. In the region between any two adjacent and separated islands 2141, the second finger electrode 142 contacts the first semiconductor layer 121, and a plurality of contact regions with low contact impedance are formed between the second finger electrode 142 and the first semiconductor layer 121, and the current can flow from the second finger electrode 142 into the first semiconductor layer 121 through these contact regions.

[0077] The material of the current blocking region 21 includes transparent insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide. The structure of the current blocking region 21 can be a single layer or an alternating multi-layer structure, such as a distributed Bragg reflector (DBR). The thickness range of the current blocking region 21 is from 700 to In one embodiment, the thickness range of the current blocking region 21 is from 700 to In another embodiment, the thickness range of the current blocking region 21 is from 1000 to

[0078] The transparent conductive layer 22 is formed on the surface of the current blocking region 21 and / or the second semiconductor layer 122, so that the current injected into the first electrode 16 can be evenly diffused through the transparent conductive layer 22 and then flow into the second semiconductor layer 122. Since the transparent conductive layer 22 is disposed on the light-emitting side of the optoelectronic element 1, it is more appropriate to select a conductive material with transparent properties. More specifically, the transparent conductive layer 22 can include a thin metal film or a metal oxide structure. The material of the thin metal film includes gold or nickel. The material of the metal oxide structure includes elements selected from at least metals such as zinc, indium, or tin, such as ZnO, InO, SnO, ITO (indium tin oxide), IZO (indium zinc oxide), or GZO (gallium-doped zinc oxide). The transparent conductive layer 22 has a high optical transmittance for the light emitted by the active layer 123, such as 60%, 70%, 75%, 80% or higher, and has high conductivity.

[0079] Referring to Figures 1B to 1C , Figure 1C , a partial top view of the optoelectronic element 1 according to an embodiment of the present invention, showing the first pad portion 211, the opening 2120, the transparent conductive layer 22, and the opening 220 of the current blocking region 21. The opening 2120 is formed in the first pad portion 211 to expose an upper surface of the second semiconductor layer 122. The transparent conductive layer 22 covers a part of the first pad portion 211 of the current blocking region 21 and includes the opening 220. The opening 220 corresponds to the position of the first pad electrode 161 to expose the opening 2120 formed in the first pad portion 211 and the upper surface of the second semiconductor layer 122. In one embodiment, the opening 220 may further expose a top surface of the first pad portion 211. As Figure 1CAs shown, any two of the first cushion portion 211, the opening 2120, and the opening 220 have substantially the same shape. In one embodiment, the first cushion portion 211, the opening 2120, and the opening 220 have substantially the same shape. In one embodiment, the first cushion portion 211, the opening 2120, and the opening 220 are circular in shape, and each circle has a common center, but is not limited thereto. In one embodiment, any two of the first cushion portion 211, the opening 2120, and the opening 220 have different shapes. In one embodiment, the first cushion portion 211 is rectangular in shape, while the opening 2120 and the opening 220 are circular in shape.

[0080] In one embodiment, the first pad electrode 161 is electrically connected to the upper surface of the second semiconductor layer 122 through the opening 2121, for example, by direct contact, and there is a contact area therebetween. The contact resistance of the contact area between the first pad electrode 161 and the second semiconductor layer 122 is higher than the contact resistance between the first pad electrode 161 and the transparent conductive layer 22. The contact area between the first pad electrode 161 and the second semiconductor layer 122 is a kind of blocking area between the first pad electrode 161 and the second semiconductor layer 122, for preventing or reducing the current from flowing into the second semiconductor layer 122 under the first pad electrode 161 at the opening 2120.

[0081] As Figure 1B In the cross-sectional view shown, the transparent conductive layer 22 covers the side surface and a part of the top surface of the first cushion portion 211. A width W1 of the opening 220 of the transparent conductive layer 22 is larger than a width W2 of the opening 2120 formed in the first cushion portion 211, but smaller than an outer edge width W3 of the first cushion portion 211. The outer edge width W3 is the maximum distance between the two outer edges of the first cushion portion 211 in the cross-sectional view. In this case, the opening 220 exposes a part of the first cushion portion 211. In another embodiment, the width W1 of the opening 220 of the transparent conductive layer 22 is equal to or greater than the outer edge width W3 of the first cushion portion 211 to expose the entire first cushion portion 211. When the width W1 of the opening 220 of the transparent conductive layer 22 is larger than the outer edge width W3 of the first cushion portion 211, the periphery of the opening 220 is separated from the outer edge of the first cushion portion 211. In other words, the transparent conductive layer 22 does not contact the first cushion portion 211.

[0082] The first pad electrode 161 is formed on the first cushion portion 211 of the current blocking region 21, fills the openings 2120 and 220, and then contacts the exposed upper surface of the second semiconductor layer 122. In one embodiment, the first pad electrode 161 is formed on the transparent conductive layer 22, contacts the transparent conductive layer 22 and the first cushion portion 211, and covers the openings 2120 and 220. As Figure 1BIn the cross-sectional view shown, a width W4 of the first pad electrode 161 is the maximum distance between two outer edges of the first pad electrode 161. In this embodiment, the width W4 is larger than a width W1 of the opening 220 and a width W2 of the opening 2120 formed in the first cushion portion 211, but smaller than an outer edge width W3 of the first cushion portion 211. In another embodiment, the first pad electrode 161 is formed above the opening 220, only covers the opening 2120 and is separated from the transparent conductive layer 22. The width W4 of the first pad electrode 161 is smaller than the width W1 of the opening 220 and the outer edge width W3 of the first cushion portion 211, but larger than the width W2 of the opening 2120 formed in the first cushion portion 211. In other words, the first pad electrode 161 contacts the first cushion portion 211 but does not contact the transparent conductive layer 22.

[0083] The adhesion between the first electrode 16 and the second semiconductor layer 122 is greater than the adhesion between the first electrode 16 and the current blocking region 21. The adhesion between the first electrode 16 and the current blocking region 21 is in turn greater than the adhesion between the first electrode 16 and the transparent conductive layer 22. Therefore, the adhesion between the first electrode 16 and the second semiconductor layer 122 dominates the adhesion between the first electrode 16 and the portion of the optoelectronic device 1 in contact with the first electrode 16. At the first pad electrode 161, the opening 2120 exposes the second semiconductor layer 122. The larger the area of the second semiconductor layer 122 exposed by the opening 2120, the more contact area there is between the first pad electrode 161 and the second semiconductor layer 122, and the total adhesion between the first pad electrode 161 and the portion of the optoelectronic device 1 in contact with the first pad electrode 161 increases accordingly. In this way, peeling of the first pad electrode 161 can be prevented and the reliability of the optoelectronic device 1 can be enhanced.

[0084] The current blocking region 21 can avoid current congestion, enabling the optoelectronic device 1 to obtain higher brightness and power. The area of the current blocking region 21 affects the current blocking efficiency. The current blocking region 21 can also improve the light extraction efficiency due to the refractive index difference between the semiconductor stack 12 and the current blocking region 21. However, the larger the area of the current blocking region 21 between the electrodes 14, 16 and the semiconductor stack 12, the higher the operating voltage of the optoelectronic device 1. In addition, at the first cushion portion 211, the adhesion of the first pad electrode 161 is also affected by the area of the second semiconductor layer 122 exposed by the opening 2120. Therefore, the areas of the opening 2120 and the first cushion portion 211 can be adjusted to meet the requirements of the reliability, brightness, and operating voltage of the optoelectronic device 1.

[0085] Figures 2A to 2HRespectively shown are partial top views of the first pad portion 211, the opening 2120, the transparent conductive layer 22, and the opening 220 of the optoelectronic element according to different embodiments of the present invention. In each embodiment, the opening 2120 has an elongated shape. In one embodiment, the opening 2120 is formed in and extends within the first pad portion 211 such that the first pad portion 211 is divided into several parts by the opening 2120. The outer edges of the several parts of the first pad portion 211 and the virtual edge of the opening 2120 form a contour. This virtual edge extends from the outer edge of any one of the several parts of the first pad portion 211 and connects to the outer edge of an adjacent part. This contour includes a composite shape, such as a circle or a polygon. Polygons include triangles, rectangles, etc. In one embodiment, when viewed from the top view of this composite shape, two virtual orthogonal lines respectively connecting any two opposite points on the contour of this shape intersect at a virtual point, and the distances from this virtual point to these two points on the contour are equal. This virtual point is the center of the composite shape.

[0086] As Figures 2A to 2G shown, when viewed from the top view, the shape of the opening 220 of the transparent conductive layer 22 is similar to the composite shape formed by the first pad portion 211 and the opening 2120, such as a circle or a rectangle. In one embodiment, as Figure 1A shown, the shape of the first pad electrode 161 formed on the opening 220 of the transparent conductive layer 22 is similar to the shape of the opening 220 and the composite shape formed by the first pad portion 211 and the opening 2120. The shape of the opening 220 and the composite shape formed by the first pad portion 211 and the opening 2120 are not limited to the above. In one embodiment, the shape of the opening 220, the composite shape formed by the first pad portion 211 and the opening 2120, and the shape of the first pad electrode 161 can be different. As Figure 2H shown in the embodiment, the opening 220 of the transparent conductive layer 22 is circular, the composite shape formed by the first pad portion 211 and the opening 2120 is rectangular or rectangular with rounded corners, and the shape of the first pad electrode 161 is circular. This will be described in detail below.

[0087] As Figure 2AAs shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, and 2120C to expose a surface (not shown) of the second semiconductor layer 122. Each of the opening branches 2120A, 2120B, and 2120C is elongated. One end of each of the opening branches 2120A, 2120B, and 2120C intersects at a center of the opening 220 and / or a center of a combined shape formed by the first cushion portion 211 and the opening 2120. The opening branches 2120A, 2120B, and 2120C extend from this end toward an outer edge of the first cushion portion 211 respectively. Each of the opening branches 2120A, 2120B, and 2120C has a width d. The widths d of the opening branches 2120A, 2120B, and 2120C may be equal or different. In one embodiment, each width d is less than or equal to 10 μm. Figure 3A is Figure 2A a magnified cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along line C-C' in. As Figure 2A shown, the transparent conductive layer 22 covers a portion of the first cushion portion 211, fills into the opening branches 2120A, 2120B, and / or 2120C, and has an opening 220 to expose a portion of the first cushion portion 211 and a portion of the opening branches 2120A - 2120C. In this embodiment, the other end of each of the opening branches 2120A, 2120B, and 2120C located at the virtual edge may be aligned with the outer edge of the first cushion portion 211. In other words, the opening branches 2120A, 2120B, and 2120C are not closed, and the opening branches 2120A, 2120B, and 2120C divide the first cushion portion 211 into three parts. In one embodiment, these three parts may have equal or unequal areas. The area A1 of the first cushion portion 211 is the sum of the areas of these three parts. The area A2 of the opening 2120 is the sum of the areas of the opening branches 2120A, 2120B, and 2120C. The total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. In this embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0088] As Figure 2BAs shown, the opening 2120 formed in the first cushion portion 211 is elongated. In this embodiment, when viewed from a top view, the opening 2120 is a straight groove, and this straight groove passes through the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120 to expose a surface (not shown) of the second semiconductor layer 122. In one embodiment, this straight groove does not pass through the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120. In one embodiment, the opening 2120 may have a width d less than or equal to 10 μm. Figure 3A Show Figure 2B An enlarged cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along line D-D' in the figure. As Figure 2B shown, the transparent conductive layer 22 covers a part of the first cushion portion 211, fills the opening 2120, and has an opening 220 to expose a part of the first cushion portion 211 and a part of the opening 2120. In this embodiment, the two ends of the opening 2120 located at the virtual edge can be aligned with an outer edge of the first cushion portion 211. In other words, the opening 2120 is not closed and divides the first cushion portion 211 into two parts. In this embodiment, similar to Figure 2A the description of the embodiment shown, the area A1 of the first cushion portion 211 is the sum of the areas of these two parts. The total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. The ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0089] As Figure 2C shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, 2120C, and 2120D and an opening area 2120E located at the center of the combined shape formed by the first cushion portion 211 and the opening 2120 to expose a surface (not shown) of the second semiconductor layer 122. Each opening branch 2120A, 2120B, 2120C, and 2120D is elongated. One end of each opening branch 2120A, 2120B, 2120C, and 2120D is connected to the opening area 2120E. The opening branches 2120A, 2120B, 2120C, and 2120D extend from the end connected to the opening area 2120E towards an outer edge of the first cushion portion 211 respectively. In one embodiment, each opening branch 2120A, 2120B, 2120C, and 2120D has a width d respectively. The widths d of the opening branches 2120A, 2120B, 2120C, and 2120D can be equal or different. Each width d is less than or equal to 10 μm.Figure 3B Yes Figure 2C A magnified cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along the line E-E' in the middle. As Figure 2C shown, the transparent conductive layer 22 covers a part of the first cushion portion 211 and is filled in the opening branches 2120A, 2120B, 2120C, and / or 2120D. The transparent conductive layer 22 has an opening 220, exposing a part of the first cushion portion 211, a part of the opening branches 2120A - 2120D, and the opening area 2120E. In this embodiment, at the other end of each opening branch 2120A, 2120B, 2120C, and 2120D located at the virtual edge, it can be aligned with the outer edge of the first cushion portion 211. In other words, the opening branches 2120A, 2120B, 2120C, and 2120D are not closed and divide the first cushion portion 211 into four parts. In one embodiment, these four parts can have equal areas or unequal areas. In this embodiment, similar to Figure 2A the description of the embodiment shown, the area A1 of the first cushion portion 211 is the sum of the areas of these four parts. The area A2 of the opening 2120 is the sum of the areas of the opening branches 2120A - 2120D and the opening area 2120E. The total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. The ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0090] As Figure 2DAs shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, and 2120C to expose a surface (not shown) of the second semiconductor layer 122. Each of the opening branches 2120A, 2120B, and 2120C is elongated. When viewed from a top view, one end of each of the opening branches 2120A, 2120B, and 2120C points to a center of the opening 220 and / or a center of a combined shape formed by the first cushion portion 211 and the opening 2120, but they do not intersect with each other. In other words, the opening branches 2120A, 2120B, and 2120C extend from an outer edge of the first cushion portion 211 towards the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120. In one embodiment, each of the opening branches 2120A, 2120B, and 2120C does not point to the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120. In one embodiment, each of the opening branches 2120A, 2120B, and 2120C has a width d. The widths d of the opening branches 2120A, 2120B, and 2120C may be equal or different. Each width d is less than or equal to 10 μm. In one embodiment, the opening branches 2120A, 2120B, and 2120C are symmetrically arranged in the first cushion portion 211. Figure 3C is Figure 2D an enlarged cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along line F-F' in. As Figure 2D shown, the transparent conductive layer 22 covers a part of the first cushion portion 211, fills into the opening branches 2120A, 2120B, and / or 2120C, and has an opening 220 to expose a part of the first cushion portion 211 and a part of the opening branches 2120A - 2120C. In this embodiment, the other end of each of the opening branches 2120A, 2120B, and 2120C located at the virtual edge may be aligned with the outer edge of the first cushion portion 211. In this embodiment, the area A2 of the opening 2120 is the sum of the areas of the opening branches 2120A, 2120B, and 2120C. The total area A3 is defined by a contour formed by the outer edge of the first cushion portion 211 and the virtual edge of the opening 2120. This virtual edge extends from any outer edge of the first cushion portion 211 and connects an adjacent outer edge, and the contour of the first cushion portion 211 and the opening 2120 is a combined shape. In other words, the total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. The ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0091] As Figure 2EAs shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, 2120C, and 2120D to expose a surface (not shown) of the second semiconductor layer 122. Each of the opening branches 2120A, 2120B, 2120C, and 2120D is elongated. When viewed from a top view, one end of each of the opening branches 2120A, 2120B, 2120C, and 2120D points to a center of the opening 220 and / or a center of a combined shape formed by the first cushion portion 211 and the opening 2120, but they do not intersect with each other. In other words, the opening branches 2120A, 2120B, 2120C, and 2120D extend from an outer edge of the first cushion portion 211 toward the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120. In one embodiment, each of the opening branches 2120A, 2120B, 2120C, and 2120D does not point to the center of the opening 220 and / or the center of the combined shape formed by the first cushion portion 211 and the opening 2120. In one embodiment, each of the opening branches 2120A, 2120B, 2120C, and 2120D has a width d. The widths d of the opening branches 2120A, 2120B, 2120C, and 2120D may be equal or different. Each width d is less than or equal to 10 μm. In one embodiment, the opening branches 2120A, 2120B, 2120C, and 2120D are symmetrically arranged in the first cushion portion 211. Figure 3D Show Figure 2E An enlarged cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along line G - G' in the middle. As Figure 2E shown, the transparent conductive layer 22 covers a part of the first cushion portion 211, fills into the opening branches 2120A, 2120B, 2120C, and / or 2120D, and has an opening 220 to expose a part of the first cushion portion 211 and a part of the opening branches 2120A - 2120D. In this embodiment, the other end of each of the opening branches 2120A, 2120B, 2120C, and 2120D located at the virtual edge may be aligned with the outer edge of the first cushion portion 211. In this embodiment, similar to Figure 2D the description of the embodiment shown, the area A2 of the opening 2120 is the sum of the areas of the opening branches 2120A, 2120B, 2120C, and 2120D. The total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. The ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0092] As Figure 2F And Figure 2GAs shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, and 2120C to expose a surface (not shown) of the second semiconductor layer 122. Each of the opening branches 2120A, 2120B, and 2120C is elongated. One end of each of the opening branches 2120A, 2120B, and 2120C intersects with each other at a center of the opening 220 and / or a center of a combined shape formed by the first cushion portion 211 and the opening 2120. The opening branches 2120A, 2120B, and 2120C extend from this end to an outer edge of the first cushion portion 211. As Figure 2F or Figure 2G shown, each of the opening branches 2120A, 2120B, and 2120C includes a plurality of segments, such as Figure 2F the two segments shown, Figure 2G the three segments shown, or more segments (not shown), where the plurality of segments are spaced apart from each other. In one embodiment, each of the opening branches 2120A, 2120B, and 2120C respectively has a width d. The widths d of the opening branches 2120A, 2120B, and 2120C may be equal or different. Each width d is less than or equal to 10 μm. Figure 3A is Figure 2F a magnified cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along line H-H' in Figure 2G and along line I-I' in Figure 2D shown. The transparent conductive layer 22 covers a part of the first cushion portion 211 and fills into the opening branches 2120A, 2120B, and / or 2120C. The transparent conductive layer 22 has an opening 220 to expose a part of the first cushion portion 211 and a part of the opening branches 2120A - 2120C. In this embodiment, the other end of each of the opening branches 2120A, 2120B, and 2120C located at the virtual edge may be substantially aligned with the outer edge of the first cushion portion 211. In one embodiment, the widths of the plurality of segments in each opening branch may be the same or unequal. In one embodiment, the plurality of segments in each opening branch have a gradually changing width. The gradually changing widths of the plurality of segments change along the extending direction of each of the opening branches 2120A, 2120B, and 2120C. In this embodiment, similar to the description of the embodiment

[0093] as Figure 2HAs shown, the opening 2120 formed in the first cushion portion 211 includes opening branches 2120A, 2120B, 2120C, and 2120D. Each of the opening branches 2120A, 2120B, 2120C, and 2120D has a width d. The widths d of the opening branches 2120A, 2120B, 2120C, and 2120D may be equal or different. Each width d is less than or equal to 10 μm. The first cushion portion 211 includes four parts divided by the opening branches 2120A, 2120B, 2120C, and 2120D. The outer edges of the four parts of the first cushion portion 211 and the virtual edges extending from the outer edges of the four parts of the first cushion portion 211 of the opening branches 2120A, 2120B, 2120C, and 2120D form a contour, and this contour includes a composite shape, and this composite shape may be a "quasi-rectangle". As used herein, "quasi-rectangle" means a shape that attempts to form a rectangle, for example, a rectangle or a rectangle with rounded corners. In one embodiment, the opening branches 2120A, 2120B, 2120C, and 2120D are symmetrically formed along the diagonal of the first cushion portion 211 to expose a surface of the second semiconductor layer 122 (not shown in the figure). In one embodiment, the opening branches extend along the midlines of each outer edge of the first cushion portion 211. Viewed from a top view, one end of each of the opening branches 2120A, 2120B, 2120C, and 2120D intersects at a center of the opening 220 and / or a center of a composite shape formed by the first cushion portion 211 and the opening 2120. Figure 3E Show Figure 2H An enlarged cross-sectional view of the first cushion portion 211, the transparent conductive layer 22, the opening 2120, and the opening 220 along the line J-J' in the figure. As Figure 2H shown, the transparent conductive layer 22 covers a part of the first cushion portion 211, fills into the opening branches 2120A, 2120B, 2120C, and / or 2120D, and has an opening 220 to expose a part of the first cushion portion 211 and the opening branches 2120A - 2120D. In this embodiment, the other end of each of the opening branches 2120A, 2120B, 2120C, and 2120D located at the virtual edge may be aligned with the outer edge of the first cushion portion 211. In one implementation, these four parts may have the same area or unequal areas. In this embodiment, similar to the description of the embodiment Figure 2A shown, the area A1 of the first cushion portion 211 is the sum of the areas of these four parts. The area A2 of the opening 2120 is the sum of the areas of the opening branches 2120A, 2120B, 2120C, and 2120D. The total area A3 is the sum of the area A1 of the first cushion portion 211 and the area A2 of the opening 2120. The ratio of the area A2 of the opening 2120 to the total area A3 is substantially between 1% and 80%. In one embodiment, the ratio of the area A2 of the opening 2120 to the total area A3 is between 10% and 40%.

[0094] Referring to Figure 2H , although the shape of the opening 220 of the transparent conductive layer 22 is circular, and the contour formed by the outer edge of the first cushion portion 211 and the virtual edges extending from the outer edge of the first cushion portion 211 of the opening branches 2120A, 2120B, 2120C and 2120D is quasi-rectangular, as Figures 2A to 2G shown in the opening 2120 design, such as opening branches, straight grooves, opening branches with multiple sections, etc., can also be used in the quasi-rectangular first cushion portion 211.

[0095] Figure 4 is a top view of the optoelectronic element 2 according to an embodiment of the present invention. The structure and material of each layer in the optoelectronic element 2 are similar to those described in the optoelectronic element 1, and will not be described herein again. One difference between the optoelectronic element 2 and Figure 1A the optoelectronic element 1 shown is that the current blocking region 21 includes a first cushion portion 211 and a first finger portion 212, and the first cushion portion 211 and the first finger portion 212 are separated from each other.

[0096] Figure 5 is a top view of the optoelectronic element 3 according to an embodiment of the present invention. The structure of each layer in the optoelectronic element 3 is similar to that described in the optoelectronic element 1, and will not be described herein again. The differences between the optoelectronic element 3 and the optoelectronic element 1 are the layouts of a first electrode 16, a second electrode 14, and correspondingly a current blocking region 21 formed under the first electrode 16 and the second electrode 14. The second electrode 14 includes a second pad electrode 141 and a second finger electrode 142 extending from the second pad electrode 141. The second finger electrode 142 is adjacent to a long side of the optoelectronic element 3 and extends toward a short side of the optoelectronic element 3 opposite to the second pad electrode 141. The first electrode 16 includes a first pad electrode 161 and a first finger electrode 162 extending from the first pad electrode 161. The first finger electrode 162 extends along the direction toward the other short side of the optoelectronic element 3 opposite to the first pad electrode 161 and parallel to the long side of the optoelectronic element 3. The current blocking region 21 is correspondingly formed under the first electrode 16 and the second electrode 14, and includes a first cushion portion 211 and a first finger portion 212 under the first electrode 16, and a second finger portion 214 under the second electrode 14. In this embodiment, the design and layout of the first cushion portion 211, the transparent conductive layer 22, the opening 2120 and the opening 220 of the optoelectronic element 3 are similar to those of Figure 1C the design and layout of the embodiment described. Based on the same die size, shape and structure of the optoelectronic element 3, select those with such as Figure 2CThe first pad portion 211 and the design and layout of the opening 2120 of the photoelectric element of the illustrated embodiment are compared with the photoelectric element 3 that has no opening in the first pad portion 211. The performance of these photoelectric elements is compared when these three photoelectric elements are lit at 20 mA.

[0097] Referring to Figure 6 the table shown, which respectively lists the photoelectric element 3 with the first pad portion 211 and the opening 2120 according to the Figure 1C illustrated embodiment, the photoelectric element with the first pad portion 211 and the opening 2120 according to the Figure 2COptical output power (Po), operating voltage (Vf), and push-pull force test results of the first pad portion 211 and the optoelectronic element with the opening 2120 of the illustrated embodiment and the optoelectronic element without any opening in the first pad portion 211 (which is used as a comparative example). All optoelectronic elements have the same size of 225 μm x 143 μm, and their shapes and most structures are also similar. The difference among these three optoelectronic elements lies in the first pad portion 211 and the opening 2120. The optoelectronic element labeled "Aspect I" includes the first pad portion 211 without any opening, which is used as a comparative example. The optoelectronic element labeled "Aspect II" includes the first pad portion 211 with a circular opening. The optoelectronic element labeled "Aspect III" includes the first pad portion 211 with four opening branches 2120A - 2120D and an opening area 2120E. In the optoelectronic element of Aspect I, the first pad portion 211 has no opening, so the ratio of the area A2 of the opening to the total area A3 is zero. In the optoelectronic element of Aspect II, the ratio of the area A2 of the opening 2120 to the total area A3 is 38.6%. In the optoelectronic element of Aspect III, the ratio of the area A2 of the opening 2120 to the total area A3 is 19.6%. The operating voltage of the optoelectronic element of Aspect II is lower than that of the optoelectronic element of Aspect I or Aspect III. The power of the optoelectronic element of Aspect I is higher than that of the optoelectronic element of Aspect II or Aspect III. On average, the operating voltages and powers of the optoelectronic elements of Aspect I, II, and III are similar. However, in the push-pull force test, the optoelectronic elements of Aspect II and III can pass the test, but the optoelectronic element of Aspect I cannot pass the test. It can be seen from the optical microscope photos that traces of the first bonding pad electrode 161 are observed on the first pad portion 211 of the optoelectronic elements of Aspect II and III. And the traces of the first bonding pad electrode 161 are larger than 50% of the area of the first bonding pad electrode 161. Therefore, the first pad portion 211 of the optoelectronic elements of Aspect II and III is beneficial to the adhesion of the first bonding pad electrode 161 and prevents the first bonding pad electrode 161 from peeling off from the optoelectronic element. The area of the opening 2120 affects the reliability of the optoelectronic element. The area of the first pad portion 211 affects the operating voltage and brightness. The ratio of the area A2 of the opening 2120 to the total area A3 between 1% and 80% can meet the requirements of the operating voltage and brightness and enhance the reliability of the optoelectronic element.

[0098] Figure 7An optoelectronic device 4 according to an embodiment of the present invention. Any one of the optoelectronic elements 1, 2, or 3 in the above embodiment is mounted on a first conductive pad 411 and a second conductive pad 412 of a carrier 41. The first conductive pad 411 and the second conductive pad 412 are electrically insulated from each other by an insulating portion 43 composed of an insulating material. The optoelectronic element is fixed to the carrier 41 in a flip-chip manner, and the surface of the growth substrate opposite to the first electrode 16 and the second electrode 14 faces upward as the light-emitting surface. In order to increase the light extraction efficiency of the optoelectronic device 4, a reflective structure 44 can be provided around the optoelectronic element.

[0099] Figure 8 An optoelectronic device 5 according to an embodiment of the present invention. The optoelectronic device 5 is a light bulb, which includes a lamp housing 502, a reflector 504, a light-emitting module 510, a lamp socket 512, a heat sink 514, a connecting portion 516, and an electrical connection element 518. The light-emitting module 510 includes a carrier portion 506 and a plurality of optoelectronic units 508 provided on the carrier portion 506. The plurality of optoelectronic units 508 can be any one of the optoelectronic elements or the optoelectronic device 4 in the foregoing embodiments.

[0100] Any person having ordinary knowledge in the technical field to which the present invention pertains can modify and vary the elements of the present invention without departing from the scope and spirit of the present invention. In view of the above, the present invention is intended to cover modifications and variations of the present invention as long as they fall within the scope of the claims of the invention and their equivalents.

Claims

1. An optoelectronic device, comprising: A semiconductor stack, including a first semiconductor layer, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer; A current blocking region, formed on the second semiconductor layer and including a first pad portion; A first opening, formed in the first pad portion; A transparent conductive layer, formed on the current blocking region and on the surface of the semiconductor stack, and the transparent conductive layer includes a second opening exposing the first opening; And A first electrode, formed on the transparent conductive layer, including a first pad electrode located on the first pad portion; Wherein the first pad electrode contacts the second semiconductor layer through the first opening and the second opening; Wherein the width of the first pad electrode is smaller than the width of the second opening, the first pad electrode contacts the first pad portion, but does not contact the transparent conductive layer; and Wherein the area of the first opening is A2, the total area of the first pad portion and the first opening is A3, and A2 / A3 = 1% - 80%.

2. The optoelectronic device according to claim 1, wherein the first electrode further comprises a first finger electrode, the current blocking region further comprises a first finger portion located under the first finger electrode, and the first finger portion is not connected to the first pad portion.

3. The optoelectronic device according to claim 1, wherein the area of the first opening is A2, the total area of the first pad portion and the first opening is A3, and A2 / A3 = 10% - 40%.

4. The optoelectronic device according to claim 1, wherein, Viewed from above, the outer edge of the first pad portion and the virtual edge of the first opening form a contour, and the contour includes a composite shape; The first opening further includes an opening region located at the center of the composite shape, and opening branches extending towards the outer edge of the first pad portion.

5. The optoelectronic device according to claim 1, wherein, Viewed from above, the outer edge of the first pad portion and the virtual edge of the first opening form a contour, and the contour includes a composite shape; wherein the composite shape is a polygon.

6. The optoelectronic device according to claim 1, wherein the first opening divides the first pad portion into a plurality of parts.

7. The optoelectronic device according to claim 1, wherein the first opening has an elongated shape, and the width of the elongated shape is less than or equal to 10 μm.

8. The optoelectronic device according to claim 1, further comprising a second electrode formed on the first semiconductor layer, wherein the second electrode comprises a second pad electrode and a second finger electrode; and wherein the current blocking region further comprises a second pad portion formed between the first semiconductor layer and the second electrode and a second finger portion formed between the first semiconductor layer and the second finger electrode.

9. The optoelectronic device according to claim 8, wherein the second finger portion comprises a plurality of separated island-like structures arranged at intervals under the second finger electrode.

10. The optoelectronic device according to claim 9, wherein the minimum distance between the second pad portion and the island-like structures is greater than the minimum distance between the island-like structures.

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