Systems and Methods for Direct Memory Access

Abstract

A method for direct memory access includes: receiving a direct memory access request that specifies an address in a data block to be accessed in a memory; randomizing an order of addresses for accessing the data block; and accessing the memory in the randomized address order. A corresponding system for direct memory access is also disclosed.

Description

Technical Field

[0001] The present invention relates to a system and method for Direct Memory Access (DMA). Specifically, the present invention relates to a system and method for DMA with enhanced security against attacks. Background Art

[0002] Direct Memory Access (DMA) allows data to be read from or written to memory without consuming the processor's load for data access. Figure 1 Shown is a model system in which a DMA controller operates with a memory. The system 100 includes a processor core 102, a DMA controller 104, and a memory 106. The processor core 102 determines to enter the DMA mode and initializes the DMA controller 104. In response, the DMA controller 104 requests access to the bus 108 and, after being authorized, starts reading data from or writing data to the memory 106 at a specified address. Access to the memory 106 does not require the participation of the processor core 102.

[0003] In the block move mode of the DMA controller, the read and / or write of data is performed in a stepwise increasing address order within a data block. External attacks can gather information from the timing and power consumption characteristics of the block move operation. There is a need for secure DMA systems and methods. Summary of the Invention

[0004] The present summary is provided to introduce a selected simplified subset of concepts detailed in the following detailed description. The present summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0005] According to one embodiment, a method for direct memory access includes:

[0006] Receiving a direct memory access request that specifies an address in a data block to be accessed in a memory;

[0007] Randomizing the order of addresses for accessing the data block; and

[0008] Accessing the memory in the randomized address order.

[0009] In one or more embodiments, randomizing the order of addresses includes:

[0010] Selecting a mode in response to the received direct memory access request; and

[0011] Using the selected mode, transform the positions of the bits of each address to be accessed in the memory.

[0012] In one or more embodiments, the mode is selected from a plurality of modes, and each of the plurality of modes is configured to transform the positions of the bits of the address to be accessed in the memory.

[0013] In one or more embodiments, transforming the positions of the bits of each address includes: transforming the position of the least significant bit of the address to be accessed in the memory.

[0014] In one or more embodiments, randomizing the order of the addresses includes: assigning a corresponding random access order to each address to be accessed in the memory.

[0015] In one or more embodiments, randomizing the order of the addresses includes: inserting redundant addresses between the specified addresses to be accessed in the memory.

[0016] In one or more embodiments, accessing the memory in a randomized address order includes reading data from the memory and / or writing data to the memory.

[0017] In one or more embodiments, accessing the memory in a randomized address order includes one or more of the following: copying data from a first memory to a second memory, copying data from a first part of the memory to a second part of the memory.

[0018] According to one embodiment, a method for direct memory access includes:

[0019] Receiving a direct memory access request that specifies accessing addresses in the memory in a first order;

[0020] Accessing the addresses in the memory in a second order different from the first order.

[0021] In one or more embodiments, the first order of the addresses is a stepwise increasing order of the addresses.

[0022] In one or more embodiments, a second order of the addresses is provided using a switching mode selected from a plurality of switching modes.

[0023] In one or more embodiments, providing the second order using the switching mode includes: transforming the positions of the bits of the address specified by the direct memory access request.

[0024] In one or more embodiments, transforming the positions of the bits of the address includes: transforming the position of the least significant bit of the address.

[0025] In one or more embodiments, the method further includes: assigning a random order to each address.

[0026] In one or more embodiments, the method further includes: expanding an address to be accessed by inserting a redundant address into a specified address in response to a direct memory access request specifying data to be read from a memory.

[0027] According to one embodiment, a system for direct memory access includes:

[0028] a DMA controller configured to receive a direct memory access request, where the direct memory access request specifies an address to be accessed in a memory; and

[0029] an out-of-order unit configured to randomize an order of the specified addresses;

[0030] wherein the DMA controller is further configured to access addresses in the memory in an order randomized by the out-of-order unit.

[0031] In one or more embodiments, the out-of-order unit is configured to randomize an order of the specified addresses by assigning a random access order to each of the specified addresses.

[0032] In one or more embodiments, the out-of-order unit is configured to add at least one redundant address to a specified address in response to a direct memory access request specifying data to be read from a memory.

[0033] In one or more embodiments, the out-of-order unit is configured to apply a switching pattern to a specified address to transform positions of bits in each of the specified addresses.

[0034] In one or more embodiments, the out-of-order unit is configured to transform positions of least significant bits of a specified address. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To enable the foregoing content of the present invention to be understood in a more specific manner, a further detailed description of the present invention may be obtained with reference to embodiments, some of which are shown by the accompanying legends. The accompanying legends only show typical embodiments of the present invention, and since the present invention may have other equally effective embodiments, the accompanying legends should not be construed as limiting the scope of the present invention. The drawings are drawn for ease of understanding rather than for measuring the present invention. For those skilled in the art, the benefits of the claimed inventive subject matter will be readily understood upon reading this description and in conjunction with the accompanying legends. In the drawings, like reference numerals are used to indicate like elements, and:

[0036] Figure 1 is a model of a system in which a DMA controller interacts with a memory;

[0037] Figure 2 is a system for direct memory access according to one embodiment;

[0038] Figure 3 A table that is an example of mapping the access order to the reordered address;

[0039] Figure 4 A table that is another example of mapping the access order to the reordered address;

[0040] Figure 5 A switching table that corresponds to the position change of bits in the address according to an embodiment;

[0041] Figure 6 It shows according to Figure 5 A table that is an example of the reordered address according to one of the switching modes in; and

[0042] Figure 7 A flowchart of a method for direct memory access according to an embodiment. Detailed implementation manners

[0043] Figure 2 A system for direct memory access according to an embodiment of the present invention. The system 200 includes a processor core 202, a DMA controller 204, and a memory 206, which are similar to those shown in Figure 1 The DMA controller 204 receives a DMA request command from the processor core 202. The request command from the processor core 202 initiates data transfer via the DMA relay and configures the DMA controller 204 for data access operations, such as reading at least one data block from the memory 206 or writing data to the memory 206. The DMA controller 204 can perform data access operations in units of data words. A data block includes multiple data words, and each word is associated with an address in the memory 206. In this embodiment, the DMA controller 204 communicates via a bus 208. The bus 208 can be implemented as Advanced Microcontroller Bus Architecture ( Advanced Microcontroller Bus Architecture, ), AHB (Advanced High-performance Bus, advanced high-performance bus), APB (Advanced Peripheral Bus, advanced peripheral bus), or any other applicable connection suitable for loading the corresponding communication protocol.

[0044] In response to a DMA request command from the processor core 202, the DMA controller 204 specifies the address to which data is to be read or written, where each word of the data is associated with an address in the memory 206, which in this example also means that each word of the data is read from or written to an address in the memory 206. The DMA controller 204 may include DMA registers for respectively setting the value specifying the address in the memory 206 to be accessed for a specific DMA channel, and a count value for setting the number of data units (i.e., data words) to be transferred. The system 200 further includes an out-of-order unit 210, which is connected to the DMA controller 204 and coupled to the bus 208. In other embodiments, the out-of-order unit 210 is integrated in the DMA controller 204. The out-of-order unit 210 randomizes the order of the addresses read from or written to the memory 206. Different from Figure 1 the system 100 in Figure 2 executing the read or write of a data block including multiple words in a step-by-step increasing address order and thus being vulnerable to attacks,

[0045] In accordance with one embodiment, the out-of-order unit 210 includes a look-up table that maps the order of accessing the memory 206 to the out-of-order addresses. The out-of-order unit 210 uses the addresses specified by the DMA controller 204 to generate out-of-order addresses according to the look-up table. Figure 3 A look-up table is shown as a simplified example, which maps the access order to the out-of-order addresses for a data block of four-word size in the memory 206 and is compared with the step-by-step increasing addresses. As can be seen from the Figure 3 example, the address of the word to be accessed in the first order in the memory 206 is "110000010", which is the third order in the sequentially increasing access order. The address of the word to be accessed in the second order in the memory 206 is "110000000", which is the first to be accessed in the sequentially increasing access order. The address "110000011" is accessed in the third order and is the fourth order in the sequentially increasing access order. The address "110000001" is finally accessed in the fourth order, while it is the second to be accessed in the sequentially increasing access. However, in other embodiments, or even for another data access request for the same data block in the memory 206, different, dynamic out-of-order access address orders may apply. The out-of-order unit 210 provides out-of-order access to the memory 206, thus presenting different timings and power consumptions for external attacks, and hence enhancing security.

[0046] Figure 3The examples shown can be implemented by specifying a random order for the addresses to be accessed, or by specifying for each access order an address randomly selected from the addresses to be accessed. It should be noted that specifying the addresses or the order should ensure that each target address is accessed at least once, so there may be duplicate addresses assigned different access orders. Figure 3 The implementation of the example in Figure 3 can also be understood as performing randomization on the least significant bits (LSBs) of the addresses. According to other embodiments, more or fewer LSBs in the address can be randomized to generate out-of-order addresses for the DMA controller 204 to access the memory 206. The system 200 can provide different access orders for the addresses, even for the same data block in the memory 206, so that accessing the same data block can also have different timing and power usage characteristics, and further enhance security by presenting different timing and power consumption models.

[0047] In another embodiment, preferably in a read operation, the out-of-order unit 210 adds redundant addresses to be accessed to further enhance robustness. As Figure 4 shows an example of this for accessing a data block of 4 words in the memory. In addition to randomizing the order of the addresses to be accessed, "redundant" addresses are added in the second, third, fifth, and seventh orders. In this embodiment, the access to a data block of 4 words in the memory 206 is extended to appear as an access to a data block of 8 words, and half of the words accessed (read or written) are redundant data. As can be seen from this embodiment, the number of addresses accessed is doubled, which is regarded as doubling the size of the data block. In addition, in other embodiments, the scaling of the size of the data block can be different, provided that the addresses accessed in the memory 206 do not increase discontinuously. Figure 4 The example implementation in Figure 4 can also be understood as randomizing 3 LSBs of the address and mixing the valid address with the "redundant" address. In various embodiments, the DMA controller 204 can also be configured to replicate access behavior. For example, when a specific address bit changes from "0" to "1", the DMA controller 204 replicates its access behavior at the same address in the memory 206 as the address just accessed. It can be understood that since the least significant bits (LSBs, also known as lower significant bits) flip more frequently than the higher significant bits, the selection of the aforementioned specific address bits for flipping the LSBs or MSBs (Middle Significant Bits) will result in different numbers of replicated access behaviors.

[0048] In various embodiments, the DMA controller includes a counter 212. The counter 212 may be implemented as a counting register, the value of which may be set by the processor core 202 via a DMA request command. The counter value specifies the number of data words read from or written to the memory 206. Subsequently, when a valid word is read from or written to the memory 206, the counter 212 counts down. When the counter 212 counts down to zero, it indicates that the access of the DMA controller 204 to the memory 206 is completed. It should be noted that accesses to "redundant" addresses or duplicate access behaviors are not counted by the counter 212 because the accessed data is not "valid". Although Figure 4 the "redundant" addresses in the embodiments of Figure 4 are configured to be different from the valid addresses being accessed, for example, the access behavior is directed to different data blocks or irrelevant addresses, but in other embodiments, the valid addresses in the accessed data block may also be accessed repeatedly. In addition, the DMA controller 204 is configured to further randomize its access by setting the value of the counter 212 to a preset value at a specific time to repeat the access to at least part of the addresses. For example, for a read operation of a data block of 4 words read from the memory 206, after 3 valid words are read, the DMA controller sets the value of the counter 212 to "2", indicating that only 2 words are read. The DMA controller 204 then re-executes the read operation of the third word.

[0049] According to another embodiment, the out-of-order unit 210 may be implemented as a switch. Figure 5 A switching table according to one embodiment is shown. For a given access round, the embodiment of the out-of-order unit 210 implemented as a switch randomizes the LSB of the specified address by changing the position of the LSB in a selected switching mode. The switching mode is selected in response to a data access request from the DMA controller 202. As Figure 5 shown, for the randomization of a 3-bit LSB address (corresponding to an access to a data block of 8 words), there are 3! - 1, i.e., 5 possible out-of-order switching modes, where switching mode 0 provides the same address order. For an access to the memory 206, after a switching mode is selected, the out-of-order unit 210 directs the access to the memory 206 to an address that is sorted based on sequentially increasing addresses but different from the sequentially increasing addresses. The sequentially increasing addresses are provided as inputs to the out-of-order unit 210. The out-of-order unit 210 provides a reordered address by using the selected switching mode to change the LSB of the input address. After all 3-bit LSB addresses are processed and the access to the data block of 8 words is completed based on the processed address order, a different switching mode may be selected for another data access operation. The selection of the switching mode varies with the data block being accessed, and different switching modes may be applied even to the same data block.

[0050] Figure 6 shows the reordered addresses of the out-of-order cell 210 when the switching mode 4 is selected according to the Figure 5 switching table. The first-order address accessed in the memory 206 is "110000000", which is the same as in the consecutive incremental addresses. The second-order address accessed is "110000010", which is generated by using the switching mode 4 to transform the positions of the 3 LSBs of the second-order step-increment address "110000001", where the 3 LSBs "001" of the address are converted to "010". According to the Figure 5 switching mode 4 in, the rightmost bit in[0] in the input address is placed in the middle position of the 3 LSBs as out[1], the middle bit in[1] among the 3 LSBs of the input address is transformed into the leftmost bit as out[2], and the leftmost bit in[2] among the 3 LSBs of the input address becomes the rightmost bit in the reordered address as out[0]. According to this embodiment, the order in which the addresses in the memory 206 are accessed is different from the step-increment order. The access to the memory 206 is robust by exhibiting different time and power consumption characteristics.

[0051] Returning to Figure 3 the example shown, the 2 LSBs of the address are transposed. In other embodiments, Figure 3 the example shown can also be implemented as using the Figure 6 switching mode selection example shown, and more LSBs can be applicable to transpose their positions. Although the addresses in the data block are accessed in a "predetermined" order according to the embodiments in Figure 5 and Figure 6 , considering the number of options of potentially selectable modes, the order of the accessed addresses is significantly different from the sequential increment order, and this embodiment can still be considered to randomize the address order.

[0052] Figure 7 Shown is a flowchart of a method for direct memory access according to an embodiment. This method is hereby referred to Figure 2The system 200 shown in FIG. is described. In step 702, the DMA controller 204 receives a DMA request from the processor core 202, for example via the bus 208. As previously described, the DMA request from the processor core 202 can specify the target address in the memory 206 to be accessed and the size of the data to be accessed. In step 704, in response to the DMA request from the processor core 202, the DMA controller 204 initiates a DMA operation, requests access to the bus 208, sets a value of the data size specified by the DMA request for the counter 212, and starts the out-of-order unit 210 with the target address specified by the DMA request. In step 706, the out-of-order unit 210 reorders the addresses of the memory 206 to be accessed. The out-of-order unit 210 can reorder the addresses through the means of the examples described above, for example by the LSB of the reordered address as shown in Figure 3 shown, by inserting irrelevant "redundant" addresses as shown in Figure 4 shown, by selecting a switching mode and transforming address bits as shown in Figure 5 and Figure 6 shown, etc.

[0053] In step 708 of the method, the DMA controller 204 accesses the memory 206 with the reordered addresses from the out-of-order unit 210. The access to the memory 206 described in step 708 can be performed in a word-by-word manner. Therefore, the address reordering in step 706 and the access to the memory 206 with the reordered addresses in step 708 can be performed continuously by reordering the addresses of all words at once, or can be performed alternately by reordering one address and accessing the reordered address.

[0054] The aforementioned "access" can be implemented as a read operation to read data from the access address of the memory, or as a write operation to write data to the access address of the memory, or as a copy operation to read data from the access address of one memory and write the read data to the access address of another memory, or as an in-memory copy operation to read data from the first part and write the read data to the second part. The DMA systems and methods of the various embodiments access the addresses of the memory in a randomized order, rather than in a step-by-step increasing order. In each round of accessing the memory, the system and method direct the access to the memory to the randomized address order. Therefore, even for accessing the same data block, the time characteristics and power consumption characteristics vary. Since it is robust against attacks, the access to the data is secure.

[0055] Reference is made herein to specific illustrated examples for the description of various exemplary embodiments. The examples of the embodiments are selected to assist those skilled in the art in forming a clear understanding of the various embodiments and to enable implementation. However, the scope of systems, structures, and devices that may be constructed to include one or more embodiments, as well as the scope of methods implemented in accordance with one or more embodiments, is not limited by the exemplary examples shown. On the contrary, those skilled in the art can understand based on this specification that many other configurations, structures, and methods can be implemented in accordance with the various embodiments.

[0056] It should be understood that for the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, lower, etc., those indications are given only with reference to the corresponding drawings, and when the orientation of the device changes during manufacturing or operation, other positional relationships may instead be present. As described above, those positional relationships are described only for clarity and are not restrictive.

[0057] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the present invention should not be limited thereto and should be given by the claims. The various drawings described are exemplary and not restrictive. In the drawings, for illustrative purposes, the dimensions of the various elements may be enlarged and may not be drawn to a specific scale. This specification should also include discontinuous transformations in tolerances and properties of the various elements and their modes of operation. It should also include various weakened embodiments of the present invention.

[0058] The term "comprising" as used in this specification and the claims does not exclude other elements or steps. Unless specifically stated, when using the singular form such as "a" or "an" to refer to a definite or indefinite element, the plural of that element should be included. Thus, the term "comprising" should not be construed as being limited to the items listed thereafter and should not be construed as excluding other elements or steps; the scope of the description "the device comprises items A and B" should not be limited to devices that only include elements A and B. This description means that, for the purposes of this specification, only elements A and B of the device are relevant. Although coupling generally includes inductive connection and connection generally means connection through, for example, wires, the terms "connected", "coupled", and "coupled" as used herein all indicate that there is an electrical connection between the coupled or connected elements and do not mean that there are no intermediate elements therebetween. When describing transistors and their connections, the terms gate, drain, and source are interchangeable with gate electrode, drain electrode, source electrode, and gate terminal, drain terminal, source terminal.

[0059] Those skilled in the art can make various specific changes without departing from the scope of the claims of the present invention.

Claims

1. A method for direct memory access, characterized in that, Comprising: Receiving a direct memory access request that specifies an address in a data block to be accessed in a memory; Randomizing an order of addresses of the accessed data block; And Accessing the memory in the randomized address order; Wherein randomizing the order of addresses includes: Selecting a mode in response to the received direct memory access request; And Using the selected mode to transform positions of least significant bits of respective addresses to be accessed in the memory.

2. The method according to claim 1, characterized in that, Randomizing the order of addresses includes: Assigning corresponding random access orders to respective addresses to be accessed in the memory.

3. A system for direct memory access, characterized in that, Comprising: A DMA controller configured to receive a direct memory access request, wherein the direct memory access request specifies an address to be accessed in the memory; And An out-of-order unit configured to randomize an order of the specified addresses; Wherein the DMA controller is further configured to access addresses in the memory in the order randomized by the out-of-order unit; Wherein the out-of-order unit is configured to apply a switching mode to the specified addresses to transform positions of least significant bits in respective specified addresses.

4. The system according to claim 3, characterized in that: The out-of-order unit is configured to randomize the order of the specified addresses by assigning random access orders to the respective specified addresses.

5. The system according to claim 3, characterized in that: The out-of-order unit is configured to add at least one redundant address to the specified addresses in response to the direct memory access request specifying reading data from the memory.

Images