Semiconductor device and method for transmitting and receiving data

Abstract

A plurality of semiconductor device stacks are arranged. Each semiconductor device in the stack is selected by an identification signal sent to the stack. In each stack, the signal is compared with a unique stack identifier stored in each semiconductor device, and when the signal is the same as the unique stack identifier, the semiconductor device is selected, and when the signal is different from the unique stack, the semiconductor device remains in a default bypass mode. Embodiments of the present application also relate to semiconductor devices and methods of sending and receiving data.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method of transmitting and receiving data. Background Art

[0002] Typically, integrated circuit chips are interconnected using so-called two-dimensional or 2D connections. For advanced devices such as system-on-chip (SoC) devices with large layouts of a large number of functional blocks (e.g., logic, I / O, memory, analog circuits, etc.), conventional 2D wiring has many limitations. These include I / O limitations because of the large number of interconnects and I / O ports required, power consumption / current leakage associated with 2D wiring, and high costs associated with 2D wiring. These problems are exacerbated as technology nodes evolve to sub-micron scales. Traditional 2D wiring also presents yield challenges, particularly for advanced node devices such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs).

[0003] So-called 3D wiring, which involves interconnecting multiple chips vertically and horizontally on a common substrate, is becoming increasingly popular for advanced devices. Printed circuit boards and / or silicon interposer packages can be used to interconnect different integrated circuits, such as advanced logic devices and associated memories, such as DRAM chips. The use of through-silicon vias (TSVs) also facilitates more efficient packaging of 3D packages and allows for wider I / O connections. This packaging opens the door to package-on-package (PoP) devices, such as a DRAM package stacked on top of a logic package. Despite the advantages, there are other challenges in packaging, especially 3D packaging, including the need to properly or more efficiently send and / or receive data in a 3D stack. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a first semiconductor device, comprising: a first unique identifier structure; a first electrical input; and a first comparator, comprising the first input connected to the first unique identifier structure, and comprising a second input connected to the first electrical input; a second semiconductor device, bonded to the first semiconductor device, the second semiconductor device comprising: a second unique identifier structure, different from the first unique identifier structure; a second electrical input, electrically connected to the first electrical input; and a second comparator, comprising a third input connected to the second unique identifier structure, and comprising a fourth input connected to the second electrical input.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a first semiconductor die, comprising: a first input region; a first output region; a first in-out region; a first identifier region; and a first external connection, electrically connected to a first comparator, the first comparator also electrically connected to the first identifier region, the output of the first comparator being connected to the first output region and the first in-out region; and a second semiconductor die, bonded to the first semiconductor die, the second semiconductor die comprising: a second input region; a second output region; a second in-out region; a second identifier region, the second identifier region having a different structure from the first identifier region; and a second comparator, electrically connected to the first external connection via a through hole, wherein the output of the second comparator is connected to the second output region and the second in-out region.

[0006] According to another aspect of an embodiment of the present invention, a method for sending and receiving data is provided, the method comprising: sending a stacker identifier signal to both a first semiconductor device and a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are bonded to each other; within the first semiconductor device, comparing the stacker identifier signal with a first unique identifier, wherein when the stacker identifier signal is the same as the first unique identifier, a first selection signal is generated; and within the second semiconductor device, comparing the stacker identifier signal with a second unique identifier, the second unique identifier being different from the first unique identifier, wherein when the stacker identifier signal is the same as the second unique identifier, a second selection signal is generated, the second selection signal being different from the first selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components can be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A stack of semiconductor devices according to some embodiments is shown.

[0009] Figure 2 A conceptual view of a stack of semiconductor devices according to some embodiments is shown.

[0010] Figure 3A-3D A diagram of stored identifier blocks is shown in accordance with some embodiments.

[0011] Figure 4 A conceptual view of stored identifier blocks is shown in accordance with some embodiments.

[0012] Figure 5A-Figure 5B A conceptual view of an output block according to some embodiments is shown.

[0013] Figure 6A-6B A conceptual view of an input block according to some embodiments is shown.

[0014] Figure 7A-7B A conceptual view of entering and exiting a block according to some embodiments is shown.

[0015] Figure 8A-B A control block according to some embodiments is shown.

[0016] Figure 9A-9D A view of a stored identifier block with fuses is shown in accordance with some embodiments.

[0017] Fig.10 A conceptual view of programming fuses according to some embodiments is shown.

[0018] Figure 11A-11B An input repair circuit according to some embodiments is shown.

[0019] Fig.12 An I / O array is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] Embodiments will now be described with respect to specific embodiments in which a stack of semiconductor devices sends and receives data signals using a unique identifier that indicates the location of each semiconductor device in the stack. However, the embodiments presented herein are not limited to the precise embodiments described herein and may be implemented in a wide variety of devices and methods.

[0023] Reference now Figure 1 , a first stack of semiconductor devices 100 is shown, including a first semiconductor device 101, a second semiconductor device 103, and a third semiconductor device 105. In one embodiment, the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 may be any suitable semiconductor die, such as a logic die, a memory die, a field programmable gate array (FPGA) die, an I / O die, an analog die, etc. However, any suitable type of semiconductor die may be used.

[0024] In an embodiment, the first semiconductor device 101 includes a first semiconductor substrate 107, a first through substrate via (TSV) 102, a first active device (in an active region of the first semiconductor substrate 107), and a first active device (in an active region of the first semiconductor substrate 107). Figure 1 109) and a first metallization layer 111. In an embodiment, the first semiconductor substrate 107 may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a semiconductor material layer such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0025] Within the first semiconductor substrate 107, the first TSV 102 may be formed to extend through the first semiconductor substrate 107 to provide a fast path for data signals from the first side of the first semiconductor substrate 107 to the second side of the first semiconductor substrate 107 so as to send the data signals to the overlying semiconductor devices (e.g., the second semiconductor device 103 and / or the third semiconductor device 105). In an embodiment, the first TSV 102 may be formed by first forming an opening of a through silicon via (TSV) in the first semiconductor substrate 107. The TSV opening exposed to a desired depth may be formed by applying and developing a suitable photoresist and removing a portion of the first semiconductor substrate 107. The TSV opening may be formed so that the depth extending into the first semiconductor substrate 107 is greater than the final desired height of the first semiconductor substrate 107. Therefore, although the depth depends on the overall design, the depth may be between about 20 μm and about 200 μm, such as a depth of about 50 μm.

[0026] Once the TSV opening is formed in the first semiconductor substrate 107, the TSV opening can be lined with a liner. The liner can be, for example, an oxide formed of tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material can be used. The liner can be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or thermal treatment, can be used. In addition, the liner can be formed to a thickness between about 0.1 μm and about 5 μm, such as about 1 μm.

[0027] Once the liner has been formed along the sidewalls and bottom of the TSV opening, a barrier layer may be formed and the remainder of the TSV opening may be filled with a first conductive material. The first conductive material may include copper, although other suitable materials may also be used, such as aluminum, alloys, doped polysilicon, combinations thereof, and the like. The first conductive material may be formed by electroplating copper onto the seed layer, filling and overfilling the TSV opening. Once the TSV opening is filled, excess liner, barrier layer, seed layer, and first conductive material outside of the TSV opening may be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0028] Once the TSV opening is filled, the second side of the first semiconductor substrate 107 is thinned to expose the opening for the first TSV 102 and form the first TSV 102 from the conductive material extending through the first semiconductor substrate 107. The thinning of the second side of the substrate can be performed by a planarization process such as CMP or etching. However, any suitable method of forming the first TSV 102 can be utilized.

[0029] The first semiconductor substrate 107 may also include a first active device 109. As will be appreciated by one of ordinary skill in the art, a wide variety of first active devices 109 and passive devices (such as transistors, capacitors, resistors, combinations of these), etc., may be used to generate the desired structural and functional requirements of the design of the first semiconductor device 101 (as further described below). The first active device 109 may be formed using any suitable method.

[0030] The first semiconductor device 101 also includes a back-end-of-line (BEOL) first metallization layer 111. The first metallization layer 111 is formed over the first semiconductor substrate 107 and the first active device 109, and is designed to connect the various active devices 109 and the first TSV 102 to form a functional circuit. In one embodiment, the first metallization layer 111 is formed of alternating layers of dielectric material and conductive material, and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.) to form conductive lines and conductive vias. The exact number of first metallization layers 111 depends on the design of the first semiconductor device 101.

[0031] In a particular embodiment, each layer of the first metallization layer 111 can be formed using a mosaic or dual mosaic process. For example, a dielectric layer can be deposited above the structure, and a photoresist can be placed above the dielectric layer. Once in place, the photoresist can be patterned by passing an energy source (e.g., light) through a mask to form a patterned energy source, which is then directed and impacted to the photoresist. Once the patterned energy hits the photoresist, the photoresist is developed using a developer to separate and remove the exposed or unexposed portions of the photoresist. The patterned photoresist is then used as a mask to form an opening through the dielectric layer or in the dielectric layer.

[0032] Once the opening has been formed through or within the dielectric layer, the conductive material may be placed into the opening. In a particular embodiment, a seed layer is first deposited, and then a deposition method such as electroplating or chemical plating is used to fill and / or overfill the opening with the conductive material. Once in place, a planarization process such as a chemical mechanical planarization process may be used to remove any excess material of the conductive material located outside the opening. However, any suitable method may be used to form the conductive lines and vias of each layer of the first metallization layer 111.

[0033] The first external connection 113 can be formed to be electrically connected to the first metallization layer 111. In one embodiment, the first external connection 113 can be a conductive column, such as a copper column, and can include one or more conductive materials, such as metals such as copper, tungsten, other conductive metals, etc., and can be formed, for example, by electroplating, chemical plating, etc. using a seed layer and a placed and patterned photoresist. In one embodiment, an electroplating process is used, wherein the seed layer and the photoresist are immersed or immersed in an electroplating solution, such as a solution containing copper sulfate (CuSO4). The seed layer surface is electrically connected to the negative side of an external DC power supply so that the seed layer is used as a cathode during the electroplating process. A solid conductive anode (such as a copper anode) is also immersed in the solution and connected to the positive pole of the power supply. Atoms from the anode dissolve into the solution, and the cathode (such as the seed layer) obtains the dissolved atoms therefrom, thereby electroplating the exposed conductive area of ​​the seed layer in the opening of the photoresist. Once formed, the photoresist can be removed and the exposed seed layer below can be removed.

[0034] In another embodiment, the first external connection 113 can be a contact bump such as a microbump or a controlled collapse chip connection (C4) bump, and can include a material such as tin or other suitable materials such as silver or copper. In an embodiment where the first external connection 113 is a contact bump, the first external connection 113 can include a material such as tin, or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the first external connection 113 is a tin solder bump, a thickness of, for example, about 100 μm can be achieved by methods such as evaporation, electroplating, printing, solder transfer, and ball placement. Once the tin layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape.

[0035] In addition, the second external connector 115 may be formed to provide a conductive area for contact between the first semiconductor device 101 and, for example, the second semiconductor device 103. In an embodiment, the second external connector 115 may include any desired number and any desired combination of ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, micro bumps (e.g., μbumps), bumps formed by chemical nickel-chemical palladium immersion gold technology (ENEPIG), etc. However, any suitable type of external connector may be used.

[0036] In an embodiment, the second external connector 115 may be a conductive column and may be formed by initially forming a photoresist (not shown) over the back side of the first semiconductor device 101. The photoresist may be patterned into a desired shape. Then, the second external connector 115 is deposited in the photoresist by a conductive material such as copper, although other conductive materials such as nickel, gold or metal alloys, combinations thereof, etc. may also be used. In addition, the second external connector 115 may be formed using a process such as electroplating or chemical plating. The process deposits, for example, copper in the opening to fill and / or overfill the opening of the photoresist, thereby forming the second external connector 115. Excess conductive material and photoresist outside the opening of the first passivation layer may be formed, and then may be removed using, for example, an ashing process, a chemical mechanical polishing (CMP) process, a combination of these processes, etc.

[0037] However, as will be appreciated by one of ordinary skill in the art, the above-described process of forming the first external connection 113 and the second external connector 115 is only one such description and is not meant to limit the embodiments to this process. Rather, the described process is intended to be illustrative only, as any suitable process or combination of processes for forming the first external connection 113 and the second external connector 115 may be utilized. All suitable processes are fully intended to be included within the scope of the present embodiments.

[0038] The second semiconductor device 103 may be similar to the first semiconductor device 101 (both of which have been described herein and are also described later herein). For example, the second semiconductor device 103 may include a second semiconductor substrate 117, a second TSV 104, a second active device 119, a back-end second metallization layer 121, and a fourth external connector 125, which may be similar to the first semiconductor substrate 107, the first TSV 102, the first active device 109, the first metallization layer 111, and the second external connector 115, respectively. In addition, the second semiconductor device 103 may include a third external connector 123, which may be similar to the first external connection 113 and / or the second external connector 115.

[0039] The third semiconductor device 105 may be similar to the first semiconductor device 101 (both of which have been described herein and are also described later herein). For example, the third semiconductor device 105 may include a third semiconductor substrate 127, a third TSV 106, a third active device 129, a back-end third metallization layer 131, a fifth external connector 133, and a sixth external connector 134, which may be similar to the first semiconductor substrate 107, the first TSV 102, the first active device 109, the first metallization layer 111, the third external connector 123, and the fourth external connector 125, respectively.

[0040] In an embodiment, the third semiconductor device 105 is bonded to the second semiconductor device 103, and the second semiconductor device 103 is bonded to the first semiconductor device 101. In an embodiment, the front sides of the second semiconductor device 103 and the third semiconductor device 105 are bonded to the front side of the first semiconductor device 101 and the back side of the second semiconductor device 103 in a front-facing configuration, and the front side of the second semiconductor device 103 is bonded to the front side first semiconductor device 101 in a face-to-face configuration. However, in other embodiments, the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 may be bonded in any suitable combination of directions. Any suitable configuration may be utilized.

[0041] For example, in an embodiment where the fifth external connector 133 and the fourth external connector 125 are both copper pillars, the fifth external connector 133 and the fourth external connector 125 are aligned with each other and then placed in physical contact. Once in physical contact, the fifth external connector 133 and the fourth external connector 125 are heated and pressure is applied to form a metal-to-metal bond. However, any other suitable bonding process may be utilized, such as dielectric-to-dielectric bonding (using, for example, Figure 1 passivation layer not shown), hybrid bonding, etc.

[0042] Similarly, in an embodiment where the second external connector 115 and the third external connector 123 are both copper pillars, the second external connector 115 and the third external connector 123 are aligned with each other and then placed in physical contact. Once in physical contact, the second external connector 115 and the third external connector 123 are heated and pressure is applied to form a metal-to-metal bond. However, any other suitable bonding process may be utilized, such as dielectric-to-dielectric bonding, hybrid bonding, etc.

[0043] In one embodiment, the first semiconductor device 101 is bonded to a support substrate 135 before or after bonding to the second semiconductor device 103. In one embodiment, the support substrate 135 may be a package substrate or a printed circuit board, such as a stack substrate formed as a stack of multiple thin layers (or stacks) of polymer materials such as bismaleimide triazine (BT), FR-4, ABF, etc. However, any other suitable substrates such as silicon interposers, silicon substrates, organic substrates, ceramic substrates, etc. may be utilized, and all such redistribution substrates provide support and connectivity to structures including the first external connection 113 and are fully intended to be included within the scope of the embodiments.

[0044] In an embodiment where the first external connection 113 is a solder bump, the first external connection 113 can be aligned with a corresponding connection of the support substrate 135. Once aligned and in physical contact, a reflow process can be performed to sequentially reflow the material of the first external connection 113 and bond the first external connection 113 to the support substrate 135. However, any suitable bonding process can be used.

[0045] Figure 2 The first semiconductor device 101, the second semiconductor device 103 and the third semiconductor device 105 are shown in a stacked arrangement on a support substrate 135 with a first control block 801 to form a first stack 100. However, Figure 2 A conceptual concept of the circuitry inside each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 is shown. For example, looking first at the first semiconductor device 101, the first semiconductor device may include a first active circuit 201 and a first I / O region 203. In an embodiment, the active circuitry may include logic circuits, memory circuits, combinations of these, etc., which provide the desired functionality of the first semiconductor device 101. However, any suitable circuitry may be utilized.

[0046] The first I / O region 203 is used to transmit and receive signals to / from the support substrate 135 and the second substrate / from the first semiconductor device 101 (e.g., receive signals from the first active circuit 201). In one embodiment, the first I / O region 203 includes a first ID block 205, a first output block 207, a first input block 209, and a first in / out block 211. However, any other suitable blocks may be utilized.

[0047] The second semiconductor device 103 and the third semiconductor device 105 may include the same structure as the first semiconductor device 101. For example, the second semiconductor device 103 may include a second active circuit 202, a second ID block 213, a second output block 215, a second input block 217, and a second in-out block 219, which may be respectively the same as the first active circuit 201, the first ID block 205, the first output block 207, the first input block 209, and the first in-out block 211. In addition, the third semiconductor device 105 may include a third active circuit 204, a third ID block 221, a third output block 223, a third input block 225, and a third in-out block 227, which may be respectively the same as the first active circuit 201, the first ID block 205, the first output block 207, the first input block 209, and the first in-out block 211.

[0048] Figure 2 In addition, a plurality of first external connections 113 are shown, which provide inputs and outputs connecting the support substrate 135 to the first I / O region 203 of the first semiconductor device 101. In a particular embodiment, the first external connections 113 may include a CS_ENI ball 228, a stacker_ID ball 229, a data output ball 231, a data input ball 233, and a data in-out ball 235. In addition, each of the CS_ENI ball 228, the stacker_ID ball 229, the data output ball 231, the data input ball 233, and the data in-out ball 235 is shown and described as a single first external connection 113, which is exemplary only and is not intended to limit the embodiment. Instead, any input and output may include two or more first external connections 113, such as four, eight, sixteen, etc. Any appropriate number of first external connections 113 may be used to provide inputs, such as each of the CS_ENI ball 228, the stacker_ID ball 229, the data output ball 231, the data input ball 233, and the data in-out ball 235.

[0049] Returning now to the first I / O region 203 of the first semiconductor device 101, the first ID block 205 is used to store a first unique identifier of the first semiconductor device 101. The first unique identifier can be used to identify where the first semiconductor device 101 is located in the first stack 100 so that a data signal can be specifically directed to the first semiconductor device 101 (as further described below). By providing a first unique identifier in the first metallization layer 111 (e.g., see Figure 1 ) is manufactured in the first ID block 205, and the first ID block 205 can be physically implemented in the first semiconductor device 101.

[0050] Figure 3A A top view, close-up view of an embodiment in which the first ID block 205 is implemented within two layers of the first metallization layer 111 of the first semiconductor device 101 is shown. In the close-up view of the first metallization layer 111, the first via block 402 of the first ID block 205 is formed of a non-volatile permanent memory structure by connecting one or more ID lines 301 (e.g., within a single layer of the first metallization layer 111) to a reference voltage line, such as one of a low voltage supply line 303 (e.g., a voltage source-source (VSS) line) or a high voltage supply line 305 (e.g., a voltage drain-drain (VDD) line). In a particular embodiment, the one or more ID lines 301 may include a first ID line 302, a second ID line 304, a third ID line 306, and a fourth ID line 308 extending parallel to each other, although any suitable number of ID lines may be used in any suitable arrangement.

[0051] In an embodiment, the low voltage supply line 303 and the high voltage supply line 305 may be located in another layer, such as a layer below or above the first metallization layer 111 from the one or more ID lines 301. To connect the one or more ID lines 301 to the low voltage supply line 303 and / or the high voltage supply line 305, one or more vias 307 may be formed to connect the one or more ID lines 301 to one of the high voltage supply line 305 or the low voltage supply line 303.

[0052] By controlling the location and fabrication of the through-holes 307 between the one or more ID lines 301 and the high voltage supply line 305 and the low voltage supply line 303, the first semiconductor device 101 can be internally assigned a first unique identification number within the first stack 100 during the fabrication of the first semiconductor device 101. Figure 3A In the illustrated embodiment, the first ID line 302 is connected to the high voltage supply line 305 through one of the vias 307, while the second ID line 304, the third ID line 306, and the fourth ID line 308 are connected to the low voltage supply line 303 through the via 307. In this way, by reading the output of one or more ID lines 301, the assigned unique identification number can be read from the first ID block 205.

[0053] However, by connecting one or more ID lines 301 to the low voltage power line 303 and the high voltage power line 305 using vias 307, different unique identification numbers can be assigned to the first semiconductor device 101 during the manufacturing process by simply changing the position of the vias 307. Figure 3B As shown, in another embodiment, the first ID line 302, the third ID line 306, and the fourth ID line 308 are connected to the high voltage supply line 305, and the second ID line 304 is connected to the high voltage supply line 305 through the through hole 307. In this way, by reading the output from one or more ID lines 301, a separate unique identification number can be read from the first ID block 205.

[0054] In yet another embodiment, Figure 3C As shown, the third unique identification number can be obtained by another rearrangement of the through hole 307 during the manufacturing process. For example, in this embodiment, the first ID line 302, the second ID line 304 and the fourth ID line 308 are respectively connected to the low voltage power line 303, and the third ID line 306 is connected to the high voltage power line 305. In this way, by reading the output of one or more ID lines 301, the third unique identification number can be read from the first ID block 205.

[0055] In yet another embodiment, Figure 3D As shown, the fourth unique identification number can be obtained by another rearrangement of the through hole 307 during the manufacturing process. For example, in this embodiment, the first ID line 302, the second ID line 304 and the third ID line 306 are respectively connected to the low voltage power line 303, and the fourth ID line 308 is connected to the high voltage power line 305. In this way, the fourth unique identification number can be read from the first ID block 205 by reading the output from the signal passing through one or more ID lines 301.

[0056] By modifying the location of one or more through-holes 307 located within a single layer of the first metallization layer 111, a unique identification number can be provided to the first semiconductor device 101 during the process of manufacturing the first semiconductor device 101. In addition, if it is desired to give a different unique identifier to the first semiconductor device, only a single photolithography mask (e.g., a photolithography mask used to pattern the location of the through-hole 307) is changed without any other changes. In this way, any desired unique identification number can be assigned to the first semiconductor device 101 using a simple and efficient process.

[0057] Figure 4A first stack 100 of a first semiconductor device 101, a second semiconductor device 103, and a third semiconductor device 105 on a supporting substrate 135 is shown, wherein for clarity, the internal logic related to the first ID block 205, the second ID block 213, and the third ID block 221 are shown (rather than the exact structure). In an embodiment, the first ID block 205 of the first semiconductor device 101, the second ID block 213 of the second semiconductor device 103, and the third ID block 221 of the third semiconductor device 105 are electrically connected to the stack_ID ball 229 and also reach the CS_ENI ball 228, respectively.

[0058] However, in this embodiment, each semiconductor device in the first stack 100 is manufactured or otherwise given a unique identifier. Figure 4 As shown, the first semiconductor device 101 is assigned a first unique identifier "1" using the first via block 402, the second semiconductor device 103 is assigned a second unique identifier "2" using the second via block 404, and the third semiconductor device 105 is assigned a third unique identifier "3" using the third via block 406. Figure 3A-3D As described, a unique identifier is assigned within each semiconductor device, such as by modifying the location of vias 307 within each metallization layer.

[0059] When it is desired to send a data signal to one semiconductor device, a stacker_ID signal 405 is sent through the stacker_ID ball 229, and a CS_ENI signal 413 is sent to each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 through the CS_ENI ball 228. In an embodiment, the stacker_ID ball 229 may be a single one of the first external connections 113, although the exact number of first external connections 113 may also be a plurality or a logarithm of the number of semiconductor devices in the first stack 100. For example, in an embodiment having sixteen semiconductor devices in the first stack 100, there may be four first external connections 113 for the stacker_ID ball 229. However, any appropriate number of first external connections 113 or pins may be utilized.

[0060] Observing the first semiconductor device 101, the stack_ID signal 405 is received in the first ID block 205 by the first comparator 407. As input, the first comparator 407 additionally has a first unique identifier, which is received as a signal from the first metallization layer 111, as described above with respect to Figure 3A-3DAs described. In the first comparator 407, the stacker_ID signal 405 is compared with the first unique identifier (e.g., "1" of the first semiconductor device 101). If the stacker_ID signal 405 received by the first semiconductor device 101 is the same as the unique identifier stored in the first semiconductor device 101, the first ID signal 415 is output from the first comparator 407 and sent to the first AND gate 409. The other input of the first AND gate 409 is connected to receive the CS_ENI signal 413 from the CS_ENI ball 228. The first AND gate 409 then determines whether both the CS_ENI signal 413 and the first ID signal 415 are present, and if both are present, the first selection signal 417 from the first AND gate 409 is output.

[0061] By using the first ID_block 205, the first semiconductor device 101 can determine whether the first semiconductor device 101 has been selected to send and / or receive data signals from the supporting substrate 135, while other semiconductor devices within the first stack 100 are generally set to a bypass mode by default. For example, if the first selection signal 417 is present, the first semiconductor device 101 has been selected to send signals to and / or receive signals from the supporting substrate 135 (described further below). Additionally, if the first selection signal 417 is not present, the first semiconductor device 101 is not selected to send signals to and / or receive signals from the supporting substrate 135, and the first semiconductor device 101 remains in its default state, where signals pass through and effectively bypass the first semiconductor device 101.

[0062] In addition, although in the above embodiment where two signals are used to determine whether the first semiconductor device 101 has been selected, although the use of the stack_ID signal 405 and the CS_ENI signal 413 is described above, this is merely exemplary and is not intended to limit the embodiment. Instead, any suitable combination of signals may be utilized. For example, in another embodiment, the first ID signal 415 itself may be used as the first selection signal 417, and the CS_ENI ball 228 and the first AND gate 409 are optional and may be removed. Any such combination of components may be utilized.

[0063] Next, looking at the second semiconductor device 103, in some embodiments, the second semiconductor device 103 is configured the same as the first semiconductor device 101, but the second ID block 213 stores a second unique identifier (e.g., "2") instead of the first unique identifier (e.g., "1"). For example, the second semiconductor device 103 can receive the stacker_ID signal 405 through the second comparator 419, and if the stacker_ID signal 405 is equal to the second unique identifier stored in the second ID_block 213, the second ID signal 421 is sent to the second AND gate 423, which has the CS_ENI signal 413 connected as an input. If the second semiconductor device 103 is selected, the second AND gate 423 outputs a second selection signal 425. If the second semiconductor device 103 is not selected, the second semiconductor device 103 remains in a default state, where the signal passes through the second semiconductor device 103.

[0064] Next, looking at the third semiconductor device 105, in some embodiments, the third semiconductor device 105 is configured the same as the first semiconductor device 101, but has a third unique identifier (e.g., "3") stored in the third ID block 221 instead of the first unique identifier (e.g., "1"). For example, the third semiconductor device 105 can receive the stacker_ID signal 405 through the third comparator 427, and if the stacker_ID signal 405 is equal to the third unique identifier stored in the third ID_block 221, the third ID signal 429 is sent to the third AND gate 431, which has the CS_ENI signal 413 connected as an input. If the third semiconductor device 105 is selected, the third AND gate 431 outputs a third selection signal 433. If the third semiconductor device 105 is not selected, the third semiconductor device 105 remains in a default state, in which the signal passes through the third semiconductor device 105.

[0065] Optionally, in some embodiments, the first ID block 205 of the first semiconductor device 101, the second ID block 213 of the second semiconductor device 103, and the third ID block 221 of the third semiconductor device 105 may also include multiple unique identifiers. For example, in addition to having respective unique identifiers (e.g., the first unique identifier, the second unique identifier, and the third unique identifier), the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 may also include a group unique identifier (e.g., "0"), which may be used to place the semiconductor device in a group of more than one semiconductor device (e.g., in a group including each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105). In such an embodiment, the first comparator 407 of the first semiconductor device 101 also compares each group unique identifier with the input stack_ID signal 405, and also outputs the first ID signal 415 when receiving the group unique identifier. By using the group unique identifier, a signal can be sent to all semiconductor devices in the group at the same time without having to send a separate ID signal for each semiconductor device.

[0066] Figure 5A-Figure 5B A conceptual version of a first output block 207 within a first semiconductor device 101 is shown, and when the first semiconductor device 101 is selected, the first output block 207 within the first semiconductor device 101 can be used to output a data signal from the first semiconductor device 101 to the supporting substrate 135. In an embodiment, the first output block 207 receives a first selection signal 417 (e.g., from the first ID block 205), and, if the first semiconductor device 101 is selected, the first output block 207 sends data from the first semiconductor device 101 to the data output ball 231. However, if the first semiconductor device 101 is not selected (e.g., the first output block 207 does not receive the first selection signal 417), the first output block 207 sends a signal received from an overlying semiconductor device (e.g., the second semiconductor device 103) to the data output ball 231.

[0067] Observing a particular embodiment, the first output block 207 is connected to a first data source 505. In some embodiments, the first data source 505 may be a data flip-flop (DFF), although any suitable data source may be used. In an embodiment, the first data source 505 is connected to the remainder of the first active circuit 201 within the first semiconductor device 101, and the output of the first data source 505 (e.g., a first data source line 506) is connected to the first output block 207.

[0068] Figure 5BA close up view of one particular embodiment of the first output block 207 is shown. In this embodiment, the first data source line 506 is connected as an input to the first multiplexer 507. Additionally, the first multiplexer 507 is connected to the first select signal 417 as a selector of the first multiplexer 507. Thus, when the first ID block 205 registers that the stacker_ID signal 405 is selecting the first semiconductor device 101, the first select signal 417 is input to the first multiplexer 507 and the signal sent along the first data source line 506 is selected as the first multiplexer output signal 502 output from the first multiplexer 507. Once the first multiplexer output signal 502 leaves the first multiplexer 507, the first multiplexer output signal 502 is applied to the first output pad 511 (having, for example, an output amplifier and electrostatic discharge protection) and is ultimately sent out 512 from the first semiconductor device 101 into the supporting substrate 135 as the first data output signal.

[0069] However, in embodiments where the first ID block 205 registers that the stack_ID signal 405 does not select the first semiconductor device 101, the first selection signal 417 is not input to the first multiplexer 507. In addition, another input of the first multiplexer 507 can be connected to receive a signal from an overlying semiconductor device (e.g., a second data output signal 514 from the output of the second output block 215 in the second semiconductor device 103). In a specific embodiment, the second data output signal 514 can be sent by the second output block 215 of the second semiconductor device 103 and input to the second input pad 509 (e.g., having a second amplifier and electrostatic discharge protection) before being connected as an input to the first multiplexer 507.

[0070] Thus, when the first semiconductor device 101 is not selected, the second data output signal 514 (from the overlying second semiconductor device 103 or third semiconductor device 105) is selected as the data output signal 512 to leave the first semiconductor device 101. In this arrangement, the first semiconductor device 101 is effectively bypassed, and the selected data from the overlying semiconductor device is sent from the first stack 100 to the supporting substrate 135.

[0071] Next, the second semiconductor device 103 and the third semiconductor device 105 are observed. The second semiconductor device 103 has a second output block 215, and the third semiconductor device 105 has a third output block 223. In some embodiments, the second output block 215 and the third output block 223 can be connected to Figure 5BThe first output block 205 described in . Thus, in each of the second output block 215 and the third output block 223, the second selection signal 425 (of the second semiconductor device 103) or the third selection signal 433 (of the third semiconductor device 105) is used to select the output of the multiplexer to output data from the selected semiconductor device or from the overlying semiconductor device. These data signals can be sent through external connections that are aligned with each other, or in embodiments where the external connections are not aligned with each other, the signals are routed through metallization layers or redistribution layers.

[0072] By utilizing the first output block 207, the second output block 215, and the third output block 223, the same structure can be manufactured in each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105, and the stacker_ID signal 405 can be used to select which semiconductor device to send data from the first stacker 100. For example, if the stacker_ID signal 405 selects the third semiconductor device 105, the third output block 223 will send data to the data output ball 231 through the second semiconductor device 103 and the first semiconductor device 101. In addition, when the third semiconductor device 105 is selected, the first semiconductor device 101 and the second semiconductor device 103 do not send data signals, and allow overlying signals to pass through them.

[0073] In addition, since the top semiconductor device (e.g., the third semiconductor device 105) within the first stack 100 has the same structure as the other semiconductor devices, the third semiconductor device 105 also has an external connector that is not connected to anything. In this way, for the top semiconductor device within the first stack 100 (e.g., the third semiconductor device 105 within the first stack 100 shown), the second input for the multiplexer can be connected to a low voltage source or a high voltage source. By connecting the input to the low voltage source or the high voltage source, a floating state such as a tri-state can be avoided.

[0074] By manufacturing and operating the output block as described above, a Lego-based structure (physically and logically) can be obtained, and no global multiplexer is required and there is no floating net problem, because only the selected semiconductor device can be driven and other semiconductor devices are set to bypass mode. In addition, there is a predictable I / O load and latency design, such as there is a local load to avoid load variations due to the number of semiconductor devices, because the first output pad 511 drives the signal from the current semiconductor device, and the second input pad 509 drives the signal received from the overlying semiconductor device.

[0075] In this way, the waiting time difference can be alleviated by using a burst mode. In particular, in this mode data, the device can repeatedly send data without performing all steps (for example, the initial delay caused by waiting for input from another device, waiting for the internal process to terminate, the delay caused by the initial communication, etc.) to transmit each data in a separate process. In this way, data is sent continuously in a fixed number of cycles (for example, N cycles), and then discontinuously in another fixed number of cycles (for example, K cycles). In this way, the average data unit per cycle is equal to N / (N+K), which is equal to 1 / (1+K / N), so when N is much larger than K, the impact from K can be ignored.

[0076] Figure 5A An alternative embodiment is also shown in which the first output block 207 is not the only output region within the first semiconductor device 101. In this embodiment, in addition to the first output block 207, a second output region 503 may be utilized to send data and signals out of the first semiconductor device 101 and into the supporting substrate 135 through, for example, one of the first external connections 113 (such as a slow data output ball 508). In an embodiment, the second output region 503 may be a general purpose I / O (GPIO) output, and in some specific embodiments, the second output region 503 may have a different data transfer speed than the first output block 207. For example, the first output block 207 may have a smaller load (e.g., less resistance / capacitance issues due to a shorter path to the input of the underlying structure), while the second output region 503 may have a larger load (e.g., greater resistance / capacitance issues due to a longer path to the output).

[0077] In embodiments where the data transmission speed of the second output region 503 is less than the data transmission speed of the first output block 207, the second output region 503 and the first output block 207 may be utilized in conjunction with each other to transfer data out of the first semiconductor device 101. For example, for speed-sensitive data that needs to be transmitted quickly, the data may be sent through the first output block 207, and then data that is less time-sensitive may be sent at a lower speed through the second output region 503. However, any suitable combination of usage between the first output block 207 and the second output region 503 may be utilized to transfer data out of the first semiconductor device 101.

[0078] In another embodiment, the second output region 503 transmits data only when selected by the selection signal 417. For example, when the stacker_ID signal 405 is received and the first selection signal 417, the second selection signal 425, and the third selection signal 433 are generated, if the first data is generated, the second output region 503 may receive the first selection signal 417, and if the first semiconductor device 101 is selected, the second output region 503 may output data through the slow data output ball 508.

[0079] In some embodiments, the second output region 503 may include a second data source 510 (e.g., a second data flip-flop (DFF)) having an output to a data output amplifier 512. In addition, the data output amplifier 512 has a selector connected to the first selection signal 417. In view of this, when the first semiconductor device 101 has been selected, the data stored in the second data source 510 is output through the slow data output 508 (while other data is output through the first output block 207). In this way, the data from the first semiconductor device 101 can be sent through the best output from the first semiconductor device 101.

[0080] Fig. 6A A conceptual view of a first input block 209 of a first semiconductor device 101, a second input block 217 of a second semiconductor device 103, and a third input block 225 of a third semiconductor device 105 is shown (with first output block 207, second output block 215, and third output block 223 also shown). The first input block 209, the second input block 217, and the third input block 225 are commonly connected to data in ball 233 to receive data in signal 607 from a supporting substrate 135. However, because the data in signal 607 is not specific to a particular semiconductor device, none of the first selection signal 417, the second selection signal 425, or the third selection signal 433 is connected to the first input block 209, the second input block 217, or the third input block 225.

[0081] Figure 6B A close up view of a schematic diagram of a first input block 209 of a first semiconductor device 101 is shown. In an embodiment, the first input block 209 includes a third input pad 601 (e.g., with a buffer and electrostatic discharge protection) and a fourth output pad 603 (e.g., with a buffer and electrostatic discharge protection) arranged in series with each other. Looking first at the third input pad 601, the input of the third input pad 601 of the first semiconductor device 101 is connected to the data in the ball 233. Thus, when the data in the signal 607 is applied to the data in the ball 233 from the supporting substrate 135, the data in the signal 607 is directed to the third input pad 601, where the third input pad 601 is used to drive the data in the signal 607 to the first semiconductor device 101.

[0082] The first output from the third input pad 601 is connected to the first active circuit 201 of the first semiconductor device 101 to pass the buffered data in the signal 609 into the first semiconductor device 101. In some embodiments, the buffered data in the signal 609 may be connected to the first data source 505 (e.g., a data flip-flop (DFF)), which may then be used to forward the amplified data in the signal 609 to the remaining circuitry of the first semiconductor device 101. However, in other embodiments, the buffered data in the signal 609 may be connected to other data sources, buffers, other memories, combinations of these, etc., and any suitable transmission of the buffered data in the signal 609 to the first semiconductor device 101 may be utilized.

[0083] The buffered data in signal 609 output from the third input pad 601 is additionally directed to the fourth output pad 603 to send the buffered data in signal 609 to the overlying second semiconductor device 103. The buffered data in signal 609 (from the third input pad 601) is applied to the input of the fourth output pad 603, and the fourth output pad 603 outputs the second buffered data in signal 611. The second buffered data in signal 611 is then directed to the second input block 217 of the second semiconductor device 103.

[0084] Return to Fig. 6A , then observe the second semiconductor device 103, in some embodiments, the second input block 217 of the second semiconductor device 103 is configured to be the same as the first input block 209 of the first semiconductor device 101. For example, the second semiconductor device 103 can receive the second buffered data in the signal 611 from the first semiconductor device 101 using the second input block 217 (e.g., including two pads with buffers arranged in series with each other). In addition, the second input block 217 outputs another buffered data in the signal to the second active circuit 202 of the second semiconductor device 103, and outputs another buffered data in the signal to the overlying semiconductor device (e.g., the third semiconductor device 105). These data signals can be sent through external connections that are aligned with each other, or in embodiments where the external connectors are not aligned with each other, the signals are routed through metallization layers or redistribution layers.

[0085] Next, looking at the third semiconductor device 105, in some embodiments, the third input block 225 of the third semiconductor device 105 is configured to be the same as the first input block 209 of the first semiconductor device 101. For example, the third semiconductor device 105 can receive buffered data in the signal from the second semiconductor device 103 using the third input block 225 (e.g., including two pads with buffers arranged in series with each other). In addition, the third input block 225 outputs another buffered data in the signal to the third active circuit 204 of the third semiconductor device 105, and outputs another buffered data in the signal. These data signals can be received through external connections that are aligned with each other, or in embodiments in which the external connectors are not aligned with each other, the signal is routed through a metallization layer or a redistribution layer.

[0086] In some embodiments, buffered data in the signal of the third input block 225 leaving the third semiconductor device 105 can be optionally looped back as an input to the third output block 223 to form a boundary scan chain (e.g., SCAN) that can be used to check the connectivity of the stacked die and help measure the delay through the semiconductor device. For example, the output of the third input block 225 is connected to the input of the third output block 223 through, for example, a metallization layer or a redistribution layer, and when all semiconductor devices (e.g., each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105) are not selected, then the data in the signal 607 will pass through the first input block 209, the second input block 217, the third input block 225, the third output block 223, the second output block 215, and the first output block 207, respectively, and be buffered and amplified by them, and then routed back to the supporting substrate 135. In this way, the amount of time it takes for the data in the signal 607 to enter and leave the first stack 100 can be measured. Such measurements may then be compared to standards to determine if any defects are present in the first stack 100, or may be used to determine the delay setting for the first control block 801 (described below).

[0087] By manufacturing and operating the input blocks as described above, a Lego-based structure is obtained (physically and logically), and no global multiplexers are required. In addition, there is a predictable I / O load and latency design, where each device within the first stack 100 drives a local load to the next device in the first stack 100, and latency differences can be mitigated by using a burst mode. This allows for shorter latency for structures like DRAM super buffer solutions.

[0088] Fig. 7AA conceptual view of a first in / out block 211 of a first semiconductor device 101, a second in / out block 219 of a second semiconductor device 103, and a third in / out block 227 of a third semiconductor device 105 is shown. When a corresponding semiconductor device is selected by a stack_ID signal 405 (read by the first ID block 205, the second ID block 213, and the third ID block 221), the first input module 211, the second input module 219, and the third input module 227 can be used to send and / or receive signals from the data in / out ball 235 of the first external connection 113. In addition, the first in / out block 211 can be used in addition to or in place of the first output block 207 and the first input block 209, the second in / out block 219 can be used in addition to or in place of the second output block 215 and the second output block 215, and the third in / out block 227 can be used in addition to or in place of the third output block 223 and the third input block 225. Any suitable combination and / or usage of structural or functional in / out blocks, input blocks, and output blocks may be used.

[0089] Figure 7B A close-up view of the schematic diagram of the first in-out block 211 is shown. In one embodiment, the first in-out block 211 includes a first I / O cell 701, a second I / O cell 703, a second multiplexer 705, and a first inverter 707. First, the first I / O cell 701 is observed. The first I / O cell 701 is connected to the data in-out ball 235 (see Fig. 7A ) to allow signals to be transmitted bidirectionally between the first semiconductor device 101 and the supporting substrate 135. For example, in some embodiments, the first I / O cell 701 can be used to send the first in-out output signal 723 from the first semiconductor device 101 to the supporting substrate 135, while in other embodiments, the first I / O cell 701 can be used to receive the first in-out input signal 721 from the supporting substrate 135.

[0090] In order to switch between the first I / O cell 701 transmitting and receiving data signals, the first I / O cell 701 also includes an input to receive an output enable ("OE") signal 711 that selects an output signal, the OE signal 711 selecting the first I / O cell 701 to transmit a signal to or receive a signal from the supporting substrate 135. The OE signal 711 is initiated within the first semiconductor device 101 when the first semiconductor device 101 determines that a change in operation is desired. For example, in some embodiments, the OE signal 711 may be applied when the first semiconductor device 101 determines to output data (e.g., output the first in-out output signal 723), while in other embodiments, the OE signal 711 may not be applied when the first semiconductor device 101 determines to receive an input signal (e.g., receive the first in-out input signal 721). However, any suitable application of one or more signals may be utilized to switch between receiving and transmitting.

[0091] The OE signal 711 is applied to the second I / O cell 703 in addition to the first I / O cell 701, so as to set the second I / O cell 703 to receive or transmit data. However, because the first I / O cell 701 and the second I / O cell 703 perform opposite functions at any single time, the OE signal 711 is applied to the second I / O cell 703 through, for example, the first inverter 707. In this way, the second I / O cell 703 is set to an operating state opposite to that of the first I / O cell 701.

[0092] In order to allow the first in / out block 211 to send data to the operation of the supporting substrate 135, the second multiplexer 705 is located between the first I / O cell 701 and the second I / O cell 703. The multiplexer output signal 713 is connected as an input to the first I / O cell 701. In addition, one input of the second multiplexer 705 is connected to the data in / out input signal 715 to receive data from the first active circuit 201 of the first semiconductor device, and the second input of the second multiplexer 705 is connected to the second I / O cell 703. Finally, the first selection signal 417 is connected to the second multiplexer 705 to select which input of the second multiplexer 705 is used as the multiplexer output signal 713 (and thus output through the first I / O cell 701).

[0093] In addition, to allow the operation of the first in / out block 211 to receive the first in / out signal 721 from the supporting substrate 135 and send the data in / out signal to the first active circuit 201 or to an overlying semiconductor device (e.g., the second semiconductor device 103), the output of the first I / O cell 701 is connected as an input of the second I / O cell 703. The output of the first I / O cell 701 is additionally routed to the first active circuit 201 of the first semiconductor device 101 as input data.

[0094] Finally, to allow connection to an overlying semiconductor device (e.g., the second semiconductor device 103), the second I / O cell 703 has a second input / output connection 717. In an embodiment, the second input / output connection 717 is connected to, for example, a second in / out block 219 located within the second semiconductor device 103 (e.g., see Fig. 7A ). Thus, the second in / out output signal 725 can be sent to the second in / out block 219 as an output of the second in / out block 219. The second I / O cell 703 can receive a signal from the second semiconductor device 103 via the second input / output connection 717. In addition, the second I / O cell 703 can receive a second in / out input signal 727 from an overlying semiconductor device (e.g., the second semiconductor device 103) via the second input / output connection 717.

[0095] In operation, when it is desired to output data to the supporting substrate 135, the OE signal 711 is set to, for example, "1". In this way, the first I / O cell 701 is set to output the second multiplexer output signal 713 from the second multiplexer 705 to the supporting substrate 135 via the first input / output connection 719. In addition, to determine the data to be output, the first selection signal 417 is set to "1", in which case data from the first semiconductor device 101 (e.g., data in and out input signal 715) is output through the second multiplexer 705, or to "0". In this case, data from the overlying semiconductor device (e.g., the second in and out input signal 727 from the second semiconductor device 103 or the third semiconductor device 105) is sent through the second multiplexer 705, effectively bypassing the first semiconductor device 101.

[0096] In an operation where data is expected to be input from the support substrate 135, the OE signal 711 is set to "0", for example. Thus, the first I / O cell 701 is arranged to receive a first inbound and outbound input signal 721 from the first input / output connection 719. The first I / O cell 701 may include an amplifier (at Figure 7B (not shown separately) to drive the input data as the first amplified input signal 724 into the first active circuit 201 of the first semiconductor device 101, and also drive the first amplified input signal 724 to the second I / O unit 703. Then, the second I / O unit 703 may also include another amplifier (also not shown). Figure 7B ), the other amplifier can be used to drive a second in / out output signal 725 through the second input / output connection 717 and to an overlying semiconductor device, such as the second semiconductor device 103.

[0097] However, despite the relative Fig. 7A and Figure 7B Specific structures and specific settings are described, but these descriptions are exemplary only and are not intended to limit the embodiments. Instead, any suitable structure and any suitable setting can be used to implement the first in-and-out block 211. All such structures and settings are fully intended to be included in the scope of the embodiments.

[0098] Next, looking at the second semiconductor device 103, in some embodiments, the second in-out block 219 of the second semiconductor device 103 is configured to be the same as the first semiconductor device 101. For example, when the second in-out block 219 is configured to receive data input from the supporting substrate 135, the second semiconductor device 103 can receive the second in-out output signal 725 from the first semiconductor device 101 through the second input module 219. In addition, the second input module 219 outputs another amplified in-out data in the signal to the internal circuit of the second semiconductor device 103, and another amplified data in the signal is sent to the overlying semiconductor device (e.g., the third semiconductor device 105). In addition, when it is desired to send data from the second semiconductor device 103, the second in-out block 219 sends the second in-out input signal 727 to the first in-out block 211 in the first semiconductor device 101. These data signals can be sent through external connections that are aligned or not aligned with each other (e.g., the signal is routed through a metallization layer or a redistribution layer).

[0099] Next, looking at the third semiconductor device 105, in some embodiments, the third in-out block 227 of the third semiconductor device 105 is configured to be the same as the first semiconductor device 101. For example, when the third in-out block 227 is configured to receive data from the supporting substrate 135, the third semiconductor device 105 can receive data from the second semiconductor device 103 through the third input module 227. In addition, when it is desired to send data from the third semiconductor device 105, the third input module 227 will send in-out input signals to the second in-out block 219 in the second semiconductor device 103. These data signals can be sent through external connections that are aligned or not aligned with each other (for example, the signals are routed through metallization wiring layers or redistribution layers).

[0100] In addition, in embodiments where the third in / out block 227 is the top semiconductor device of the first stack 100, the input of the second I / O cell 703 within the third semiconductor device 105 can be tied to a reference voltage. In some embodiments, the reference voltage can be a low voltage source or a high voltage source. By tying the input to a reference voltage, floating states such as tri-states can be avoided.

[0101] By manufacturing and operating the access block as described above, a Lego-based structure (physically and logically) with bidirectional I / O pins (e.g., for an FPGA) is obtained, and each semiconductor device within the stack 100 has a similar load, so that the total load does not change as the number of semiconductor devices in the first stack 100 becomes larger. This also forms a flexible design and allows the user to configure the first external connection 113 associated with the access block as an input or output connection, which provides greater flexibility.

[0102] Fig. 8A A first control block 801 is shown that may be connected to the first stack 100 through, for example, the support substrate 135. In an embodiment, the first control block 801 may be stack_ID based, and in order to receive and capture data output from semiconductor devices (e.g., the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105) located within the first stack 100, a fast shared I / O controller may be used.

[0103] In an embodiment, the first control block 801 may include one or more separate timing adjustment units 803 (for clarity, in Fig. 8A ). Each individual timing adjustment unit 803 includes two or more delay lines 807 for receiving an input clock signal 811 and separating the clock signal 811 into a plurality of clock signals (one for each line), wherein each of the separated plurality of clock signals is delayed by a different amount based on the structure of the delay line 807.

[0104] In certain embodiments, each of the two or more delay lines 807 includes a different number of delay elements 809, such that each of the two or more delay lines 807 delays a different amount of the clock signal 811. In one embodiment, the delay element 809 may be a buffer, an inverter, a combination of these, etc., which may delay the clock signal 811 as the clock signal 811 operates through the delay element 809. However, any suitable type of structure may be used for the delay element 809.

[0105] To obtain different amounts of delay, each of the two or more delay lines 807 includes a different number of delay elements 809. Fig. 8A In the precise embodiment shown, a first of the two or more delay lines 807 includes two delay elements 809, and a second of the two or more delay lines 807 includes a single delay element 809. However, any suitable number of delay elements 809 (excluding delay elements 809) may be used to provide the desired delayed clock signal 811 for the input signal.

[0106] Once each of the two or more delay lines 807 delays the incoming clock signal 811 into a separate delayed clock signal, the separate delayed clock signal is input to the third multiplexer 805. By inputting the separate delayed clock signals into the third multiplexer 805, one delayed clock signal can be selected as the output of the third multiplexer 805, thereby allowing the input clock signal 811 to be delayed by any selected delay amount.

[0107] In addition, in order to determine which one of the two or more delay lines 807 should be output from the third multiplexer 805, the two or more delay lines 807 are respectively associated with the respective semiconductor devices of the first stack 100 (e.g., the first delay line is associated with the first semiconductor device 101, the second delay line is associated with the second semiconductor device 103, etc.). This association can be done using simulation data, by actual testing of the semiconductor devices within the first stack 100, a combination of these, etc. However, any suitable method of determining the wait time and associating the respective semiconductor devices with the respective delay lines can be used.

[0108] In certain embodiments where actual testing is desired, the above description of Figure 6A-6B The traceback test measurement described may be used to determine the latency of a data signal as it travels through the first stack 100. A signal may be applied to the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105, and then received back from the first stack 100, thereby measuring the delay for data sent to each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105. However, any suitable method for obtaining actual test data may be utilized.

[0109] Once the delay data for each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 is obtained, the data may be stored in the first control block 801. The data may be stored by generating a table that associates a unique identifier of each semiconductor device with an associated output cell wait time and an associated delay line. However, any suitable method may be used to store the association.

[0110] In operation, when it is desired to read data from one of the semiconductor devices in the first stack 100, the unique identifier of the desired semiconductor is utilized to specifically select which of the two or more delay lines 807 is output through the third multiplexer 805. In particular, the stack_ID signal 405 can be used to select which delayed signal is output from the third multiplexer 805 based on which of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 is sending an output signal.

[0111] Once the clock signal 811 is delayed and then outputs the third multiplexer 805 based on the desired semiconductor device within the first stack 100, the clock signal 811 is applied to the data receiver 812 together with the data from the first stack 100. In a specific embodiment, the data receiver 812 can be a data flip-flop that receives data from the first stack 100 and, together with the delayed clock signal 811 from the third multiplexer 805, captures the data sent from the first stack. However, any suitable type of data receiver 812 may be used. By inputting the data from the first stack 100 and the selected clock signal from the third multiplexer 805 to the data receiver 812, the data receiver 812 can read and capture data from any one of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105.

[0112] However, although specific embodiments are described in which data is captured from individual semiconductor devices within the first stack 100 using delay lines and data flip-flops, this is exemplary only and not limiting to these embodiments. Instead, any suitable input / output control protocol may be utilized. All such protocols are fully intended to be included within the scope of the embodiments.

[0113] Figure 8B Another embodiment is shown in which a first control block 801 is connected to a first stack 100, a second control block 815 is connected to a second stack 817, and a third control block 819 is connected to a third stack 821. In an embodiment, the second stack 817 and the third stack 821 may be similar to the first stack 100, for example by having a plurality of semiconductor devices, each with a unique identifier indicating its position in the stack. Each of the second control block 815, the third control block 819, the second stack 817, and the third stack 821 may be connected to each other by, for example, a support substrate 135, but any suitable configuration may be used.

[0114] Additionally, the second control block 815 and the third control block 819 may be similar to the first control block 801. For example, each of the second control block 815 and the third control block 819 may include a plurality of delay lines, a multiplexer, and a data receiver. However, any suitable structure may be used.

[0115] In this embodiment, a single clock signal 811 may be applied to each of the first stack 100, the second stack 817, the third stack 821, the first control block 801, the second control block 815, and the third control block 819. The clock signal 811 in this embodiment may be modified based on which of the first stack 100, the second stack 817, or the third stack 821 is desired to be read from.

[0116] For example, when it is desired to send data from the first stack 100 from the first stack 100, the clock signal 811 may be set to 4 GHz (e.g., 0.25 ns). Additionally, when it is desired to send data from the second stack 817 from the second stack 817, the clock signal 811 may be set to 2 GHz (e.g., 0.5 ns). Finally, when it is desired to send data from the third stack 821 from the third stack 821, the clock signal may be set to 1 GHz (e.g., 1 ns). However, any suitable setting of the clock signal 811 may be utilized, such as the delay data stored in the above table, the delay data related to the number of delay elements 809, or the delay data determined by other means using, for example, software training.

[0117] Given the ability to modify the clock signal 811 based on which stack is selected (e.g., the first stack 100, the second stack 817, or the third stack 821), faster overall data transmission speeds can be achieved. For example, if the third stack 821 requires a clock signal 811 of no greater than 1 GHz (e.g., the clock speed is limited by the architecture, a particular node of manufacturing, etc.), the ability to modify the clock signal 811 allows the other stacks (e.g., the first stack 100 and the second stack 817) to operate at a faster transmission speed than the limiting speed of the third stack 821. Otherwise, the clock signal 811 must be set to the slowest clock speed in the worst case (e.g., the speed of the third stack 821 is limited).

[0118] By manufacturing and operating the stack 100 as described above, a scalable 3D-IC chip based on embedded ID is selected, and the I / O structure is quickly shared across the die across a heterogeneous stack of multiple semiconductor dies. In this way, a scalable, flexible, and low-cost solution for selecting semiconductor dies while sharing I / O structures can be achieved with minimal customization that does not depend on the number of semiconductor dies in the stack and provides better performance.

[0119] Figure 9A-9DAnother embodiment that can be used to store a unique identification number is shown, and the unique identification number is assigned to each semiconductor device (e.g., the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105) within the first stack 100. In this embodiment, instead of using different masks for the through-holes 307 (when the rest of the mask used is the same) to manufacture the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105, the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 are manufactured using exactly the same mask. In this way, after the manufacturing process is completed, each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 is exactly the same.

[0120] However, in this embodiment, instead of a unique arrangement of vias 307 for connecting ID line 301 to high voltage power line 305 and low voltage power line 303, fuse 901 is fabricated and then programmed to connect and / or disconnect ID line 301 from high voltage power line 305 and low voltage power line 303. By fabricating and then programming fuse 901, each semiconductor device (e.g., each of first semiconductor device 101, second semiconductor device 103, and third semiconductor device 105) can be fabricated in the same manner, and a unique identifier of each semiconductor device can be programmed into each semiconductor device after their placement within first stack 100 has been decided.

[0121] exist Figure 9A-9D In the particular embodiment shown, two lines (e.g., first ID line 302 and second ID line 304) can use four fuse structures to provide up to four unique identifiers for any of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105. For example, first observe Fig. 9A , if it is desired to assign a binary identifier "0", each fuse 901 connecting the first ID line 302 and the second ID line 304 to the high voltage power line 305 is programmed to be open, thereby disconnecting both the first ID line 302 and the second ID line 304 from the high voltage power line 305. In addition, each fuse 901 connecting the first ID line 302 and the second ID line 304 to the low voltage power line 303 is programmed to be closed, thereby connecting the first ID line 302 and the second ID line 304 to the low voltage power line 303. In this way, when the first ID line 302 and the second ID line 304 are read, a unique identifier "0" is obtained.

[0122] Fig. 9BAnother embodiment is shown in which a fuse 901 is utilized to program a unique identifier "1". In this embodiment, the fuse 901 is programmed to connect the first ID line 302 to the high voltage supply line 305 while disconnecting the first ID line 302 from the low voltage supply line 303. Similarly, the fuse 901 is programmed to connect the second ID line 304 to the low voltage supply line 303 and disconnect the second ID line 304 from the high voltage supply line 305. Thus, when the first ID line 302 and the second ID line 304 are read, a unique identifier "1" is obtained.

[0123] Fig. 9C Another embodiment is shown in which a unique identifier "2" is programmed using a fuse 901. In this embodiment, the fuse 901 is programmed to connect the first ID line 302 to the low voltage supply line 303 while disconnecting the first ID line 302 from the high voltage supply line 305. Similarly, the fuse 901 is programmed to connect the second ID line 304 to the high voltage supply line 305 and disconnect the second ID line 304 from the low voltage supply line 303. In this way, when the first ID line 302 and the second ID line 304 are read, a unique identifier "2" is obtained.

[0124] Fig.9D Yet another embodiment is shown in which fuse 901 is utilized to program a unique identifier "3". In this embodiment, fuse 901 is programmed to connect first ID line 302 to high voltage supply line 305 while disconnecting first ID line 302 from low voltage supply line 303. Similarly, fuse 901 is programmed to connect second ID line 304 to high voltage supply line 305 and disconnect second ID line 304 from low voltage supply line 303. Thus, when first ID line 302 and second ID line 304 are read, a unique identifier "3" is obtained.

[0125] Fig.10 An embodiment is shown in which fuses 901 in the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 are sequentially programmed after the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 are placed in the first stack 100 (e.g., in a known good stack (KGS)). In a specific embodiment, the first ID block 205 includes a first fuse block 1001, wherein the first fuse block 1001 includes the following: Figure 9A-9D The unprogrammed block of fuse 901 shown is not the first via block 402 (as described above with respect to Figure 4 In addition, the first stack_ID block 205 includes a first comparator 407 and a first AND gate 409, wherein the first AND gate 409 also receives a signal from the CS_ENI ball 228.

[0126] In this embodiment, fuses 901 are present in the first fuse block 1001, but additional structures are utilized to allow sequential programming of fuses 901. For example, in one embodiment, the first ID block 205 also includes a first fuse completion block 1003 that indicates whether programming of the first fuse block 1001 has been performed. Additionally, the fuse completion block 1003 has an output that sends a signal to an input of a fourth AND gate 1005, which also includes another input connected to the CS_ENI ball 228.

[0127] Using this structure, when it is desired to program the first semiconductor device 101, the CS_ENI ball 228 is set to "1", the default setting of the first fuse block 1001 is set so that the unique identifier is set to "0" and the direction defaults to, for example, "1", where "1" represents a forward-facing direction, and the first fuse completion block 1003 has a default setting of "0". By setting the CS_ENI ball 228 to "1", only the first selection signal 417 is activated, while the second selection signal 425 (in the second semiconductor device 103) and the third selection signal 433 (in the third semiconductor device 105) are not activated. This is because the default "0" setting of the first fuse completion block 1003 prevents the signal on the CS_ENI ball 228 from crossing the fourth AND gate 1005 and entering the overlying semiconductor devices (e.g., the second semiconductor device 103 and the third semiconductor device 105).

[0128] Once the first selection signal 417 of the first semiconductor device 101 has been activated, the fuses 901 within the first fuse block 1001 may be programmed. In an embodiment, the fuses 901 within the first fuse block 1001 are programmed by sending a programming signal to the first fuse block 1001 via the data in ball 233 or the data in and out ball 235. For example, in some embodiments, the programming signal may be sent to open or close the fuses in the first fuse block 1001 so as to set the unique identifier of the first fuse block 1001 to "1". However, any suitable method for programming the first semiconductor device 101 to have a unique identifier "1" may be used.

[0129] Once the first fuse block 1001 of the first semiconductor device 101 has been programmed, the first fuse completion block 1003 may be set to "1". In an embodiment, the first fuse block 1001 may be set by sending a programming signal via a fuse or anti-fuse located within the first fuse completion block 1003. However, any suitable method of setting the first fuse completion block 1003 may be utilized.

[0130] However, once the first completion block 1003 has been set to “1”, the fourth AND gate 1005 will now send the signal from the CS_ENI ball 228 into the second semiconductor device 103 through the fourth AND gate 1005. In an embodiment, the second semiconductor device 103 includes a second fuse block 1007, a second fuse completion block 1009, and a fifth AND gate 1011, wherein the second fuse block 1007, the second fuse completion block 1009, and the fifth AND gate 1011 are the same as the first fuse block 1001, the first fuse completion block 1003, and the fourth AND gate 1005.

[0131] Once the signal from the CS_ENI ball 228 enters the second semiconductor device 103, the programming process described above with respect to the programming of the first semiconductor device 101 may be repeated for the second semiconductor device 103. Starting with the CS_ENI ball 228 now entering the second semiconductor device 103, the second selection signal 425 is activated, and the fuse 901 within the second fuse block 1007 is programmed. Additionally, once the fuse 901 is programmed, the second fuse completion block 1009 is set to "1", and the signal from the CS_ENI ball 228 is forwarded to the third semiconductor device 105 via the fifth AND gate 1011.

[0132] Once the signal from the CS_ENI ball 228 enters the third semiconductor device 105, the programming process described above with respect to the programming of the first semiconductor device 101 may be repeated for the third semiconductor device 105. Starting with the CS_ENI ball 228 now entering the third semiconductor device 105, the third selection signal 433 is activated, and the fuse 901 within the third fuse block 1012 is programmed. Additionally, once the fuse 901 is programmed, the completed third fuse 1013 is set to "1" to complete the programming of the third semiconductor device 105.

[0133] Once all semiconductor devices in the stack have been programmed, and once all fuses have been set to "1," any desired group identifiers may be programmed. In an embodiment, the group identifier may be programmed simultaneously with the desired unique group ID. However, any suitable method of programming semiconductor devices with group IDs may be utilized.

[0134] By using the fuse 901, the same structure and process can be used to manufacture each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105. In addition, once the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 have been bonded and physically in place within the first stack 100, each can be programmed with their respective positions within the first stack 100. Such programming allows for a more efficient manufacturing process.

[0135] Additionally, in this embodiment, each individual semiconductor device (e.g., first semiconductor device 101, second semiconductor device 103, and third semiconductor device 105) may be given its own I / O definition based not only on the position within stack 100 but also on the direction within stack 100, wherein fuses 901 and unique identifiers are used to configure the I / O, and the I / O definition is associated with first external connection 113. In an embodiment, each of first semiconductor device 101, second semiconductor device 103, and third semiconductor device 105 may be manufactured such that first external connection 113 (e.g., ball grid array) may be designed to have X symmetry, Y symmetry, or complete X and Y symmetry.

[0136] When the first external connector 113 is symmetrical, then a single design can be used to utilize different orientations, rearward facing and forward facing, and the orientation can then be programmed during programming of the fuse 901. In particular, in addition to programming the fuse 901 to add a unique identifier, the fuse 901 can also be programmed to also include the orientation of each individual semiconductor device in the stack 100. In a particular embodiment, the first semiconductor device 101 can be physically placed in the stack 100 in a rearward facing manner, the second semiconductor device 103 can be physically placed in the stack 100 in a forward facing manner, and the third semiconductor device can be physically placed in the stack 100 in a rearward facing manner. Thus, during programming of the fuses 901, the fuses 901 may include one or more fuses 901 that indicate the orientation of each semiconductor device, such as the fuses 901 within the first semiconductor device 101 being programmed to indicate that the first semiconductor device 101 is in a facing-backward configuration, the fuses 901 within the second semiconductor device 103 being programmed to indicate that the second semiconductor device 103 is in a facing-forward configuration, and the fuses 901 within the third semiconductor device 105 being programmed to indicate that the third semiconductor device 105 is in a facing-backward configuration. However, any suitable configuration may be used.

[0137] Fig.11A An alternative embodiment is shown that can be used to help repair any input path into the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 in the event that one of the input paths becomes defective. First, observe that each of the first semiconductor device 101, the data output ball 231, the data input ball 233, and the data in-out ball 235, instead of including a single first external connection 113, includes multiple first external connections 113. For example, as Fig.11A As shown, the data output ball 231 includes at least four first external connections 113 (in Fig.11AOnly two first external connections 113 are shown in the cross section.

[0138] When the data output ball 231 includes a plurality of first external connections 113, a first I / O multiplexer unit 1101 is additionally added to the first semiconductor device 101. In an embodiment, the first I / O multiplexer unit 1101 includes a plurality of individual I / O multiplexers 1103 (see, for example, Fig. 11B ). In an embodiment where the data output ball 231 includes four first external connections 113, the first I / O multiplexer unit 1101 includes four of the plurality of separate I / O multiplexers 1103. However, any suitable number of first external connections 113 and any suitable number of the plurality of separate I / O multiplexers may be utilized.

[0139] Watch Now Fig. 11B , Fig. 11B FIG. 1 shows a schematic diagram of a first I / O multiplexer unit 1101. Fig. 11B In the illustrated embodiment, each of the plurality of individual I / O multiplexers 1103 has at least two inputs connected to at least one first external connection 113. For example, a first of the plurality of individual I / O multiplexers 1103 is connected to a first of the first external connections 113, a second of the first external connections 113, a second of the plurality of individual I / O multiplexers 1103 is connected to a first of the first external connections 113 and a third of the first external connections 113, and a third of the first external connections 113, a third of the plurality of individual I / O multiplexers 1103 is connected to a third of the first external connections 113 and a fourth of the first external connections 113, and a fourth of the plurality of individual I / O multiplexers 1103 is connected to a second of the first external connections 113 and a third of the first external connections 113. However, any suitable connections between the plurality of individual I / O multiplexers 1103 and the first external connections 113 may be utilized.

[0140] In addition, the selector of each I / O multiplexer 1103 can be connected to one or more control lines 1105, which are used to select the output from each independent I / O multiplexer 1103. With the presence of one or more control lines 1105, and because each individual I / O multiplexer 1103 has at least two inputs, when one of the inputs (for example, the second one of the first external connections 113) is defective (in Fig. 11BWhen a defect is detected in one of the first external connections 113 (indicated by "X" in the figure), one or more control lines 1105 can switch the corresponding individual I / O multiplexer 1103 to output a non-defective signal (e.g., a signal from the first one of the first external connections 113). In this way, a defect in one of the first external connections 113 can be repaired using an individual I / O multiplexer 1103.

[0141] return Fig.11A , the first semiconductor device 101 may also include any number of I / O multiplexer units, such as a second I / O multiplexer unit 1107. In an embodiment, the second I / O multiplexer unit 1107 is connected to multiple of the first external connections 113, such as multiple first external connections 113 associated with data in ball 233, data in and out of ball 235, or any other inputs and outputs associated with the first semiconductor device 101.

[0142] Additionally, for the second semiconductor device 103 and the third semiconductor device 105, any or all inputs of the second semiconductor device 103 or the third semiconductor device 105 may also have multiple connections that feed into each of the I / O multiplexer cells 1109. Each I / O multiplexer cell 1109 may be similar to the first I / O multiplexer cell 1101 and may be used to help repair defective connections between the second semiconductor device 103 and the third semiconductor device 105.

[0143] Although the above description applies the first I / O multiplexer unit 1101 to the data output ball 231, the data ball 233, and the data in-out ball 235, this is merely exemplary and not intended to be limiting. Instead, the I / O multiplexer unit may be applied to any input or output signal to the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105. All such combinations are fully intended to be included in the scope of the embodiments.

[0144] Fig.12Another embodiment is shown, where instead of operating each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 individually, the first in-out block 211, the second in-out block 219, and the third in-out block 227 are instead operated as an I / O array 1201, where portions of the I / O array 1201 are located in different regions of the semiconductor devices. For example, in an embodiment where the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105 are field programmable gate arrays (FPGAs), the first in-out block 211, the second in-out block 219, and the third in-out block 227 are each fabricated using a programmable gate array. In this way, each of the first in-out block 211, the second in-out block 219, and the third in-out block 227 can be programmed to provide different I / O communications between all semiconductor devices within the first stack 100.

[0145] By using the first in / out block 211, the second in / out block 219, and the third in / out block 227 as the I / O array 1201, the I / O array 1201 can be used as a general I / O array, thereby allowing a single input or output to be shared between all semiconductor devices, and all single inputs or outputs to be applied to each of the first semiconductor device 101, the second semiconductor device 103, and the third semiconductor device 105. This can be particularly useful in embodiments where the semiconductor devices are oriented in different directions from each other, for example, when the second semiconductor device 103 is in a different orientation from the first semiconductor device 101 and the third semiconductor device 105, the I / O can be redefined by a unique identifier of the same die, and different groups can be connected together by remapping the I / O controlled by the unique identifier.

[0146] By utilizing the unique identifiers and input / output structures described herein, faster data input / output can be achieved within a stack 100 of multiple semiconductor devices. This can be achieved using a universal solution that is independent of the number of semiconductor devices within the stack 100 and does not require complex customization of the I / O structures based on the precise location of each semiconductor device within the stack 100. In this way, better performance can be achieved with a low-cost, universal, flexible, and scalable solution.

[0147] In one embodiment, a semiconductor device includes: a first semiconductor device including: a first unique identifier structure; a first electrical input; and a first comparator including a first input connected to the first unique identifier structure and including a second input connected to the first electrical input; a second semiconductor device bonded to the first semiconductor device, the second semiconductor device including: a second unique identifier structure different from the first unique identifier structure; a second electrical input electrically connected to the first electrical input; and a second comparator including a third input connected to the second unique identifier structure and including a fourth input connected to the second electrical input. In one embodiment, the first unique identifier structure includes: a first reference voltage line; a second reference voltage line; and a plurality of identification lines, each of the plurality of identification lines being electrically connected to one of the first reference voltage line or the second reference voltage line through one or more through-holes. In one embodiment, the first unique identifier structure includes: a first reference voltage line; a second reference voltage line; and a plurality of identification lines, each of the plurality of identification lines being electrically connected to or isolated from one of the first reference voltage line or the second reference voltage line through one or more fuses. In one embodiment, an output from the first comparator is connected to an output region of the first semiconductor device. In one embodiment, an output from the output region is connected to a control block through a substrate, and the control block includes a plurality of delay lines. In one embodiment, the first semiconductor device further comprises: a first AND gate including a fifth input connected to the first comparator; and a sixth input connected to an external connector of the first semiconductor device. In one embodiment, an output from the second comparator is connected to an input region of the second semiconductor device.

[0148] In another embodiment, a semiconductor device includes: a first semiconductor die including: a first input region; a first output region; a first access region; a first identifier region; and a first external connection electrically connected to a first comparator, the first comparator also electrically connected to the first identifier region, the output of the first comparator connected to the first output region and the first access region; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including: a second input region; a second output region; a second access region; a second identifier region, the second identifier region having a different structure than the first identifier region; and a second comparator electrically connected to the first external connection through a via, wherein the output of the second comparator is connected to the second output region and the second access region. In one embodiment, an AND gate is also included, located between the output of the first comparator and the first access region. In one embodiment, the first identifier region includes a fuse. In one embodiment, the first identifier region includes a first set of lines in a first pattern and a first via in a second pattern, and wherein the second identifier region includes a second set of lines in the first pattern and includes a second set of vias in a third pattern different from the second pattern. In one embodiment, the input of the first output region is connected to the output of the second output region. In one embodiment, the input of the first access region is connected to the output of the second access region. In one embodiment, the first external connection is a stack identifier connection.

[0149] In yet another embodiment, a method of sending and receiving data includes: sending a stacker identifier signal to both a first semiconductor device and a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are bonded to each other; in the first semiconductor device, comparing the stacker identifier signal with a first unique identifier, wherein when the stacker identifier signal is the same as the first unique identifier, a first selection signal is generated; and in the second semiconductor device, comparing the stacker identifier signal with a second unique identifier, the second unique identifier is different from the first unique identifier, wherein when the stacker identifier signal is the same as the second unique identifier, a second selection signal is generated, the second selection signal is different from the first selection signal. In one embodiment, it also includes programming the first semiconductor device by sending a programming signal via a fuse. In one embodiment, it also includes: after programming the first semiconductor device and after bonding the first semiconductor device to the second semiconductor device, programming the second semiconductor device. In one embodiment, after programming the first semiconductor device and before programming the second semiconductor device, programming a programming completion indicator is programmed. In one embodiment, before sending the stack identifier signal, the first semiconductor device is manufactured using a first set of mask patterns and the second semiconductor device is manufactured using a second set of mask patterns, wherein each mask pattern in the first set of mask patterns and the second set of mask patterns is the same except for one mask pattern. In one embodiment, the one mask pattern is a pattern for a via.

[0150] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A stack of semiconductor devices, comprising: A first semiconductor device comprising: a first unique identifier structure; a first electrical input; a first comparator including a first input connected to the first unique identifier structure and including a second input connected to the first electrical input; a first AND gate including a fifth input connected to the first comparator; and a sixth input connected to an external connector of the first semiconductor device; A second semiconductor device is bonded to the first semiconductor device, the second semiconductor device comprising: a second unique identifier structure, different from the first unique identifier structure; a second electrical input electrically connected to said first electrical input; and A second comparator includes a third input connected to the second unique identifier structure and includes a fourth input connected to the second electrical input.

2. The stack of semiconductor devices according to claim 1, wherein: The first unique identifier structure comprises: a first reference voltage line; a second reference voltage line; and A plurality of identification lines, each of the plurality of identification lines being electrically connected to one of the first reference voltage line or the second reference voltage line through one or more through holes.

3. The stack of semiconductor devices according to claim 1, wherein: The first unique identifier structure comprises: a first reference voltage line; a second reference voltage line; and A plurality of identification lines, each of which is electrically connected to or isolated from one of the first reference voltage line or the second reference voltage line through one or more fuses.

4. The stack of semiconductor devices according to claim 1, wherein: An output from the first comparator is connected to an output region of the first semiconductor device.

5. The stack of semiconductor devices according to claim 4, wherein: Outputs from the output region are connected through a substrate to a control block, which includes a plurality of delay lines.

6. The stack of semiconductor devices according to claim 1, wherein: The first semiconductor device is a logic die.

7. The stack of semiconductor devices according to claim 1, wherein: An output from the second comparator is connected to an input region of the second semiconductor device.

8. A semiconductor device comprising: A first semiconductor die comprising: First input area; First output area; First entry and exit area; a first identifier region; and a first external connection electrically connected to a first comparator, the first comparator also electrically connected to the first identifier region, an output of the first comparator connected to the first output region and the first in-out region; and A second semiconductor die bonded to the first semiconductor die, the second semiconductor die comprising: Second input area; Second output area; Second entry and exit area; a second identifier region having a different structure than the first identifier region; and A second comparator is electrically connected to the first external connection through a through-hole, wherein an output of the second comparator is connected to the second output region and the second in-out region. 9 . The semiconductor device according to claim 8 , further comprising an AND gate between the output of the first comparator and the first in-out region.

10. The semiconductor device according to claim 8, wherein The first identifier area includes a fuse.

11. The semiconductor device according to claim 8, wherein The first identifier region includes a first set of lines in a first pattern and a first set of vias in a second pattern, and wherein the second identifier region includes a second set of lines in the first pattern and includes a second set of vias in a third pattern different from the second pattern.

12. The semiconductor device according to claim 8, wherein The input of the first output region is connected to the output of the second output region.

13. The semiconductor device according to claim 8, wherein: The input of the first in-out zone is connected to the output of the second in-out zone.

14. The semiconductor device according to claim 8, wherein: The first external connection is a stack identifier connection.

15. A method for sending and receiving data, the method comprising: sending a stack identifier signal to both a first semiconductor device and a second semiconductor device, wherein the first semiconductor device and the second semiconductor device are bonded to each other; comparing the stacker identifier signal with a first unique identifier within the first semiconductor device, wherein a first selection signal is generated when the stacker identifier signal is identical to the first unique identifier; comparing the stacker identifier signal to a second unique identifier in the second semiconductor device, the second unique identifier being different from the first unique identifier, wherein when the stacker identifier signal is the same as the second unique identifier, generating a second selection signal, the second selection signal being different from the first selection signal; programming the first semiconductor device by sending a programming signal through a fuse; and After programming the first semiconductor device and after bonding the first semiconductor device to the second semiconductor device, programming the second semiconductor device.

16. The method according to claim 15, wherein: The first semiconductor device is a logic device.

17. The method according to claim 15, wherein: The fuse is located in the first semiconductor device.

18. The method according to claim 17, wherein: After programming the first semiconductor device, a program completion indicator is programmed before programming the second semiconductor device.

19. The method according to claim 15, wherein: Prior to transmitting the stack identifier signal, the first semiconductor device is manufactured using a first set of mask patterns and the second semiconductor device is manufactured using a second set of mask patterns.

20. The method according to claim 15, wherein: The first semiconductor device includes active circuits including logic circuits and memory circuits.

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