Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure. The semiconductor structure includes: a gallium nitride (GaN) layer located on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source component and a drain component disposed on the AlGaN layer and inserted by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source component, wherein the field plate includes a stepped structure. Embodiments of the present application also relate to a method for forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] In semiconductor technology, gallium nitride (GaN) is used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs), due to its properties. In some instances, GaN-based devices are used in integrated circuits to obtain high breakdown voltage and low on-resistance. However, breakdown voltage is a relevant factor. Considering breakdown voltage and other device parameters including threshold voltage, existing GaN-based devices are far from satisfactory. Therefore, there is a need for a structure of a GaN-based device with an enhanced breakdown voltage and a method for manufacturing the same for solving the above-mentioned problems. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, including: a gallium nitride (GaN) layer located on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the gallium nitride layer; a gate stack disposed on the aluminum gallium nitride layer; a source component and a drain component disposed on the aluminum gallium nitride layer and inserted by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source component, wherein the field plate includes a stepped structure.

[0004] Some other embodiments of the present application provide a semiconductor structure, including: a first III-V compound layer, located on a substrate; a second III-V compound layer, directly located on the first III-V compound layer, the second III-V compound layer being different in composition from the first III-V compound layer and also including aluminum; a gate stack, located on the second III-V compound layer; a source component and a drain component, disposed on the second III-V compound layer; and a field plate, disposed above the gate stack and electrically connected to the source component, wherein the field plate includes at least three segments having a stepped structure.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first III-V compound layer on a substrate; forming a second III-V compound layer on the first III-V compound layer, wherein the second III-V compound layer is different in composition from the first III-V compound layer and also includes aluminum; forming a gate stack on the second III-V compound layer; forming a source component and a drain component on the second III-V compound layer, and the source component and the drain component are inserted by the gate stack; and forming a field plate above the gate stack and electrically connecting the field plate to the source component, wherein the field plate includes at least three segments configured in a stepped structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1a is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed according to some embodiments;

[0008] Figure 1b is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN)-based device constructed according to some embodiments;

[0009] Figures 2a to 8a According to the combination of various embodiments Figure 1a A cross-sectional view of a gate structure in a semiconductor structure;

[0010] Figures 2b to 8b According to each embodiment, Figures 2a to 8a The gate stack of Figure 1a Schematic diagram of the semiconductor structure;

[0011] Fig. 9 is a cross-sectional view of a semiconductor structure having a GaN-based transistor constructed according to some embodiments;

[0012] Fig.10 is a cross-sectional view of a semiconductor structure having a gallium nitride (GaN)-based transistor constructed according to some embodiments;

[0013] Fig.11 A method for manufacturing a semiconductor structure having a GaN-based device (such as Figure 1a , Figure 1b , Fig. 9 and Fig.10 Flowcharts of those semiconductor structures);

[0014] Figures 12 to 19 A semiconductor structure (such as Figure 1a , Fig. 9 and Fig.10 cross-sectional views of those semiconductor structures);

[0015] Figure 20 to Figure 24 A semiconductor structure (such as Figure 1a , Fig. 9 and Fig.10 cross-sectional views of those semiconductor structures);

[0016] Figure 25 to Figure 27 is a cross-sectional view of a semiconductor structure at various stages of fabrication according to various embodiments; and

[0017] Fig.28 is a graphical representation of various characteristic data of a gallium nitride (GaN)-based device according to some embodiments. DETAILED DESCRIPTION

[0018] It can be considered that the following disclosure provides many different embodiments or examples for implementing the different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. The present invention may repeat reference numerals and / or characters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Figure 1a is a cross-sectional view of one embodiment of a semiconductor structure (or device structure) 100 having a gallium nitride (GaN) based transistor. Figure 1b is a cross-sectional view of one embodiment of a semiconductor structure 180 having a GaN-based device. Figures 2a to 8a According to the present invention, various embodiments are combined in Figure 1a A cross-sectional view of a gate structure in a semiconductor structure. Figures 2b to 8b According to various embodiments of the present invention, Figures 2a to 8a The gate structure Figure 1a Schematic diagram of the semiconductor structure. Figure 1a , Figure 1b , Figures 2a to 8a , Figures 2b to 8b Together with the other figures, a GAN-based device (such as semiconductor structure 100 (or 180)) and a method of manufacturing the same are described.

[0020] refer to Figure 1aThe semiconductor structure 100 includes a sapphire substrate 110. Optionally, the substrate may be a silicon carbide (SiC) substrate or a silicon substrate. For example, the silicon substrate may be a (111) silicon wafer.

[0021] The semiconductor structure 100 also includes a heterojunction formed between two different semiconductor material layers, such as material layers with different band gaps. For example, the semiconductor structure 100 includes a non-doped narrow-band gap channel layer and a wide-band gap n-type donor supply layer. In one embodiment, the semiconductor structure 100 includes a first III-V compound layer (or buffer layer) 114 formed on the substrate 110 and a second III-V compound layer (or barrier layer) 116 formed on the buffer layer 114. The buffer layer 114 and the barrier layer 116 are compounds made of the III-V group in the periodic table. However, the buffer layer 114 and the barrier layer 116 are different from each other in composition. The buffer layer 114 is undoped or unintentionally doped (UID). In the present embodiment of the semiconductor structure 100, the buffer layer 114 includes a gallium nitride (GaN) layer (also referred to as the GaN layer 114). The barrier layer 116 includes an aluminum gallium nitride (AlGaN) layer (also referred to as the AlGaN layer 116). In some embodiments, the GaN layer 114 and the AlGaN layer 116 may be in direct contact with each other.

[0022] In the depicted embodiment, the GaN layer 114 is undoped. Optionally, due to the precursor used to form the GaN layer 114, the GaN layer 114 is unintentionally doped, such as lightly doped with n-type. The GaN layer 114 can be epitaxially grown by metal organic vapor phase epitaxy (MOVPE) using a gallium-containing precursor and a nitrogen-containing precursor. The gallium-containing precursor includes trimethyl gallium (TMG), trimethylaluminum (TEG) or other suitable chemicals. The nitrogen-containing precursor includes ammonia (NH3), tert-butylamine (TBAm), phenylhydrazine or other suitable chemicals. In one example, the thickness of the GaN layer 114 ranges between about 0.5 microns and about 10 microns. In another example, the thickness of the GaN layer 114 is about 2 microns.

[0023] The AlGaN layer 116 is n-type doped, such as lightly n-type doped. Alternatively or additionally, the AlGaN layer 116 has an n-type dopant introduced from an adjacent layer. In some embodiments, the AlGaN layer 116 is p-type doped, such as lightly p-type doped. The AlGaN layer 116 is deposited on the GaN layer 114 by selective epitaxial growth. The AlGaN layer 116 can be epitaxially grown by MOVPE using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor includes TMA, TEA, or other suitable chemicals. The gallium-containing precursor includes TMG, TEG, or other suitable chemicals. The nitrogen-containing precursor includes ammonia, TBAm, phenylhydrazine, or other suitable chemicals. In one example, the thickness of the AlGaN layer 116 ranges between about 5 nanometers and about 50 nanometers. In another example, the thickness of the AlGaN layer 116 is about 15 nanometers.

[0024] The electrons in the AlGaN layer 116 fall into the GaN layer 114, thereby generating a very thin layer 118 of high-mobility conducting electrons in the GaN layer 114. This thin layer 118 is referred to as a two-dimensional electron gas (2-DEG) that forms a carrier channel. The thin layer 118 of 2-DEG is located at the interface of the AlGaN layer 116 and the GaN layer 114. Therefore, the carrier channel has a high electron mobility because the GaN layer 114 is undoped or unintentionally doped, and the electrons can move freely without collision or substantially reduced collision with impurities.

[0025] The semiconductor structure 100 also includes a source component 120A and a drain component 120B formed on the substrate 110 and configured to be electrically connected to the channel layer 118. The source component 120A and the drain component 120B are also collectively referred to as a source / drain (S / D) component 120. The S / D component 120 includes one or more conductive materials. For example, the S / D component 120 includes a metal selected from the group consisting of titanium, aluminum, nickel and gold. The S / D component 120 can be formed by a process such as physical vapor deposition (PVD) or other suitable techniques. A thermal annealing process can be applied to the S / D component 120 so that the S / D component 120 and the AlGaN layer 116 react to form an alloy to perform effective electrical connection from the S / D component 120 and the channel to the ohmic contact. As an example, a rapid thermal annealing (RTA) device and process are used for thermal annealing.

[0026] The gate stack 122 is formed on the barrier layer 116 and interposed between the source and drain components 120. In some embodiments, the gate stack 122 includes a junction isolation component disposed on the barrier layer (in this embodiment, an AlGaN layer) 116. The junction isolation component includes at least one doped semiconductor layer so as to form a pn junction with the barrier layer 116. In the depicted embodiment, the junction isolation component includes at least one p-type doped III-V compound, and the barrier layer 116 is n-type doped. In yet another embodiment, the p-type doped III-V compound layer is a p-type doped GaN (p-GaN) layer, wherein the GaN is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. According to some embodiments, the dopant concentration ranges from 10 19 cm -3 with 10 21 cm -3 In the depicted embodiment, the junction isolation feature of p-GaN and the barrier layer 116 of n-AlGaN are configured to form a pn junction to provide isolation and capacitive coupling with the channel layer 118. In some embodiments, the gate stack 122 includes a conductive material layer, such as a metal, a metal alloy, other suitable conductive material, or a combination thereof, disposed on the junction isolation feature and serving as a gate electrode. The conductive material layer is configured for voltage biasing and electrical coupling with the channel layer.

[0027] In some instances, the gate stack 122 includes at least one n-type doped semiconductor layer and one p-type doped semiconductor layer to form a diode, which can be an n-type doped III-V compound layer and a p-type doped III-V compound layer, respectively. In another example, the n-type doped III-V compound layer and the p-type doped III-V compound layer are an n-type doped GaN layer (or n-GaN layer) and a p-type doped GaN layer (p-GaN layer), respectively. The diode in the gate stack provides a junction isolation effect. In the present embodiment, the gate stack 122, the S / D component 120, and the 2-DEG channel in the buffer layer 114 are configured as a GaN-based transistor. Specifically, the transistor configured in this way is also referred to as a high electron mobility transistor (HEMT).

[0028] Figures 2a to 8a Various embodiments of a gate stack 122 of a semiconductor structure 100 constructed according to various aspects of the present invention are shown. The gate stack 122 is also described according to various embodiments. Figure 2aIn one embodiment shown, the gate stack 122 includes a metal layer 124 and a junction isolation feature 126 disposed below the metal layer 124. The metal layer 124 may include any suitable metal or metal alloy, such as copper, aluminum, tungsten, nickel, cobalt, other suitable metals, or combinations thereof. The junction isolation feature 126 includes at least one doped semiconductor layer so as to form a pn junction with the AlGaN layer 116. In the depicted embodiment, the junction isolation feature 126 includes at least one p-type doped semiconductor layer, and the AlGaN layer 116 is n-type doped. In yet another embodiment, the p-type doped III-V compound layer is a p-type doped GaN layer (p-GaN layer).

[0029] Figure 2b Shows that there is Figure 2a Schematic diagram of a GaN-based transistor of the semiconductor structure 100 having a gate stack 122. Figure 2b In FIG. 1 , “G”, “S” and “D” represent gate, source and drain, respectively. A 2-DEG channel is defined between the source and drain. A diode 138 a is formed between the p-GaN layer 130 and the barrier layer 116 having an n-type dopant. The resulting capacitance from the diode 138 a is reduced, while the device switching speed is increased.

[0030] Optionally, the junction isolation component 126 may also include another n-type doped GaN layer, another p-type doped GaN layer, or both. A junction (or diode) is formed between each pair of adjacent n-GaN layers and p-GaN layers. Various diodes between the n-GaN and p-GaN layers are electrically configured in series. These diodes not only provide isolation from the channel to the gate electrode with reduced gate leakage, but also increase the device switching speed, as explained below. Since various diodes are coupled in series, the corresponding capacitors are also coupled in series. Therefore, the total capacitance of the series capacitors will be less than the capacitance of any one of them. Therefore, due to the reduction in capacitance, the device switching speed is improved.

[0031] In one embodiment, the interface between the metal layer and the diode is an ohmic contact formed by thermal annealing, wherein the annealing temperature ranges between about 800° C. and about 900° C. In another embodiment, the interface between the metal layer and the diode is a Schottky contact. In this case, the process for forming the gate stack is free of thermal annealing.

[0032] exist Figure 3aIn one embodiment shown, the junction isolation feature 126 of the gate stack 122 includes a p-GaN layer 130 and an n-GaN layer 132 disposed on the p-GaN layer 130. The p-GaN layer 130 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. In one embodiment, the p-GaN layer 130 can be formed by metal organic chemical vapor deposition (MOCVD) or other suitable techniques. In another embodiment, the thickness of the p-GaN layer 130 ranges between about 1 nm and about 100 nm. The n-GaN layer 132 is doped with an n-type dopant such as silicon, oxygen, or a combination thereof. In one embodiment, the n-GaN layer 132 can be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the n-GaN layer 132 ranges between about 1 nm and about 100 nm.

[0033] Figure 3b Shows that there is Figure 3a Schematic diagram of a GaN-based transistor of the semiconductor structure 100 having a gate stack 122. Figure 3b In FIG. 1 , “G”, “S” and “D” represent gate, source and drain, respectively. A 2-DEG channel is defined between the source and drain. A diode 138 a is formed between the p-GaN layer 130 and the barrier layer 116 having an n-type dopant. A second diode 138 b is formed between the p-GaN layer 130 and the n-GaN layer 132. The diodes 138 a and 138 b are configured in series. The resulting capacitance from the diodes 138 a and 138 b is reduced, while the device switching speed is increased.

[0034] exist Figure 4a In another embodiment shown, the junction isolation feature 126 of the gate stack 122 is similar to Figure 3a 1. The junction isolation feature 126 in FIG. 1 is shown in FIG. 1, but further includes an additional p-GaN layer 134 disposed on the n-GaN layer 132. The additional p-GaN layer 134 and the n-GaN layer 132 are configured to form another diode for additional isolation effect. The additional p-GaN layer 134 is similar to the p-GaN layer 130 in composition and formation. For example, the p-GaN layer 134 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof.

[0035] Figure 4b Shows that there is Figure 4aSchematic diagram of a GaN-based transistor of a semiconductor structure 100 having a gate stack 122. Symbols "G", "S" and "D" represent a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and the drain. A diode 138a is formed between the p-GaN layer 130 and the barrier layer 116 having an n-type dopant. A second diode 138b is formed between the p-GaN layer 130 and the n-GaN layer 132. A third diode 138c is formed between the n-GaN layer 132 and the p-GaN layer 134. Diodes 138a, 138b and 138c are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is further reduced, and the device switching speed is further increased.

[0036] exist Figure 5a In another embodiment shown, the junction isolation feature 126 of the gate stack 122 is similar to Figure 3a 1, but further includes an additional p-GaN layer 134 disposed on the n-GaN layer 132 and an additional n-GaN layer 136 disposed on the p-GaN layer 134. The additional p-GaN layer 134 and the additional n-GaN layer 136 are similar in composition and formation to the p-GaN layer 130 and the n-GaN layer 132, respectively. For example, the n-GaN layer 136 is doped with an n-type dopant such as silicon or oxygen.

[0037] Figure 5b Shows that there is Figure 5a Schematic diagram of a GaN-based transistor of a semiconductor structure 100 having a gate stack 122. Symbols "G", "S" and "D" represent a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and the drain. A diode 138a is formed between the p-GaN layer 130 and the barrier layer 116 having an n-type dopant. A second diode 138b is formed between the p-GaN layer 130 and the n-GaN layer 132. A third diode 138c is formed between the n-GaN layer 132 and the p-GaN layer 134. A fourth diode 138d is formed between the p-GaN layer 134 and the n-GaN layer 136. Diodes 138a, 138b, 138c and 138d are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is further reduced, and the device switching speed is thereby further increased.

[0038] exist Figure 6a In one embodiment shown, the junction isolation feature 126 of the gate stack 122 includes an n-GaN layer 132 and a p-GaN layer 130 disposed on the n-GaN layer 132 . Figure 5a The gate stack 122 is similar to Figure 3aThe gate stack 122 of the embodiment of the present invention is shown in FIG. 1 , but the p-GaN layer 130 and the n-GaN layer 132 are configured differently. The p-GaN layer 130 is doped with a p-type dopant such as magnesium, calcium, zinc beryllium, carbon, or a combination thereof. In one embodiment, the p-GaN layer 130 can be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the p-GaN layer 130 ranges between about 1 nm and about 100 nm. The n-GaN layer 132 is doped with an n-type dopant such as silicon, oxygen, or a combination thereof. In one embodiment, the n-GaN layer 132 can be formed by MOCVD or other suitable techniques. In another embodiment, the thickness of the n-GaN layer 132 ranges between about 1 nm and about 100 nm.

[0039] Figure 6b Shows that there is Figure 6a Schematic diagram of a GaN-based transistor of the semiconductor structure 100 having a gate stack 122. A diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132 for isolation, thereby preventing gate leakage.

[0040] exist Figure 7a In another embodiment shown, the junction isolation feature 126 of the gate stack 122 is similar to Figure 3a The junction isolation feature 126 in FIG. 1 is similar to that in FIG. 1 , but has a different structure. Specifically, an n-GaN layer 132 is disposed on the barrier layer 116. A p-GaN layer 130 is disposed on the n-GaN layer 132. An additional n-GaN layer 136 is disposed on the p-GaN layer 130.

[0041] Figure 7b Shows that there is Figure 7a Schematic diagram of a GaN-based transistor of the semiconductor structure 100 with a gate stack 122. One diode 138e is formed between the p-GaN layer 130 and the n-GaN layer 132. Another diode 138f is formed between the p-GaN layer 130 and the n-GaN layer 136. The diodes 138e and 138f are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes provides isolation to prevent gate leakage and also enhances device switching speed.

[0042] exist Figure 8a In another embodiment shown, the junction isolation feature 126 of the gate stack 122 is similar to Figure 5a The junction isolation feature 126 in FIG. 1 is the same as that in FIG. Figure 8aThe gate stack 122 in FIG. 1 includes an n-GaN layer 132 on the barrier layer 116, a p-GaN layer 130 on the n-GaN layer 132, an additional nn-GaN layer 136 on the p-GaN layer 130, and an additional p-GaN layer 134 disposed on the additional n-GaN layer 136. Each of the n-GaN layer and the p-GaN layer is similar in composition and formation to the Figure 4a For example, the n-GaN layer 136 is doped with an n-type dopant such as silicon or oxygen.

[0043] Figure 8b Shows that there is Figure 8a Schematic diagram of a GaN-based transistor of a semiconductor structure 100 having a gate stack 122. Symbols "G", "S" and "D" represent a gate, a source and a drain, respectively. A 2-DEG channel is defined between the source and the drain. A diode 138e is formed between the n-GaN layer 132 and the p-GaN layer 130. A second diode 138f is formed between the p-GaN layer 130 and the additional n-GaN layer 136. A third diode 138g is formed between the n-GaN layer 136 and the additional p-GaN layer 134. Diodes 138e, 138f and 138g are configured in series. The resulting capacitance between the gate electrode and the channel from these diodes is reduced, and the device switching speed is further increased thereby.

[0044] Back to Figure 1a, the semiconductor structure 100 also includes a field plate 148, which is configured to be adjacent to the gate stack 122 and is designed to redistribute the electric field distribution, thereby reducing the surface field (RESURF) and increasing the breakdown voltage. According to various embodiments, there may also be other advantages, such as improving the quality factor (FOM), such as Qgd, Ronsp*Cgd, Ron*Coss, Ron*Ciss, Ron*Crss, etc. For example, the corresponding GaN-based transistor can be stabilized by reducing the offset or non-offset of the threshold voltage. In the depicted embodiment, the field plate 148 is disposed on the first dielectric material layer 150 and is positioned between the gate stack 122 and the drain component 120B. The field plate 148 extends from the bottom of the trench toward the drain component 120B to the outside of the trench. Specifically, in the depicted embodiment, the field plate 148 is arranged to be away from the drain component 120B in the horizontal direction. In other words, the field plate 148 is configured not to overlap with the drain component 120B in a top view. Field plate 148 includes a conductive material, such as a metal, a metal alloy, a silicide, other suitable conductive materials, or a combination thereof. In some embodiments, field plate 148 includes titanium nitride, titanium, titanium aluminum, aluminum copper, or a combination thereof. In the depicted embodiment, field plate 148 is electrically connected to source component 120A through conductive elements 152 and 154 of the interconnect structure. Compared with the field plate connected to the gate, the source has a stable voltage (0V or Vss), which does not have a trapping effect below the field plate. In some instances, conductive element 152 may include a metal line and a through hole extending vertically from source component 120A to the metal line. Conductive element 154 may include a through hole extending from field plate 148 to conductive element 152. Conductive elements 152 and 154 are at least partially embedded in another dielectric material layer 156.

[0045] Specifically, the field plate 148 has a stepped structure (staircase structure) having at least three segments connected in sequence and oriented alternately in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely a first segment 148A extending horizontally (along the X direction), a second segment 148B extending vertically (along the Y direction) from the first segment 148A, and a third segment 148C extending horizontally (along the X direction) from the second segment 148B. The disclosed stepped structure of the field plate 148 can effectively reduce the surface field and enhance the breakdown voltage, and is beneficial to other performance parameters. In the off-state operation, the path from the drain to the source may have a huge voltage drop, and the peak electric field will appear in the boundary (such as the gate edge, the field plate edge, the metal edge...). More steps in the stepped structure of the field plate 148 can provide more electric field peaks and maintain more voltage drop in the channel, which is the voltage drop between the drain and the source and is a component of the electric field. The structure and formation of the field plate 148 will be described in further detail later.

[0046] Steering Figure 1b FIG. 1 is a cross-sectional view of a semiconductor structure 180 having a gallium nitride (GaN)-based device constructed according to one or more embodiments. The semiconductor structure 180 is similar to Figure 1a The semiconductor 100 in FIG. However, the semiconductor structure 180 includes a GaN-based device having two electrodes and not a gate, also referred to as a GaN-based diode. The semiconductor structure 180 also includes a field plate 148 similarly configured between the source component 120A and the drain component 120B, and the field plate 148 is electrically connected to the source component 120A, such as through conductive components 152 and 154. The field plate 148 extends from the bottom of the trench toward the drain component 120B to the outside of the trench. Specifically, the field plate 148 is arranged to be horizontally away from the drain component 120B. In other words, the field plate 148 is configured not to overlap with the drain 120B in a top view.

[0047] Fig. 9 is a cross-sectional view of a semiconductor structure 182 having a GaN-based transistor constructed according to one or more other embodiments. Fig. 9 , Figures 2a to 8a and Figures 2b to 8b , together describe a semiconductor structure 182 and a method for manufacturing the same.

[0048] The semiconductor structure 182 is similar to Figure 1a The semiconductor structure 100 of FIG. 1 is a semiconductor structure 100 of FIG. 1 , but further includes a dielectric material layer (or insulating layer) 141 formed on the barrier layer 116 and disposed between the source component 120A and the drain component 120B. Specifically, the dielectric material layer 141 is formed between the barrier layer 116 and the gate stack 122. According to various examples, the dielectric material layer 141 includes a dielectric material selected from the following: silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), zinc oxide (ZnO2), hafnium oxide (HfO2), or a combination thereof. In one embodiment, the thickness of the dielectric material layer 141 ranges between about 3 nm and about 100 nm. The dielectric material layer 141 can be formed by any suitable manufacturing technique such as chemical vapor deposition (CVD), PVD, atomic layer deposition (ALD), or thermal oxidation. The dielectric material layer 141 also provides isolation to prevent gate leakage and also improves the device switching speed.

[0049] Fig. 9 The gate stack 122 is similar to Figure 1a For example, the gate stack 122 includes a junction isolation feature 126 disposed on the dielectric material layer 141 and a metal layer 124 disposed on the junction isolation feature 126. In addition, according to various embodiments, the gate stack 122 may have Figures 2a to 8a Any of the structures shown.

[0050] exist Fig. 9 In the embodiment, the semiconductor structure 182 also includes a field plate 148, which is configured adjacent to the gate stack 122 and is designed to redistribute the electric field distribution, thereby reducing the surface field and increasing the breakdown voltage. The field plate 148 is similar in structure, configuration, and formation to Figure 1a Field plate 148. In the depicted embodiment, field plate 148 is disposed on dielectric material layer 150 and positioned between gate stack 122 and drain component 120B. Field plate 148 extends from the bottom of the trench toward drain component 120B to the outside of the trench. Specifically, field plate 148 is disposed horizontally away from drain 120B. In other words, field plate 148 is configured not to overlap drain 120B in a top view. Field plate 148 includes a conductive material, such as a metal, a metal alloy, a silicide, or other suitable conductive material. In the depicted embodiment, field plate 148 is electrically connected to source component 120A through conductive elements 152 and 154 of an interconnect structure. Specifically, field plate 148 has a stepped structure having at least three segments that are sequentially connected and oriented alternately in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely a first segment 148A extending horizontally (along the X direction), a second segment 148B extending vertically (along the Y direction) from the first segment, and a third segment 148C extending horizontally (along the X direction) from the second segment.

[0051] Fig.10 FIG. 1 is a cross-sectional view of one embodiment of a semiconductor structure 184 having a GaN-based transistor. The semiconductor structure 184 is similar to Figure 1a The semiconductor structure 100 of FIG. 1 is shown in FIG. 1 , but the gate stack 122 further includes a dielectric material layer (or insulating layer) 144 disposed between the metal layer 124 and the junction isolation component 126. According to various examples, the dielectric material layer 144 includes a dielectric material selected from the group consisting of: SiO2, Si3N4, Al2O3, Ta2O, TiO2, ZnO2, HfO2, or a combination thereof. In one embodiment, the thickness of the dielectric material layer 144 ranges between about 3 nm and about 100 nm. The dielectric material layer 144 can be formed by any suitable manufacturing technique such as CVD, PVD, ALD, or thermal oxidation. The dielectric material layer 144 also provides isolation to prevent gate leakage and also increases the device switching speed. The junction isolation component 126 can have different structures, such as Figure 2a to Figure 2b to Figure 8a to Figure 8b Any of those structures shown.

[0052] Fig.10The semiconductor structure 184 in FIG. 1 also includes a field plate 148 that is configured adjacent to the gate stack 122 and is designed to redistribute the electric field distribution, thereby reducing the surface field and increasing the breakdown voltage. The field plate 148 is similar in structure, configuration, and formation to FIG. Figure 1a The field plate 148 is provided on the dielectric material layer 150 and is positioned between the gate stack 122 and the drain component 120B. The field plate 148 includes a conductive material, such as a metal, a metal alloy, a silicide, or other suitable conductive material or a combination thereof. In the depicted embodiment, the field plate 148 is electrically connected to the source component 120A through the conductive elements 152 and 154 of the interconnect structure. Specifically, the field plate 148 has a stepped structure having at least three segments that are sequentially connected and alternately oriented in different directions, such as two orthogonal directions (X and Y directions). In the depicted embodiment, the field plate 148 includes three segments, namely, a first segment 148A extending horizontally (along the X direction), a second segment 148B extending vertically (along the Y direction) from the first segment 148A, and a third segment 148C extending horizontally (along the X direction) from the second segment 148B.

[0053] Fig.11 1 is a flow chart of a method 200 of manufacturing a semiconductor structure having a III-V compound device, or specifically a GaN-based device, such as 100, 180, 182, or 184, according to some embodiments. The method 200 includes a block 202 to form a III-V semiconductor compound-based device, such as including Figure 1a The GaN-based transistor of the channel layer 118, the source component 120A, the drain component 120B and the gate stack 122 of the present invention. At box 204, a first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition (such as CVD) and then additionally by a CMP process. At box 206, the first dielectric layer 150 is patterned to form a trench in the first dielectric layer 150. Box 206 may include one or more patterning processes to form a trench with a desired profile so that a field plate 148 with a desired stepped structure is formed. At 208, a conductive layer is deposited on the first dielectric layer 150 and in the trench of the first dielectric layer 150 by a suitable deposition, such as PVD. At 210, the conductive layer is patterned to form a field plate 148 with a stepped structure. The field plate 148 extends from the bottom of the trench toward the drain component 120B to the outside of the trench. At 212 , an interconnect structure is formed on the III-V semiconductor compound based device and the field plate 148 such that the field plate 148 is electrically connected to the source feature 120A. The method 200 may further include other fabrication processes performed at block 214 before, during, and / or after the above operations.

[0054] Figures 12 to 192 is a cross-sectional view of a semiconductor structure 100 constructed according to some embodiments at different stages of fabrication. A method 200 for fabricating a III-V compound-based device is described in detail below with reference to these figures. The semiconductor structure 100 is used as an exemplary structure fabricated by the method 200 .

[0055] refer to Fig.12 A III-V semiconductor compound based device, such as a GaN based transistor, is formed on a substrate 110. The III-V semiconductor compound based device includes a channel layer 118, a source feature 120A, a drain feature 120B, and a gate stack 122 configured to form a functional field effect transistor. Figure 1a The structure and formation of III-V semiconductor compound based devices are described in . In particular, the gate stack 122 can have different structures, such as Figure 1a , Figures 2a to 8b and Figures 9 and 10 Those structures shown.

[0056] refer to Fig.13 A first dielectric layer 150 is formed on the III-V semiconductor compound-based device by deposition, such as CVD, flowable CVD (CVD), spin coating, ALD, other suitable deposition, or a combination thereof. The first dielectric layer 150 includes one or more dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials, other suitable dielectric materials, or a combination thereof. In some embodiments, the formation of the first dielectric layer 150 includes deposition and CMP.

[0057] refer to Fig.14, the first dielectric layer 150 is patterned to form a trench 160 in the first dielectric layer 150. The operation for patterning the first dielectric layer 150 may include one, two, or more patterning processes applied to the first dielectric layer 150 to form the trench 160 having a desired profile, so that the field plate 148 having the desired stepped structure is subsequently formed. For example, the first dielectric layer 150 may be patterned two, three, or more times so that the trench 160 includes a stepped profile. The patterning process may include forming a hard mask and applying an etching process to the first dielectric layer 150 through the opening of the hard mask to form a trench in the first dielectric layer 150. The hard mask may be formed by a procedure including depositing a hard mask material layer and etching the hard mask material layer through the opening of the patterned photoresist layer. In some examples, the hard mask material layer includes silicon oxide and silicon nitride that are subsequently deposited on the first dielectric layer 150. The hard mask layer may be formed by thermal oxidation, CVD, ALD, or any other suitable method. The procedure for forming a hard mask also includes forming a patterned photoresist (resist) layer by a photolithography process, and etching a hard mask material layer through the opening of the patterned resist layer to transfer the opening to the hard mask material layer. An exemplary photolithography process may include forming a resist layer, exposing the resist by a photolithography exposure process, performing a post-exposure baking process, and generating a photoresist layer to form a patterned photoresist layer. The photolithography process may optionally be replaced by other techniques such as electron beam writing, ion beam writing, maskless patterning or molecular printing. In some other embodiments, the patterned photoresist layer can be directly used as an etching mask for an etching process to form a groove. The etching process may include dry etching, wet etching, or a combination thereof with one or more suitable etchants to etch the first dielectric layer 150.

[0058] refer to Fig.15 , a conductive layer 148 is deposited on the first dielectric layer 150 and in the trench 160 of the first dielectric layer 150 by suitable deposition, such as PVD. The conductive layer 148 includes a conductive material, such as a metal, a metal alloy, a silicide, other suitable conductive materials, or a combination thereof. In some embodiments, the conductive layer 148 includes titanium nitride, titanium, titanium aluminum, aluminum copper, or a combination thereof. In other embodiments, the conductive layer 148 includes two or more conductive material layers, such as a barrier layer and a fill metal layer. In other embodiments, the barrier layer includes titanium nitride and titanium, or tantalum nitride and tantalum, and the fill metal layer includes aluminum copper, aluminum, tungsten, other suitable metals, or a combination thereof.

[0059] refer to Fig.16, the conductive layer 148 is patterned to form a field plate, also labeled 148. The field plate 148 has a stepped structure. The patterning process includes a patterning process similar to the patterning process to pattern the first dielectric layer 150 but with different one or more different etchants and process conditions. For example, the patterning process may include a photolithography process and etching, and a patterned hard mask may be additionally used as an etching mask. In the described embodiment, the field plate 148 includes three segments 148A, 148B, and 148C that are continuously connected and alternately oriented.

[0060] A multilayer interconnect structure is formed to electrically connect the field plate 148 to the source component 120A. The multilayer interconnect structure is designed to couple various devices to form a functional integrated circuit. The multilayer interconnect structure includes vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines distributed in multiple metal layers. In the depicted embodiment, the multilayer interconnect structure includes conductive components 152 and 154 configured to electrically connect the field plate 148 to the source component 120A. The multilayer interconnect structure can be configured differently with different conductive elements to electrically connect the field plate 148 to the source component 120A.

[0061] The formation of the multilayer interconnect structure may include any suitable technique or procedure. For example, the multilayer interconnect structure may be formed by: a dual damascene process or a single damascene process, such as a damascene process implemented in a copper-based multilayer interconnect structure, optionally a metal deposition and patterning process, such as a process implemented in an aluminum-based multilayer interconnect structure, or other suitable techniques. According to some embodiments, the multilayer interconnect structure, and in particular the conductive features 152 and 154 thereof, are described below.

[0062] refer to Fig.17 , a second dielectric layer 156 is formed on the first dielectric layer 150 and the field plate 148 by deposition, such as CVD, PVD, spin coating, ALD, other suitable deposition, or a combination thereof. The second dielectric layer 156 can be similar or different in composition to the first dielectric layer 150, and can include one or more dielectric materials, such as silicon oxide, silicon nitride, low-k dielectric materials, other suitable dielectric materials, or a combination thereof. In some examples, the second dielectric layer 156 includes an etch stop layer (such as silicon nitride) and a fill dielectric layer (such as silicon oxide or low-k dielectric material) disposed on the etch step layer. In some embodiments, the formation of the second dielectric layer 156 includes deposition and CMP.

[0063] Still reference Fig.17, the second dielectric layer 156 is patterned to form trenches 162 and 164 to at least partially expose the source feature 120A and the field plate 148 within the corresponding trenches. The patterning process is similar to the other patterning processes described above, and may include a photolithography process and etching, and a hard mask may be additionally used as an etching mask. In some embodiments, the trenches 162 and 164 may be formed individually or collectively by two or more photolithography and etching processes.

[0064] refer to Fig.18 , one or more conductive material layers 166 are deposited in the trenches 162 and 164 and on the second dielectric layer 156 by suitable deposition, such as PVD, CVD, plating, other suitable deposition, or a combination thereof. For example, a seed layer is deposited in the trenches by PVD, and an electroless plating process is applied to fill the metal in the trenches. In some embodiments, a high temperature reflow process may be applied to the conductive material to obtain a better trench filling effect.

[0065] refer to Fig.19 The conductive material layer 166 is patterned by a process including photolithography and etching to form conductive features 152 and 154. The patterning process is similar to the other patterning processes described above and may include photolithography and etching, and a hard mask may be additionally used as an etching mask.

[0066] exist Fig.19 In the semiconductor structure 100 of FIG. 1 , the field plate 148 is not only designed and formed to have a stepped structure, but also configured to have various sizes and distances to obtain optimized performance. In particular, the field plate 148 is designed to span a width W and a height H, and is placed horizontally at a spacing S from the gate stack 122. The drain component 120B is a first distance D1 from the gate stack 122. The conductive component 152 is a second distance D2 from the gate stack 122. All of those dimensions are based on the electric field distribution, experimental data, and for improved performance (such as breakdown voltage and threshold voltage shift) including Fig.28 The field plate 148 is designed based on the understanding of the theoretical analysis of the performance of the field plate 148). In some embodiments, the width W ranges between 0.25 μm and 5 μm, and the height H ranges between 30 nm and 500 nm. Specifically, it is found through experiments that the relevant points in the field plate are all located between the drain and the source. Therefore, in some embodiments, the field plate 148 is designed to have a first ratio S / D1 less than 1, such as 0≤S / D≤95%, a second ratio W / D1 greater than 5%, such as 5≤W / D1≤100%; and a third ratio H / D2 less than 50%, such as 0≤S / D≤50%. In some embodiments, the first ratio S / D1 ranges between 5% and 15%; the second ratio W / D1 ranges between 40% and 60%; and the third ratio H / D2 ranges between 5% and 15%.

[0067] Similarly, Figure 1b The field plate 148 in the semiconductor structure 180 is not only designed and formed to have a stepped structure, but also configured to have various sizes and distances to obtain optimized performance. In particular, referring to Figure 1b , the field plate 148 is designed to span a width W and a height H, and is placed horizontally a third distance D3 from the source feature 120A. The source feature 120A and the drain feature 120B are a fourth distance D4. The conductive feature 152 is a fifth distance D5 from the barrier layer 116. All of those dimensions are designed based on an understanding of the electric field distribution, experimental data, and theoretical analysis for improved performance including breakdown voltage. In particular, according to some embodiments, the fourth ratio D1 / D4 is less than 1, such as 0≤S / D≤95%; the fifth ratio W / D4 is greater than 5%, such as 5≤W / D1≤100%; and the sixth ratio H / D5 is less than 50%, such as 0≤S / D≤50%. In some embodiments, the fourth ratio D1 / D4 ranges between 50% and 70%; the fifth ratio W / D4 ranges between 20% and 30%; and the sixth ratio H / D5 ranges between 5% and 15%.

[0068] The conductive members 152 and 154 may be formed separately. Figure 20 to Figure 24 An embodiment is provided. The conductive feature 154 is formed by a single damascene process, which includes patterning the second dielectric layer 156 to form the trench 164, such as Fig. 20 and filling one or more conductive materials in the trench 164 by deposition; and performing a CMP process to remove excess conductive material on the second dielectric layer 156, thereby forming a conductive feature 154, as Fig.21 The conductive feature 152 is formed by a process including: patterning the second dielectric layer 156 to form a trench 162, such as Fig. 22 By a suitable deposition method on the second dielectric layer 156 and in the trench 162 is deposited a conductive material layer 166, such as Fig.23 and performing a patterning process on the conductive material layer 166 to form a conductive member 152, such as Fig.24 shown.

[0069] Figure 25 to Figure 27 is a cross-sectional view of a semiconductor structure 100 constructed according to some other embodiments. Fig. 27 The semiconductor structure 100 in Figure 1a , Fig. 9 , Fig.10 , Fig.19 or Fig.24 The semiconductor structure 100, except Fig. 27The field plate 148 in the embodiment includes five segments having a stepped structure that are continuously connected and oriented alternately in two orthogonal directions (X and Y directions). Such a field plate 148 can be formed by the method 200, but the block 206 includes two patterning processes applied to the first dielectric layer 150 to form a trench having a stepped structure. In particular, as Fig.25 As shown, a first patterning process is applied to the first dielectric layer 150 to form a trench 170, and as shown in FIG. Fig.26 As shown, a second patterning process is also applied to the first dielectric layer 150 to form the trench 172. Thereafter, operations 208-212 are performed to form the field plate 148, as shown in FIG. Fig. 27 As shown. In an alternative embodiment, the semiconductor structure 100 is a two-terminal device without the gate stack 122, but the field plate has a stepped structure with five segments. In some embodiments, the field plate 148 in the semiconductor structure 100 may include a stepped structure with 4, 6, 7, 8 or more segments formed by a similar procedure. For example, instead of two patterning processes for the dielectric material layer 150, the method may include three or more patterning processes to obtain the desired trench profile, so that the field plate 148 may have various segments formed in the trench.

[0070] Fig.28 is a diagrammatic view of the electric field (E-field) along the X direction constructed according to some embodiments. The electric field strength is presented by the vertical axis. Fig.28 The graph (a) in FIG. 1 includes two data sets, the first set labeled “FP1” and the semiconductor structure having a field plate with a disclosed stepped structure (such as Fig.19 The second set marked as "FP2" is associated with a semiconductor structure having a field plate different from the structure of the stepped structure (as a reference). Specifically, the electric field of EP1 has three peaks at different locations, corresponding to Fig.19 In particular, the second peak is contributed by the junction portion of the first and second segments of the field plate 148, which is absent in field plates with different structures. This redistributes the electric field and reduces the maximum electric field (at P3), thereby correspondingly reducing the breakdown voltage. Due to the geometry of the stepped structure of the disclosed field plate (such as Fig.19 148), the various corner portions of the edge of the field plate with a stepped structure will be more helpful in redistributing the electric field and reducing the surface field, thereby correspondingly reducing the breakdown voltage. Fig. 27 The field plate 148 in has a stepped structure with five segments and more edge portions, which will more effectively redistribute the electric field and reduce the surface field.

[0071] Fig.28The graph (b) in FIG. 1 shows gate leakage current (Idoff) versus gate voltage (Vd). The gate voltage is represented on the horizontal axis, and the gate leakage current is represented on the vertical axis. The data show that the gate leakage current of the semiconductor structure having a stepped field plate is substantially reduced.

[0072] Fig.28 The curve graph (c) in shows the dynamic Ronratio (or dRon ratio) versus gate voltage (Vd). The gate voltage is represented on the horizontal axis, and the dynamic Ronratio is presented on the vertical axis. The data show that the dynamic Ronratio of the semiconductor structure with a stepped field plate is substantially increased. The dRon ratio is the dynamic Ron ratio. For example, the dynamic Ron in 60V is defined as Rds(60V) / Rds(1V). Rds(60V / 1V) means Rds under sustained transient switching stress Vds=60 / 1V. If the value is closer to 1, it means a better channel capture effect, where the AC Vds stress will cause less capture in the channel.

[0073] Although various embodiments are provided and explained in the present invention. Without departing from the spirit of the present invention, other alternatives and embodiments may be used. For example, a GaN-based device (such as 100, 180, 182 or 184) may further include an aluminum nitride (AlN) layer disposed between the buffer layer 114 and the barrier layer 116. In one embodiment, the AlN layer is selectively epitaxially grown on the buffer layer 114. The AlN layer can be epitaxially grown using MOVPE of an aluminum-containing precursor and a nitrogen-containing precursor. The aluminum-containing precursor includes TMA, TEA or other suitable chemicals. The nitrogen-containing precursor includes ammonia, TBAm, phenylhydrazine or other suitable chemicals. In one example, the thickness of the AlN layer ranges between about 5nm and about 50nm.

[0074] Alternatively, the AlN layer may replace the AlGaN layer as a barrier layer. In another embodiment, the sizes of the various n-GaN layers and p-GaN layers may vary depending on the device specifications, performance, and circuit requirements. For example, the thicknesses of the various n-GaN layers and p-GaN layers may be adjusted based on the threshold voltage or other device / circuit considerations. In another embodiment, the gate stack 122 of the semiconductor structure (such as 100, 182, or 184) may include more n-GaN layers and / or p-GaN layers configured in the junction isolation feature 126.

[0075] The present invention provides a III-V compound-based device with a field plate having a stepped structure and a method for manufacturing the same. The disclosed field plate has a plurality of segments that are continuously connected and alternately oriented in different directions. The disclosed field plate can effectively reduce the surface field, thereby increasing the breakdown voltage or maintaining a high breakdown voltage, reducing leakage current, and reducing the shift of the threshold voltage.

[0076] In one exemplary aspect, the present invention provides a semiconductor structure. The semiconductor structure includes: a gallium nitride (GaN) layer located on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source component and a drain component disposed on the AlGaN layer and inserted by the gate stack; a dielectric material layer disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source component, wherein the field plate includes a stepped structure.

[0077] In some embodiments, the field plate includes a first segment extending horizontally, a second segment extending vertically from the first segment, and a third segment extending horizontally from the second segment. In some embodiments, the first segment is horizontally spaced from the gate stack by a first dimension D1; the drain component is horizontally spaced from the gate stack by a second dimension D2; and the first ratio D1 / D2 is less than 95%. In some embodiments, the field plate spans a width W horizontally; and the second ratio W / D2 is greater than 5% and less than 100%. In some embodiments, the source component is electrically connected to the field plate by a conductive component; the conductive component extends horizontally from the source component; the conductive component is vertically spaced from the gate stack by a third dimension D3; the field plate spans a height H vertically; and the third ratio H / D3 is less than 50%. In some embodiments, the field plate also includes a fourth segment extending vertically from the third segment and a fifth segment extending horizontally from the fourth segment. In some embodiments, the gate stack includes a III-V compound p-type doped layer. In some embodiments, the gate stack also includes a dielectric layer located below the III-V compound p-type doped layer. In some embodiments, the gate stack further comprises a III-V compound n-type doped layer located adjacent to the III-V compound p-type doped layer. In some embodiments, the III-V compound n-type doped layer comprises an n-type gallium nitride layer, and the III-V compound p-type doped layer comprises a p-type gallium nitride layer. In some embodiments, the III-V compound p-type doped layer is doped with impurities selected from the group consisting of magnesium, calcium, zinc, beryllium, and carbon; and the III-V compound n-type doped layer is doped with impurities selected from the group consisting of silicon and oxygen. In some embodiments, the field plate comprises a conductive material selected from the group consisting of titanium nitride, titanium, titanium aluminum, aluminum copper, and combinations thereof. In some embodiments, the gallium nitride layer is undoped or unintentionally doped. In some embodiments, the source component, the drain component, and the gate stack are configured with the gallium nitride layer and the aluminum gallium nitride layer to form a high electron mobility transistor.

[0078] In another exemplary aspect, the present invention provides a semiconductor structure. The semiconductor structure includes: a first III-V compound layer located on a substrate; a second III-V compound layer located directly on the first III-V compound layer, the second III-V compound layer being different in composition from the first III-V compound layer and also including aluminum; a gate stack located on the second III-V compound layer; a source component and a drain component disposed on the second III-V compound layer; and a field plate disposed above the gate stack and electrically connected to the source component, wherein the field plate includes at least three segments having a stepped structure.

[0079] In some embodiments, the substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first III-V compound layer includes a gallium nitride (GaN) layer; the second III-V compound layer includes an aluminum gallium nitride (AlGaN) layer; and the gate stack includes a p-type doped III-V compound layer. In some embodiments, the field plate includes a first segment extending horizontally, a second segment extending vertically from the first segment, and a third segment extending horizontally from the second segment. In some embodiments, the field plate further includes a fourth segment extending vertically from the third segment and a fifth segment extending horizontally from the fourth segment.

[0080] In yet another exemplary aspect, the present invention provides a method. The method includes: forming a first III-V compound layer on a substrate; forming a second III-V compound layer on the first III-V compound layer, wherein the second III-V compound layer is different in composition from the first III-V compound layer and further includes aluminum; forming a gate stack on the second III-V compound layer; forming a source component and a drain component on the second III-V compound layer, and the source component and the drain component are inserted by the gate stack; and forming a field plate above the gate stack and electrically connecting the field plate to the source component, wherein the field plate includes at least three segments configured in a stepped structure.

[0081] In some embodiments, forming the first III-V compound layer includes forming an undoped gallium nitride layer; forming the second III-V compound layer includes forming an aluminum gallium nitride layer; and forming the field plate includes: forming a dielectric material layer on the gate stack, the source component and the drain component, performing a first patterning process to form a trench in the dielectric material layer, depositing a conductive layer on the dielectric material layer, and performing a second patterning process on the conductive layer to produce a patterned conductive layer, the patterned conductive layer having a first segment located in the bottom surface of the trench, a second segment located on the sidewall of the trench, and a third segment located on the top surface of the dielectric material layer, wherein the first segment, the second segment and the third segment are continuously connected.

[0082] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a gallium nitride layer disposed on a substrate and having a plane normal direction oriented from the substrate to the gallium nitride layer; An aluminum gallium nitride layer is arranged on the top surface of the gallium nitride layer along the normal direction of the plane; A gate stack, disposed on the aluminum gallium nitride layer; a source feature and a drain feature disposed on the aluminum gallium nitride layer and interposed by the gate stack; a dielectric material layer disposed on the gate stack; a field plate disposed on the dielectric material layer and electrically connected to the source component, wherein the field plate comprises a stepped structure; and a conductive member electrically connecting a portion of the field plate that is farthest from the gate stack in a vertical direction to the source member, The stepped structure includes a first section extending horizontally along a first direction perpendicular to the plane normal direction, a second section extending vertically from the first section along the plane normal direction, and a third section extending horizontally from the second section along the first direction, and the third section is located above the first section along the plane normal direction. And wherein, in the vertical direction, the field plate is located above the gate stack and the source and drain components and is vertically spaced apart from the gate stack and the source and drain components, and in the horizontal direction, the field plate is positioned between the gate stack and the drain component and is horizontally spaced apart from the gate stack and the drain component, and the field plate does not overlap with the gate stack and the source and drain components in both the vertical and horizontal directions.

2. The semiconductor structure according to claim 1, wherein: The conductive member extends across the field plate to the source member.

3. The semiconductor structure according to claim 1, wherein: The first segment is horizontally spaced apart from the gate stack by a first dimension D1; The drain component is horizontally spaced apart from the gate stack by a second dimension D2; and The first ratio D1 / D2 is less than 95%.

4. The semiconductor structure according to claim 3, wherein: The field plates span a width W horizontally; and The second ratio W / D2 is greater than 5% and less than 100%.

5. The semiconductor structure according to claim 4, wherein: The source component is electrically connected to the field plate through a conductive component; The conductive member extends horizontally from the source member; The conductive component is vertically spaced apart from the gate stack by a third dimension D3; The field plate vertically spans a height H; and The third ratio H / D3 is less than 50%.

6. The semiconductor structure according to claim 2, wherein: The field plate further includes a fourth segment vertically extending from the third segment and a fifth segment horizontally extending from the fourth segment.

7. The semiconductor structure according to claim 1, wherein: The gate stack includes a III-V compound p-type doped layer.

8. The semiconductor structure according to claim 7, wherein: The gate stack also includes a dielectric layer underlying the III-V compound p-type doped layer.

9. The semiconductor structure according to claim 8, wherein: The gate stack also includes a III-V compound n-type doped layer adjacent to the III-V compound p-type doped layer.

10. The semiconductor structure according to claim 9, wherein: The III-V compound n-type doping layer includes an n-type gallium nitride layer, and the III-V compound p-type doping layer includes a p-type gallium nitride layer.

11. The semiconductor structure according to claim 10, wherein: The III-V compound p-type doping layer is doped with impurities selected from the group consisting of magnesium, calcium, zinc, beryllium and carbon; and The III-V compound n-type doping layer is doped with impurities selected from the group consisting of silicon and oxygen.

12. The semiconductor structure according to claim 1, wherein: The field plate includes a conductive material selected from the group consisting of titanium nitride, titanium, titanium aluminum, aluminum copper, and combinations thereof.

13. The semiconductor structure according to claim 1, wherein: The gallium nitride layer is undoped or unintentionally doped.

14. The semiconductor structure according to claim 1, wherein: The source feature, the drain feature, and the gate stack are configured with the gallium nitride layer and the aluminum gallium nitride layer to form a high electron mobility transistor.

15. A semiconductor structure comprising: a first III-V compound layer located on a substrate and having a plane normal direction oriented from the substrate to the first III-V compound layer; a second III-V compound layer directly disposed on top of the first III-V compound layer along the plane normal direction, the second III-V compound layer being different in composition from the first III-V compound layer and further comprising aluminum; a gate stack disposed on the second III-V compound layer; a source component and a drain component disposed on the second III-V compound layer; a field plate disposed over the gate stack and electrically connected to the source component, wherein the field plate includes at least three segments having a stepped structure; and a conductive member electrically connecting a portion of the field plate that is farthest from the gate stack in a vertical direction to the source member, The stepped structure includes a first section extending horizontally along a first direction perpendicular to the plane normal direction, a second section extending vertically from the first section along the plane normal direction, and a third section extending horizontally from the second section along the first direction, and the third section is located above the first section along the plane normal direction. And wherein, in the vertical direction, the field plate is located above the gate stack and the source and drain components and is vertically spaced apart from the gate stack and the source and drain components, and in the horizontal direction, the field plate is positioned between the gate stack and the drain component and is horizontally spaced apart from the gate stack and the drain component, and the field plate does not overlap with the gate stack and the source and drain components in both the vertical and horizontal directions.

16. The semiconductor structure according to claim 15, wherein: The substrate comprises one of a sapphire substrate, a silicon substrate and a silicon carbide substrate; The first III-V compound layer comprises a gallium nitride layer; The second III-V compound layer comprises an aluminum gallium nitride layer; The gate stack includes a p-type doped III-V compound layer.

17. The semiconductor structure according to claim 15, wherein: The conductive member extends across the field plate to the source member.

18. The semiconductor structure according to claim 15, wherein: The field plate further includes a fourth segment vertically extending from the third segment and a fifth segment horizontally extending from the fourth segment.

19. A method of forming a semiconductor structure, comprising: forming a first III-V compound layer on a substrate, wherein the first III-V compound layer has a plane normal direction oriented from the substrate to the first III-V compound layer; forming a second III-V compound layer on a top surface of the first III-V compound layer along the plane normal direction, wherein the second III-V compound layer is different in composition from the first III-V compound layer and further comprises aluminum; forming a gate stack on the second III-V compound layer; forming a source feature and a drain feature on the second III-V compound layer, and the source feature and the drain feature are interposed by the gate stack; and forming a field plate over the gate stack and electrically connecting the field plate to the source feature, wherein the field plate includes at least three segments configured in a stepped structure, wherein a portion of the field plate that is farthest from the gate stack in a vertical direction is electrically connected to the source component through a conductive component, The stepped structure includes a first section extending horizontally along a first direction perpendicular to the plane normal direction, a second section extending vertically from the first section along the plane normal direction, and a third section extending horizontally from the second section along the first direction, and the third section is located above the first section along the plane normal direction. And wherein, in the vertical direction, the field plate is located above the gate stack and the source and drain components and is vertically spaced apart from the gate stack and the source and drain components, and in the horizontal direction, the field plate is positioned between the gate stack and the drain component and is horizontally spaced apart from the gate stack and the drain component, and the field plate does not overlap with the gate stack and the source and drain components in both the vertical and horizontal directions.

20. The method according to claim 19, wherein: Forming the first III-V compound layer includes forming an undoped gallium nitride layer; Forming the second III-V compound layer includes forming an aluminum gallium nitride layer; and Forming the field plate includes: forming a dielectric material layer on the gate stack, the source feature, and the drain feature, performing a first patterning process to form trenches in the dielectric material layer, depositing a conductive layer on the dielectric material layer, and A second patterning process is performed on the conductive layer to produce a patterned conductive layer, wherein the patterned conductive layer has a first segment located in the bottom surface of the groove, a second segment located on the side wall of the groove, and a third segment located on the top surface of the dielectric material layer, wherein the first segment, the second segment and the third segment are continuously connected.

Images