Monolithic post-complementary metal oxide-semiconductor integration of pyroelectric-based infrared detectors

Abstract

A complementary metal oxide semiconductor (CMOS) device having a micro-electromechanical system (MEMS) component embedded in a MEMS region is disclosed. The MEMS component is, for example, an infrared (IR) thermal sensor. The MEMS sensor is monolithically integrated on the CMOS device after CMOS processing. For example, the MEMS sensor is formed on the BEOL dielectric of the CMOS device. The device is packaged with a CMOS compatible IR transparent cover to seal the MEMS sensor in the MEMS region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62,827,205, filed April 1, 2019. This application is cross-referenced to U.S. Patent Application Serial No. 16 / 809,561, filed March 5, 2020, which is a continuation-in-part of co-pending U.S. Patent Application Serial No. 16 / 517,653, filed July 21, 2019, which is a continuation-in-part of U.S. Patent Application Serial No. 15 / 647,284, entitled Expandable Thermoelectric-Based Infrared Detector, now U.S. Patent No. 10,403,674, filed July 12, 2017. This application cross-references U.S. Patent Application Serial No. 16 / 224,782, filed December 18, 2018, which is a divisional application of U.S. Patent Application Serial No. 15 / 653,558, entitled Pyroelectric-Based Infrared Detectors with High CMOS Integration, now U.S. Patent No. 10,199,424, filed July 19, 2017. This application further cross-references PCT International Application entitled Heterogeneous Integration of Complementary Metal Oxide Semiconductor and MEMS Sensors, filed on April 1, 2020, filed on the same date, which claims the benefit of U.S. Provisional Application No. 62,827,207, filed April 1, 2019. This application further cross-references U.S. Provisional Application No. 62,827,861, filed April 2, 2019. The entire disclosure of which is incorporated herein by reference in its entirety for all purposes. Background Art

[0003] The demand for uncooled infrared (IR) detectors continues to grow owing to the increased demand in numerous applications. These applications include air conditioning systems, mobile phones, autonomous vehicles, Internet of Things (IoT), fire protection, and traffic safety, to name a few. Moreover, more applications for uncooled IR detectors are expected in the near future.

[0004] Micro-electromechanical system (MEMS) IR detectors have been proposed. In addition, it is desirable to embed MEMS IR detectors into complementary metal oxide semiconductor (CMOS) integrated circuits due to the compactness and cost-effectiveness of the resulting system. However, embedding MEMS IR detectors into ICs poses great challenges due to the limited thermal budget available for post-CMOS processes.

[0005] The present disclosure is directed to a cost-effective and compact system with an embedded infrared detector. Summary of the invention

[0006] Embodiments of the present disclosure generally relate to devices and methods of forming such devices. In particular, embodiments relate to CMOS devices embedded with MEMS components or sensors. The MEMS components may be, for example, IR sensors.

[0007] In one embodiment, a method for forming a device includes providing a substrate prepared with a complementary metal oxide semiconductor (CMOS) region having a CMOS component, and a BE dielectric having an interconnect for interconnecting the CMOS component. The method also includes forming a MEMS layer on the BE dielectric, the MEMS layer including a MEMS region having a MEMS component, the MEMS component including a recrystallized polysilicon structure. The MEMS layer occupies a portion of the BE dielectric. The method further includes forming a substrate sealing ring on the BE dielectric surrounding the MEMS layer, and providing a cover having a cover inner surface and a cover outer surface. The cover inner surface includes a cover sealing ring, the cover sealing ring bonded to a substrate bonding ring on the BE dielectric to hermetically seal the MEMS layer.

[0008] In one embodiment, a device includes: a substrate, the substrate being prepared with a complementary metal oxide semiconductor (CMOS) region having a CMOS component, and a BE dielectric having an interconnect for interconnecting the CMOS component. The device also includes a MEMS layer located on the BE dielectric, the MEMS layer including a MEMS region having a MEMS component, the MEMS component including a recrystallized polysilicon structure. The MEMS layer occupies a portion of the BE dielectric. The device also includes a substrate sealing ring on the BE dielectric surrounding the MEMS layer, and a cover having a cover inner surface and a cover outer surface. The cover inner surface includes a cover sealing ring, the cover sealing ring bonded to a substrate bonding ring on the BE dielectric to hermetically seal the MEMS layer.

[0009] These and other advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and drawings.In addition, it should be understood that the features of the various embodiments described herein are not mutually exclusive and may exist in various combinations and permutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate preferred embodiments of the present disclosure and, together with the description, serve to explain the principles of various embodiments of the present disclosure, wherein like numerals represent like parts.

[0011] Figure 1 is a top view of a semiconductor wafer;

[0012] Figure 2a-2f shows a simplified cross-sectional view of an embodiment of a device;

[0013] Figure 3 a cross-sectional view showing a portion of a device in greater detail;

[0014] Figure 4a-4b shows a top view and a cross-sectional view of an exemplary embodiment of a thermopile structure for an IR sensor;

[0015] Figure 4c An exemplary layout of a 2×3 sensor array is shown;

[0016] Figure 5a-5i One embodiment of a process for forming a device is shown;

[0017] Figure 6a The energy of the laser heat source is plotted as a function of time;

[0018] Figure 6b Shows the use of Figure 6a A laser heat source for simulating a structure by laser annealing; and

[0019] Figure 6c The temperature of the structure heated by the laser heat source is simulated as a function of time at different depths. DETAILED DESCRIPTION

[0020] Embodiments generally relate to devices, such as semiconductor devices or integrated circuits (ICs) having embedded microelectromechanical systems (MEMS) modules. The IC is, for example, a complementary metal oxide semiconductor (CMOS) device. For a MEMS module, it may include one or more pyroelectric-based infrared (IR) detectors. The MEMS detectors are compatible with CMOS processing. The device may be incorporated into a product, such as a thermal imager. For example, a device may include a plurality of MEMS sensors that may be arranged to form a sensor array for a thermal imager. The sensors may be used for other types of applications, such as single pixel or line array temperature or motion sensors.

[0021] The fabrication of the device may involve forming features on a substrate to form circuit components, such as transistors, resistors, capacitors, as part of the front-end-of-line (FEOL) processing. As part of the back-end-of-line (BEOL) processing, interconnects are formed to interconnect the components so that the device can perform the desired function. After BEOL processing, the MEMS sensor is embedded on the device. In addition, the process also includes sealing the MEMS sensor with a cap to hermetically seal the MEMS sensor.

[0022] In order to form the features, such as CMOS circuit components, interconnects, and MEMS sensors, layers are repeatedly deposited on a substrate and patterned as desired using photolithography techniques. For example, a wafer is patterned by exposing a photoresist layer with an exposure source using a mask containing a desired pattern. After exposure, the photoresist layer is developed, thereby transferring the pattern of the mask to the photoresist layer. This forms a photoresist etch mask. Etching is performed using an etch mask to replicate the pattern on the wafer below, which may include one or more layers, depending on the process stage. During the formation of the device, many masks can be used for different patterning processes. In addition, multiple devices can be formed in parallel on a wafer. The device is hermetically sealed with a cap. In one embodiment, the device is sealed at the wafer level. For example, the device wafer is sealed by a cap wafer, the device is sealed in parallel, and the device wafer and the cap wafer form a wafer stack. The wafer stack is processed to singulate the packaged device.

[0023] Figure 1 A simplified plan view of an embodiment of a semiconductor wafer 101 is shown. The semiconductor wafer may be, for example, a silicon wafer. The wafer may be a lightly doped p-type wafer. Other types of wafers, such as silicon-on-insulator (SOI) or silicon-germanium wafers, and wafers doped with other types of dopants or dopant concentrations may also be used.

[0024] The wafer includes an active surface 111 on which a device 115 is formed. A plurality of devices may be formed in parallel on the wafer. The devices are arranged, for example, in rows along a first (x) direction and in columns along a second (y) direction. A cover wafer having a processed cover is provided. For example, the cover wafer is processed separately from the wafer. The cover wafer is bonded to the wafer having the devices, and the devices are packaged in parallel at the wafer level. The wafer stack is cut to separate the devices into individually packaged chips. In one embodiment, the wafer stack is partially cut to expose bonding pads on the device semiconductor wafer, and then a complete cut is performed to singulate the packaged devices.

[0025] Figure 2a-2f A simplified cross-sectional view of an embodiment of a device 200 is shown. The device is, for example, a CMOS device with an embedded MEMS structure or component. In one embodiment, the device is a CMOS device embedded with a pyroelectric-based infrared sensor. In some embodiments, the MEMS structure of the device includes a plurality of pyroelectric-based infrared sensors. The plurality of sensors may be arranged to form a sensor array. For example, the device may be an infrared imager, wherein each sensor may be a pixel of the infrared imager. Other types of MEMS structures or applications are also possible.

[0026] The device comprises a substrate 201. For example, the substrate may be a portion of a wafer, such as Figure 1As shown. Common elements may not be described or described in detail. The substrate may be, for example, a semiconductor substrate, such as a silicon substrate. The substrate may be, for example, a lightly doped p-type silicon substrate. Other types of substrates or wafers may also be used.

[0027] In one embodiment, the substrate includes a CMOS region 210 having CMOS components. The CMOS region, for example, includes a CMOS device region having CMOS devices or components. The CMOS components may include metal oxide semiconductor (MOS) transistors, such as n-type MOS transistors and p-type MOS transistors. Other types of CMOS components, such as diodes, capacitors, and resistors, may also be provided in the CMOS device region. P-type MOS transistors and n-type MOS transistors are complementary transistors. The transistor includes a device well serving as a transistor body. In addition, the transistor includes a gate on the substrate, the gate being disposed above the device well between the first and second source / drain (S / D) regions in the device well.

[0028] The gate of the transistor may include a gate electrode above the gate dielectric. The gate electrode may be polysilicon and the gate dielectric may be thermally oxidized silicon. Other types of materials or gate arrangements may also be used. For a p-type MOS transistor, the device well is an n-type well and the S / D region is a heavily doped p-type region. On the other hand, an n-type transistor has a p-type device well and a heavily doped n-type S / D region. The S / D region may include a lightly doped extension region. The lightly doped extension region is lightly doped with a dopant of the same polarity type as the heavily doped S / D region. The sidewalls of the gate may include a dielectric spacer. The spacer helps to align the S / D and lightly doped extension regions. The device well may include a device well contact, which is heavily doped with a dopant of the same polarity type as the device well.

[0029] The CMOS device area may include different types of regions for different types of transistors having different operating characteristics or voltages. For example, low voltage transistors may be provided in a low voltage (LV) area, intermediate or medium voltage transistors may be provided in a medium voltage (MV) area, and high voltage transistors may be provided in a high voltage (HV) area. Other types of device areas may also be included. For example, a memory area may be included in which a memory array is disposed.

[0030] As discussed, a sensor array may be included having a plurality of sensors arranged in a matrix of rows and columns of sensors. Each sensor corresponds to a pixel in the pixel array. In this case, the CMOS component may include a selection switch, row and column decoders, and readout circuitry. Other CMOS components may also be included. The CMOS component is configured to read each pixel of the array. Once the entire array of sensors is read out, an image may be reconstructed. The image is, for example, a frame corresponding to the sensors of the array.

[0031] Isolation regions are typically provided to isolate CMOS components. For example, isolation regions are provided for CMOS device regions. Additionally, isolation regions may be provided to isolate device well contacts from S / D contacts. Other arrangements of isolation regions are also possible. Isolation regions may be field oxide (FOX) isolation regions. Other types of isolation regions, such as shallow trench isolation (STI) regions, may also be used.

[0032] An interlayer dielectric (ILD) layer 220 may be disposed on the substrate. The ILD layer covers the CMOS device region with the CMOS components. The ILD layer is, for example, a silicon oxide layer. Other types of dielectric layers or combinations of dielectric layers may also be used.

[0033] Metal contact plugs, such as tungsten plugs, are provided in the ILD layer and coupled to contact regions on the substrate and the CMOS component. For example, the contact plugs are coupled to the S / D regions and gates of the CMOS component, and to well taps for biasing the well and the substrate. It is also possible to provide contact plugs for other types of contact regions. The contact plugs can be formed, for example, by a damascene process. Other techniques for forming contact plugs are also available.

[0034] A back-end-of-line (BEOL) dielectric 230 is provided on the substrate above the ILD layer 220. For example, the BEOL dielectric covers the CMOS region. The BEOL dielectric may include a plurality of intermetal dielectric (IMD) layers formed by the BEOL dielectric layers. For example, the BEOL dielectric may include y IMD layers, where y is 2–8. Other numbers of IMD layers (including 1) may also be used depending on the design and CMOS process. The ILD layers and the BEOL dielectric may be referred to as a BE dielectric.

[0035] The IMD layer may include a via dielectric layer and a metal dielectric layer. Depending on the design and process method, the via dielectric layer and the metal dielectric layer of the IMD layer may be formed by one or more dielectric layers. The via dielectric layer may be disposed above the metal dielectric layer. It is also possible to provide a metal dielectric layer located above the via dielectric layer. For example, a metal layer (Mx) may be disposed below the first via layer (Vx). For example, in the case of 3 IMD layers, x may be 1 to 3. The metal dielectric layer includes metal lines, and the via dielectric layer includes via contacts. The first metal layer dielectric M1 is disposed above the ILD layer. Other configurations of the BEOL dielectric layer are also available.

[0036] Metal lines and via contacts can be formed using damascene techniques, such as single or dual damascene processes. In the case of a single damascene process, contacts and metal lines are formed in separate processes. In the case of a dual damascene process, metal lines and contacts are formed in the same process. For example, metal lines of Mx and via contacts of Vx-1 are formed in the same process. In some embodiments, the IMD layer can be formed by a combination of damascene and reactive ion etching (RIE) processes. For example, metal lines can be formed by an RIE process, while contacts are formed by a single damascene process. In the case of an RIE process, a metal layer is formed and patterned by RIE using an etch mask to form metal lines. It should be understood that different IMD layers of BEOL dielectrics can be formed using different techniques or a combination of techniques or processes. For example, the first IMD layer can form contacts using a damascene process and form metal lines using an RIE process, and the intermediate IMD layer can be formed using a dual damascene process. Alternatively, the IMD layer can be formed by a combination of damascene and RIE processes. Other settings for forming the IMD layer are also available.

[0037] As for the top metal layer of the BEOL dielectric, it can be used as a pad layer with a pad metal line. The pad line can be formed by a damascene or RIE process. A passivation layer can be formed above the pad line. The passivation layer can include, for example, one or more dielectric layers. In one embodiment, the passivation layer includes a silicon nitride layer located above the silicon oxide layer, thereby forming a SiO2 / SiN passivation stack. Other types of passivation layers or stacks are also available. A pad opening 235 can be provided in the passivation layer to expose the contact pad of the pad line. Other methods for forming the pad layer are also available. The passivation layer can be considered as the top dielectric layer of the BEOL dielectric.

[0038] The ILD and IMD layers may be planarized to form a flat top surface over the CMOS region. For example, CMP is performed on the substrate. Other planarization techniques, such as spin-on-glass (SOG) for filling gaps or planarizing the substrate surface, may also be used. The total thickness of the ILD and IMD layers over the structure may be between 100–400 nm. Providing any other thickness for the IMD layer is also possible.

[0039] Above the BEOL dielectric is a MEMS layer 240. In one embodiment, the MEMS layer is a monolithically integrated MEMS layer. For example, the MEMS layer is formed above the BEOL dielectric using a CMOS process. In one embodiment, the MEMS layer is formed above the BEOL dielectric using a CMOS process that is a post-CMOS compatible process. Monolithic integration of the MEMS layer can reduce device footprint and reduce manufacturing costs. Additionally, other advantages include, for example, greater fill factor and shorter interconnect length, which results in faster and smaller parasitics for sensor readout.

[0040] In one embodiment, the MEMS layer 240 is disposed on and within the BEOL dielectric of the device. For example, the MEMS layer occupies a portion of the BEOL dielectric. The MEMS level defines a MEMS region 245 of the device. In other words, the MEMS region or MEMS layer is surrounded by the CMOS region below. The MEMS region is provided with a MEMS component. In one embodiment, the MEMS component is a sensor array having sensors. The sensors can be disposed within a MEMS device region of the MEMS region. For example, each sensor can be located in its respective MEMS device region. In one embodiment, the sensors of the array are pyroelectric-based IR MEMS sensors. It is also possible to provide other types of MEMS sensors for the MEMS region. The sensors can be arranged as a matrix with M rows and N columns of sensors, thereby forming an M×N array. Typical array sizes can include, for example, a 32×32 array or an 80×64 array. Other array sizes are also possible. The size of the array can depend on, for example, the desired image resolution. In some cases, the array can be a row of sensors, such as an M x 1 or 1x N array. It is also possible to provide a single MEMS sensor for the MEMS region. The sensor can correspond to a pixel of a pixel array of an image. In addition, the sensor array may further include one or more blind sensors corresponding to one or more blind pixels. For example, the blind pixels are used for calibration purposes.

[0041] In one embodiment, the MEMS layer includes a base dielectric layer. The base dielectric layer forms the bottom of the MEMS layer. For example, the base dielectric layer contacts a passivation layer of the BEOL dielectric. The base dielectric layer can be a silicon oxide layer. Other types of dielectric layers are also possible. An IR reflector is disposed on the base dielectric layer for the MEMS sensor. The IR reflector can be a metal IR reflector. For example, the metal IR reflector can be formed of titanium (Ti), tungsten (W), or aluminum. Other types of IR reflectors compatible with CMOS are also available.

[0042] In one embodiment, the MEMS layer includes a sacrificial layer disposed over the base layer and the IR reflector. The sacrificial layer is used to facilitate the structure of the lower sensor cavity. In one embodiment, the sacrificial layer is an amorphous silicon (αSi) layer. Other types of sacrificial layers may also be used.

[0043] The MEMS dielectric layer is disposed on the sacrificial layer. The MEMS dielectric layer can be, for example, a silicon oxide layer. Other types of dielectric layers are also possible. In some cases, the dielectric layer can be a dielectric layer stack. The MEMS dielectric layer is used as a membrane on which the MEMS structure of the sensor of the sensor array is arranged. In one embodiment, the MEMS structure is a thermopile wire structure used as a thermoelectric IR sensor or detector. The thermopile pipeline structure can be similar to those described in, for example, USSN 16 / 517,653, USSN 10,403,674, USSN 16 / 224,782 and USSN 10,199,424, which have been incorporated herein by reference for all purposes. Other types of MEMS structures or sensors, including non-IR sensors, can also be disposed in the MEMS area.

[0044] In one embodiment, the thermopile wire structure includes first and second polarity doped thermowire segments. In one embodiment, the thermowire structure includes doped polysilicon. In one embodiment, the doped polysilicon is recrystallized into amorphous silicon using laser annealing. Other types of thermoelectric materials may also be used for the thermopile wire structure. Metal contacts may be used to couple the first and second polarity doped segments of the thermopile wire structure. The metal contact may be disposed at the junction of the first polarity doped segment and the second polarity doped segment. The metal contact is, for example, a Ti or Al alloy contact. Other types of metal contacts may also be available. The first sensor terminal is coupled to the first polarity doped thermowire segment, and the second sensor terminal is coupled to the second polarity doped thermowire segment material. The terminals may be part of the doped thermoelectric material.

[0045] An absorber layer may be provided above the line structure. The absorber layer is, for example, configured to absorb incident IR radiation. The absorber layer may be a titanium nitride (TiN) layer. Other types of absorber layers may also be used. For example, the absorber layer may be a nickel chromium (NiCr) layer or a doped silicon layer. In one embodiment, the absorber is configured to absorb a majority of the incident IR radiation. For example, the absorber may be configured to absorb greater than 85% of the incident IR radiation having a wavelength of 8–14 μm. Any other configuration may also be provided. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2–5 μm. For example, another harmonic of the interferometric absorber is used. In one embodiment, the absorber is configured to absorb >50% of the incident radiation having a wavelength of 2-5 μm.

[0046] In one embodiment, a sensor protection layer is disposed above the absorber layer. The sensor protection layer is used to protect the sensor from subsequent etching processes. For example, the protection layer is used to protect the line structure and the absorber layer from an etchant (e.g., XeF2) used to form the lower sensor cavity in the release process. In one embodiment, the protection layer is a silicon oxide layer. Other types of layers that are transparent to IR radiation and selective to the etchant used in the release process to form the lower sensor cavity can also be used.

[0047] Release openings are provided in the MEMS dielectric layer and other layers above, such as the absorber layer and the protective layer, to remove the sacrificial layer when forming the lower sensor cavity in the release process. In one embodiment, the lower sensor cavity has a height (between the bottom and the top) selected to optimally reflect the desired wavelength of IR radiation through the reflector. The height can be defined, for example, by the thickness of the sacrificial layer. In one embodiment, the height of the lower sensor cavity is sufficient to ensure a 1 / 4 wavelength optical distance between the absorber and the reflector. For example, the optical distance for detecting IR radiation with a wavelength of 8–12 μm is approximately 2–3 μm. Other distances are also available depending on the wavelength to be detected. For example, by reducing or increasing the optical distance, IR radiation with a smaller or larger wavelength can be detected, respectively. The optical distance is defined as the distance at which the IR radiation wave has a path through multiple layers.

[0048] A MEMS to CMOS (MC) contact may be provided at the MEMS layer. The MC contact provides electrical connection of the MEMS sensors of the array to the CMOS components of the CMOS region. The MC contact may be a through layer via (TLV) contact. The MC contact is, for example, coupled to a terminal of the sensor and a top metal or pad layer that is connected to the CMOS components of the CMOS region. In one embodiment, a MC contact is provided for each sensor of the array. For example, a first and a second MC contact is provided for the first and second terminals of each sensor.

[0049] In one embodiment, the lower sensor cavity is a common lower sensor cavity of the sensor array. For example, a single lower sensor cavity is used as a common lower sensor cavity for sensors of the sensor array. The bottom sensor cavity is defined by a base dielectric layer with a reflector, and the top of the lower sensor cavity is defined by a patterned MEMS dielectric layer. The cavity has no sidewalls. For example, after removing the sacrificial layer, the MEMS dielectric layer with the sensor structure is mechanically supported by the MC contacts.

[0050] A cap 250 is disposed on the substrate to encapsulate the MEMS region. For example, the cap is bonded to the top of the BEOL dielectric to form a vacuum above the MEMS region. In one embodiment, the cap is formed of a material that is transparent to infrared radiation. For example, the cap can transmit infrared radiation to the sensor. The cap can be a silicon (Si) cap. Other types of materials, such as germanium (Ge), silicon germanium (SiGe), or zinc sulfide (ZnS), can also be used to form the cap. It is also possible to provide a cap formed of other types of materials that transmit infrared radiation.

[0051] In one embodiment, the cover includes an anti-reflective region 260. The anti-reflective region promotes transmission of infrared radiation through the cover. In one embodiment, the anti-reflective region includes a bottom grating on the inner (bottom) surface of the cover and a top grating on the outer (top) surface of the cover. The grating can have a moth-eye grating pattern or structure to promote transmission of infrared radiation. The grating can have other types of patterns that promote transmission of infrared radiation. The grating can be formed by etching the surface of the cover. In one embodiment, the grating is arranged to reduce refraction and reflection of incident IR light. In some embodiments, one of the surfaces can be provided with a surface grating. For example, the top surface or the bottom surface can be provided with a surface grating. Other arrangements of gratings can also be used.

[0052] In another embodiment, the anti-reflection zone includes an anti-reflection coating disposed on the front and back sides of the cover. For example, an anti-reflection coating is provided instead of a surface grating or pattern. It is also possible to provide an anti-reflection coating on one of the surfaces. For example, the anti-reflection coating can be disposed on the top surface or the bottom surface. Materials with different reflectivities can be deposited alternately on the surface of the anti-reflection zone. For example, the material for the anti-reflection coating can be zinc sulfide (ZnS) or germanium (Ge). It is also possible to provide any other material and deposition technique for the anti-reflection coating. The anti-reflection coating can be deposited on the cover surface and patterned to remain in the anti-reflection zone. In the case where one of the cover surfaces includes a surface pattern, the other cover surface can include an anti-reflection coating. For example, the anti-reflection zone includes a combination of a surface pattern on one cover surface and an anti-reflection coating on another cover surface.

[0053] In one embodiment, a getter 270 is disposed on the inner surface of the cap. The getter absorbs moisture and degassing inside the packaged device. The getter can be, for example, a zirconium alloy, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba) or magnesium (Mg). Other types of getter materials can also be used, such as rare earth elements including cerium (Ce) or lanthanum (La). The getter helps maintain vacuum and improves reliability. In one embodiment, the getter is disposed outside the MEMS region 245 of the MEMS layer 240 and the anti-reflection region 260 of the cap.

[0054] A sealing ring 280 is employed to facilitate bonding the cap to the substrate. The sealing rings include, for example, a cap sealing ring 280a and a substrate sealing ring 280b. The substrate sealing ring is disposed, for example, on a BEOL dielectric surrounding the MEMS layer. The cap and substrate sealing rings cooperate to bond the cap to the substrate. In one embodiment, the sealing ring may be a metal or a metal alloy. The sealing ring may be a gold-based sealing ring, such as gold, gold-tin, or a combination thereof. Other materials and structures may also be provided for the sealing ring. For example, aluminum, copper, silver-titanium, germanium, tin, titanium nitride, silicon oxide, silicon nitride, or a combination thereof, including gold and gold-tin. In one embodiment, the sealing ring is fitted by thermal compression. Other techniques for bonding the cap to the substrate by forming a thermocompression bond or a eutectic bond are also available.

[0055] When the cap is bonded to the substrate, the cap forms a cap cavity 252, encapsulating the MEMS region 245 inside the cap bonding region 251. In one embodiment, the cap hermetically seals the MEMS region. The cavity volume can be defined, for example, by the height of the sealing ring. In addition, the desired distance between the anti-reflection region and the sensor can be determined by the height of the sealing ring. As discussed, in one embodiment, the lower sensor cavity does not have cavity sidewalls. For example, the lower sensor cavity is in communication with the cap cavity.

[0056] Reference Figure 2a , the cover includes a flat or substantially flat inner and outer surface. It should be understood that the anti-reflection area may include a surface pattern and / or an anti-reflection coating to make it substantially flat. However, flat includes flat and substantially flat. Thus, the volume and distance between the anti-reflection areas are determined by the height of the sealing ring.

[0057] In another embodiment, if Figure 2b As shown, the cover includes a cover recess 256 on its inner surface. The cover recess is, for example, disposed on the bottom surface of the cover outside the anti-reflection zone. The cover recess may have a square or rectangular footprint or shape. Other shapes of the cover recess are also available. Depending on the thickness of the cover wafer, the depth of the cover recess may be in the range of 10, 20, 30, 100 to 500 μm. Cover recesses deeper than 500 um are also available. In one embodiment, the cover recess improves the overall vacuum level within the cavity. For example, the cover recess increases the total volume of the cover cavity between the cover and the MEMS layer. After the cover wafer is bonded to the device substrate, the larger volume improves the overall vacuum level. In this way, better imaging quality can be captured from the device.

[0058] In one embodiment, a getter 270 is disposed on the inner surface of the lid recess. The getter absorbs moisture and degassing within the packaged device. The getter may be, for example, a zirconium alloy, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba) or magnesium (Mg). Other types of getter materials may also be used, such as rare earth elements including cerium (Ce) or lanthanum (La). The getter helps maintain the vacuum and improves reliability.

[0059] In another embodiment, Figure 2c As shown, a cover is provided, except that a cover recess 256 is provided above the MEMS area 245. Providing an anti-reflection area 260 in the cover recess allows the distance between the anti-reflection area and the sensor to be controlled by the depth of the cover recess, which is independent of the height of the sealing ring. A getter 270 can be provided on the inner surface of the cover outside the cover recess. The getter absorbs moisture and degassing within the packaged device. The getter helps maintain a vacuum and improves reliability.

[0060] In another embodiment, Figure 2d As shown, a cover 250 is provided. The cover is processed to include a cover recess 256. The cover recess is, for example, disposed inside a cover bonding area 251 of a cover having a cover sealing ring 280a. For example, the cover bonding area is located at the edge of the inner surface of the cover surrounding the cover recess. For a given sealing ring height, the cover recess increases the overall cover cavity volume. In addition, the depth can be increased by increasing the depth of the cover recess without increasing the sealing ring height. A getter 270 can be disposed on the inner surface of the cover recess outside the anti-reflection area 260 located above the MEMS area 245. The getter absorbs moisture and degassing within the packaged device. The getter helps maintain a vacuum and improves reliability.

[0061] like Figure 2e As shown, a cover 250 is provided having shallow and deep cover recesses 256 and 257. Similar to Figure 2d The cover recess is surrounded by the cover bonding area 251 of the cover having the cover sealing ring 280a. In addition, the deep cover recess is arranged outside the cover anti-reflection area 260. The deep recess increases the volume of the cover cavity 252. The getter 270 can be arranged on the inner surface of the deep recess outside the anti-reflection area 260. The getter absorbs moisture and degassing in the packaged device. The getter helps to maintain vacuum and improve reliability.

[0062] In another embodiment, Figure 2f As shown, a cover 250 is provided. The cover is similar to Figure 2e The capping, except similar to Figure 2c , the deep cover recess 257 is disposed above the MEMS region. For example, the anti-reflection region 260 is located within the deep cover recess. The getter 270 can be disposed on the inner surface of the shallow cover recess 256 outside the deep cover recess. The getter absorbs moisture and degassing within the packaged device. The getter helps maintain vacuum and improves reliability.

[0063] Figure 3 A simplified cross-sectional view of a portion of an embodiment of a device 300 is shown. As shown, the device includes a portion of a device having a CMOS region and a MEMS device region. The device may be similar to Figure 2a-2fCommon elements may not be described or may not be described in detail.

[0064] The device comprises a substrate 301. The substrate may be, for example, a semiconductor substrate, such as a silicon substrate. The substrate may be, for example, a lightly doped p-type silicon substrate. Other types of substrates or wafers may also be used.

[0065] In one embodiment, the substrate includes a CMOS region 310 having CMOS components in a CMOS device region. The CMOS components may include metal oxide semiconductor (MOS) transistors, such as n-type MOS transistors and p-type MOS transistors. As shown, a portion of the device includes a first and a second transistor, each transistor having a gate 312 between S / D regions 314 and 316. The MOS transistor may be an n-type, p-type, or a combination of n-type and p-type MOS transistors. The CMOS region may also include other types of CMOS components, such as diodes, capacitors, and resistors. Isolation regions may be provided to isolate CMOS components. For example, isolation regions are provided to isolate first and second CMOS device regions having first and second transistors.

[0066] An interlayer dielectric (ILD) layer 320 may be disposed on the substrate. The ILD layer covers the substrate and the CMOS region with the CMOS component. The ILD layer is, for example, a silicon oxide layer. Other types of dielectric layers or combinations of dielectric layers are also available. Metal contact plugs 328, such as tungsten plugs, are provided in the ILD layer and are coupled to the contact regions on the substrate and the CMOS component. For example, the contact plugs are coupled to the S / D regions and gates of the CMOS component, and to the well taps for biasing the well and the substrate. Providing contact plugs for other types of contact regions is also available. The contact plugs may, for example, be formed by a damascene process. Other techniques for forming contact plugs are also available.

[0067] A back-end-of-line (BEOL) dielectric 330 is provided on the substrate above the ILD layer 320. The BEOL dielectric may include a plurality of intermetal dielectric (IMD) layers formed from the BEOL dielectric layers. For example, the BEOL dielectric may include y IMD layers, where y is 2–8. Other numbers of IMD layers (including 1) may also be used depending on the design and CMOS process. The ILD layers and the BEOL dielectric may be referred to as a BE dielectric.

[0068] The IMD layer may include a via dielectric layer 336 and a metal dielectric layer 332. The via dielectric layer and the metal dielectric layer of the IMD layer may be formed by one or more dielectric layers, depending on the design and process methods. The via dielectric layer may be disposed above the metal dielectric layer. For example, a metal layer (Mx) may be disposed below the first via layer (Vx). For example, as shown, the BEOL includes three IMD layers (x=1 to 3). The metal dielectric layer includes a metal line 334, and the via dielectric layer includes a via contact 338. The first metal layer dielectric M1 is disposed above the ILD layer. Other configurations of the BEOL dielectric layer are also available.

[0069] Metal lines and via contacts can be formed using damascene techniques, such as single or dual damascene processes. In the case of a single damascene process, contacts and metal lines are formed in separate processes. In the case of a dual damascene process, metal lines and contacts are formed in the same process. For example, metal lines of Mx and via contacts of Vx-1 are formed in the same process. In some embodiments, the IMD layer can be formed by a combination of damascene and reactive ion etching (RIE) processes. For example, metal lines can be formed by an RIE process, while contacts are formed by a single damascene process. In the case of an RIE process, a metal layer is formed and patterned by RIE using an etch mask to form metal lines. It should be understood that different IMD layers of BEOL dielectrics can be formed using different techniques or a combination of techniques or processes. For example, the first IMD layer can form contacts using a damascene process, metal lines can be formed using an RIE process, and the intermediate IMD layer can be formed using a dual damascene process. Alternatively, the IMD layer can be formed by a combination of damascene and RIE processes. Other settings for forming the IMD layer are also available.

[0070] As for the top metal layer (e.g., M3) of the BEOL dielectric, it can be used as a pad layer with a pad metal line. The pad line can be formed by a damascene or RIE process. A passivation layer 337 can be formed above the pad line. The passivation layer can include, for example, one or more dielectric layers. In one embodiment, the passivation layer includes a silicon nitride layer above the silicon oxide layer, forming a SiO2 / SiN passivation stack. Other types of passivation layers or stacks are also available. A pad opening can be provided in the passivation layer to expose the contact pad of the pad line. Other methods for forming the pad layer are also available.

[0071] The ILD and IMD layers can be planarized to form a flat top surface above the CMOS region. For example, CMP is performed on the substrate. Other planarization techniques, such as spin-on-glass (SOG) for filling gaps or planarizing the substrate surface, are also available.

[0072] The MEMS layer 340 is disposed above the BEOL dielectric. In one embodiment, the MEMS layer is a monolithically integrated MEMS layer. In one embodiment, the MEMS layer includes a substrate or buffer layer 339. The substrate layer is a dielectric substrate layer, such as silicon oxide. The substrate layer is used, for example, as an etch stop layer. As discussed, the cross-sectional view is a MEMS device region of a sensor (e.g., an IR sensor) of a MEMS array.

[0073] As shown, the MEMS device region includes a lower sensor cavity 342. For example, the substrate layer serves as the bottom of the lower sensor cavity. In one embodiment, the lower sensor cavity is a common lower sensor cavity of the sensor array. For example, the sensors of the sensor array share the same lower sensor cavity.

[0074] The IR reflector 350 is disposed at the bottom of the lower sensor cavity. The IR reflector may be, for example, a metal IR reflector. For example, the metal IR reflector may be formed of titanium (Ti), tungsten (W), or aluminum (Al). Other types of IR reflectors compatible with post-CMOS are also available.

[0075] The MEMS dielectric layer 358 forms the top of the lower sensor cavity. The MEMS dielectric layer can be, for example, a silicon oxide layer. Other types of dielectric layers can also be used. In some cases, the dielectric layer can be a dielectric layer stack. The MEMS dielectric layer acts as a membrane on which the MEMS structure 362 of the sensor is arranged. In one embodiment, the MEMS structure 362 is a thermopile wire structure used as a thermoelectric IR sensor or detector. Other types of MEMS structures or sensors, including non-IR sensors, can also be arranged in the sensor area.

[0076] In one embodiment, the thermopile wire structure includes first and second polarity doped thermopile wire segments 366 and 368. In one embodiment, the thermopile wire structure includes doped polysilicon. In one embodiment, the doped polysilicon is recrystallized into amorphous silicon using laser annealing. The laser annealing can recrystallize the amorphous silicon and activate the dopants. Other types of thermoelectric materials compatible with post-CMOS can also be used for the thermopile wire structure.

[0077] Metal contacts 370 may be used to couple first and second polarity doped wire segments of the thermopile wire structure. Metal contacts may be provided at the junction of adjacent ends of the wire structure or at the interface of the segments. Other types of metal contacts may also be used. A first sensor terminal 365 is coupled to the first polarity doped thermopile wire segment material, and a second sensor terminal 367 is coupled to the second polarity doped thermopile wire segment material. The terminals may be part of the doped thermoelectric material.

[0078] An absorber layer 372 may be provided above the line structure. The absorber layer is, for example, configured to absorb incident IR radiation. The absorber layer may be a titanium nitride (TiN) layer. Other types of absorber layers may also be used. For example, the absorber layer may be a nickel chromium (NiCr) layer or a doped silicon layer. In one embodiment, the absorber is configured to absorb a majority of the incident IR radiation. For example, the absorber may be configured to absorb greater than 85% of the incident IR radiation having a wavelength of 8–14 μm. Any other configuration may also be provided. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2–5 μm. For example, another harmonic of the interferometric absorber is used. In one embodiment, the absorber is configured to absorb >50% of the incident radiation having a wavelength of 2-5 μm.

[0079] In one embodiment, a sensor protection layer 380 is disposed above the absorber layer. The sensor protection layer is used to protect the sensor from subsequent etching processes. For example, the protection layer is used to protect the line structure and the absorber layer from corrosion by an etchant such as XeF2, which is used to form the lower device cavity in the release process. In one embodiment, the protection layer is a silicon oxide layer. Other types of layers that are transparent to IR radiation and selective to the etchant used to form the lower device cavity in the release process are also available. In one embodiment, the sensor protection layer may include multiple dielectric layers. For example, a first dielectric layer is disposed on the line structure and is patterned to form openings for contacts. Metal contacts and the absorber layer are formed, and then a top protection layer is provided, covering the line structure and the absorber layer.

[0080] Release openings 382 are provided in the dielectric base layer and other layers thereover, such as a protective layer, to enable removal of the lower sensor cavity sacrificial material during a release process to form the lower sensor cavity.

[0081] MEMS to CMOS (MC) contacts 348 may be provided at the MEMS layer. MC contacts provide electrical connection of the MEMS sensor to the CMOS components in the CMOS region. MC contacts are coupled, for example, to the terminals of the sensor and the top metal or pad layer of the BEOL dielectric, which is connected to the CMOS components in the CMOS region. In one embodiment, MC contacts are provided for each sensor of the array. For example, first and second MC contacts are provided for the first and second terminals of each sensor. After the release process, the MC contacts provide mechanical support for the MEMS dielectric layer with the sensor.

[0082] The cap encapsulates the MEMS region of the MEMS layer. The cap forms an upper sensor cavity. In one embodiment, the cap forms a common upper sensor cavity for the MEMS region sensors. A pad opening is provided to expose pads in the CMOS region located at the edge of the MEMS layer.

[0083] Figure 4a A simplified top view of an embodiment of a MEMS sensor or structure 450 is shown. Figure 4b Various cross-sectional views of the MEMS structure along A-A', B-B' and C-C' are shown. The top view does not include the protective layer. The MEMS structure is a wire structure. The wire structure is a thermopile used as a thermoelectric IR sensor or detector. The wire structure is disposed on a membrane or dielectric layer defining the top of the lower device cavity. In one embodiment, the wire structure includes a single wire unit (N=1) having a curved shape and occupying the membrane surface.

[0084] In one embodiment, the line unit comprises recrystallized amorphous silicon. Other types of line units are also available. For example, a post-CMOS compatible thermoelectric material may be used to form the line structure.

[0085] The line unit includes first and second line segments 420 and 440. The first end 451 is part of the first line segment, and the second end 452 is part of the second line segment. In one embodiment, the first end and the second end can be used as a cold junction of the thermopile. A first line structure terminal 454 is arranged at the first end, and a second line structure terminal 456 is arranged at the second end. The terminals are, for example, part of the line unit of the line structure. The terminals are used as terminals of a MEMS structure or a sensor.

[0086] In one embodiment, the first line segment is doped with a dopant of a first polarity type and the second line segment is doped with a dopant of a second polarity type. For example, the first line segment is heavily doped with a dopant of the first polarity type and the second line segment is heavily doped with a dopant of the second polarity type. The first polarity type may be p-type and the second polarity type may be n-type. Providing a first polarity type of n-type and a second polarity type of p-type is also possible. Separate implants may be used to dope the line segments.

[0087] The line structure can be patterned using mask and etching techniques. For example, a photoresist is disposed on the line structure layer. The photoresist can be exposed by an exposure source through a mask containing a desired line structure pattern. After development, the pattern of the mask is transferred to the photoresist to form an etching mask. The line structure layer is patterned using an etching mask to form a line structure using etching. The etching mask can be, for example, a photoresist mask. Etching can be, for example, an anisotropic etching, such as reactive ion etching (RIE). Other etching processes can also be used. In one embodiment, etching forms a line structure having a first and a second line segment. Alternatively, the line structure can be a discontinuous line structure having, for example, a first and a second segment. The first segment and the second segment can be electrically connected by a metal contact.

[0088] As shown in the figure, the wire segments are mirror images of each other. This results in wire segments of approximately the same length. By providing the wire segments with a meandering design, the sensor area can be used efficiently while forming a wire structure with a desired resistance. For example, the resistance of the wire structure is approximately 5–50 kΩ. Other resistances are also available.

[0089] To dope the first and second segments, separate implants may be used. For example, a first implant using a first implant mask is used to dope the first segment, and a second implant using a second implant mask is used to dope the second segment. In one embodiment, the segments are recrystallized αSi segments. Laser annealing is used to recrystallize the αSi segments and activate the dopants.

[0090] A wire dielectric layer 458 covers the wire structure, filling the gaps. The wire dielectric layer provides mechanical support for the thermopile film. The wire dielectric layer can be, for example, spun glass (SOG). Other types of wire dielectric layers are also possible. The top surface of the dielectric layer can be located 100-400 nm above the top of the wire structure. Providing a dielectric layer with other thicknesses above the top of the wire structure is also useful.

[0091] A contact 466 is provided to electrically couple the first and second segments. The contact is, for example, a metal contact, such as titanium (Ti) or aluminum (Al). Other types of contacts are also available. To form the contact, a contact opening is formed in the dielectric layer to expose the wire structure near the junction of the first segment and the second segment. A metal layer is formed on the substrate and patterned so that the contact couples the first segment and the second segment. The metal layer can be, for example, titanium (Ti) or aluminum (Al) formed by sputtering or electroplating. Other types of metal layers or formation techniques are also available.

[0092] An absorber layer 457 is formed on the substrate, covering the dielectric layer. The absorber layer can be patterned using an etch and mask process. The patterned absorber layer serves as an absorber above the wire structure. In one embodiment, the absorber layer is patterned, covering the central portion of the wire structure and the contact, leaving the leg portions outside the central portion exposed. The absorber layer absorbs IR radiation, for example. The absorber layer can be a TiN or NiCr layer. The absorber layer can be formed, for example, by sputtering. Other types of absorber layers are also available. In one embodiment, the absorber is configured to absorb most of the IR radiation. For example, the absorber can be configured to absorb greater than 85% of IR radiation with wavelengths of 8 to 14 μm. Absorption of other wavelengths is also possible. As shown, the absorber layer is disposed above the contact. The absorber serves as a hot junction of the thermopile. The first end 451 of the first wire structure and the second end 452 of the second wire structure serve as the cold junction of the thermopile. The leg portions of the wire structure not covered by the absorber provide thermal isolation between the hot junction and the cold junction.

[0093] A protective layer 459 may be provided. The protective layer, for example, covers the MEMS structure. The protective layer protects the MEMS structure from the effects of subsequent processes. The protective layer is, for example, a silicon oxide layer formed by CVD. Other types of protective layers are also available.

[0094] Figure 4c A sensor array 404 is shown. The sensor array includes a plurality of sensor cells 410. The sensor cells include switches coupled to a MEMS structure, such as a Figure 4a-4b One or more line structures described in the description. Common elements may not be described or described in detail.

[0095] The sensor cells are arranged to form an array having M rows and N columns. The sensor cells correspond to pixels of the sensor array. The sensor cells are connected by row lines (RL m ) in the row direction, through the column line (CL n ) are coupled in the column direction. The sensor units may correspond to pixels. In addition, common lines (Coms) are also used to couple the sensor units in each column. For example, each column of the sensor is coupled to a respective Com (e.g., Com1, Com2, or Com3). As shown, the array includes a 2x 3 array (M=2 and N=3). For example, the sensor units are arranged in 2 rows (RL1 and RL2) and 3 columns (CL1, CL2, and CL3). Arrays of other sizes are also available. For example, the sensor array may be a 32x 32 or 80x 62 array.

[0096] The pixels of the sensor array may include a plurality of sensors arranged in a matrix on a substrate. For example, each pixel may include a sensor region and a CMOS switch or connection region. The sensor region is disposed in, for example, a sensor array region of the substrate. For example, the sensor array region includes a plurality of sensor regions corresponding to the sensor pixels.

[0097] In one embodiment, a first terminal of the MEMS structure of the sensor cell is coupled to the switch 495 and a second terminal is coupled to a common line (Com). As shown, each column of the sensor cells is coupled to a respective Com (e.g., Com1, Com2, and Com3). The switch can be a transistor having a first and a second S / D terminal and a gate or control terminal. For example, the first S / D terminal of the switch is coupled to the first terminal of the MEMS structure and the second S / D terminal is coupled to CL. RL is coupled to the gate or control terminal of the switch. In one embodiment, the n-type terminal of the sensor cell is coupled to Com and the p-type terminal of the sensor cell is coupled to CL. Other settings for coupling the sensor cells to CL and Com are also available. An RL can be selected to select a row of sensor cells. CL is activated to select a column of sensor cells. The selected cell is the intersection of the selected RL and CL. The interconnects between the CMOS components and the sensor pixels can be implemented through the ILD and IMD layers of the BEOL dielectric.

[0098] In one embodiment, the sensor array is configured to read out a row of sensor cells or pixels. For example, a row of array pixels is read out at a time. In one embodiment, the RL of the array is selected. This selects a row of pixels. The CL is then selected so that the pixels of the selected RL are read out. In one embodiment, the array is configured to read out a row of pixels at a time from the first row to the last row. The readout information is stored in a memory. After all pixels are read out or all rows are scanned, an image or frame of the imager is generated. For example, the information read out from the pixels stored in the memory can be reconstructed to form an image.

[0099] exist Figure 4cIn the case of a 2×3 array in FIG. 1 , scanning pixels to form an image may include selecting RL1 (the first row) to select pixels coupled to RL1. After selecting RL1, CL1, CL2, and CL3 are selected so that the pixels coupled to RL1 are read out. The pixel information coupled to RL1 is stored in a memory. The next or second row RL2 is selected to select pixels of RL2. After selecting RL2, CL1, CL2, and CL3 are selected so that the pixels coupled to RL2 are read out. The pixel information coupled to RL2 is stored in a memory. Since RL2 is the last row of the array, the pixel information is reconstructed to form an image or frame of the imager. By repeating the sensing, readout, and reconstruction processes, many frames may be collected. For example, the image or frame is time-dependent. A selection logic and output logic component may be used to select a cell for outputting information. The logic component may be a CMOS transistor or component located in a CMOS region of the device. Other logic components may be included, including a memory and a reconstruction logic component, to store and reconstruct information to form one or more images. In one embodiment, the memory and the reconstruction logic component may be off-chip logic. Providing these logic components as on-chip logic components or a combination of on-chip or off-chip components is also possible.

[0100] Figure 5a-5i A simplified cross-sectional view of a process for forming a device is shown. The device may be similar to Figure 2a-2f As shown in the figure, the cross-sectional view is, for example, Figure 3 The device described is a part of the device. For example, the part of the device includes a CMOS area and a MEMS area. Common elements may not be described or described in detail.

[0101] Reference Figure 5a , a device 500 is provided. For example, the device has been processed to form a CMOS component in a CMOS region 510 on a substrate 501. The device includes a substrate 501. The substrate can be, for example, a semiconductor substrate, such as a silicon substrate. The substrate can be, for example, a lightly doped p-type silicon substrate. Other types of substrates or wafers can also be used.

[0102] CMOS components may include pMOS and nMOS transistors. Other CMOS components such as resistors, capacitors, and diodes may also be included in the CMOS region. CMOS components are configured to include digital and analog circuits. As shown, a portion of CMOS region 510 includes a first and a second transistor. The transistor includes a gate 512 between S / D regions 514 and 516. Isolation regions such as FOX or STI may be provided to isolate CMOS components. For example, an isolation region is provided to isolate a first and a second CMOS device region having a first and a second transistor.

[0103] An ILD layer 520 is formed on the substrate. The ILD layer covers the substrate and the CMOS region having the CMOS group. The ILD layer is, for example, a silicon oxide layer. Other types of dielectric layers or combinations of dielectric layers are also available. Metal contact plugs 528, such as tungsten plugs, are provided in the ILD layer and coupled to the contact regions on the substrate and the CMOS component. For example, the contact plugs are coupled to the S / D regions and gates of the CMOS component, and to the well taps for biasing the well and the substrate. Providing contact plugs for other types of contact regions is also available.

[0104] The contact plug can be formed, for example, by a damascene process. For example, an ILD layer is formed on a substrate. The surface of the ILD layer can be planarized by, for example, chemical mechanical polishing (CMP). The ILD is patterned to form a contact hole in the ILD layer. A metal layer such as tungsten is deposited on the substrate to fill the contact opening. Excess metal above the ILD layer can be removed by, for example, CMP, leaving the contact plug in the contact opening. Other techniques for forming the contact plug are also available.

[0105] A back-end-of-line (BEOL) dielectric 530 is provided on the substrate above the ILD layer 520. For example, the BEOL dielectric covers the CMOS region. The BEOL dielectric may include a plurality of intermetal dielectric (IMD) layers formed by the BEOL dielectric layers. For example, the BEOL dielectric may include y IMD layers, where y is 2–8. Other numbers of IMD layers (including 1) may also be used depending on the design and CMOS process. The ILD layers and the BEOL dielectric may be referred to as a BE dielectric.

[0106] The IMD layer may include a via dielectric layer 536 and a metal dielectric layer 532. The via dielectric layer and the metal dielectric layer of the IMD layer may be formed by one or more dielectric layers, depending on the design and process methods. The via dielectric layer may be disposed above the metal dielectric layer. For example, a metal layer (Mx) may be disposed below the first via layer (Vx). For example, as shown, the BEOL includes three IMD layers (x=1 to 3). The metal dielectric layer includes a metal line 534, and the via dielectric layer includes a via contact 538. The first metal layer dielectric M1 is disposed above the ILD layer. Other configurations of the BEOL dielectric layer are also available.

[0107] As shown, the BEOL dielectric includes 3 IMD layers. For example, the first IMD layer includes M1 and V1, the second IMD layer includes M2 and V2, and the third or top IMD layer includes M3. In one embodiment, M1 can be formed by a single damascene technique. For example, an M1 dielectric can be formed above the IMD layer and patterned to form a trench corresponding to the M1 metal line. A metal layer such as copper or a copper alloy can be formed on the substrate, filling the trench and covering the M1 dielectric. Other types of metals or alloys, such as aluminum, can also be used. Excess metal is removed by CMP, and the M1 metal line is retained in the M1 dielectric. It is also possible to form M1 using an RIE process. In the RIE process, a metal layer is formed on the ILD layer and patterned to form the M1 metal line. A dielectric layer is formed on the substrate to fill the gaps between the metal lines. CMP can be performed to remove excess dielectric layers. In some cases, the dielectric can be a self-planarizing layer, such as spin-on glass.

[0108] For M2 and V1, they can be formed by a dual damascene process. For example, a dielectric layer can be formed above M1 on a substrate. The dielectric layer is patterned to form a trench for M2 and a via opening for V1 to form a dual damascene structure. The dual damascene structure can be formed using a via-first or via-last dual damascene process. In addition, multiple dielectric layers can be used to form a dual damascene structure. For example, an etch stop layer can be used between M1 and V1. A metal layer such as copper or a copper alloy can be formed on the substrate to fill the dual damascene structure. Other types of metals or alloys, such as aluminum, can also be used. Excess metal is removed by CMP, leaving the M2 metal line above the V1 via contact. Forming M2 and V1 using other processes, such as a single damascene for V1 and a combination of RIE for M2, is also available.

[0109] The formation of M3 and V2 can be similar to that of M2 and V1. In other embodiments, V2 can be formed using a damascene process, and M3 can be formed using a damascene process or a RIE process. M3 can be formed of aluminum, for example. Other types of metals, such as copper or copper alloys, can also be used.

[0110] As for M3, it can be used as a pad layer. For example, the M3 metal line can be used as a pad metal line. A passivation layer 537 can be formed above the pad line. The passivation layer can include, for example, one or more dielectric layers. In one embodiment, the passivation layer includes a silicon nitride layer above the silicon oxide layer, forming a SiO2 / SiN passivation stack. Other types of passivation layers or stacks are also available. A pad opening can be provided in the passivation layer to expose the contact pad of the pad line. Other methods for forming the pad layer are also available.

[0111] exist Figure 5bIn one embodiment, the process begins by forming a substrate or buffer layer 539 on the passivation layer. The substrate layer is a dielectric substrate layer, such as silicon oxide. Other types of substrate layers are also available. The substrate layer can be formed by chemical vapor deposition. In one embodiment, the substrate layer can be formed by a low temperature process. For example, the buffer layer can be formed by PECVD. Other low temperature processes, such as LPCVD or APCVD are also available. The substrate layer should be thick enough to protect the underlying passivation layer from corrosion by an etchant (e.g., XeF2) that is used to form the lower sensor cavity in a subsequent release process.

[0112] The IR reflector 550 is formed on the base layer. The IR reflector can be a metal IR reflector. For example, the metal IR reflector can be formed of titanium (Ti), tungsten (W) or aluminum. Other types of infrared reflectors are also available. To form the IR reflector, a metal layer of the IR reflector is formed on a substrate. For example, the metal layer is formed on the base layer. The metal layer can be formed by, for example, sputtering. Other techniques for forming the metal layer are also available. The metal layer is patterned to form the IR reflector. Patterning the metal layer can include a mask and an etching process. For example, a resist mask is formed over the metal layer and developed to expose portions of the metal layer to be removed by an etching process, such as reactive ion etching (RIE). Other techniques for patterning the metal layer are also available. The patterning process, for example, forms individual IR reflectors for sensors of a sensor array.

[0113] In one embodiment, Figure 5c As shown, a sacrificial layer 559 is formed on the substrate. The sacrificial layer is, for example, a low temperature sacrificial layer. In one embodiment, the sacrificial layer is an amorphous silicon (αSi) amorphous layer. The αSi sacrificial layer is formed using a low temperature process. For example, the sacrificial layer is formed using a low temperature process, such as PECVD at a temperature below 400°C. Other types of low temperature sacrificial layers and / or low temperature processes for forming sacrificial layers are also available.

[0114] In one embodiment, the thickness of the sacrificial layer is used to define the height of the lower sensor cavity of the sensor array. For example, the thickness of the sacrificial layer should be equal to the height of the lower sensor cavity. For example, in the case where the lower sensor cavity is 1.2 um high, the sacrificial layer should be about 1.2 um high.

[0115] Reference Figure 5d , a MEMS dielectric layer 558 is formed on the substrate. For example, the MEMS dielectric layer is formed on the sacrificial layer. In one embodiment, the MEMS dielectric layer is used as a membrane layer for the sensor of the MEMS region. In one embodiment, the MEMS dielectric layer is a low temperature oxide. For example, a lower temperature oxide can be formed by PECVD. Other low temperature processes can also be used to form the MEMS dielectric layer.

[0116] The MEMS structure layer 562 is formed on the substrate. For example, the MEMS structure layer is formed on the MEMS dielectric layer. In one embodiment, the MEMS structure layer is an αSi layer. The MEMS structure layer is formed by a low temperature process. For example, the MEMS structure layer can be formed by PECVD.

[0117] like Figure 5e As shown, the process begins to form a MEMS structure. In one embodiment, the process begins to form a thermopile structure for a MEMS device region. For example, a thermopile structure is formed for each MEMS device region of the sensor array. In one embodiment, the process includes patterning a MEMS structure layer 562 to form a thermopile wire structure. For example, the thermopile wire structure includes first and second wire segments 566 and 568.

[0118] The line segments are doped with dopants of first and second polarity types. For example, the first line segment is doped with a dopant of a first polarity type, such as n-type, and the second line segment is doped with a dopant of a second polarity type, such as p-type. The doping of the first and second line segments can be achieved by ion implantation. For example, a first implant mask is used to dope the first line segment for a first ion implantation, and a second implant mask is used to dope the second line segment for a second ion implantation. Alternatively, the doping of the line segments can be achieved by in-situ doping when forming the MEMS structure layer. For example, the MEMS structure layer is doped when deposited.

[0119] The doped wire segments are treated to crystallize the MEMS structure layer. For example, the wire segments are treated to crystallize the αSi wire segments. In one embodiment, pulsed laser annealing is used to achieve recrystallization of the wire segments. Pulsed laser annealing can be performed using an excimer laser. Other types of pulsed laser annealing are also available. Laser annealing also activates the dopants of the doped wire segments. Alternatively, other techniques can be used to recrystallize the wire segments.

[0120] A dielectric layer 580 is formed above the thermopile structure. The dielectric layer may be, for example, an intermediate dielectric layer that is disposed above the MEMS dielectric layer and covers the thermopile structure. In one embodiment, the intermediate dielectric layer is a low temperature oxide layer. For example, similar to the MEMS dielectric layer, the oxide layer is formed by a low temperature process.

[0121] Reference Figure 5f, forming a contact 570 on the intermediate layer connecting the first and second line segments. For example, a thermopile connection bridge or contact is formed to connect the first and second line segments. In one embodiment, forming the contact includes forming a contact opening in the intermediate dielectric layer. For example, a first contact opening is formed to expose the adjacent end of the first line segment adjacent to the second line segment, and a second contact opening is formed to expose the adjacent end of the second line segment adjacent to the first line segment. A metal layer such as Ti is formed on the intermediate dielectric layer. Other types of metal layers can also be used. The metal layer is, for example, lined on the top of the intermediate dielectric layer and the contact opening. The metal layer is patterned to form a connection bridge connecting the first and second line segments.

[0122] An absorber 572 is formed on the line structure. For example, the absorber is formed on the line structure and covers the contact 570. In one embodiment, the absorber is formed to cover a central portion of the line structure, including the contact. The absorber layer is, for example, configured to absorb incident IR radiation. The absorber can be a titanium nitride (TiN) absorber. Other types of absorbers are also available. For example, the absorber layer can be a nickel chromium (NiCr) layer or a doped amorphous silicon layer. In one embodiment, the absorber is configured to absorb a majority of the incident IR radiation. For example, the absorber can be configured to absorb greater than 85% of the incident IR radiation having a wavelength of 8-14 μm. Any other configuration is also available. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2-5 μm. For example, another harmonic of the interferometric absorber is used. In one embodiment, the absorber is configured to absorb >50% of the incident radiation having a wavelength of 2-5 μm.

[0123] To form the absorber, an absorber layer is formed on the substrate, covering the line structure, contacts and the intermediate dielectric layer. Depending on the material of the absorber layer, the absorber layer can be formed by sputtering or a low temperature process. For example, a metal absorber layer can be formed by sputtering and an amorphous silicon layer can be formed by a low temperature process. The amorphous silicon layer can be doped in situ or by ion implantation. After the absorber layer is deposited, it is patterned to form the absorber.

[0124] A top dielectric layer 581 is formed on the substrate, covering the line structure and the absorber. The top dielectric layer serves as a protective layer over the line structure. In one embodiment, the top dielectric layer is a low temperature oxide. For example, the oxide is formed by a low temperature process. Other types of dielectric layers may also be used.

[0125] exist Figure 5g, MC contacts 548 are formed. The MC contacts provide electrical connection of the MEMS sensor to the CMOS components in the CMOS area. The MC contacts are coupled, for example, to the terminals of the sensor and the top metal or pad layer, which is connected to the CMOS components in the CMOS area. In one embodiment, MC contacts are provided for each sensor of the array. For example, first and second MC contacts are provided for the first and second terminals 565 and 567 of each sensor. In one embodiment, the MC contacts can be coupled to the CMOS transistors in the CMOS area. For example, one terminal is coupled to the gate of the CMOS transistor and the other terminal is coupled to the common line. Other arrangements of MC contacts are also available.

[0126] To form the MC contact, a MC contact via may be formed. For example, the MC contact via is formed by a mask and etch process, such as RIE using a resist mask. The contact via extends from the protective dielectric layer to the top metal layer M3 of the BEOL dielectric layer 530. As shown, the contact via includes a wider opening in the protective dielectric layer and the intermediate dielectric layer to expose the top surface of the first and second terminals of the line structure of the line. For example, a two-step etch is used, one etch to form a wider upper portion and the other etch to form a narrower lower portion. In one embodiment, the first etch is used to form the upper portion and the second etch is used to form the lower portion. A metal layer is formed on the substrate, filling the contact via opening and covering the exposed terminals and the surface of the protective dielectric layer. The metal layer may be, for example, copper or a copper alloy. Other types of metal layers are also available. The metal layer may be formed by electroplating or sputtering. Other techniques for forming the metal layer are also available. Excess metal is removed by CMP so that the top metal is coplanar with the protective layer. Other techniques for removing excess metal, such as RIE, are also available.

[0127] Reference Figure 5h , a release opening 582 is formed in the dielectric stack, which includes the MEMS dielectric layer 558 and the layers above it. For example, a release opening is formed through the protective layer 581, the intermediate dielectric layer 580 and the MEMS dielectric layer 558. For example, the release opening exposes the sacrificial layer 559 that fills one or more cavities. The release opening can be formed using a mask and etching process. For example, RIE can be used using an etch mask to form the release opening. Other techniques for forming the release opening are also available.

[0128] exist Figure 5i In one embodiment, the sacrificial layer is removed to form a lower sensor cavity. In one embodiment, the sacrificial layer is removed by, for example, a release etch. The release etch may be, for example, a dry MEMS release etch. The dry MEMS release etch may employ a release etch, such as XeF2. Other types of release processes may also be used. After the release etch, the MC contacts provide mechanical support for the MEMS dielectric layer with the sensor.

[0129] The process continues to form a cap over the MEMS area. For example, the cap forms a cap cavity that encapsulates the MEMS sensor. In one embodiment, the cap forms a common cap cavity for the sensors in the MEMS area. For example, the cap can be bonded to the device using a bonding ring on the cap and on the BEOL dielectric outside the MEMS layer. For example, the bonding can be achieved using thermocompression bonding. Other bonding techniques are also available. In one embodiment, wafer-level vacuum packaging is performed to bond the cap wafer to the device wafer. Before forming the cap to encapsulate the device, a pad opening can be formed to expose the pads of the pad layer. The pads are located, for example, outside the cap bonding area.

[0130] Figure 6a A graph 600 of laser power over time is shown. Figure 6b Shows the use of Figure 6a The laser source simulates the structure 601 by laser annealing. For example, the structure is similar to the structure used to form a CMOS device monolithically integrated with a MEMS sensor. The thickness of each layer is shown. Figure 6c Shows Figure 6b 602 shows a graph of the temperature at different portions of the structure of the sensor line. As shown, the laser annealing can effectively recrystallize the amorphous silicon layer used to form the sensor line structure and activate the dopants of the line structure while maintaining the peak temperature of the top metal layer (M3) and the structure below it at less than or equal to 350°C and below the post-CMOS compatible temperature. Other techniques can also be used to recrystallize the line segments while maintaining the top metal layer (M3) and the structure below it within the post-CMOS compatible temperature.

[0131] As previously described, the device monolithically integrates the MEMS component with the CMOS component. In one embodiment, the monolithic integration of the MEMS component after the fabrication of the CMOS component is facilitated by depositing the MEMS structural layers such as αSi using a low temperature process, doping the layers, recrystallizing the layers, and activating the dopants using pulsed laser annealing such as an excimer laser. The laser annealing can recrystallize the MEMS structural layers and activate the dopants without heating the BEOL dielectric and ILD layers above a threshold temperature. For example, the metal layers in the ILD and BEOL dielectric can be maintained at about 350°C, which is well within the thermal budget of the post-CMOS process.

[0132] The present disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. Therefore, the foregoing embodiments should be considered in all respects to be illustrative rather than limiting the invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description, and all changes falling within the equivalent meaning and scope of the claims are intended to be included therein.

Claims

1. A method for forming a MEMS device, comprising: A substrate is provided, wherein the substrate is prepared A complementary metal oxide CMOS region having CMOS components, and a BE dielectric having interconnects for interconnecting said CMOS components; forming a MEMS layer in a MEMS region on a top surface of the BE dielectric, comprising, forming a MEMS structure layer including amorphous silicon, patterning the MEMS structure layer to form a MEMS structure of a MEMS component, and recrystallizing the MEMS structure to form a MEMS structure of recrystallized polysilicon of the MEMS component; forming a substrate sealing ring on the BE dielectric surrounding the MEMS layer; providing a closure having a cap inner surface and a cap outer surface, wherein the cap inner surface includes a cap sealing ring; and The cap sealing ring of the cap is bonded to the substrate sealing ring on the BE dielectric to hermetically seal the MEMS layer.

2. The method for forming a MEMS device according to claim 1, wherein forming the MEMS layer comprises: forming a buffer layer on a top surface of the BE dielectric; forming a sacrificial layer on the buffer layer; forming a MEMS dielectric layer on the sacrificial layer; A MEMS structure layer is formed on the MEMS dielectric layer, wherein the MEMS structure layer includes amorphous silicon.

3. The method of forming a MEMS device according to claim 2, comprising: patterning the MEMS structure layer including amorphous silicon to form a MEMS structure of the MEMS component; doping the MEMS structure; as well as The MEMS structure is laser annealed, wherein the laser annealing forms the MEMS structure in a recrystallized state with activated dopants. 4 . The method of forming a MEMS device of claim 3 , wherein doping the MEMS structure comprises implanting ions into the MEMS structure.

5. The method for forming a MEMS device according to any one of claims 2 to 4, comprising: forming MC contacts to connect terminals of a MEMS structure to interconnects in the BE dielectric, wherein the MC contacts extend through layers beneath the MEMS structure, including a sacrificial layer; forming a release opening in the MEMS dielectric layer to expose the sacrificial layer; as well as The sacrificial layer is removed to form a bottom MEMS cavity between the MEMS structure and the buffer layer on the top surface of the BE dielectric, wherein MC contacts mechanically support the MEMS dielectric layer with the MEMS structure suspended above the bottom MEMS cavity.

6. The method for forming a MEMS device according to claim 5, wherein: The MEMS component of the MEMS region includes a pyroelectric based infrared (IR) sensor array having an IR sensor.

7. A MEMS device comprising: a substrate fabricated with a complementary metal oxide CMOS region having CMOS components and a BE dielectric having interconnects for interconnecting the CMOS components; a MEMS layer disposed in a MEMS region on a top surface of the BE dielectric, wherein the MEMS layer includes a MEMS region having a MEMS component, the MEMS component including a recrystallized polysilicon structure, wherein the MEMS layer occupies a portion of the BE dielectric layer; a substrate sealing ring surrounding the MEMS layer on the BE dielectric; a closure having a cap inner surface and a cap outer surface, wherein the cap inner surface includes a cap sealing ring; and Therein, the cover sealing ring of the cap is bonded to the substrate bonding ring on the BE dielectric to hermetically seal the MEMS layer.

8. The MEMS device according to claim 7, wherein: The MEMS layer includes: a buffer layer on a top surface of the BE dielectric; MEMS dielectric layer; and A MEMS structure layer located on the MEMS dielectric layer, wherein the MEMS structure layer includes an amorphous silicon structure that can be converted into a recrystallized polysilicon structure of a MEMS component, and is laser annealed to form a laser annealed recrystallized gold crystal silicon MEMS structure; A bottom MEMS cavity is disposed between the MEMS dielectric layer and the MEMS buffer layer.

9. The MEMS device according to claim 8, comprising: MC contacts for connecting terminals of the MEMS structure to interconnects in the BE dielectric, the MC contacts extending through a layer of the MEMS layer below the MEMS structure; and Wherein, the MC contact mechanically supports a MEMS dielectric layer having a recrystallized MEMS structure suspended above the bottom MEMS cavity.

10. The MEMS device according to any one of claims 7 to 9, wherein: The MEMS region includes a pyroelectric based infrared (IR) sensor array having an IR sensor.

Images