Buffer circuit, receiver circuit and semiconductor device

Abstract

The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data according to a first enable signal and to invert and output the data; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate according to the first enable signal and output the inverted output as a first buffer signal, and configured to compensate for a duty cycle skew of the first buffer signal according to a level of an external voltage.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor circuits, and more particularly, to a buffer circuit, a receiver circuit including the buffer circuit, and a semiconductor device including the receiver circuit. Background Art

[0002] The semiconductor device includes a receiver circuit for receiving an input signal provided from the outside.

[0003] The receiver circuit may operate according to a heterogeneous power supply voltage, ie, a power supply voltage provided from the outside (hereinafter, referred to as an external power supply voltage) and / or an internally generated power supply voltage (hereinafter, referred to as an internal power supply voltage).

[0004] It is very important that the receiver circuit has stable output characteristics regardless of variations in the heterogeneous supply voltage. Summary of the invention

[0005] In an embodiment, a buffer circuit may include: a first logic gate, which is connected to an internal voltage terminal and configured to receive data according to a first enable signal and invert and output the data; and a second logic gate, which is connected to the internal voltage terminal and configured to invert the output of the first logic gate according to the first enable signal and output the inverted output as a first buffer signal, and is configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

[0006] In an embodiment, a receiver circuit may include: a first buffer circuit, which is connected to an internal voltage terminal and is configured to receive data according to a first enable signal and output the data as a first buffer signal and compensate for a duty cycle skew of the first buffer signal according to an external voltage; and a second buffer circuit, which is configured to receive data in response to a reference voltage according to a second enable signal and output the data as a second buffer signal, wherein an output terminal of the first buffer circuit and an output terminal of the second buffer circuit are connected to each other.

[0007] In an embodiment, a semiconductor device may include: a receiver circuit connected to an internal voltage terminal and configured to generate received data by performing a first data reception operation of receiving data according to a first enable signal and outputting the data as a first buffer signal and compensating for a duty cycle skew of the first buffer signal according to an external voltage; a memory area; and a write path circuit including a circuit configuration for writing the received data in the memory area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a configuration of a semiconductor system according to an embodiment.

[0009] Figure 2 is a diagram showing a configuration of a semiconductor device according to an embodiment.

[0010] Figure 3 is a diagram showing a configuration of a receiver circuit according to an embodiment.

[0011] Figure 4 It is shown Figure 3 A diagram of the configuration of the first buffer.

[0012] Figure 5 is a diagram showing a configuration of a receiver circuit according to another embodiment.

[0013] Figure 6 It is shown Figure 5 A diagram of the configuration of the first buffer.

[0014] Figure 7 It is shown Figure 5 FIG. 1 is a diagram of an example of a circuit configuration of a first buffer. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0016] Various embodiments may be directed to providing a buffer circuit capable of having stable output characteristics regardless of a variation in a power supply voltage, a receiver circuit including the buffer circuit, and a semiconductor device including the receiver circuit.

[0017] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component. For example, without departing from the scope of the concept according to the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0018] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0019] Logical "high" level and logical "low" level can be used to describe the logical level of an electrical signal. A signal with a logical "high" level can be distinguished from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage corresponds to a signal with a logical "low" level. In an embodiment, the logical "high" level can be set to a voltage level higher than the voltage level of the logical "low" level. In addition, according to the embodiment, the logical level of the signal can be set to be different or opposite. For example, a specific signal with a logical "high" level in one embodiment can be set to have a logical "low" level in another embodiment. In addition, the configuration of the logic gate or multiple logic gates required to implement the same function or operation can be modified. That is, according to the specific circumstances, a logic gate configuration of one type of operation and another logic gate configuration for the same type of operation can be replaced with each other. If necessary, various logic gates can be applied to achieve the configuration.

[0020] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the beginning of the process or algorithm, or may be set during the period of execution of the process or algorithm.

[0021] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0022] Figure 1 is a diagram showing a configuration of a semiconductor system 100 according to an embodiment.

[0023] Reference Figure 1 , a semiconductor system 100 according to an embodiment may include a semiconductor device 101 and a memory controller 103 .

[0024] The memory controller 103 may provide a power supply voltage, data DQ, a reference voltage VREF, and / or a control signal CRTL to the semiconductor device 101 .

[0025] The power supply voltage is a power supply for the operation of the semiconductor device 101 , and is hereinafter referred to as an external voltage VCCQ.

[0026] The control signal CRTL may include a plurality of signals, ie, a command, an address, and various signals for controlling data reception of the semiconductor device 101 .

[0027] Various signals for controlling data reception may have different values ​​according to the operation mode of the semiconductor device 101. Various signals for controlling data reception may have different values ​​according to, for example, a low speed mode, a high speed mode, etc. defined in the specification of the semiconductor device 101 (to be described below).

[0028] The memory controller 103 may receive data DQ provided from the semiconductor device 101 .

[0029] The semiconductor device 101 may include a volatile memory device such as a DRAM and / or a nonvolatile memory device such as a NAND FLASH.

[0030] The semiconductor device 101 may receive data DQ provided from the memory controller 103 and write the data DQ in the internal memory area according to the control signal CRTL, or read data DQ written in the internal memory area and provide the data DQ to the memory controller 103 according to the control signal CRTL.

[0031] Figure 2 is a diagram showing a configuration of a semiconductor device according to an embodiment.

[0032] Reference Figure 2 , a semiconductor device 101 according to an embodiment may include a memory region 110 , a write path circuit 130 , a pad array 150 , and a receiver circuit 200 .

[0033] The memory area 110 may include a volatile memory cell array (eg, DRAM) and / or a nonvolatile memory cell array (eg, NAND FLASH) and various circuits for data input / output between the memory cell array and the outside of the memory area 110 .

[0034] Write path circuit 130 may include various circuit configurations for writing received data RXOUT in memory region 110 .

[0035] The pad array 150 may include pads 151 , 153 , 155 , . . . for receiving data DQ, a reference voltage VREF, and a control signal CRTL.

[0036] According to the control signal CRTL, the receiver circuit (RX) 200 may selectively perform a first data receiving operation of receiving data DQ regardless of a reference voltage VREF and a second data receiving operation of receiving data DQ in response to the reference voltage VREF.

[0037] The receiver circuit 200 may output a result of the first data reception operation or a result of the second data reception operation as reception data RXOUT.

[0038] Figure 3 is a diagram showing a configuration of a receiver circuit 200 according to an embodiment.

[0039] Figure 2 The receiver circuit 200 may be implemented in various ways. Figure 3is a diagram showing a configuration of a receiver circuit 200 - 1 according to an embodiment.

[0040] Reference Figure 3 , the receiver circuit 200 - 1 according to the embodiment may include a first buffer circuit ( BF1 ) 300 , a second buffer circuit ( BF2 ) 500 , and a multiplexing circuit (MUX) 700 .

[0041] When the first enable signal EN_CMOS is enabled, the BF1 300 may perform a first data receiving operation of receiving data DQ and outputting the data DQ as a first buffer signal BF1OUT.

[0042] When the third enable signal EN_VREFCMOS is disabled, BF1 300 may fix the first buffer signal BF1OUT to a predetermined level, thereby substantially preventing the first buffer signal BF1OUT from transitioning. The term "predetermined" (e.g., predetermined level) used herein with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0043] When the second enable signal EN_VREF is enabled, the BF2 500 may perform a second data receiving operation of receiving data DQ according to the reference voltage VREF and outputting the data DQ as the second buffer signal BF2OUT.

[0044] BF2 500 may fix the second buffer signal BF2OUT to a predetermined level according to the third enable signal EN_VREFCMOS, thereby substantially preventing the second buffer signal BF2OUT from transitioning.

[0045] The MUX 700 may output one of the first buffer signal BF1OUT and the second buffer signal BF2OUT as the reception data RXOUT according to the second enable signal EN_VREF.

[0046] Reference Figure 1 and Figure 2 The described control signal CRTL may include a first enable signal EN_CMOS, a second enable signal EN_VREF, and a third enable signal EN_VREFCMOS.

[0047] When the semiconductor device 101 is operated in the low-speed mode defined in the specification, the memory controller 103 may enable the first enable signal EN_CMOS to, for example, a high level, and may disable the second enable signal EN_VREF to, for example, a low level. The low-speed mode may refer to an operation mode in which the operating frequency of the semiconductor device 101 is selected to be a first value defined in the specification. With the first enable signal EN_CMOS enabled and the second enable signal EN_VREF disabled, the BF 1300 suitable for the low-speed operation may be selected and the first data receiving operation may be performed.

[0048] When the semiconductor device 101 is operated in a high-speed mode defined in the specification, the memory controller 103 may disable the first enable signal EN_CMOS to a low level and may enable the second enable signal EN_VREF to a high level. The high-speed mode may refer to an operation mode in which the operating frequency of the semiconductor device 101 is selected to be a second value higher than the first value defined in the specification. With the first enable signal EN_CMOS disabled and the second enable signal EN_VREF enabled, the BF2 500 suitable for high-speed operation may be selected and the second data receiving operation may be performed.

[0049] The third enable signal EN_VREFCMOS is a signal that substantially prevents the output level transition of BF1 300 and BF2 500 while data reception is not performed. Since the third enable signal EN_VREFCMOS is disabled only when both the first enable signal EN_CMOS and the second enable signal EN_VREF are disabled, the third enable signal EN_VREFCMOS can be generated by performing a logical OR operation with the first enable signal EN_CMOS and the second enable signal EN_VREF.

[0050] Figure 4 It is shown Figure 3 Diagram of the BF1 300 configuration.

[0051] Reference Figure 4 , Figure 3 The BF1 300 may include a first logic gate 310 , a second logic gate 330 , a level shifter (LS) 350 , a third logic gate 370 , and a fourth logic gate 390 .

[0052] The first logic gate 310 and the second logic gate 330 may operate according to an external voltage VCCQ.

[0053] The external voltage VCCQ may be provided from outside the semiconductor device 101 (eg, from the memory controller 103 ).

[0054] The third logic gate 370 and the fourth logic gate 390 may operate according to the internal voltage VCCI.

[0055] The internal voltage VCCI may be generated using the external voltage VCCQ in the semiconductor device 101 .

[0056] The first logic gate 310 may be configured as a NAND gate, and may invert and output the data DQ when the first enable signal EN_CMOS is at a high level.

[0057] The second logic gate 330 may be configured as an inverter, and may invert and output the output of the first logic gate 310 .

[0058] The LS 350 may convert the level of the output signal of the second logic gate 330 into the level of the internal voltage VCCI and output the signal.

[0059] Each of the third logic gate 370 and the fourth logic gate 390 may be configured as an inverter, and may buffer the output of the LS 350 and output the buffered output as a first buffer signal BF1OUT.

[0060] Figure 5 is a diagram showing a configuration of a receiver circuit according to another embodiment.

[0061] Figure 2 The receiver circuit 200 may be implemented in various ways, and Figure 5 is a diagram showing a configuration of a receiver circuit 200 - 2 according to another embodiment.

[0062] Reference Figure 5 , a receiver circuit 200 - 2 according to another embodiment may include a first buffer circuit ( BF1 ) 900 and a second buffer circuit ( BF2 ) 500 .

[0063] The first buffer circuit BF1 900 uses an internal voltage VCCI as a power supply and can be configured to perform a first data receiving operation of receiving data DQ, outputting data as a first buffer signal BF1OUT, and compensating for a duty cycle skew of the first buffer signal BF1OUT according to an external voltage VCCQ when a first enable signal EN_CMOS is enabled.

[0064] When the third enable signal EN_VREFCMOS is disabled, the first buffer circuit BF1 900 may fix the first buffer signal BF1OUT to a predetermined level, thereby substantially preventing the first buffer signal BF1OUT from transitioning. In an embodiment, the first buffer circuit BF1 900 may fix the first buffer signal BF1OUT to a predetermined level according to the third enable signal EN_VREFCMOS.

[0065] When the second enable signal EN_VREF is enabled, the second buffer circuit BF2 500 may perform a second data receiving operation of receiving data DQ according to the reference voltage VREF and outputting the data DQ as a second buffer signal BF2OUT.

[0066] The second buffer circuit BF2500 may fix the second buffer signal BF2OUT to a predetermined level according to the third enable signal EN_VREFCMOS, thereby substantially preventing the second buffer signal BF2OUT from transitioning.

[0067] Figure 6 It is shown Figure 5 Diagram of the BF1 900 configuration.

[0068] Reference Figure 6 , Figure 5 The BF1 900 may include a first logic gate 910 and a second logic gate 920 .

[0069] The first logic gate 910 and the second logic gate 920 may use the internal voltage VCCI as a power source. In an embodiment, the first logic gate 910 and the second logic gate 920 may be connected to the internal voltage VCCI terminal to receive the internal voltage VCCI as a power source. In an embodiment, the internal voltage VCCI terminal may supply power to the first logic gate 910 and the second logic gate 920.

[0070] The first logic gate 910 and the second logic gate 920 may operate according to the internal voltage VCCI.

[0071] The first logic gate 910 may be configured as a tri-state inverter, and may invert and output the data DQ when the first enable signal EN_CMOS is at a high level. In an embodiment, the first logic gate 910 may be configured as a tri-state inverter, and may invert and output the data DQ when the first enable signal EN_CMOS is at a high level to output a result signal.

[0072] The second logic gate 920 may be configured as a tri-state inverter, and may invert the output of the first logic gate 910 when the first enable signal EN_CMOS is at a high level and output the inverted output as the first buffer signal BF1OUT. In an embodiment, the second logic gate 920 may be configured as a tri-state inverter, and may invert the result signal of the first logic gate 910 to output the result signal as an inverted output when the first enable signal EN_CMOS is at a high level and output the inverted output as the first buffer signal BF1OUT.

[0073] The second logic gate 920 may adjust the amount of sink current according to the level of the external voltage VCCQ and compensate for a duty cycle skew of the first buffer signal BF1OUT generated according to a difference between the internal voltage VCCI and the external voltage VCCQ.

[0074] When the third enable signal EN_VREFCMOS is disabled, the second logic gate 920 may fix the first buffer signal BF1OUT to a predetermined level, thereby substantially preventing the first buffer signal BF1OUT from transitioning.

[0075] Figure 7 It is shown Figure 5 FIG. 9 is a diagram of an example of a circuit configuration of the BF1 900.

[0076] Reference Figure 7 , the first logic gate 910 of BF1 900 may include first to fifth transistors 911 to 915 .

[0077] The first transistor 911 may be connected to a terminal of an internal voltage VCCI through a source thereof and receive data DQ through a gate thereof.

[0078] The second transistor 912 may be connected to the drain of the first transistor 911 through its source, receive the inverted first enable signal ENB_CMOS through its gate, and be connected to the first output node 916 through its drain.

[0079] The inverted first enable signal ENB_CMOS may be generated by inverting the first enable signal EN_CMOS through an inverter, or may be provided from the outside of the semiconductor device 101 .

[0080] The third transistor 913 may be connected to the first output node 916 through its drain and receive the first enable signal EN_CMOS through its gate.

[0081] The fourth transistor 914 may be connected to the source of the third transistor 913 through a drain thereof and receive data DQ through a gate thereof.

[0082] The fifth transistor 915 may be connected to the source of the fourth transistor 914 through a drain thereof, receive the first enable signal EN_CMOS through a gate thereof, and be connected to a ground terminal through a source thereof.

[0083] When the first enable signal EN_CMOS is at a high level, the first logic gate 910 may invert and output the data DQ.

[0084] The second logic gate 920 of the BF1 900 may include first to sixth transistors 921 to 926 .

[0085] The first transistor 921 may be connected to a terminal of the internal voltage VCCI through its source and may be connected to the first output node 916 through its gate.

[0086] The second transistor 922 may be connected to the drain of the first transistor 921 through its source, receive the inverted first enable signal ENB_CMOS through its gate, and be connected to the second output node 927 through its drain.

[0087] The first buffered signal BF1OUT may be output through the second output node 927 .

[0088] The third transistor 923 may be connected to the second output node 927 through its drain and receive the first enable signal EN_CMOS through its gate.

[0089] The fourth transistor 924 may be connected to the source of the third transistor 923 through its drain and receive the external voltage VCCQ through its gate.

[0090] The fourth transistor 924 may compensate for a duty cycle skew of the first buffer signal BF1OUT according to a level of the external voltage VCCQ.

[0091] The fifth transistor 925 may be connected to the source of the fourth transistor 924 via its drain and to the first output node 916 via its gate.

[0092] The sixth transistor 926 may be commonly connected to the gate of the fifth transistor 925 and the first output node 916 through its drain, receive the inverted third enable signal ENB_VREFCMOS through its gate, and may be connected to the ground terminal through its source.

[0093] When the third enable signal EN_VREFCMOS is at a high level, the sixth transistor 926 may fix the first buffer signal BF1OUT to a predetermined level, thereby substantially preventing the first buffer signal BF1OUT from transitioning.

[0094] The inverted third enable signal ENB_VREFCMOS may be generated by inverting the third enable signal EN_VREFCMOS through an inverter, or may be provided from the outside of the semiconductor device 101 .

[0095] When the first enable signal EN_CMOS is at a high level, the second logic gate 920 may invert and output an output signal of the first logic gate 910 and substantially prevent an increase in the duty ratio of the first buffer signal BF1OUT due to a difference between the levels of the external voltage VCCQ and the internal voltage VCCI.

[0096] When the level of the external voltage VCCQ is higher than the level of the internal voltage VCCI, the duty ratio of the first buffer signal BF1OUT may increase beyond a target value.

[0097] Therefore, the external voltage VCCQ is applied to the gate of the fourth transistor 924 of the second logic gate 920 to compensate for the increase in the duty cycle due to the increase in the level of the external voltage VCCQ, and when the level of the external voltage VCCQ is higher than the level of the internal voltage VCCI, the increase in the duty cycle of the first buffer signal BF1OUT can be substantially prevented by increasing the sink current passing through the fourth transistor 924.

[0098] It will be appreciated by those skilled in the art that the present disclosure may be implemented in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive. The scope of the present disclosure is defined by the claims described below, rather than by the detailed description, and should be interpreted as the meaning and scope of the claims and all modifications or modified forms derived from their equivalent concepts are included within the scope of the present disclosure.

[0099] CROSS-REFERENCE TO RELATED APPLICATIONS

[0100] This application claims the benefit of Korean Application No. 10-2020-0059675, filed on May 19, 2020, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Claims

1. A buffer circuit, comprising: a first logic gate connected to the internal voltage terminal and configured to receive data according to a first enable signal and to invert and output the data; as well as a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate to output the inverted output as a first buffer signal according to the first enable signal, and to compensate for a duty cycle skew of the first buffer signal according to a level of an external voltage.

2. The buffer circuit according to claim 1, wherein: The first logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving the data; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node; a third transistor including a drain connected to the output node and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the data; and A fifth transistor includes a drain connected to the source of the fourth transistor, a gate for receiving the first enable signal, and a source connected to a ground terminal.

3. The buffer circuit according to claim 1, wherein: The second logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving an output of the first logic gate; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node for outputting the first buffer signal; a third transistor including a drain connected to the output node for outputting the first buffer signal and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the external voltage, and configured to compensate for a duty cycle skew of the first buffer signal according to the external voltage; and a fifth transistor including a drain connected to the source of the fourth transistor, a gate for receiving the output of the first logic gate, and a source connected to a ground terminal.

4. A receiver circuit, the receiver circuit comprising: a first buffer circuit coupled to the internal voltage terminal and configured to receive data according to a first enable signal and output the data as a first buffer signal, and to compensate for a duty cycle skew of the first buffer signal according to an external voltage; as well as a second buffer circuit configured to receive the data in response to a reference voltage according to a second enable signal and output the data as a second buffer signal, The output terminal of the first buffer circuit and the output terminal of the second buffer circuit are connected to each other.

5. The receiver circuit of claim 4, wherein: The first buffer circuit is configured to fix the first buffer signal to a predetermined level according to a third enable signal.

6. The receiver circuit of claim 4, wherein: The second buffer circuit is configured to fix the second buffer signal to a predetermined level according to a third enable signal.

7. The receiver circuit of claim 4, wherein: The first buffer circuit comprises: a first logic gate coupled to the internal voltage terminal and configured to receive data according to the first enable signal and to invert and output the data; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate according to the first enable signal to output the inverted output as the first buffer signal, and to compensate for a duty cycle skew of the first buffer signal according to a level of the external voltage.

8. The receiver circuit of claim 7, wherein: The first logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving the data; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node; a third transistor including a drain connected to the output node and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the data; and A fifth transistor includes a drain connected to the source of the fourth transistor, a gate for receiving the first enable signal, and a source connected to a ground terminal.

9. The receiver circuit of claim 7, wherein: The second logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving an output of the first logic gate; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node for outputting the first buffer signal; a third transistor including a drain connected to the output node for outputting the first buffer signal and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the external voltage, and configured to compensate for a duty cycle skew of the first buffer signal according to the external voltage; and a fifth transistor including a drain connected to the source of the fourth transistor, a gate for receiving the output of the first logic gate, and a source connected to a ground terminal.

10. A semiconductor device, comprising: a receiver circuit, wherein a first buffer circuit in the receiver circuit is coupled to an internal voltage terminal and configured to generate reception data by performing a first data reception operation of receiving data according to a first enable signal and outputting the data as a first buffer signal and compensating for a duty cycle skew of the first buffer signal according to an external voltage, and a second buffer circuit in the receiver circuit is configured to generate reception data by performing a second data reception operation of receiving the data in response to a reference voltage according to a second enable signal and outputting the data as a second buffer signal, wherein an output terminal of the first buffer circuit and an output terminal of the second buffer circuit are connected to each other; memory regions; and A write path circuit includes a circuit configuration for writing the received data in the memory area.

11. The semiconductor device according to claim 10, wherein: The memory area includes at least one of a volatile memory cell array and a nonvolatile memory cell array.

12. The semiconductor device according to claim 10, wherein: When the semiconductor device is set to operate in a low speed mode, the first data reception operation is performed in response to the semiconductor device receiving a control signal including the second enable signal disabled and the first enable signal enabled.

13. The semiconductor device according to claim 12, wherein: When the semiconductor device is set to operate in a high-speed mode, the second data reception operation is performed in response to the semiconductor device receiving a control signal including the first enable signal disabled and the second enable signal enabled.

14. The semiconductor device according to claim 10, wherein: The first buffer circuit is configured to fix the first buffer signal to a predetermined level according to a third enable signal.

15. The semiconductor device according to claim 10, wherein: The second buffer circuit is configured to fix the second buffer signal to a predetermined level according to a third enable signal.

16. The semiconductor device according to claim 10, wherein: The first buffer circuit comprises: a first logic gate coupled to the internal voltage terminal and configured to receive data according to the first enable signal and to invert and output the data; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and output the inverted output as the first buffer signal according to the first enable signal, and to compensate for a duty cycle skew of the first buffer signal according to a level of the external voltage.

17. The semiconductor device according to claim 16, wherein: The first logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving the data; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node; a third transistor including a drain connected to the output node and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the data; and A fifth transistor includes a drain connected to the source of the fourth transistor, a gate for receiving the first enable signal, and a source connected to a ground terminal.

18. The semiconductor device according to claim 16, wherein: The second logic gate comprises: a first transistor including a source for receiving an internal voltage and a gate for receiving an output of the first logic gate; a second transistor including a source connected to the drain of the first transistor, a gate for receiving the inverted first enable signal, and a drain connected to an output node for outputting the first buffer signal; a third transistor including a drain connected to the output node for outputting the first buffer signal and a gate for receiving the first enable signal; a fourth transistor including a drain connected to the source of the third transistor and a gate for receiving the external voltage, and configured to compensate for a duty cycle skew of the first buffer signal according to the external voltage; and a fifth transistor including a drain connected to the source of the fourth transistor, a gate for receiving the output of the first logic gate, and a source connected to a ground terminal.

Images