Control Circuit, Control System and Method of an Energy Storage Inverter

Abstract

The present invention discloses a control circuit, a control system and a method for an energy storage inverter. The control circuit is used to detect the states of a plurality of controlled switches of a DRED circuit to control the power transmission between the energy storage inverter and the power grid. The control circuit includes: a plurality of output detection units, a first priority decoder, a plurality of input detection units, and a second priority decoder. The control circuit of the energy storage inverter of the present invention can accurately identify the situation where a single switch is closed or multiple controlled switches are closed simultaneously, and distinguish priorities according to this situation, so as to accurately control the bidirectional power transmission between the energy storage inverter and the power grid; the control system of the present invention adopts this control circuit, uses fewer components, and can reduce costs; the control method of the present invention has simple steps, can accurately control the response of the energy storage inverter to DRM devices, so as to control the energy storage inverter to perform corresponding operations, and better meet the requirements of safety specifications.

Description

Technical Field

[0001] The present invention belongs to the field of inverters, and relates to a control circuit, a control system and a control method for a energy storage inverter, in particular to a control circuit, a control system and a control method for an energy storage inverter capable of responding to a DRM device. Background Art

[0002] In 2016, the Australian Grid Corporation released the latest safety standards for photovoltaic grid-connected inverters and photovoltaic energy storage inverters in Australia and New Zealand, "AS NZS 4777.2-2015". And it is required that all photovoltaic inverters sold to Australia and New Zealand after mid-July 2016 must comply with the latest safety standards. In the "AS NZS 4777.2-2015" safety standard, DRMs (Demand Response Modes) are newly added: by using an external control box - DRED (Demand Response Enabling Device), active power scheduling and reactive power scheduling of the power grid can be realized in real time and quickly, and the photovoltaic inverter can also operate stably during the scheduling process. The grid company requires that the DRM device can be remotely controlled and the energy storage inverter can be operated, so as to control the input and output power of the energy storage inverter, or the connection or disconnection with the power grid.

[0003] In the prior art, when the controlled switch of a single DRED is closed, the energy storage inverter can be controlled to perform corresponding operations, but the priorities of all controlled switches are the same. When multiple controlled switches are closed at the same time, the circuit cannot accurately identify the switch states at this time and distinguish priorities, so it is impossible to control the energy storage inverter to preferentially perform corresponding operations; at the same time, there are more electronic components in the circuit, which will increase the cost. Summary of the Invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to provide a control circuit, a control system and a control method for an energy storage inverter, which can accurately identify the states of the controlled switches of the DRED circuit and distinguish priorities according to this situation, so as to accurately control the electrical energy output and input of the energy storage inverter.

[0005] To achieve the above object, a technical solution adopted by the present invention is:

[0006] A control circuit for an energy storage inverter, which is used to detect the states of a plurality of controlled switches of a DRED circuit to control the power transmission between the energy storage inverter and the power grid. The control circuit includes:

[0007] Multiple output detection units, which are used to respectively detect the states of the controlled switches corresponding to the power output of the energy storage inverter;

[0008] A first priority decoder, which has M first input ports and N first output ports, N < M. Each of the first input ports has an N-bit first code corresponding to the output power of the energy storage inverter to the power grid. The output ends of the output detection units are respectively connected to one of the first input ports. When the first input port with a higher priority is at an effective level, the N first output ports output the N-bit first code corresponding to this first input port;

[0009] Multiple input detection units, which are used to respectively detect the states of the controlled switches corresponding to the power input of the energy storage inverter; and

[0010] A second priority decoder, which has P second input ports and Q second output ports, Q < P. Each of the second input ports has a Q-bit second code corresponding to the input power of the power grid to the energy storage inverter. The output ends of the input detection units are respectively connected to one of the second input ports. When the second input port with a higher priority is at an effective level, the Q second output ports output the Q-bit second code corresponding to this second input port.

[0011] Preferably, the multiple output detection units include:

[0012] A first output detection unit, which is used to detect whether the controlled switch S5 of the DRED circuit is closed;

[0013] A second output detection unit, which is used to detect whether both the controlled switches S6 and S7 of the DRED circuit are closed;

[0014] A third output detection unit, which is used to detect whether the controlled switch S6 of the DRED circuit is closed;

[0015] A fourth output detection unit, which is used to detect whether the controlled switch S7 of the DRED circuit is closed; and

[0016] A fifth output detection unit, which is used to detect whether the controlled switch S8 of the DRED circuit is closed;

[0017] Among them, the priorities of the first input ports respectively connected to the output ends of the first output detection unit, the second output detection unit, the third output detection unit, the fourth output detection unit and the fifth output detection unit decrease in turn.

[0018] By setting up the second output detection unit, it is possible to detect the situation where both the controlled switches S6 and S7 are closed, and then set the priority accordingly, so as to distinguish the priorities of the cases where multiple switches of the DRED circuit are closed simultaneously, and thus preferentially execute the corresponding operations to control the output of the energy storage inverter.

[0019] Preferably, the multiple output detection units further include a sixth output detection unit, and the sixth output detection unit includes a comparator U5-A. The non-inverting input terminal of the comparator U5-A is connected to the first reference voltage input terminal, and the inverting input terminal is used to connect to the detection output terminal COM LOAD0 of the DRED circuit through a voltage-dividing resistor R17. The detection output terminal COMLOAD0 is connected to the parallel connection side of the controlled switches S5 to S8 through a controlled switch S9. The output terminal of the comparator U5-A is connected to the first input port with the highest priority of the first priority decoder.

[0020] Preferably, the first priority decoder has first input ports 0 to 7 with gradually increasing priorities. The first input port 0 is used to connect to the detection output terminal REF GEN0 of the DRED circuit through a resistor R20, and the REF GEN0 is connected to the other parallel connection side of the controlled switches S5 to S8; the first input ports 1 to 5 are respectively connected to the output terminals of the fifth output detection unit, the fourth output detection unit, the third output detection unit, the second output detection unit, and the first output detection unit; the first input port 6 is used to connect to the detection output terminal COM LOAD0; the first input port 7 is connected to the output terminal of the sixth output detection unit.

[0021] Preferably, the DRED circuit has a detection output terminal DRM1 / 5 connected to the midpoint between the controlled switches S1 and S5, a detection output terminal DRM2 / 6 connected to the midpoint between the controlled switches S2 and S6, a detection output terminal DRM3 / 7 connected to the midpoint between the controlled switches S3 and S7, and a detection output terminal DRM4 / 8 connected to the midpoint between the controlled switches S4 and S8. The first output detection unit, the third output detection unit, the fourth output detection unit, and the fifth output detection unit respectively include comparators. The non-inverting input terminals of the comparators are used to connect to the corresponding detection output terminals, the inverting input terminals are connected to the first reference voltage terminal, and the output terminals are connected to the corresponding first input ports of the first priority decoder.

[0022] Preferably, the second output detection unit includes a comparator U5-B, a first diode, a second diode, and a resistor R20. The non-inverting input terminal of the comparator U5-B is connected to the negative electrodes of the first diode and the second diode respectively through the resistor R20. The positive electrode of the first diode is connected to the output terminal of the third output detection unit, and the positive electrode of the second diode is connected to the output terminal of the fourth output detection unit. The inverting input terminal of the comparator U5-B is connected to the input terminal of the second reference unit, and the output terminal is connected to the corresponding first input port of the first priority decoder.

[0023] Preferably, the multiple input detection units include:

[0024] A first input detection unit for detecting whether the controlled switch S1 of the DRED circuit is closed;

[0025] A second input detection unit for detecting whether both the controlled switches S2 and S3 of the DRED circuit are closed;

[0026] A third input detection unit for detecting whether the controlled switch S2 of the DRED circuit is closed;

[0027] A fourth input detection unit for detecting whether the controlled switch S3 of the DRED circuit is closed; and

[0028] A fifth input detection unit for detecting whether the controlled switch S4 of the DRED circuit is closed;

[0029] Wherein, the priorities of the second input ports respectively connected to the output terminals of the first input detection unit, the second input detection unit, the third input detection unit, the fourth input detection unit, and the fifth input detection unit decrease in sequence.

[0030] By providing the second input detection unit, the situation where both the controlled switches S2 and S3 are closed can be detected, and the priorities can be set accordingly, so as to distinguish the priorities of the situations where multiple switches of the DRED circuit are closed simultaneously, and thus perform the corresponding operations preferentially to control the input of the energy storage inverter.

[0031] Preferably, the second priority decoder has second input ports 0 to 7 with increasing priorities. The second input port 0 is grounded through a resistor R02; the second input ports 1 to 5 are respectively connected to the output terminals of the fifth input detection unit, the fourth input detection unit, the third input detection unit, the second input detection unit, and the first input detection unit; the second input ports 6 and 7 are respectively connected to the first reference voltage input terminal through resistors R67.

[0032] Preferably, the DRED circuit has a detection output terminal DRM1 / 5 connected to the midpoint of the controlled switches S1 and S5, a detection output terminal DRM2 / 6 connected to the midpoint of the controlled switches S2 and S6, a detection output terminal DRM3 / 7 connected to the midpoint of the controlled switches S3 and S7, and a detection output terminal DRM4 / 8 connected to the midpoint of the controlled switches S4 and S8. The first input detection unit, the third input detection unit, the fourth input detection unit, and the fifth input detection unit each include a comparator. The non-inverting input terminal of each comparator is used to connect to the corresponding detection output terminal, the inverting input terminal is connected to the first reference voltage terminal, and the output terminal is connected to the corresponding second input port of the second priority decoder.

[0033] Preferably, the second input detection unit includes a comparator U5-C, a third diode, a fourth diode, and a resistor R19. The non-inverting input terminal of the comparator U5-C is respectively connected to the cathodes of the third diode and the fourth diode through the resistor R19. The anode of the third diode is connected to the output terminal of the third input detection unit, and the anode of the fourth diode is connected to the output terminal of the fourth input detection unit. The inverting input terminal of the comparator U5-C is connected to the second reference power input terminal, and the output terminal is connected to the corresponding second input port of the second priority decoder.

[0034] Another technical solution adopted by the present invention is:

[0035] A control system of a energy storage inverter includes a control chip. The control system further includes the control circuit as described above. The first output port of the first priority decoder and the second output port of the second priority decoder are respectively connected to the GPIO ports of the control chip. The control chip identifies the states of the controlled switches of the DRED circuit according to the level signals of the first output port and the second output port, and correspondingly controls the output or input power of the inverter circuit of the energy storage inverter.

[0036] Another technical solution adopted by the present invention is:

[0037] A control method of an energy storage inverter adopts the control circuit as described above. The detection method includes the following steps:

[0038] Detect the states of the controlled switches S0 to S9 of the DRED circuit through multiple output detection units and multiple input detection units;

[0039] Each first input port of the first priority decoder respectively receives the level of the output end of the corresponding output detection unit, and outputs the first code corresponding to the first input port with an effective level and a high priority. The control chip identifies the states of the controlled switches S5 to S8 of the DRED circuit according to the first code output by the first priority decoder, and correspondingly controls the output power of the energy storage inverter.

[0040] Each second input port of the second priority decoder respectively receives the level of the output end of the corresponding input detection unit, and outputs the second code corresponding to the second input port with an effective level and a high priority. The control chip identifies the states of the controlled switches S1 to S4 of the DRED circuit according to the second code output by the second priority decoder, and correspondingly controls the input power of the energy storage inverter.

[0041] The present invention adopts the above scheme and has the following advantages compared with the prior art:

[0042] A control circuit, a control system and a control method for an energy storage inverter of the present invention respectively identify the states of a plurality of detected controlled switches of a DRED controller by setting an output detection unit and an input detection unit, and respectively input them into a first priority decoder and a second priority decoder for priority judgment, and output a first code or a second code corresponding to the state of the detected controlled switch. Then, according to the first code or the second code, the output and input of the energy storage inverter are correspondingly controlled, so that the energy storage inverter can accurately control the energy transfer between it and the power grid in response to a DRM device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1a FIG. is a control circuit diagram of an energy storage inverter according to this embodiment;

[0045] Figure 1b is Figure 1a a partial enlarged view of the second output detection unit in;

[0046] Figure 1c is Figure 1a a partial enlarged view of the sixth output detection unit in;

[0047] Figure 1d is Figure 1a a partial enlarged view of the second input detection unit in;

[0048] Figure 2 Circuit diagram of the DRM device;

[0049] Figure 3 Circuit diagram of a control system of an energy storage inverter according to this embodiment;

[0050] Figure 4 Schematic diagram of the output control of an energy storage inverter in this embodiment;

[0051] Figure 5 Schematic diagram of the input control of an energy storage inverter in this embodiment;

[0052] Figure 6 Truth table of the first priority decoder and the second priority decoder.

[0053] Wherein:

[0054] 10. Output detection unit; 20. Input detection unit; 30. DRED circuit; 40. Detection output terminal;

[0055] 11. First output detection unit; 12. Second output detection unit; 13. Third output detection unit; 14. Fourth output detection unit; 15. Fifth output detection unit; 16. Sixth output detection unit;

[0056] 21. First input detection unit; 22. Second input detection unit; 23. Third input detection unit; 24. Fourth input detection unit; 25. Fifth input detection unit. Specific implementation manner

[0057] The following elaborates on the preferred embodiments of the present invention in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0058] As shown in FIG. 1 and Figure 2 shown, a control circuit of an energy storage inverter in this embodiment is used to detect the states of a plurality of controlled switches of the DRED circuit to control the power transmission between the energy storage inverter and the power grid. Here, the power transmission includes the output of the energy storage inverter to the power grid and the input of the power grid to the energy storage inverter. As Figure 3 shown, the DRED circuit is an important part of the DRM device and is controlled by power grid companies, etc. Refer to Figure 2As shown in the figure, the DRED circuit includes ten controlled switches S0 to S9, which have six detection output terminals, namely detection output terminal DRM1 / 5, detection output terminal DRM2 / 6, detection output terminal DRM3 / 7, detection output terminal DRM4 / 8, detection output terminal REF GEN0, and detection output terminal COM LOAD0. Among them, the detection output terminal DRM1 / 5 is connected to the midpoint of the controlled switches S1 and S5 of the DRM control device, the detection output terminal DRM2 / 6 is connected to the midpoint of the controlled switches S2 and S6 of the DRM control device, the detection output terminal DRM3 / 7 is connected to the midpoint of the controlled switches S3 and S7 of the DRM control device, the detection output terminal DRM4 / 8 is connected to the midpoint of the controlled switches S4 and S8 of the DRM control device, and the detection output terminal DRM0 is also connected to the parallel connection of the controlled switches S5, S6, S7, and S8 and grounded; the detection output terminal COM_LOAD0 is connected to the parallel connection of the controlled switches S1, S2, S3, and S4.

[0059] The control circuit includes a plurality of output detection units 10, a plurality of input detection units 20, a first priority decoder U1, and a second priority decoder U2. Among them, the output detection unit 10 is used to detect the states of the controlled switches S5 to S8, and S0 and S9 corresponding to the power output of the energy storage inverter respectively, and output a level signal to the first priority decoder U1; the first priority decoder U1 is used to receive the level signals from each output detection unit 10, and output a code according to the different priority situations of different interfaces to control the output power of the energy storage inverter to the power grid. The input detection unit 20 is used to detect the states of the controlled switches S1 to S4, and S0 and S9 corresponding to the power input of the energy storage inverter respectively, and output a level signal to the second priority decoder U2; the second priority decoder U2 is used to receive the level signals from each input detection unit 20, and output a code according to the different priority situations of different interfaces to control the input power of the power grid to the energy storage inverter.

[0060] As shown in Figure 1, the first priority decoder U1 and the second priority decoder U2 are 38 decoders. The first priority decoder U1 has M first input ports and N first output ports, N < M. Each first input port has an N-bit first code corresponding to the output power of the energy storage inverter to the power grid. The output terminals of each output detection unit 10 are respectively connected to a first input port. When the first input port with a higher priority is at an effective level, the N first output ports output the N-bit first code corresponding to this first input port. Specifically in this embodiment, M = 8, N = 3. The first priority decoder U1 has eight first input ports with increasing priorities in sequence, namely the first input port 0 to 7. This first priority decoder also has three first output ports, namely the first output port S1, S2, and S3.

[0061] The above-mentioned multiple output detection units 10 specifically include: a first output detection unit 11, which is used to detect whether the controlled switch S5 of the DRED circuit is closed; as Figure 1b shown, a second output detection unit 12, which is used to detect whether both the controlled switches S6 and S7 of the DRED circuit are closed; a third output detection unit 13, which is used to detect whether the controlled switch S6 of the DRED circuit is closed; a fourth output detection unit 14, which is used to detect whether the controlled switch S7 of the DRED circuit is closed; a fifth output detection unit 15, which is used to detect whether the controlled switch S8 of the DRED circuit is closed; as Figure 1c shown, and a sixth output detection unit 16. The first input port 7 of the first priority decoder U1 is connected to the output terminal COM LOAD2 of the sixth output detection unit 16, the first input port 6 is connected to the detection output terminal COM_LOAD0 of the DRM device, the first input port 5 is connected to the output terminal DRM5 of the first output detection unit 11, the first input port 4 is connected to the output terminal DRM6 / 7 of the second output detection unit 12, the first input port 3 is connected to the output terminal DRM6 of the third output detection unit 13, the first input port 2 is connected to the output terminal DRM7 of the fourth output detection unit 14, the first input port 1 is connected to the output terminal DRM8 of the fifth output detection unit 15, and the first input port 0 is connected to the detection output terminal DRM0 of the DRM device. Among them, the first input port 7 has the highest priority, and the priority decreases in the order from 7 to 0.

[0062] The first output detection unit 11 includes a comparator U3-A. The non-inverting input terminal of the comparator U3-A is connected to the detection output terminal DRM1 / 5 of the DRED circuit. Specifically, the detection output terminal DRM1 / 5 is connected to the second reference voltage input terminal through a pull-up resistor R01, and a second reference voltage of 3.3V is accessed. As Figure 2 shown, the detection output terminal DRM1 / 5 is connected to the midpoint between the controlled switches S1 and S5. The inverting input terminal of the comparator U3-A is connected to the midpoint between a resistor R1 and a resistor R2. The other end of the resistor R1 is connected to the first reference voltage input terminal, and the other end of the resistor R2 is grounded. The output terminal DRM5 of the comparator U3-A is connected to the first input port 5 of the first priority decoder U1 through a resistor R24, and the output terminal DRM5 is also connected to the first reference voltage input terminal through a pull-up resistor R25. In this embodiment, the first reference voltage input terminals are all used to access a reference voltage of 5V, which will not be elaborated below.

[0063] The second output detection unit 12 includes a comparator U5-B, a first diode D1, a second diode D2, and a resistor R18. The non-inverting input terminal of the comparator U5-B is connected to the negative electrodes of the first diode D1 and the second diode D2 connected in parallel through the resistor R18. The positive electrode of the first diode D1 is connected to the output terminal of the third output detection unit 13, and the positive electrode of the second diode D2 is connected to the output terminal of the fourth output detection unit. The inverting input terminal of the comparator U5-B is connected to the second reference voltage input terminal, and the output terminal DRM6 / 7 is connected to the corresponding first input port 4 of the first priority decoder U1. The output terminal DRM6 / 7 is also connected to the first reference voltage terminal through a pull-up resistor R26. In this embodiment, the second reference voltage input terminals are all used to access a reference voltage of 3.3V, which will not be elaborated below.

[0064] The third output detection unit 13 includes a comparator U3-B. The non-inverting input terminal of the comparator U3-B is connected to the detection output terminal DRM2 / 6 of the DRED circuit. Specifically, the detection output terminal DRM2 / 6 is connected to the second reference voltage input terminal through a pull-up resistor R01 to access a second reference voltage of 3.3V. As Figure 2 shown, the detection output terminal DRM2 / 6 is connected to the midpoint between the controlled switches S2 and S6. The inverting input terminal of the comparator U3-B is connected to the midpoint between a resistor R3 and a resistor R4. The other end of the resistor R3 is connected to the first reference voltage input terminal, and the other end of the resistor R4 is grounded. The output terminal DRM6 of the comparator U3-B is connected to the first input port 3 of the first priority decoder U1 through a resistor R27, and the output terminal DRM6 is also connected to the first reference voltage input terminal through a pull-up resistor R28. The output terminal of the comparator U3-B is also connected to the positive electrode of the first diode D1 of the second output detection unit 12.

[0065] The fourth output detection unit 14 includes a comparator U3-C. The non-inverting input terminal of the comparator U3-C is connected to the detection output terminal DRM3 / 7 of the DRED circuit. Specifically, the detection output terminal DRM3 / 7 is connected to the second reference voltage input terminal through a pull-up resistor R01 to access a second reference voltage of 3.3V. As Figure 2 shown, the detection output terminal DRM3 / 7 is connected to the midpoint between the controlled switches S3 and S7. The inverting input terminal of the comparator U3-C is connected to the midpoint between a resistor R5 and a resistor R6. The other end of the resistor R5 is connected to the first reference voltage input terminal, and the other end of the resistor R6 is grounded. The output terminal DRM7 of the comparator U3-C is connected to the first input port 2 of the first priority decoder U1 through a resistor R29, and the output terminal DRM7 is also connected to the first reference voltage input terminal through a pull-up resistor R30. The output terminal DRM7 is also connected to the positive electrode of the second diode D2 of the second output detection unit 12.

[0066] The fifth output detection unit 15 includes a comparator U3-D. The non-inverting input terminal of the comparator U3-D is connected to the detection output terminal DRM4 / 8 of the DRED circuit. Specifically, the detection output terminal DRM4 / 8 is connected to the second reference voltage input terminal through a pull-up resistor R01, and a second reference voltage of 3.3V is applied. As Figure 2 shown, the detection output terminal DRM4 / 8 is connected to the midpoint between the controlled switches S4 and S8. The inverting input terminal of the comparator U3-D is connected to the midpoint between a resistor R7 and a resistor R8. The other end of the resistor R7 is connected to the first reference voltage input terminal, and the other end of the resistor R8 is grounded. The output terminal DRM8 of the comparator U3-D is connected to the first input port 1 of the first priority decoder U1 through a resistor R31, and the output terminal DRM8 is also connected to the first reference voltage input terminal through a pull-up resistor R32.

[0067] The detection output terminal DRM0 is connected to the detection output terminal REF GEN0 through a resistor R00, and the detection output terminal DRM0 is connected to the first input port 0 of the first priority decoder U1.

[0068] The sixth output detection unit 16 includes a comparator U5-A. The non-inverting input terminal of the comparator U5-A is connected to the midpoint between a resistor R21 and a resistor R22. The other end of the resistor R21 is connected to the first reference voltage input terminal, and the other end of the resistor R22 is grounded. The inverting input terminal of the comparator U5-A is used to connect to the detection output terminal COMLOAD0 of the DRED circuit through a voltage-dividing resistor R17. As Figure 2 shown, the detection output terminal COM LOAD0 is connected to the parallel connection side of the controlled switches S5 to S8 through a controlled switch S9, and the detection output terminal COM LOAD0 is also connected to the first reference voltage input terminal through a pull-up resistor R02. The output terminal COM LOAD2 of the comparator U5-A is connected to the first input port 7 with the highest priority of the first priority decoder U1, and the output terminal COM LOAD2 of the comparator U5-A is also connected to the first reference voltage input terminal through a pull-up resistor R33. One end of a resistor R23 is grounded, and the other end is connected to the midpoint between the comparator U5-A and the resistor R17.

[0069] As shown in FIG. 1, the second priority decoder U2 has P second input ports and Q second output ports, where Q < P. Each second input port has a Q-bit second code corresponding to the input power of the power grid to the energy storage inverter. The output terminals of each input detection unit 20 are respectively connected to a second input port. When the second input port with a higher priority is at an effective level, the Q second output ports output the Q-bit second code corresponding to this second input port. Specifically, in this embodiment, P = 8 and Q = 3. The second priority decoder U2 has eight second input ports 0 to 7 with increasing priorities; the second priority decoder U2 also has three second output ports, namely second output ports S1, S2, and S3.

[0070] The above-mentioned multiple input detection units 20 specifically include a first input detection unit 21, which is used to detect whether the controlled switch S1 of the DRED circuit is closed; a second input detection unit 22, which is used to detect whether both the controlled switches S2 and S3 of the DRED circuit are closed; a third input detection unit 23, which is used to detect whether the controlled switch S2 of the DRED circuit is closed; a fourth input detection unit 24, which is used to detect whether the controlled switch S3 of the DRED circuit is closed; and a fifth input detection unit 25, which is used to detect whether the controlled switch S4 of the DRED circuit is closed. The second input port 7 of the second priority decoder U2 is connected to the first reference voltage input terminal through a resistor R67, and a reference voltage of 5V is connected; the second input port 6 is connected to the first reference voltage input terminal through another resistor R67, and a reference voltage of 5V is connected; the second input port 5 is connected to the output terminal of the first input detection unit 21, the second input port 4 is connected to the output terminal of the second input detection unit 22, the second input port 3 is connected to the output terminal of the third input detection unit 23, the second input port 2 is connected to the output terminal of the fourth input detection unit 24, the second input port 1 is connected to the output terminal of the fifth input detection unit 25, and the second input port 0 is grounded through a resistor R0. Among them, the second input port 7 has the highest priority, and the priorities decrease in the order of 7 to 0.

[0071] The first input detection unit 21 includes a comparator U4-A. The inverting input terminal of the comparator U4-A is connected to the detection output terminal DRM1 / 5 of the DRED circuit. Specifically, this detection output terminal DRM1 / 5 is connected to the second reference voltage input terminal through a pull-up resistor R01, and a second reference voltage of 3.3V is connected. As Figure 2As shown, the detection output terminal DRM1 / 5 is connected to the midpoint between the controlled switches S1 and S5. The non-inverting input terminal of comparator U4-A is connected to the midpoint between resistor R9 and resistor R10. The other end of resistor R9 is connected to the first reference voltage input terminal, and the other end of resistor R10 is grounded. The output terminal DRM1 of comparator U4-A is connected to the second input port 5 of the second priority decoder U2 through resistor R34. The output terminal DRM1 is also connected to the first reference voltage input terminal through the pull-up resistor R35.

[0072] The second input detection unit 22 includes comparator U5-C, third diode D3, fourth diode D4, and resistor R19. As Figure 1d shown, the non-inverting input terminal of comparator U5-C is connected to the negative electrodes of the third diode D3 and the fourth diode D4 through resistor R19 (i.e., the parallel connection end connected to the negative electrodes of the third diode D3 and the fourth diode D4 through resistor R19). The positive electrode of the third diode D3 is connected to the output terminal of the third input detection unit 23, and the positive electrode of the fourth diode D4 is connected to the output terminal of the fourth input detection unit. The inverting input terminal of comparator U5-C is connected to the midpoint between resistor R11 and resistor R12. The other end of resistor R11 is connected to the first reference voltage input terminal, and the other end of resistor R12 is grounded. The output terminal DRM2 / 3 of comparator U5-C is connected to the second input port 4 of the second priority decoder U2. The output terminal DRM2 / 3 is also connected to the first reference voltage input terminal through the pull-up resistor R36.

[0073] The third input detection unit 23 includes comparator U4-B. The inverting input terminal of comparator U4-B is connected to the detection output terminal DRM2 / 6 of the DRED circuit. Specifically, the detection output terminal DRM2 / 6 is connected to the second reference voltage input terminal through the pull-up resistor R01 to access the second reference voltage of 3.3V. As Figure 2 shown, the detection output terminal DRM2 / 6 is connected to the midpoint between the controlled switches S2 and S6. The non-inverting input terminal of comparator U4-B is connected to the midpoint between resistor R11 and resistor R12. The other end of resistor R11 is connected to the first reference voltage input terminal, and the other end of resistor R12 is grounded. The output terminal DRM2 of comparator U4-B is connected to the second input port 3 of the second priority decoder U2 through resistor R37. The output terminal DRM2 of comparator U4-B is also connected to the first reference voltage input terminal through the pull-up resistor R38. The output terminal DRM2 of comparator U4-B is also connected to the positive electrode of the third diode D3 of the second input detection unit 22.

[0074] The fourth input detection unit 24 includes a comparator U4-C. The inverting input terminal of the comparator U4-C is connected to the detection output terminal DRM3 / 7 of the DRED circuit. Specifically, the detection output terminal DRM3 / 7 is connected to the second reference voltage input terminal through a pull-up resistor R01, and a second reference voltage of 3.3V is accessed. As Figure 2 shown, the detection output terminal DRM3 / 7 is connected to the midpoint between the controlled switches S3 and S7. The non-inverting input terminal of the comparator U4-C is connected to the midpoint between a resistor R13 and a resistor R14. The other end of the resistor R13 is connected to the first reference voltage input terminal, and the other end of the resistor R14 is grounded. The output terminal DRM3 of the comparator U4-C is connected to the first input port 2 of the second priority decoder U2 through a resistor R39. The output terminal DRM3 is also connected to the first reference voltage input terminal through a pull-up resistor R40. The output terminal DRM3 of the comparator U4-C is also connected to the anode of the fourth diode D4 of the second input detection unit 22.

[0075] The fifth input detection unit 25 includes a comparator U4-D. The inverting input terminal of the comparator U4-D is connected to the detection output terminal DRM4 / 8 of the DRED circuit. Specifically, the detection output terminal DRM4 / 8 is connected to the second reference voltage input terminal through a pull-up resistor R01, and a second reference voltage of 3.3V is accessed. As Figure 2 shown, the detection output terminal DRM4 / 8 is connected to the midpoint between the controlled switches S4 and S8. The non-inverting input terminal of the comparator U4-D is connected to the midpoint between a resistor R15 and a resistor R16. The other end of the resistor R15 is connected to the first reference voltage input terminal, and the other end of the resistor R16 is grounded. The output terminal DRM4 of the comparator U4-D is connected to the first input port 1 of the second priority decoder U2 through a resistor R41. The output terminal DRM4 is also connected to the first reference voltage input terminal through a pull-up resistor R42.

[0076] The present invention also provides a control system for an energy storage inverter, as Figure 3 shown, including a DSP control chip and the control circuit as described above. The control circuit is connected to the controlled switches in the DRED circuit through each detection output terminal. The first output port of the first priority decoder U1 and the second output port of the second priority decoder U2 are respectively connected to the GPIO ports of the DSP control chip. The DSP control chip identifies the states of the controlled switches in the DRED circuit according to the level signals of the first output port and the second output port, and correspondingly controls the output or input power of the inverter circuit of the energy storage inverter. Specifically, the first priority decoder U1 identifies the states of the controlled switches S5 to S8 in the DRED circuit according to the control circuit, and outputs the corresponding first coding situation through the first output port, and the corresponding operations for controlling the energy storage inverter such as Figure 4As shown, it can be seen that the control system can not only control the active and reactive power output by the energy storage inverter, but also control the disconnection of the energy storage inverter from the power grid. At the same time, it can also detect whether the energy storage inverter is normally connected to the DRM and issue an alarm signal as appropriate; the second priority decoder U2 identifies the states of the controlled switches S1 to S4 of the DRED circuit according to the control circuit, outputs the corresponding second encoding through the second output port, and the corresponding operations for controlling the energy storage inverter, such as Figure 5 As shown. It can be seen that the control system can control the active and reactive power input from the power grid to the energy storage inverter.

[0077] The present invention also provides a control method for an energy storage inverter, as Figure 4 and Figure 5 shown, adopting the control circuit and control system as described above. The control method includes a control method for the output power of the energy storage inverter and a control method for the input power of the energy storage inverter. Among them, as Figure 4 shown, the steps of the control method for the output power of the energy storage inverter are as follows:

[0078] Detect the midpoint of the connection between the controlled switches S1 and S5 at the output end DRM1 / 5, detect the midpoint of the connection between the controlled switches S2 and S6 at the output end DRM2 / 6, detect the midpoint of the connection between the controlled switches S3 and S7 at the output end DRM3 / 7, detect the midpoint of the connection between the controlled switches S4 and S8 at the output end DRM4 / 8, detect the other parallel end of the controlled switches S5 to S8 at the output end REF GEN0, and connect it to DRM0 and ground; detect the parallel end of one side of the controlled switches S1 to S4 at the output end COM_LOAD0 and pull it up to +5V voltage through a resistor;

[0079] The detection output terminal COM_LOAD0 is connected to the inverting input terminal of comparator U5-A through a voltage-dividing resistor R17, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the non-inverting input terminal to determine whether S9 is disconnected. The output terminal of comparator U5-A is connected to the first input port 7 with the highest priority of the first priority decoder U1, and COM_LOAD2 is output to the first priority decoder U1; the detection output terminal DRM1 / 5 is connected to the non-inverting input terminal of comparator U3-A, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the inverting input terminal to determine whether S5 is closed. The output terminal of comparator U3-A is connected to the first input port 5 of the first priority decoder U1, and DRM5 is output to the first priority decoder U1; the non-inverting input terminal of comparator U5-B is connected to the cathodes of the first diode D1 and the second diode D2 through a resistor R18 respectively. The anode of the first diode D1 is connected to the output terminal of comparator U3-B, and the anode of the second diode D2 is connected to the output terminal of U3-C. The input voltage of the non-inverting input terminal is compared with the second reference voltage input by the second reference voltage input terminal connected to the inverting input terminal to determine whether S6 and S7 are closed simultaneously. The output terminal of comparator U5-B is connected to the first input port 4 of the first priority decoder U1, and DRM6 / 7 is output to the first priority decoder U1; the detection output terminal DRM2 / 6 is simultaneously connected to the non-inverting input terminal of comparator U3-B, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the inverting input terminal to determine whether S6 is closed. The output terminal of comparator U3-B is connected to the first input port 3 of the first priority decoder U1, and DRM6 is output to the first priority decoder U1; the detection output terminal DRM3 / 7 is connected to the non-inverting input terminal of comparator U3-C, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the inverting input terminal to determine whether S7 is closed. The output terminal of comparator U3-C is connected to the first input port 2 of the first priority decoder U1, and DRM7 is output to the first priority decoder U1; the detection output terminal DRM4 / 8 is connected to the non-inverting input terminal of comparator U3-D, and is compared with the first reference voltage connected to the first reference voltage input terminal connected to the inverting input terminal to determine whether S8 is closed. The output terminal of comparator U3-D is connected to the first input port 1 of the first priority decoder U1, and DRM8 is output to the first priority decoder U1;

[0080] The first output ports S1, S2, and S3 of the first priority decoder U1 are connected to the GPIO ports of the DSP control chip DSP. The DSP control chip identifies the states of the controlled switches S5 to S8 of the DRED circuit according to the level signals output by the first output ports, and correspondingly controls the output power of the inverter circuit of the energy storage inverter, so that the energy storage inverter accurately responds to the control of the DRM device;

[0081] When S5 is closed, the output voltage of the detection output terminal DRM1 / 5 is 0V, which is less than the first reference voltage of the non-inverting input terminal. The comparator U3-A outputs a low level to the first input port 5. The first input port 5 inputs a low-level signal, and the rest of the first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is L, H, L. At this time, the output power of the energy storage inverter is controlled to be 0 by this control method;

[0082] When S6 is closed, the output voltage of the detection output terminal DRM2 / 6 is 0V, which is less than the first reference voltage of the non-inverting input terminal. The comparator U3-B outputs a low level to the first input port 3. The first input port 3 inputs a low-level signal, and the rest of the first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is L, L, H. At this time, the active power output by the energy storage inverter is controlled to be less than 50% by this control method;

[0083] When S7 is closed, the output voltage of the detection output terminal DRM3 / 7 is 0V, which is less than the first reference voltage of the non-inverting input terminal. The comparator U3-C outputs a low level to the first input port 2. The first input port 2 inputs a low-level signal, and the rest of the first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is H, L, H. At this time, the active power output by the energy storage inverter is controlled to be less than 75% and the reactive power is less than 60% by this control method;

[0084] When S8 is closed, the output voltage of the detection output terminal DRM4 / 8 is 0V, which is less than the first reference voltage of the non-inverting input terminal. The comparator U3-D outputs a low level to the first input port 1. The first input port 1 inputs a low-level signal, and the rest of the first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is L, H, H. At this time, the output power of the energy storage inverter is not limited by this control method;

[0085] When S9 is disconnected, the output of the detection output terminal COM LOAD0 is high level, which is greater than the first reference voltage of the inverting input terminal. The comparator U5-A outputs a low level to the first input port 1. The first input port 1 inputs a low-level signal, and the rest of the first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is L, L, L. At this time, the energy storage inverter issues an alarm signal that DRM is not connected;

[0086] When S6 and S7 are closed, the output voltages of the detection output terminals DRM2 / 6 and DRM3 / 7 are 0V, which is less than the second reference voltage of the non-inverting input terminal. The comparators U3-B and U3-C output low levels to the inverting input terminal of the comparator U5-B, which is less than the second reference voltage of the non-inverting input terminal. The comparator U5-B outputs a low level to the first input port 4, the comparator U3-B outputs a low level to the first input port 3, and the comparator U3-C outputs a low level to the first input port 2. The first input ports 4 to 2 input low-level signals, and the remaining first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is H, H, L. At this time, the active power output by the energy storage inverter is controlled to be less than 50% and the reactive power is less than 60% through this control method;

[0087] When S0 is closed, the detection output terminal COM_LOAD0 outputs a low level to the first input port 6. The first input port 6 inputs a low-level signal, and the remaining first input ports input high-level signals. The three-bit first encoding output by the first output ports S1, S2, and S3 is H, L, L. At this time, the energy storage inverter is controlled to disconnect from the power grid through this control method.

[0088] As Figure 5 shown, the control method steps for the input power of the energy storage inverter are as follows:

[0089] The detection output terminal DRM1 / 5 is connected to the midpoint between the controlled switches S1 and S5, the detection output terminal DRM2 / 6 is connected to the midpoint between the controlled switches S2 and S6, the detection output terminal DRM3 / 7 is connected to the midpoint between the controlled switches S3 and S7, and the detection output terminal DRM4 / 8 is connected to the midpoint between the controlled switches S4 and S8;

[0090] The detection output terminal DRM1 / 5 is connected to the inverting input terminal of comparator U4-A, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the non-inverting input terminal to determine whether S1 is closed. The output terminal of comparator U4-A is connected to the second input port 5 of the second priority decoder U2, and DRM1 is output to the second priority decoder U2; the non-inverting input terminal of comparator U5-C is connected to the cathodes of the third diode D3 and the fourth diode D4 through the resistor R19 respectively. The anode of the third diode D3 is connected to the output terminal of comparator U4-B, and the anode of the fourth diode D4 is connected to the output terminal of U4-C. The input voltage of the non-inverting input terminal is compared with the second reference voltage input by the second reference voltage input terminal connected to the inverting input terminal to determine whether S2 and S3 are closed simultaneously. The output terminal of comparator U5-C is connected to the second input port 4 of the second priority decoder U2, and DRM2 / 3 is output to the first priority decoder U1; the detection output terminal DRM2 / 6 is simultaneously connected to the inverting input terminal of comparator U4-B, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the non-inverting input terminal to determine whether S2 is closed. The output terminal of comparator U4-B is connected to the second input port 3 of the second priority decoder U2, and DRM2 is output to the second priority decoder U2; the detection output terminal DRM3 / 7 is connected to the inverting input terminal of comparator U4-C, and is compared with the first reference voltage input by the first reference voltage input terminal connected to the non-inverting input terminal to determine whether S3 is closed. The output terminal of comparator U4-C is connected to the second input port 2 of the second priority decoder U2, and DRM3 is output to the first priority decoder U1; the detection output terminal DRM4 / 8 is connected to the inverting input terminal of comparator U4-D, and is compared with the first reference voltage connected to the first reference voltage input terminal connected to the non-inverting input terminal to determine whether S4 is closed. The output terminal of comparator U4-D is connected to the second input port 1 of the second priority decoder U2, and DRM4 is output to the second priority decoder U2;

[0091] The second output ports of the second priority decoder U2 are respectively connected to the GPIO ports of the DSP control chip. The DSP control chip identifies the states of the controlled switches S1 to S4 of the DRED circuit according to the level signals of the second output ports, and correspondingly controls the input power of the inverter circuit of the energy storage inverter, so that the energy storage inverter accurately responds to the control of the DRM device;

[0092] When S1 is closed, the detection output terminal DRM1 / 5 outputs a voltage of 3.8V, which is greater than the first reference voltage of the non-inverting input terminal. The comparator U4-A outputs a low level to the second input port 5. The second input port 5 inputs a low level signal, and the other second input ports input high level signals. The three-bit second code output by the second output ports S1, S2, and S3 is L, H, L. At this time, the input power of the energy storage inverter is controlled to be 0 through this control method;

[0093] When S2 is closed, the output voltage of the detection output terminal DRM2 / 6 is 3.8V, which is greater than the first reference voltage of the non-inverting input terminal. The comparator U4-B outputs a low level to the second input port 3. The second input port 3 inputs a low-level signal, and the remaining second input ports input high-level signals. The three-bit second encoding output by the second output ports S1, S2, and S3 is L, L, H. At this time, the active power input to the energy storage inverter is controlled to be less than 50% through this control method;

[0094] When S3 is closed, the output voltage of the detection output terminal DRM3 / 7 is 3.8V, which is greater than the first reference voltage of the non-inverting input terminal. The comparator U4-C outputs a low level to the second input port 2. The second input port 2 inputs a low-level signal, and the remaining second input ports input high-level signals. The three-bit second encoding output by the second output ports S1, S2, and S3 is H, L, H. At this time, the active power input to the energy storage inverter is controlled to be less than 75% and the reactive power is less than 60% through this control method;

[0095] When S4 is closed, the output voltage of the detection output terminal DRM4 / 8 is 3.8V, which is greater than the first reference voltage of the non-inverting input terminal. The comparator U4-D outputs a low level to the second input port 1. The second input port 1 inputs a low-level signal, and the remaining second input ports input high-level signals. The three-bit second encoding output by the second output ports S1, S2, and S3 is L, H, H. At this time, the power output by the energy storage inverter is not limited through this control method;

[0096] When S2 and S3 are closed, the output voltages of the detection output terminal DRM2 / 6 and the detection output terminal DRM3 / 7 are 3.5V, which is greater than the second reference voltage of the non-inverting input terminal. The comparators U4-B and U4-C output low levels to the non-inverting input terminal of the comparator U5-C. It is less than the second reference voltage of the inverting input terminal. The comparator U5-C outputs a low level to the second input port 4. The comparator U4-B outputs a low level to the second input port 3. The comparator U4-C outputs a low level to the second input port 2. The second input ports 4 to 2 input low-level signals, and the remaining second input ports input high-level signals. The three-bit second encoding output by the second output ports S1, S2, and S3 is H, H, L. At this time, the active power output by the energy storage inverter is controlled to be less than 50% and the reactive power is less than 60% through this control method.

[0097] Such as Figure 6As shown, it can be seen that the priorities of the first input ports 0 to 7 and the second input ports 0 to 7 increase successively. Specifically, taking the first priority decoder U1 as an example, when the input of its first input port 7 is at a low level, regardless of whether the first input ports 0 to 6 are connected to a level signal or regardless of the level of the level signal, the three-bit first output codes of the first output port are all L, L, L. Therefore, the first priority decoder U1 executes the corresponding operations for controlling the output power of the energy storage inverter by identifying the states of the controlled switches of the DRED circuit corresponding to the level signals of the first input ports 0 to 7, and the priorities increase successively. Specifically, the first input interface 4 is connected to a comparator U5-B for detecting whether the controlled switches S6 and S7 are closed simultaneously. The first input interface 3 and the first input interface 2 are respectively connected to a comparator U3-B and a comparator U3-C for detecting whether the controlled switches S6 and S7 are closed separately. When it is detected that the controlled switches S6 and S7 are closed simultaneously, the comparator U5-B outputs a low-level signal to the first input interface 4, and the first priority decoder U1 preferentially executes the corresponding operations in this state. That is, the priority of the operations corresponding to the case where the controlled switches S6 and S7 are closed simultaneously is higher than the operations corresponding to the case where any single one of the controlled switches S6 and S7 is closed. The same situation can also be analogized to the second priority decoder U2, which can illustrate that the priority of the operations corresponding to the case where the controlled switches S2 and S3 are closed simultaneously is higher than the operations corresponding to the case where any single one of the controlled switches S2 and S3 is closed, and this will not be elaborated here. It is easy to understand that the case where the controlled switches S6 and S7 in the first priority decoder U1 are closed simultaneously and the case where the controlled switches S2 and S3 in the second priority decoder U2 are closed simultaneously are an optimal example, and this example of priority determination can also be applied to other controlled switches in any number (at least two) in practical applications.

[0098] From Figure 4 and Figure 5 it can be seen that the first priority decoder U1 and the second priority decoder U2 are respectively used to control the electrical energy input and output of the energy storage inverter, so as to achieve the purpose of non-interference and can independently complete their respective functions.

[0099] The control circuit of the energy storage inverter in this embodiment includes multiple output detection units for detecting the states of controlled switches, a first priority decoder U1 with eight first input ports and three first output ports for outputting three-bit first codes to control the output of the energy storage inverter to the power grid, and a second priority decoder U2 with eight first ports and three second output ports for outputting three-bit second codes to control the input of the power grid to the energy storage inverter. When multiple controlled switches are closed simultaneously, their priority is higher than that of any one switch closed alone. The comparator in the output detection unit can accurately identify this state and output a level signal to the first priority decoder U1 and the second priority decoder U2. After performing priority judgment, a first code or a second code corresponding to the detected state of the controlled switch is output, and then the output and input of the energy storage inverter are controlled correspondingly, that is, the power output of the energy storage inverter to the power grid, the power input of the power grid to the energy storage inverter, and the connection between the power grid and the energy storage inverter; the control circuit can also perform active and reactive power scheduling on the input and output of the energy storage inverter respectively through the first code output by the first priority decoder and the second code output by the second priority decoder; the control system of the present invention adopts this control circuit, uses fewer components, and can reduce costs; the control method of the present invention has simple steps, can accurately control the response of the energy storage inverter to DRM devices, thereby controlling the energy storage inverter to perform corresponding operations, and can better meet the requirements of safety specifications.

[0100] The above embodiments are only used to illustrate the technical concept and characteristics of the present invention, and are a preferred embodiment. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. Any equivalent transformation or modification made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A control circuit of an energy storage inverter, which is used to detect the states of a plurality of controlled switches of a DRED circuit to control the power transmission between the energy storage inverter and the power grid, and is characterized in that, The control circuit includes: a plurality of output detection units, which are used to respectively detect the states of controlled switches corresponding to the power output of the energy storage inverter; a first priority decoder, which has M first input ports and N first output ports, N < M, each of the first input ports has an N-bit first code corresponding to the output power of the energy storage inverter to the power grid, the output ends of the output detection units are respectively connected to one of the first input ports, when the first input port with a higher priority is at an effective level, the N first output ports output the N-bit first code corresponding to this first input port; a plurality of input detection units, which are used to respectively detect the states of controlled switches corresponding to the power input of the energy storage inverter; and a second priority decoder, which has P second input ports and Q second output ports, Q < P, each of the second input ports has a Q-bit second code corresponding to the input power of the power grid to the energy storage inverter, the output ends of the input detection units are respectively connected to one of the second input ports, when the second input port with a higher priority is at an effective level, the Q second output ports output the Q-bit second code corresponding to this second input port.

2. The control circuit according to claim 1, wherein The plurality of output detection units include: a first output detection unit, which is used to detect whether the controlled switch S5 of the DRED circuit is closed; a second output detection unit, which is used to detect whether both the controlled switches S6 and S7 of the DRED circuit are closed; a third output detection unit, which is used to detect whether the controlled switch S6 of the DRED circuit is closed; a fourth output detection unit, which is used to detect whether the controlled switch S7 of the DRED circuit is closed; and a fifth output detection unit, which is used to detect whether the controlled switch S8 of the DRED circuit is closed; wherein, the priorities of the first input ports respectively connected to the output ends of the first output detection unit, the second output detection unit, the third output detection unit, the fourth output detection unit and the fifth output detection unit decrease in sequence.

3. The control circuit according to claim 2, characterized in that, The plurality of output detection units further include a sixth output detection unit, the sixth output detection unit includes a comparator U5-A, the in-phase input end of the comparator U5-A is connected to a first reference voltage input end, the anti-phase input end is used to connect to the detection output end COM LOAD0 of the DRED circuit through a voltage-dividing resistor R17, the detection output end COM LOAD0 is connected to a parallel end on one side of the controlled switches S5 to S8 through a controlled switch S9, and the output end of the comparator U5-A is connected to the first input port with the highest priority of the first priority decoder.

4. The control circuit according to claim 3, wherein, The first priority decoder has first input ports 0 to 7 with increasing priorities. The first input port 0 is used to connect to the detection output terminal REF GEN0 of the DRED circuit through a resistor R20. This REF GEN0 is connected to the other parallel ends of the controlled switches S5 to S8. The first input ports 1 to 5 are respectively connected to the output terminals of the fifth output detection unit, the fourth output detection unit, the third output detection unit, the second output detection unit, and the first output detection unit. The first input port is used to connect to the detection output terminal COM LOAD0. The first input port is connected to the output terminal of the sixth output detection unit.

5. The control circuit according to claim 2, characterized in that The DRED circuit has a detection output terminal DRM1 / 5 connected to the midpoint between the controlled switches S1 and S5, a detection output terminal DRM2 / 6 connected to the midpoint between the controlled switches S2 and S6, a detection output terminal DRM3 / 7 connected to the midpoint between the controlled switches S3 and S7, and a detection output terminal DRM4 / 8 connected to the midpoint between the controlled switches S4 and S8. The first output detection unit, the third output detection unit, the fourth output detection unit, and the fifth output detection unit each include a comparator. The non-inverting input terminal of each comparator is used to connect to the corresponding detection output terminal, the inverting input terminal is connected to the first reference voltage terminal, and the output terminal is connected to the corresponding first input port of the first priority decoder; and / or, the second output detection unit includes a comparator U5-B, a first diode D1, a second diode D2, and a resistor R18. The non-inverting input terminal of the comparator U5-B is respectively connected to the negative electrodes of the first diode D1 and the second diode D2 through the resistor R18. The positive electrode of the first diode D1 is connected to the output terminal of the third output detection unit. The positive electrode of the second diode D2 is connected to the output terminal of the fourth output detection unit. The inverting input terminal of the comparator U5-B is connected to the second reference power input terminal, and the output terminal is connected to the corresponding first input port of the first priority decoder.

6. The control circuit according to claim 1, wherein The multiple input detection units include: The first input detection unit is used to detect whether the controlled switch S1 of the DRED circuit is closed. The second input detection unit is used to detect whether both the controlled switches S2 and S3 of the DRED circuit are closed. The third input detection unit is used to detect whether the controlled switch S2 of the DRED circuit is closed. The fourth input detection unit is used to detect whether the controlled switch S3 of the DRED circuit is closed; and The fifth input detection unit is used to detect whether the controlled switch S4 of the DRED circuit is closed. Among them, the priorities of the second input ports respectively connected to the output terminals of the first input detection unit, the second input detection unit, the third input detection unit, the fourth input detection unit, and the fifth input detection unit decrease in sequence.

7. The control circuit according to claim 6, wherein The second priority decoder has second input ports 0 to 7 with increasing priorities. The second input port 0 is grounded through a resistor R0. The second input ports 1 to 5 are respectively connected to the output terminals of the fifth input detection unit, the fourth input detection unit, the third input detection unit, the second input detection unit, and the first input detection unit. The second input ports 6 and 7 are respectively connected to the first reference voltage input terminal through resistors R67.

8. The control circuit according to claim 6, wherein The DRED circuit has a detection output terminal DRM1 / 5 connected to the midpoint between the controlled switches S1 and S5, a detection output terminal DRM2 / 6 connected to the midpoint between the controlled switches S2 and S6, a detection output terminal DRM3 / 7 connected to the midpoint between the controlled switches S3 and S7, and a detection output terminal DRM4 / 8 connected to the midpoint between the controlled switches S4 and S8. The first input detection unit, the third input detection unit, the fourth input detection unit, and the fifth input detection unit each include a comparator. The non-inverting input terminal of each comparator is used to connect to the corresponding detection output terminal, the inverting input terminal is connected to the first reference voltage terminal, and the output terminal is connected to the corresponding second input port of the second priority decoder; and / or, the second input detection unit includes a comparator U5-C, a third diode D3, a fourth diode D4, and a resistor R19. The non-inverting input terminal of the comparator U5-C is respectively connected to the negative electrodes of the third diode and the fourth diode through the resistor R19. The positive electrode of the third diode is connected to the output terminal of the third input detection unit, the positive electrode of the fourth diode is connected to the output terminal of the fourth input detection unit, the inverting input terminal of the comparator U5-C is connected to the second reference unit input terminal, and the output terminal is connected to the corresponding second input port of the second priority decoder.

9. A control system for an energy storage inverter, including a control chip, characterized in that, The control system further includes the control circuit according to any one of claims 1 to 8. The first output port of the first priority decoder and the second output port of the second priority decoder are respectively connected to the GPIO ports of the control chip. The control chip identifies the states of the controlled switches of the DRED circuit according to the level signals of the first output port and the second output port, and correspondingly controls the output or input power of the inverter circuit of the energy storage inverter.

10. A control method for an energy storage inverter, characterized in that, Adopting the control circuit according to any one of claims 1 to 8, the control method includes the following steps: Detect the states of the controlled switches S0 to S9 of the DRED circuit through a plurality of output detection units and a plurality of input detection units. Each first input port of the first priority decoder respectively receives the level of the output terminal of the corresponding output detection unit, and outputs the first code corresponding to the first input port with an effective level and a high priority. The control chip identifies the states of the controlled switches S5 to S8 of the DRED circuit according to the first code output by the first priority decoder, and correspondingly controls the output power of the energy storage inverter. Each second input port of the second priority decoder respectively receives the level of the output end of the corresponding input detection unit, and outputs the second code corresponding to the second input port with an effective level and a high priority. The control chip identifies the states of the controlled switches S1 to S4 of the DRED circuit according to the second code output by the second priority decoder, and correspondingly controls the input power of the energy storage inverter.

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