Memory controller and operating method thereof

Abstract

The present invention discloses an electronic device. According to the present invention, a memory controller with improved operation speed may include: a main memory; a processor configured to generate a command for accessing data stored in the main memory; a scheduler configured to store the command and output the command according to a preset standard; a cache memory configured to cache and store data accessed by the processor among the data stored in the main memory; and a hazard filter configured to: store information about an address of the main memory corresponding to a write command among the commands; when receiving the write command, provide a pre-completion response to the write command to the scheduler; and provide the write command to the main memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2020-0061130 filed on May 21, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory controller and an operating method thereof. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be classified into a volatile memory device and a nonvolatile memory device.

[0005] A volatile memory device may be a device that stores data only when power is supplied thereto and loses the stored data when the power supply is interrupted. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0006] A nonvolatile memory device is a device that does not lose stored data even if power supply is interrupted. Nonvolatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, etc. Summary of the invention

[0007] Embodiments of the present disclosure provide a memory controller having an improved operating speed and an operating method thereof.

[0008] According to an embodiment of the present disclosure, a memory controller may include: a main memory; a processor configured to generate a command for accessing data stored in the main memory; a scheduler configured to store the command and output the command according to a preset standard; a cache memory configured to cache and store data stored in the main memory and accessed by the processor; and a hazard filter configured to store information about an address of the main storage corresponding to a write command among the commands, and when receiving the write command, provide a pre-completion response to the write command to the scheduler, and provide the write command to the main memory.

[0009] A memory controller according to an embodiment of the present disclosure may include: a main memory, including main data stored in an area corresponding to a plurality of main memory addresses; a cache memory, configured to cache and store a portion of the main data in a cache line corresponding to the plurality of main memory addresses; a processor, configured to generate a command for accessing the main data; a scheduler, configured to provide the commands to the cache memory according to an order in which the commands are generated; and a hazard filter, configured to provide a pre-write completion response to the scheduler in response to a write command among the commands, and to provide the write command to the main memory to perform an operation corresponding to the write command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram for describing a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 Is used to describe Figure 1 Schematic diagram of a memory device.

[0012] Figure 3 Is used to describe Figure 2 An illustration of the configuration of any one of the storage blocks.

[0013] Figure 4 It is used to describe the reference Figure 1 A diagram illustrating a read-modify-write operation of L2P mapping data stored in main memory is described.

[0014] Figure 5 is a diagram for describing a read-modify-write operation of a valid page table (VPT) of a physical address.

[0015] Figure 6 is a diagram illustrating a structure of a memory controller according to an embodiment of the present disclosure.

[0016] Figure 7 It shows reference Figure 6 A flow chart describing the operation of the memory controller.

[0017] Figure 8 is a diagram for describing a structure of a memory controller according to another embodiment of the present disclosure.

[0018] Fig. 9 and Fig.10 It is used to describe the reference Figure 8 A flow chart describing the operation of the memory controller.

[0019] Fig.11 It is shown Figure 1 Schematic diagram of an embodiment of a memory controller.

[0020] Fig.12 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0021] Fig.13 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0022] Fig.14 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0023] The specific structural or functional description of the embodiments according to the concepts disclosed in this specification or application is only used to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms, and these descriptions are not limited to the embodiments described in this specification or application.

[0024] Figure 1 is a diagram for describing a storage device 50 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100. The storage device 50 may be a device that stores data under the control of a host 500 such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, an in-vehicle infotainment system, etc.

[0026] The storage device 50 may be any one of various types of storage devices according to a host interface as a communication method with the host 500. For example, the storage device 50 may include one of the following: an SSD, a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, or micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, etc.

[0027] The memory device 50 may be manufactured as one of various types of packages. For example, the memory device 50 may be manufactured as one of the following: package on package (POP), system-in-package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level manufacturing package (WFP), wafer-level stacked package (WSP), etc.

[0028] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells storing data.

[0029] Each of the memory cells may be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0030] The memory cell array (not shown) may include a plurality of memory blocks. One memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0031] In an embodiment, the memory device 100 may be: a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate fourth generation (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory device, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for the convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

[0032] The memory device 100 is configured to receive a command CMD and an address ADDR from a memory controller 200, and access an area selected by the address ADDR in a memory cell array. The memory device 100 may perform an operation indicated by the command CMD on an area selected by the address ADDR. For example, the memory device 100 may perform a write operation (or a programming operation), a read operation, and an erase operation in response to the command CMD. During a programming operation, the memory device 100 may program data to an area selected by the address ADDR. During a read operation, the memory device 100 may read data from an area selected by the address ADDR. During an erase operation, the memory device 100 may erase data stored in an area selected by the address ADDR.

[0033] The memory controller 200 may control the overall operations of the memory device 50 .

[0034] When power is supplied to the memory device 50, the memory controller 200 may run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 500, a flash translation layer (FTL) that controls communication between the memory controller 200 and the host 500, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0035] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 500, and convert the LBA into a physical block address (PBA) indicating an address of a memory cell in the memory device 100 where the received data is to be stored. In this specification, LBA and "logical address" or "logical address" may be used with the same meaning. In this specification, PBA and "physical address" may be used with the same meaning.

[0036] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 500. During a program operation, the memory controller 200 may provide a write command, a PBA, write data, etc. to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0037] In an embodiment, the memory controller 200 may generate commands, addresses, and data regardless of the presence or absence of a request from the host 500, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data for performing read operations and program operations along with performing wear leveling, read recycling, garbage collection, etc. to the memory device 100.

[0038] In an embodiment, the memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the two or more memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be a method of controlling operations on the two or more memory devices 100 to overlap with each other.

[0039] The storage device 50 may further include a main memory 300. The main memory 300 may temporarily store data provided from the host 500, or may temporarily store data read from the memory device 100. In an embodiment, the main memory 300 may be a volatile memory device. For example, the main memory 300 may include a dynamic random access memory (DRAM), a static random access memory (SRAM), or both.

[0040] In an embodiment, the main memory 300 may read metadata stored in the memory device 100 and store the read metadata therein.

[0041] The metadata may be data including various information required to control the memory device 50. For example, the metadata may include bad block information about bad blocks among a plurality of memory blocks included in the memory device 100 and firmware to be executed by the processor 210 of the memory controller 200.

[0042] In an embodiment, the metadata may include mapping data indicating a correspondence between a logical address provided by the host 500 and a physical address of a memory cell included in the memory device 100; and a valid page table indicating whether data stored in a page included in the memory device 100 is valid data. In an embodiment, the valid page table may include a plurality of valid page tables. The valid page table may include data in a bitmap form indicating whether data stored in a page in units of 4KB is valid.

[0043] Optionally, in various embodiments, the metadata may include read count data indicating the number of read operations performed on a storage block included in the memory device 100; cycle data indicating the number of erase times of a storage block included in the memory device 100; hot / cold data indicating whether data stored in a page included in the memory device 100 is hot data or cold data; and log data indicating changes to the mapping data.

[0044] In an embodiment, the metadata stored in the main memory 300 may include a data block having a different type of data structure for the type of metadata. For example, the metadata may have different data sizes for its type. Therefore, the sizes of the metadata stored in the main memory 300 may be different from each other for the type of metadata.

[0045] In an embodiment of the present disclosure, the memory controller 200 may include a processor 210 and a cache memory 220 .

[0046] The processor 210 may control the overall operation of the memory controller 200. The processor 210 may run firmware (FW). The processor 210 may perform operations required to access the memory device 100. For example, the processor 210 may provide a command to the memory device 100, and control the memory device 100 and the main memory 300 to perform operations corresponding to the command.

[0047] For example, when receiving a write request from the host 500 , the processor 210 may convert a logical address corresponding to the write request into a physical address. The processor 210 may store mapping data indicating a correspondence relationship between logical addresses and physical addresses in the main memory 300 .

[0048] In order to store the mapping data, the processor 210 may read a mapping segment from the main memory 300, the mapping segment including mapping information of the logical address provided by the host 500. Thereafter, the processor 210 may record the physical address corresponding to the logical address in the mapping segment. The processor 210 may store the mapping segment in which the physical address is recorded again in the main memory 300. When the physical address is allocated, the data of the valid page table corresponding to the allocated physical address may also be updated.

[0049] In an embodiment, the mapping data stored in the main memory 300 may be updated. For example, when a write request for new data is input for a previously requested logical address, the previously stored data may become invalid data, and the physical address corresponding to the corresponding logical address may be changed. Alternatively, when the location of stored data is changed due to various background operations such as garbage collection, read recovery, and wear leveling, the mapping data corresponding to the location of the data may be updated.

[0050] The cache memory 220 may store data to be accessed by the processor 210, which is read from the main memory 300. The storage capacity of the cache memory 220 may be smaller than the storage capacity of the main memory 300. In an embodiment, the cache memory 220 may be a volatile memory device. For example, the cache memory 220 may include a dynamic random access memory (DRAM) or a static random access memory (SRAM), or both. The cache memory 220 may be a memory having an operating speed faster than that of the main memory 300.

[0051] Since the storage capacity of the cache memory 220 is smaller than that of the main memory 300, the cache memory 220 may store only metadata accessed by the processor 210 among metadata stored in the main memory 300. Storing data stored in a specific address among data stored in the main memory 300 in the cache memory 220 is called caching.

[0052] When the cache memory 220 stores data to be accessed by the processor 210, which is read from the main memory 300, the cache memory 220 may provide the corresponding data to the processor 210. Since the operation speed of the cache memory 220 is faster than the operation speed of the main memory 300, when the data to be accessed by the processor 210 is stored in the cache memory 220, the processor 210 may obtain the data faster than obtaining the data from the main memory 300. The case where the data to be accessed by the processor 210 is stored in the cache memory 220 is called a cache hit, and the case where the data to be accessed by the processor 210 is not stored in the cache memory 220 is called a cache miss. As the number of cache hits increases, the speed of operations processed by the processor 210 may be improved.

[0053] An operation method of the cache memory 220 may be classified into a direct-mapped cache, a set-associative cache, or a fully-associative cache.

[0054] The direct-mapped cache may be a many-to-one (n:1) method in which multiple addresses of the main memory 300 correspond to one address of the cache memory 220. That is, in the direct-mapped cache, data stored in a specific address of the main memory 300 may be cached in a pre-mapped address of the cache memory 220.

[0055] The fully associative cache may be an operation method in which the address of the cache memory 220 is not pre-mapped to a specific address of the main memory 300, and therefore, the address of the blank portion of the cache memory 220 may cache data stored in any address of the main memory 300. When determining whether there is a cache hit, the fully associative cache is required to search all addresses of the cache memory 220.

[0056] The set associative cache is an intermediate form of the direct-mapped cache and the fully associative cache, and manages the cache memory 220 by dividing it into a plurality of cache sets. In addition, the cache set may be divided into cache ways or cache lines.

[0057] The host 500 may communicate with the storage device 50 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0058] Figure 2 Is used to describe Figure 1 Schematic diagram of a memory device 100.

[0059] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input / output (I / O) circuit 140 , and a control logic 150 .

[0060] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi, i being a positive integer greater than 1. The plurality of memory blocks BLK1 to BLKi are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKi may be connected to the input / output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source selection lines, and drain selection lines. In an embodiment, the column lines CL may include bit lines.

[0061] Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. The memory cells connected to the same word line among the plurality of memory cells may be defined as one physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells of the memory device 100 may be configured as a single-layer cell (SLC) storing one bit of data, a multi-layer cell (MLC) storing two bits of data, a triple-layer cell (TLC) storing three bits of data, or a quad-layer cell (QLC) capable of storing four bits of data.

[0062] In an embodiment, the voltage generator 120, the address decoder 130, and the input / output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit drives the memory cell array 110 under the control of the control logic 150. The peripheral circuit may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0063] The voltage generator 120 is configured to generate a plurality of operating voltages using an external power supply voltage supplied to the memory device 100. The voltage generator 120 may operate under the control of the control logic 150.

[0064] In an embodiment, the voltage generator 120 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100.

[0065] In an embodiment, the voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may be configured to generate various voltages required in the memory device 100. For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselect read voltages.

[0066] The voltage generator 120 may include a plurality of pump capacitors receiving an internal power supply voltage, and may generate a plurality of operating voltages by selectively enabling the plurality of pump capacitors under the control of the control logic 150 .

[0067] A plurality of operating voltages generated by the voltage generator 120 may be supplied to the memory cell array 110 through the address decoder 130 .

[0068] The address decoder 130 is connected to the memory cell array 110 through the row line RL. The address decoder 130 is configured to operate under the control of the control logic 150. The address decoder 130 can receive the address ADDR from the control logic 150. The address decoder 130 can decode the block address among the received address ADDR. The address decoder 130 can select at least one storage block among the storage blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 can decode the row address among the received address ADDR. The address decoder 130 can select at least one word line among the word lines of the selected storage block according to the decoded row address. In an embodiment, the address decoder 130 can decode the column address among the received address ADDR. The address decoder 130 can connect the input / output circuit 140 and the memory cell array 110 to each other according to the decoded column address.

[0069] According to an embodiment of the present disclosure, during a read operation, the address decoder 130 may apply a read voltage to a selected word line and apply a read pass voltage having a higher voltage level than the read voltage to unselected word lines.

[0070] For example, the address decoder 130 may include components such as a row decoder, a column decoder, and an address buffer.

[0071] The input / output circuit 140 may include a plurality of page buffers. The plurality of page buffers may be connected to the memory cell array 110 through bit lines. During a program operation, write data may be stored in a selected memory cell based on data stored in the plurality of page buffers corresponding to input data DATA provided by an external device.

[0072] During a read operation, read data stored in a memory cell may be selected through bit line sensing, and the sensed data may be stored in a page buffer. Thereafter, the data stored in the page buffer is output as output data DATA to an external device.

[0073] The control logic 150 may control the address decoder 130, the voltage generator 120, and the input / output circuit 140. The control logic 150 may operate in response to a command CMD output from an external device. The control logic 150 may generate various signals to control peripheral circuits in response to the command CMD and the address ADDR.

[0074] Figure 3 Is used to describe Figure 2 An illustration of the configuration of any one of the storage blocks.

[0075] For example, Figure 3 The storage block BLKi is shown in FIG.

[0076] Reference Figure 3 , a plurality of word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the strings ST, respectively, and the source line SL may be connected to the strings ST in common. Since the strings ST may be configured to be identical to each other, the string ST connected to the first bit line BL1 will be specifically described as an example.

[0077] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. In an embodiment, one string ST may include at least one source selection transistor SST and a drain selection transistor DST, and may include memory cells MC1 to MC16, but the embodiment is not limited thereto. In another embodiment, the number of memory cells included in one string may be greater than 16.

[0078] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be commonly connected to the source select line SSL, the gates of the drain select transistors DST in different strings ST may be commonly connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 in different strings ST may be commonly connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Therefore, the memory block BLKi may include a plurality of physical pages PGs that are the same number as the word lines WL1 to WL16.

[0079] One memory cell can store one bit of data. This is generally referred to as a single-level cell (SLC). In this case, one physical page PG can store data corresponding to one logical page (LPG). The data corresponding to one logical page (LPG) may include data bits having the same number of cells as included in one physical page PG.

[0080] In other embodiments, one memory cell may store two or more bits of data. In this case, one physical page PG may store data corresponding to two or more logical pages.

[0081] Figure 4 It is used to describe the reference Figure 1 A read-modify-write operation of logical-to-physical (L2P) mapped data stored in the main memory 300 is described.

[0082] Reference Figure 1 and Figure 4 , the L2P mapping data stored in the main memory 300 can be updated.

[0083] For example, when a write request is input from the host 500, the processor 210 may assign a physical address to a logical address input from the host 500 according to the write request, and update the valid page table information corresponding to the physical address. Afterwards, when a write request for writing new data is input for a previously requested logical address, the previously stored data may become invalid data, and a new physical address may be assigned to the previously requested logical address. That is, the physical address assigned to the logical address is changed. At the same time, when the location of the stored data is changed due to various background operations such as garbage collection, read recovery, and wear leveling, the L2P mapping data may be updated.

[0084] The L2P mapping data may include multiple mapping segments. Each of the mapping segments may include multiple mapping entries. The mapping entries may include information about the correspondence between the logical address and the physical address.

[0085] Here, it is assumed that a write request for data corresponding to the first logical block address LBA1 is input from the host 500. The processor 210 may read the mapping segment 0 (1) including the mapping entry of the first logical block address LBA1 among the L2P mapping data stored in the main memory 300.

[0086] The processor 210 may allocate a first physical block address PBA1 as a physical address corresponding to the first logical block address LBA1 (2).

[0087] The processor 210 may store the mapping segment 0 including the mapping entry (3) to which the first logical block address LBA1 to which the first physical block address PBA1 is assigned in the main memory 300. Thus, the L2P mapping data stored in the main memory 300 is updated.

[0088] Figure 5 is a diagram for describing a read-modify-write operation of a valid page table (VPT) of a physical address.

[0089] The VPT may include data in the form of a bitmap indicating whether the data stored in the page included in the memory device 100 is valid data. The VPT may include a plurality of bits corresponding to the plurality of pages, respectively. A bit in a "set" state may indicate that the data stored in the corresponding page is valid data, and a bit in a "clear" state may indicate that the data stored in the corresponding page is invalid data.

[0090] Reference Figure 1 , Figure 4 and Figure 5 , a VPT including a zeroth physical block address PBA0 and a first physical block address PBA1 will be described.

[0091] Generally, when the memory controller 200 stores data in the memory device 100, the memory controller 200 secures a free block that is a blank memory block in which no data is stored, and then sequentially stores the data in the pages included in the free block. After the data is stored in the page, the bit of the VPT corresponding to the page is changed to a "set" state. Therefore, before the data is stored, all bits of the VPT corresponding to the physical block address to be allocated may be in a "clear" state.

[0092] Assumption reference Figure 4 The described mapping segment 0 is in a state where the zeroth physical block address PBA0 is assigned as the physical address corresponding to the zeroth logical block address LBA0.

[0093] When it is assumed that the bit corresponding to the page of the zeroth physical block address PBA0 is the first bit1, the processor 210 can read the VPT including the zeroth physical block address PBA0 (501), and modify the "clear" state of the first bit1 to the "set" state. In an embodiment, the bit "1" can indicate the "set" state, and the bit "0" can indicate the "clear" state. Alternatively, the bit "0" can indicate the "set" state, and the bit "1" can indicate the "clear" state. The processor 210 can store the VPT in which the "clear" state of the first bit1 is modified to the "set" state in the main memory 300 (503).

[0094] Afterwards, because as reference Figure 4 The first physical block address PBA1 is newly allocated, so the processor 210 can read the VPT including the first physical block address PBA1 again (505).

[0095] When it is assumed that the bit corresponding to the page of the first physical block address PBA1 is the second bit bit2, the processor 210 may modify the “clear” state of the second bit bit2 to a “set” state.

[0096] The processor 210 may store the VPT in which the “clear” state of the second bit bit2 is modified to the “set” state in the main memory 300 ( 507 ).

[0097] In reference Figure 4 and Figure 5 In the described embodiment, the main memory 300 may be accessed according to the data access mode of the firmware (FW), and the cache memory 220 may be used accordingly.

[0098] For example, when write requests are sequentially input from the host 500, the processor 210 may sequentially execute the data access mode of the main memory 300. That is, the L2P mapping data and the VPT may be continuously accessed so as to allocate a physical block address for storing data, and store the page of the allocated physical block address as a valid data page. Therefore, the access to the L2P mapping data and the VPT may have a very high locality.

[0099] In contrast, when a write request is randomly input from the host 500, the processor 210 may process the data access pattern of the main memory 300 in a mixed manner of sequential access and random access. For example, access to L2P mapped data may be random, and access to VPT may be sequential.

[0100] Figure 6 is a diagram showing a structure of a memory controller 400 according to an embodiment of the present disclosure.

[0101] Reference Figure 6 , the memory controller 400 may include a processor 410 , a cache controller 420 , and a main memory 430 .

[0102] The processor 410 and the main memory 430 may be configured separately and with reference to Figure 1 The processor 210 and main memory 300 are described to operate identically.

[0103] The cache controller 420 may include a scheduler 421 and a cache memory 422 .

[0104] The scheduler 421 may store an access request input from the processor 410 and an address corresponding to the access request. The scheduler 421 may provide the access request to the cache memory 422 or receive a completion response for the provided access request.

[0105] The scheduler 421 may receive an access request and an address to be accessed from the processor 410. When the access request received from the processor 410 is a write request, the scheduler 421 may receive the write request, the write address, and the write data. The scheduler 421 may transmit the write request, the write address, and the write data to the cache memory 422. The write data may be stored in an area corresponding to the write address in the main memory 430 through the cache memory 422. The main memory 430 may store the write data in an area corresponding to the write address, and then provide a write completion response to the cache controller 420, which indicates that the write request has been executed. The write completion response may be transmitted to the processor 410 through the cache memory 422 and the scheduler 421.

[0106] When the access request received from the processor 410 is a read request, the scheduler 421 may receive the read request and the read address. The scheduler 421 may transmit the read request and the read address to the cache memory 422. When the data corresponding to the read request is cached in the cache line corresponding to the read address (cache hit), the cache memory 422 may provide the cached data to the scheduler 421. The scheduler 421 may transmit the received data to the processor 410. When the data corresponding to the read request is not cached in the cache line corresponding to the read address (cache miss), the cache memory 422 may provide the read request and the read address to the main memory 430. The main memory 430 may provide the read data stored in the area corresponding to the read address to the cache controller 420. The read data may be stored in the cache line corresponding to the read address in the cache memory 422 (cache). The read data may be transmitted to the processor 410 through the scheduler 421.

[0107] When a read request for an address corresponding to the same cache line as a write request is input before completion of the write request, the data stored in the cache memory 422 may be different from the data stored in the main memory 430, which is input after the write request. In this case, when the data corresponding to the read request is already cached in the cache memory 422, a cache hit may occur, and thus data different from the most recently written data may be provided to the processor 410 (a hazard occurs).

[0108] In order to prevent danger from occurring, when a conflict occurs in the cache lines corresponding to the addresses of the input access requests, that is, when a first access request and a second access request for the address corresponding to the same cache line are input, the scheduler 421 may maintain the second access request input after the first access request without transmitting the second access request to the cache memory 422 until the first access request is processed.

[0109] However, considering the data access pattern of the main memory 430 , it may frequently happen that many read requests are held or pending inside the scheduler 421 due to preceding write requests.

[0110] Therefore, the read latency occurring in the cache memory 422 may become longer, and thus the processing speed of the processor 410 may be slower.

[0111] Figure 7 It shows reference Figure 6 A flow chart describing the operation of memory controller 400 is shown.

[0112] Reference Figure 6 and Figure 7 In step S601 , the processor 410 may provide a read request for the address ADDR0 to the scheduler 421 .

[0113] In step S603 , the scheduler 421 may store the read request for the address ADDR0 , and because there is no previous read request or write request for the address ADDR0 , the scheduler 421 may provide the read request for the address ADDR0 to the cache memory 422 .

[0114] In step S605, the cache memory 422 may check whether the data corresponding to the address ADDR0 has been cached in the cache memory 422. When the data corresponding to the address ADDR0 does not exist in the cache memory 422, a cache miss may occur.

[0115] When a cache miss occurs, the cache memory 422 may provide a read request for the address ADDR0 to the main memory 430 in step S607 .

[0116] In step S609 , the main memory 430 may read out data corresponding to the address ADDR0 , ie, ADDR0 DATA, and provide the read data ADDR0 DATA to the cache memory 422 .

[0117] In step S611, the cache memory 422 may store the read data ADDR0 DATA in the cache memory 422 (cache).

[0118] In step S613, the cache memory 422 may provide the read data ADDR0 DATA to the scheduler 421. In step S615, the scheduler 421 may provide the read data ADDR0 DATA to the processor 410.

[0119] In step S617 , the processor 410 may provide a write request for the address ADDR0 to the scheduler 421 .

[0120] In step S619 , the scheduler 421 may provide a write request for the address ADDR0 to the cache memory 422 .

[0121] In step S621, the cache memory 422 may store the write data in the cache memory 422. Alternatively, the write data may not be stored in the cache memory 422, and an indication that the data cached in the cache line corresponding to the address ADDR0 is dirty data may be stored in the cache memory 422.

[0122] In step S623 , the cache memory 422 may provide a write request for the address ADDR0 to the main memory 430 .

[0123] When the write request is executed in the main memory 430, in step S625, the processor 410 may provide another read request for the address ADDR0 to the scheduler 421. In this case, because the scheduler 421 has not received the write request completion response WRITE ADDR0COMPLETION for the address ADDR0 that is the same as the address ADDR0 of the other read request, the other read request is not output to the cache memory 422 and is held or blocked in the scheduler 421.

[0124] In step S627 , the main memory 430 may execute the write request for the address ADDR0 , ie, store the write data in the area corresponding to the address ADDR0 , and provide a write completion response WRITE ADDR0 COMPLETION to the scheduler 421 .

[0125] In step S629 , the scheduler 421 may provide a write completion response WRITE ADDR0 COMPLETION to the processor 410 .

[0126] In step S631 , the scheduler 421 may provide other read requests for the address ADDR0 to the cache memory 422 .

[0127] In step S633, the cache memory 422 may check whether the newly written data corresponding to the address ADDR0 has been cached in the cache memory 422. Because the newly written data corresponding to the address ADDR0 has not been cached in the cache memory 422, a cache miss may occur.

[0128] In step S635 , the cache memory 422 may provide other read requests for the address ADDR0 to the main memory 430 .

[0129] In step S637 , the main memory 430 may read out the newly written data corresponding to the address ADDR0 , ie, ADDR0 DATA, and provide the read data ADDR0 DATA to the cache memory 422 .

[0130] In step S639, the cache memory 422 may store the read data ADDR0 DATA in the cache memory 422 (cache).

[0131] In step S641, the cache memory 422 may provide the read data ADDR0 DATA to the scheduler 421. In step S643, the scheduler 421 may provide the read data ADDR0 DATA to the processor 410.

[0132] According to reference Figure 7 In the described embodiment, when there is a conflict among the cache lines corresponding to the addresses of the input access requests, for example, when the first access request and the second access request corresponding to the address corresponding to the same cache line are sequentially input, the scheduler 421 may hold the second access request without transmitting the second access request to the cache memory 422 until the first access request is processed. Therefore, considering the data access pattern of the main memory 430 processed by the processor 410, it may frequently occur that many read requests are held or blocked inside the scheduler 421 due to the previous write request. Therefore, the read delay occurring in the cache memory 422 may become longer, and thus the processing speed of the processor 410 may be slower.

[0133] Figure 8 is a diagram for describing a structure of a memory controller 700 according to an embodiment of the present disclosure.

[0134] Reference Figure 8 , the memory controller 700 may include a processor 710 , a cache controller 720 , and a main memory 730 .

[0135] The processor 710 and the main memory 730 can be respectively connected to the reference Figure 1 and Figure 6 The processor 210 and the processor 410 and the main memory 230 and the main memory 430 are described to be configured and operated identically.

[0136] The cache controller 720 may include a scheduler 721 , a cache memory 722 , and a danger filter 723 .

[0137] The scheduler 721 may store an access request input from the processor 710 and an address corresponding to the access request. The scheduler 721 may provide the input access request to the cache memory 722 or receive a completion response for the provided access request.

[0138] The scheduler 721 may receive at least an access request and an address to be accessed from the processor 710. When the access request received from the processor 710 is a write request, the scheduler 721 may receive the write request, the write address, and the write data. The scheduler 721 may transmit the write request, the write address, and the write data to the cache memory 722. The write data may be provided to the danger filter 723 through the cache memory 722.

[0139] When the access request received from the processor 710 is a read request, the scheduler 721 may receive the read request and the read address. The scheduler 721 may transmit the read request and the read address to the cache memory 722. When the data corresponding to the read address has been cached in the cache line corresponding to the read address (cache hit), the cache memory 722 may provide the cached data to the scheduler 721. The scheduler 721 may transmit the received data to the processor 710. When the data corresponding to the read address has not been cached in the cache line corresponding to the read address (cache miss), the cache memory 722 may provide the read request and the read address to the main memory 730. The main memory 730 may provide the read data stored in the area corresponding to the read address to the cache controller 720. The read data may be stored in the cache line corresponding to the read address in the cache memory 722 (cache). The read data may be transmitted to the processor 710 through the scheduler 721.

[0140] When a read request for an address corresponding to the same cache line as the read request is input before a write request for the address is completed, the data in the cache memory 722 may be previous data different from the write data most recently stored in the main memory 730 in response to the write request. In this case, when the data corresponding to the read request is already cached in the cache memory 722, a cache hit may occur, and thus the previous data stored in the cache memory 722 and different from the most recently written data may be provided to the processor 710 (a hazard occurs).

[0141] In order to prevent danger from occurring, when a conflict occurs in cache lines corresponding to addresses of input access requests, that is, when access requests for addresses corresponding to the same cache line are sequentially input, the scheduler 721 may hold the access request input later without transmitting the access request input later to the cache memory 722 until the access request input first is processed.

[0142] For example, assuming that the first access request input is a write request, and the later access request input is a read request, the first access request input and the later access request input are for addresses corresponding to the same cache line. In this case, the scheduler 721 may hold the read request without transmitting the read request to the cache memory 722 until the write request is completed in the main memory 730.

[0143] The danger filter 723 may receive a write request, a write address, and write data that have passed through the scheduler 721 and the cache memory 722, and store the write request and / or the write address in an internal lookup table LUT. Thereafter, the danger filter 723 may provide the write request, the write address, and the write data to the main memory 730. In an embodiment, when a write request is received from the cache memory 722 or a write request is provided to the main memory 730, the danger filter 723 may provide a pre-write completion response to the scheduler 721 before receiving a write completion response from the main memory 730.

[0144] After receiving the pre-write completion response from the hazard filter 723, the scheduler 721 may provide the read request and the read address held or blocked by the scheduler 721 to the cache memory 722. The hazard filter 723 may receive the read request when a cache miss for the read request occurs in the cache memory 722. The hazard filter 723 may check whether a write request for the same address as the read address is included in the internal lookup table LUT.

[0145] When a write request for the same address as the read address is stored in the internal lookup table LUT, the hazard filter 723 may hold the read request until a write completion response is received from the main memory 730. When a write request for the same address as the read address is not stored in the internal lookup table LUT, the hazard filter 723 may provide the read request to the main memory 730.

[0146] That is, the hazard filter 723 can issue a pre-write completion response for a write request to the scheduler 721 before receiving a write completion response from the main memory 730, and handle a hazard situation that may occur later. Therefore, the read latency can be improved.

[0147] Fig. 9 and Fig.10 Is used to describe Figure 8 Flowchart of the operation of the memory controller 700.

[0148] Reference Fig. 9 and Fig.10 In step S901 , the processor 710 may provide a read request for the address ADDR0 to the scheduler 721 .

[0149] In step S903 , the scheduler 721 may store the read request for the address ADDR0 . When there is no previous read request or write request for the address ADDR0 , the scheduler 721 may provide the read request for the address ADDR0 to the cache memory 722 .

[0150] In step S905, the cache memory 722 may check whether the data corresponding to the address ADDR0 has been cached in the cache memory 722. When the data corresponding to the address ADDR0 has not been cached in the cache memory 722, a cache miss may occur.

[0151] When a cache miss occurs, the cache memory 722 may provide a read request for the address ADDR0 to the danger filter 723 in step S907 .

[0152] In step S909 , the dangerous filter 723 may transmit a read request for the address ADDR0 to the main memory 730 .

[0153] In step S911 , the main memory 730 may read out data corresponding to the address ADDR0 , ie, ADDR0 DATA, and provide the read data ADDR0 DATA to the cache memory 722 .

[0154] In step S913, the cache memory 722 may store the read data ADDR0 DATA in the cache memory 722 (cache).

[0155] In step S915, the cache memory 722 may provide the read data ADDR0 DATA to the scheduler 721. In step S917, the scheduler 721 may provide the read data ADDR0 DATA to the processor 710.

[0156] In step S919 , the processor 710 may provide a write request for the address ADDR0 to the scheduler 721 .

[0157] In step S921 , the scheduler 721 may provide a write request for the address ADDR0 to the cache memory 722 .

[0158] In step S923, the cache memory 722 may store the write data in the cache memory 722. In another embodiment, the write data may not be stored in the cache memory 722, and an indication that the data cached in the cache line corresponding to the address ADDR0 is dirty data may be stored in the cache memory 722.

[0159] In step S925 , the cache memory 722 may provide a write request for the address ADDR0 to the dangerous filter 723 .

[0160] In step S927 , the hazard filter 723 may provide the pre-write completion response to the scheduler 721 . In addition, the write address ADDR0 may be stored in an internal lookup table of the hazard filter 723 .

[0161] In step S929 , the dangerous filter 723 may provide a write request to the main memory 730 .

[0162] When a write request is executed in the main memory 730 , the processor 710 may provide another read request for the address ADDR0 to the scheduler 721 in step S931 .

[0163] In step S933 , because the scheduler 721 has received a pre-write request completion response for address ADDR0 from the dangerous filter 723 , which is the same as address ADDR0 for other read requests, the scheduler 721 may provide other read requests for the address ADDR0 to the cache memory 722 .

[0164] In step S935, the cache memory 722 may check whether the data corresponding to the address ADDR0 has been cached in the cache memory 722. When the data corresponding to the address ADDR0 has not been cached in the cache memory 722, a cache miss may occur.

[0165] When a cache miss occurs, the cache memory 722 may provide other read requests for the address ADDR0 to the danger filter 723 in step S937 .

[0166] In step S939, the danger filter 723 may determine whether a write request for the same address as other read requests is stored in the internal lookup table LUT. As a result of the determination, when a write request for the same address as other read requests is stored in the internal lookup table LUT and a write completion response for the write request has not been received, other read requests for address ADDR0 may be maintained or blocked in the danger filter 723.

[0167] In step S941, the main memory 730 may provide a write completion response to the danger filter 723. Although not shown, when receiving the write completion response from the main memory 730, the danger filter 723 may remove information about the write request, such as the write request or an address corresponding to the write request, from the lookup table LUT.

[0168] In step S943 , the dangerous filter 723 may provide other read requests for the address ADDR0 to the main memory 730 .

[0169] In step S945 , the main memory 730 may read out the read data corresponding to the address ADDR0 , ie, ADDR0 DATA, and provide the read data ADDR0 DATA to the cache memory 722 .

[0170] In step S947, the cache memory 722 may store the read data ADDR0 DATA in the cache memory 722 (cache).

[0171] In step S949, the cache memory 722 may provide the read data ADDR0 DATA to the scheduler 721. In step S951, the scheduler 721 may provide the read data ADDR0 DATA to the processor 710.

[0172] In an embodiment, when the processor 710 provides a read request following a write request to the cache controller 720, if the write request is not for the same address as the read request, and thus no write request for the same address as the read request is stored in the internal lookup table LUT, the hazard filter 723 can provide the read request to the main memory 730 without waiting for the write request to complete the response.

[0173] According to the above operations in the cache controller 720, the read latency can be reduced, so the processing speed of the processor 410 can be faster.

[0174] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Schematic diagram of a memory controller 200 .

[0175] Reference Figure 1 and Fig.11 , the memory controller 200 may include a processor 210 , a RAM 220 , an error correction circuit 230 , a ROM 260 , a host interface 270 , and a flash memory interface 280 .

[0176] The processor 210 may control the overall operation of the memory controller 200. The RAM 220 may be used as a buffer memory, a cache memory, and an operation memory of the memory controller 200. Figure 1 The depicted cache memory 220 may be a RAM 220. In an embodiment, the RAM 220 may be a SRAM.

[0177] The ROM 260 may store various information required for the operation of the memory controller 200 in the form of firmware.

[0178] The memory controller 200 may communicate with an external device (eg, the host 500 , an application processor, etc.) through the host interface 270 .

[0179] The memory controller 200 may communicate with the memory device 100 through the host interface 280. The memory controller 200 may transmit commands CMD, addresses ADDR, and control signals CTRL to the memory device 100 through the flash interface 280, and receive data DATA read from the memory device 100. For example, the flash interface 280 may include a NAND interface.

[0180] Fig.12 is a block diagram illustrating a memory card system 2000 to which a memory device according to an embodiment of the present disclosure is applied.

[0181] Reference Fig.12 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0182] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host (not shown). The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may utilize a reference Figure 1 The memory controller 200 described is configured.

[0183] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, an error corrector, and the like.

[0184] The memory controller 2100 may communicate with an external device such as a host through the connector 2300. The memory controller 2100 may communicate with the external device according to a specific communication standard. For example, the memory controller 2100 may be configured to communicate with the external device according to at least one of various communication standards such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, NVMe, etc. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

[0185] For example, the memory device 2200 can be configured as any one of various non-volatile memory elements such as: electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin torque magnetic RAM (STT-MRAM), etc.

[0186] The memory controller 2100 and the memory device 2200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), a Universal Flash Storage (UFS), etc.

[0187] Fig.13 is a block diagram illustrating a solid state drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

[0188] Reference Fig.13 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through a signal connector 3001, and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0189] According to an embodiment of the present disclosure, the SSD controller 3210 may execute a reference Figure 1 The functions of the memory controller 200 are described.

[0190] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, NVMe, etc.

[0191] The auxiliary power supply device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 can receive power PWR from the host 3100 and can be charged by the power PWR therein. When the power supply from the host 3100 is not stable, the auxiliary power supply device 3230 can provide auxiliary power to the SSD 3200. For example, the auxiliary power supply device 3230 can be located inside the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located in the mainboard and can provide auxiliary power to the SSD 3200.

[0192] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0193] Fig.14 is a block diagram illustrating a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

[0194] Reference Fig.14, the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0195] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0196] The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc., or a nonvolatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as one semiconductor device.

[0197] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as: code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module 4300 may be included in the application processor 4100.

[0198] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be implemented as a non-volatile semiconductor memory element such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a three-dimensional NAND flash memory. For example, the storage module 4400 may be provided as a removable storage device (removable drive) such as a memory card or an external drive of the user system 4000.

[0199] For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with the reference Figure 1The memory module 4400 may be similar to the memory device 100 described in the previous embodiment. Figure 1 The described storage device 50 operates identically.

[0200] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include one or more of the following user input interfaces: a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, a piezoelectric element, etc. The user interface 4500 may include one or more of the following user output interfaces: a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, a monitor, etc.

[0201] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are only examples. Therefore, the systems and devices described herein should not be limited based on the described embodiments.

Claims

1. A memory controller, comprising: A main memory temporarily stores data read from the nonvolatile memory; a processor that generates a command for accessing data stored in the main memory; a scheduler, storing the command and outputting the command according to a preset standard; a cache memory that caches and stores data accessed by the processor among the data stored in the main memory; as well as a danger filter storing information about an address of the main memory corresponding to a write command among the commands, providing a pre-completion response for receiving the write command to the scheduler upon receiving the write command, and providing the write command to the main memory, wherein the pre-completion response is provided to the scheduler before writing data corresponding to the write command to the main memory, wherein the scheduler, in response to receipt of the pre-completion response, outputs to the cache memory a read command corresponding to the same address as the main memory address corresponding to the write command, wherein when the data corresponding to the read command is stored in the cache memory, the cache memory provides the data corresponding to the read command to the scheduler, and When data corresponding to the read command is not stored in the cache memory, the danger filter provides the read command to the main memory according to whether a write completion response to the write command is received from the main memory. 2 . The memory controller of claim 1 , wherein the scheduler holds the read command without outputting the read command to the cache memory until a pre-completion response to the write command is received from the hazard filter. 3 . The memory controller according to claim 1 , wherein the scheduler outputs commands for different addresses among the addresses of the main memory according to an order of the commands received from the processor.

4. The memory controller according to claim 1, wherein when a read command for the main memory corresponding to the write command is input, the hazard filter provides the read command to the main memory after receiving a write completion response for the write command from the main memory.

5. The memory controller according to claim 1, wherein when data corresponding to a read command among the commands is stored in a cache line corresponding to an address of the read command, the cache memory provides the data stored in the cache line to the scheduler. 6 . The memory controller according to claim 1 , wherein when data corresponding to a read command among the commands does not exist in a cache line corresponding to an address of the read command, the cache memory transfers the read command to the danger filter. 7 . The memory controller of claim 1 , wherein the hazard filter comprises a lookup table storing information about the address of the main memory corresponding to the write command.

8. The memory controller of claim 7, wherein when a write completion response to the write command is received from the main memory, the hazard filter removes information about the address of the main memory corresponding to the write command from the lookup table.

9. The memory controller of claim 1, wherein when caching data from the main memory to the cache memory, a plurality of addresses of the main memory are mapped with one address of the cache memory.

10. The memory controller of claim 1, wherein the main memory is a dynamic random access memory.

11. The memory controller of claim 1, wherein the cache memory is a static random access memory.

12. A memory controller comprising: a main memory that temporarily stores main data read from the nonvolatile memory in an area corresponding to a plurality of main memory addresses; a cache memory that caches and stores a portion of the primary data in cache lines corresponding to the plurality of primary memory addresses; a processor, generating a command for accessing the master data; a scheduler that provides the commands to the cache memory according to the order in which the commands are generated; as well as a dangerous filter that, in response to reception of a write command among the commands received from the scheduler, provides a pre-write completion response to the scheduler, and provides the write command to the main memory to perform an operation corresponding to the write command, wherein the pre-write completion response is provided to the scheduler before writing data corresponding to the write command to the main memory, wherein the scheduler outputs to the cache memory a read command corresponding to the same address as the main memory address corresponding to the write command in response to receipt of the pre-write completion response, wherein when the data corresponding to the read command is stored in the cache memory, the cache memory provides the data corresponding to the read command to the scheduler, and When data corresponding to the read command is not stored in the cache memory, the danger filter provides the read command to the main memory according to whether a write completion response to the write command is received from the main memory. 13 . The memory controller of claim 12 , wherein the hazard filter comprises a lookup table storing a main memory address corresponding to the write command among the plurality of main memory addresses.

14. The memory controller of claim 13, wherein in response to a read command among the commands, the hazard filter provides the read command to the main memory according to whether the main memory address corresponding to the read command is stored in the lookup table. 15 . The memory controller of claim 12 , wherein any blank cache line among the cache lines caches data from the region corresponding to the plurality of main memory addresses, the blank cache line not storing data.

16. The memory controller according to claim 12, wherein when data corresponding to a read command among the commands is stored in a cache line corresponding to a main memory address of the read command, the cache memory provides the data stored in the cache line to the scheduler. 17 . The memory controller according to claim 12 , wherein when data corresponding to a read command among the commands does not exist in a cache line corresponding to a main memory address of the read command, the cache memory transfers the read command to the danger filter.

18. The memory controller of claim 12, wherein the main memory is a dynamic random access memory.

19. The memory controller of claim 12, wherein the cache memory is a static random access memory.

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