Low power consumption verification method, device, electronic device and storage medium

Abstract

The present application proposes a low-power verification method, device, electronic device and storage medium, wherein the method includes: determining the register transfer level RTL model of the system-level chip and the control logic test case in the low-power mode; performing simulation verification on the system-level chip in the RTL simulation stage according to the control logic test case and the RTL model; when the verification is successful in the RTL simulation stage, generating the unified power format UPF model of the system-level chip according to the RTL model, and simulating the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model; when the verification is successful in the RTL+UPF simulation stage, generating the PG netlist of the system-level chip according to the UPF model, simulating the system-level chip in the PG netlist simulation stage according to the control logic test case and the PG netlist, so as to determine whether the verification is successful in the PG netlist simulation stage. The method can verify the RTL alone, solve the low-power verification blind spot, and reduce the complexity of debugging the RTL.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a low-power verification method, device, electronic device and storage medium. Background Art

[0002] With the advancement of large-scale integrated circuit chip technology and the reduction of chip area, the requirements for chip power consumption have become more stringent. Low-power design can effectively reduce power consumption according to chip scenarios, and low-power verification has developed into an independent branch of chip verification.

[0003] In the related art, the low power consumption of the entire chip is verified during the low power consumption verification, and there are blind spots in the low power consumption verification. Summary of the invention

[0004] The purpose of this application is to solve one of the technical problems in the above technology at least to a certain extent.

[0005] The present application proposes a low-power verification method to implement separate verification of register transfer level (RTL), solve the blind spot of low-power verification, and reduce the complexity of debugging RTL.

[0006] The first aspect of the present application proposes a low-power verification method, including: determining a register transfer level RTL model of a system-level chip and a control logic test case in a low-power mode; performing simulation verification on the system-level chip in the RTL simulation stage according to the control logic test case and the RTL model to determine whether the verification is successful in the RTL simulation stage; when the verification is successful in the RTL simulation stage, generating a unified power format UPF (Unified Power Format) model of the system-level chip according to the RTL model, and performing simulation on the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the verification is successful in the RTL+UPF simulation stage, generating a PG netlist of the system-level chip according to the UPF model, and performing simulation on the system-level chip in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0007] The low-power verification method of the embodiment of the present application, by determining the register transfer level RTL model of the system-level chip and the control logic test case in the low-power mode; according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; when the RTL simulation stage is successfully verified, the unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the RTL+UPF simulation stage is successfully verified, the PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage. The method can verify RTL alone, solve the low-power verification blind spot, and reduce the complexity of debugging RTL.

[0008] Optionally, the control logic test cases include: test cases corresponding to each power domain in low power mode; the simulation verification of the system-level chip in the RTL simulation stage according to the control logic test cases and the RTL model includes: for each power domain, controlling the input value of the register in the RTL model according to the test case corresponding to the power domain to obtain the actual output value of each circuit unit in the RTL model; comparing the actual output value of each circuit unit with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage.

[0009] Optionally, for each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to obtain the actual output value of each circuit unit in the RTL model, including: for each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to perform a simulation process; and each circuit unit in the RTL model is called during the simulation process to obtain the actual output value of each circuit unit during the simulation process.

[0010] Optionally, each circuit unit in the RTL model includes at least one of the following units: a power domain switch, a gated clock, a reset unit, an isolation and logic circuit signal switch.

[0011] Optionally, the UPF model is provided with a reinitialization logic to adjust the values ​​of each circuit unit in the UPF model to a preset initial value after the reinitialization logic is triggered.

[0012] Optionally, the setting method of the reinitialization logic includes at least one of the following methods: adding the reinitialization logic to the UPF model; nesting outer logic outside the UPF model, wherein the outer logic includes the reinitialization logic.

[0013] Optionally, a unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model, including: for each power domain, controlling the input value of the register in the UPF model according to the test case corresponding to the power domain to obtain the actual voltage value of the circuit pins of each circuit unit in the UPF model; comparing the actual voltage value of each circuit pin with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage.

[0014] Optionally, the PG netlist is a netlist that is not provided with a standard delay format file, and is used to perform netlist function simulation on the system-level chip.

[0015] The second aspect of the present application proposes a low-power verification device, including: a determination module, used to determine the register transfer level RTL model of the system-level chip and the control logic test case in the low power mode; a first simulation module, used to perform simulation verification on the system-level chip in the RTL simulation stage according to the control logic test case and the RTL model, so as to determine whether the verification is successful in the RTL simulation stage; a second simulation module, used to generate a unified power format UPF model of the system-level chip according to the RTL model when the verification is successful in the RTL simulation stage, and simulate the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; a third simulation module, used to generate a PG netlist of the system-level chip according to the UPF model when the verification is successful in the RTL+UPF simulation stage, and simulate the system-level chip in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0016] The low-power verification device of the embodiment of the present application determines the register transfer level RTL model of the system-level chip and the control logic test case in the low-power mode; according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; when the verification is successful in the RTL simulation stage, the unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the verification is successful in the RTL+UPF simulation stage, the PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage. The device can verify the RTL alone, solve the low-power verification blind spot, and reduce the complexity of debugging RTL.

[0017] The third aspect embodiment of the present application proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the low power consumption verification method proposed in the first aspect embodiment of the present application.

[0018] The fourth aspect embodiment of the present application proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the low-power consumption verification method proposed in the first aspect embodiment of the present application.

[0019] The fifth aspect embodiment of the present application proposes a computer program product. When the instruction processor in the computer program product executes, the low power consumption verification method proposed in the first aspect embodiment of the present application is executed.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0022] Figure 1 A flowchart of a low power consumption verification method provided in Embodiment 1 of the present application;

[0023] Figure 2 A flowchart of a low power consumption verification method provided in Embodiment 2 of the present application;

[0024] Figure 3 A flowchart of a low power consumption verification method provided in Embodiment 3 of the present application;

[0025] Figure 4 A schematic diagram of the structure of a low power consumption verification device provided in Embodiment 4 of the present application;

[0026] Figure 5 The invention is a block diagram of an electronic device for a low power consumption verification method according to an exemplary embodiment. DETAILED DESCRIPTION

[0027] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0028] The following describes the low power consumption verification method, device, electronic device and storage medium according to the embodiments of the present disclosure with reference to the accompanying drawings.

[0029] Figure 1 This is a flow chart of a low power verification method provided in Embodiment 1 of the present application. It should be noted that the low power verification method can be applied to a low power verification device. The device can be configured in an electronic device. The electronic device can be a mobile terminal, for example, a mobile phone, a tablet computer, a personal digital assistant, and other hardware devices with various operating systems.

[0030] like Figure 1 As shown, the low power verification method includes the following steps:

[0031] Step 101 : determining a register transfer level (RTL) model of a system-on-chip and a control logic test case in a low power consumption mode.

[0032] In the embodiment of the present application, the register transfer level RTL model can be determined according to the flow of digital signals of the system-level chip between logic units such as hardware registers, memories, combinational logic devices and buses, and their logic algebraic operation mode, and when the system-level chip is in a low power mode, control logic test cases such as registers and circuit units in the system-level chip are obtained. It should be noted that the low power mode may include an idle mode and a sleep mode.

[0033] Step 102 , according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage.

[0034] In order to facilitate the low-power verification of the system-level chip, the total power supply can be divided into multiple power domains. According to the test cases and RTL models corresponding to each power domain in the low-power mode, the system-level chip is simulated and verified in the RTL simulation stage. According to the simulation verification results, it can be determined whether the verification is successful in the RTL simulation stage.

[0035] Step 103, when the verification is successful in the RTL simulation stage, a unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage.

[0036] Furthermore, when the verification is successful at the RTL simulation stage, the logic of registers, circuit units, etc. in the system-level chip, as well as the power logic, can be generated according to the RTL model. Furthermore, the system-level chip can be simulated at the RTL+UPF simulation stage according to the test cases corresponding to each power domain in the low-power mode and the UPF model. According to the simulation results, it can be determined whether the verification is successful at the RTL+UPF simulation stage. When the verification is unsuccessful at the RTL simulation stage, the low-power verification device can report an error and end the simulation.

[0037] Step 104, when the verification is successful in the RTL+UPF simulation stage, a PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0038] In the embodiment of the present application, when the RTL+UPF simulation stage is successfully verified, the PG netlist of the system-level chip can be generated according to the UPF model, and the system-level chip can be simulated in the PG netlist simulation stage according to the test cases corresponding to each power domain in the low-power mode and the PG netlist, and the logic of the registers, circuit units, etc. and the power logic are verified to be consistent with the PG netlist. When the logic of the registers, circuit units, etc. and the power logic are consistent with the PG netlist, it can be determined that the verification is successful in the PG netlist simulation stage. It should be noted that due to the simulation time limit, the PG netlist is a netlist that is not provided with a standard delay format file, and the compilation option needs to be used to increase the delay. The PG netlist can be used to simulate the netlist function of the system-level chip.

[0039] In summary, by determining the register transfer level RTL model of the system-level chip and the control logic test case in the low power mode; according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; when the verification is successful in the RTL simulation stage, the unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the verification is successful in the RTL+UPF simulation stage, the PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage. This method can verify the RTL alone, solve the blind spot of low power verification, and reduce the complexity of debugging RTL.

[0040] In order to accurately determine whether the RTL simulation stage is successfully verified, Figure 2 As shown, Figure 2 A flowchart of the low-power verification method provided in the second embodiment of the present application. In the embodiment of the present application, the actual output value of each circuit unit in the RTL model can be obtained, and the actual output value of each circuit unit can be compared with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage. Figure 2 The illustrated embodiment may include the following steps:

[0041] Step 201 : determining a register transfer level (RTL) model of a system-on-chip and a control logic test case in a low power consumption mode.

[0042] Step 202 : for each power domain, control the input value of the register in the RTL model according to the test case corresponding to the power domain, so as to obtain the actual output value of each circuit unit in the RTL model.

[0043] Optionally, for each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to perform a simulation process; during the simulation process, each circuit unit in the RTL model is called to obtain the actual output value of each circuit unit during the simulation process.

[0044] That is to say, for each power domain in the low power mode, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain, and RTL simulation is performed. During the simulation process, the actual output value of each circuit unit in the simulation process is obtained by calling each circuit unit in the RTL model. It should be noted that each circuit unit in the RTL model includes at least one of the following units: power domain switch, gated clock, reset unit, isolation and logic circuit signal switch.

[0045] In an embodiment of the present application, the RTL model and the power domain are powered on by default. First, configure the global register so that the RTL model sends a power-off request to the power management unit (Power Management Unit, PMU). After receiving the request, the PMU enters the power-off process. The various circuit units in the RTL model are verified, including power domain switches, gated clocks, reset units, isolation, logic circuit signal switches, and dynamic frequency adjustment. When verifying the power domain switch in the RTL simulation phase, check whether the logical electrical signal is correct. Optionally, establish power-on and power-off tasks for each power domain to control the power-on and power-off process for test case calls. When the power domain is powered on and off, after the power management control unit receives the power-off request from the power domain, it controls the clock, reset, isolation, and logic electrical circuit signal switches in turn, verifies that the platform monitor is bound to the power management control unit, checks its timing and monitors it. Among them, the control logic test cases in low power mode may include: PMU direct connection ignore (BYPASS) mode, only turn off the clock, PMU software control path, configure the power channel handshake module, the subsystem sends software requests to control the power mode, double data rate synchronous dynamic random access memory (DDR) memory shallow sleep, each subsystem is configured with shallow sleep, and PMU forces the subsystem to enter shallow sleep and chip deep sleep. The test process in the RTL simulation stage can be as follows: (1) configure the bus timeout value; (2) configure the system power-off enable; (3) enable the system power-on and power-off interrupts; (4) configure the register power-off enable bit; (5) set the interrupt status; (6) clear the interrupt.

[0046] Step 203 , comparing the actual output value of each circuit unit with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage.

[0047] Furthermore, the actual output value of each circuit unit is compared with the theoretical output value of each circuit unit under the input numerical value. When the actual output value of each circuit unit is within the theoretical output range of each circuit unit under the input numerical value, it can be determined that the verification is successful in the RTL simulation stage; when the actual output value of each circuit unit is not within the theoretical output range of each circuit unit under the input numerical value, it can be determined that the verification is not successful in the RTL simulation stage and the simulation is terminated.

[0048] Step 204, when the verification is successful in the RTL simulation stage, a unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage.

[0049] Step 205, when the verification is successful in the RTL+UPF simulation stage, a PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0050] In the embodiment of the present application, steps 201, 204 and step 205 can be implemented in any manner in the embodiments of the present application, and the present application does not impose any specific limitation.

[0051] In summary, for each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to obtain the actual output value of each circuit unit in the RTL model; the actual output value of each circuit unit is compared with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage. In this way, it can be accurately determined whether the verification is successful in the RTL simulation stage.

[0052] In order to accurately determine whether the verification is successful in the RTL+UPF simulation stage, Figure 3 As shown, Figure 3 A flowchart of the low power verification method provided in the third embodiment of the present application. In the embodiment of the present application, the actual voltage value of the circuit pin of each circuit unit in the UPF model can be obtained, and the actual voltage value of each circuit pin can be compared with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage. Figure 3 The illustrated embodiment may include the following steps:

[0053] Step 301 : determining a register transfer level (RTL) model of a system-on-chip and a control logic test case in a low power consumption mode.

[0054] Step 302 , according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage.

[0055] Step 303, for each power domain, control the input value of the register in the UPF model according to the test case corresponding to the power domain, so as to obtain the actual voltage value of the circuit pin of each circuit unit in the UPF model.

[0056] In order to make the UPF description information correspond to the RTL model, in an embodiment of the present application, the UPF model is provided with a reinitialization logic to adjust the numerical value of each circuit unit in the UPF model to a preset initial value after the reinitialization logic is triggered. The setting method of the reinitialization logic may include at least one of the following methods: adding the reinitialization logic to the UPF model, nesting the outer logic outside the UPF model, wherein the outer logic includes the reinitialization logic.

[0057] In an embodiment of the present application, for each power domain in low power mode, the input value of the register in the UPF model can be controlled according to the test case corresponding to the power domain to perform simulation. During the simulation process, the circuit pins of each circuit unit in the UPF model are called to obtain the actual voltage value of the circuit pins of each circuit unit in the UPF model.

[0058] Step 304 , compare the actual voltage value of each circuit pin with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage.

[0059] Furthermore, if the actual voltage value of each circuit pin is within the theoretical voltage range of each circuit pin, it can be determined that the verification is successful in the RTL+UPF simulation stage; if the actual voltage value of each circuit pin is not within the theoretical voltage range of each circuit pin, it can be determined that the verification fails in the RTL+UPF simulation stage and the simulation is terminated.

[0060] Step 305, when the verification is successful in the RTL+UPF simulation stage, a PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0061] In the embodiment of the present application, steps 301-302 and step 305 can be implemented in any manner in the embodiments of the present application, and the present application does not impose any specific limitation.

[0062] In summary, by controlling the input values ​​of the registers in the UPF model according to the test cases corresponding to each power domain, the actual voltage values ​​of the circuit pins of each circuit unit in the UPF model can be obtained; the actual voltage values ​​of each circuit pin are compared with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage. Therefore, it can be accurately determined whether the verification is successful in the RTL+UPF simulation stage.

[0063] The low-power verification method of the embodiment of the present application, by determining the register transfer level RTL model of the system-level chip and the control logic test case in the low-power mode; according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; when the RTL simulation stage is successfully verified, the unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the RTL+UPF simulation stage is successfully verified, the PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage. The method can verify RTL alone, solve the low-power verification blind spot, and reduce the complexity of debugging RTL.

[0064] Figure 4 This is a schematic diagram of the structure of the low-power verification device provided in Example 4 of the present application.

[0065] like Figure 4 As shown, the low power consumption verification device 400 includes: a determination module 410 , a first simulation module 420 , a second simulation module 430 and a third simulation module 440 .

[0066] Among them, the determination module 410 is used to determine the register transfer level RTL model of the system-level chip and the control logic test case in the low power consumption mode; the first simulation module 420 is used to perform simulation verification on the system-level chip in the RTL simulation stage according to the control logic test case and the RTL model to determine whether the verification is successful in the RTL simulation stage; the second simulation module 430 is used to generate a unified power format UPF model of the system-level chip according to the RTL model when the verification is successful in the RTL simulation stage, and simulate the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; the third simulation module 440 is used to generate a PG netlist of the system-level chip according to the UPF model when the verification is successful in the RTL+UPF simulation stage, and simulate the system-level chip in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage.

[0067] As a possible implementation method of an embodiment of the present application, the control logic test case includes: a test case corresponding to each power domain in low power consumption mode; the first simulation module 420 is specifically used to: for each power domain, control the input value of the register in the RTL model according to the test case corresponding to the power domain to obtain the actual output value of each circuit unit in the RTL model; compare the actual output value of each circuit unit with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage.

[0068] As a possible implementation method of an embodiment of the present application, the first simulation module 420 is also used to: for each power domain, control the input value of the register in the RTL model according to the test case corresponding to the power domain to perform a simulation process; during the simulation process, call each circuit unit in the RTL model to obtain the actual output value of each circuit unit during the simulation process.

[0069] As a possible implementation of an embodiment of the present application, each circuit unit in the RTL model includes at least one of the following units: a power domain switch, a gated clock, a reset unit, an isolation and logic circuit signal switch.

[0070] As a possible implementation method of an embodiment of the present application, the UPF model is provided with a reinitialization logic to adjust the values ​​of each circuit unit in the UPF model to a preset initial value after the reinitialization logic is triggered.

[0071] As a possible implementation method of an embodiment of the present application, the setting method of the reinitialization logic includes at least one of the following methods: adding the reinitialization logic to the UPF model; nesting the outer logic outside the UPF model, wherein the outer logic includes the reinitialization logic.

[0072] As a possible implementation method of an embodiment of the present application, the second simulation module 430 is specifically used to: for each power domain, control the input value of the register in the UPF model according to the test case corresponding to the power domain, so as to obtain the actual voltage value of the circuit pins of each circuit unit in the UPF model; compare the actual voltage value of each circuit pin with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage.

[0073] As a possible implementation method of an embodiment of the present application, a PG netlist is a netlist that is not provided with a standard delay format file and is used to perform netlist function simulation on a system-level chip.

[0074] The low-power verification device of the embodiment of the present application, by determining the register transfer level RTL model of the system-level chip and the control logic test case in the low-power mode; according to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; when the verification is successful in the RTL simulation stage, the unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; when the verification is successful in the RTL+UPF simulation stage, the PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage. This method can verify RTL alone, solve the low-power verification blind spot, and reduce the complexity of debugging RTL.

[0075] In order to implement the above embodiments, the present application also proposes an electronic device, such as Figure 5 As shown, Figure 5 The invention is a block diagram of an electronic device for a low power consumption verification method according to an exemplary embodiment.

[0076] like Figure 5 As shown, the electronic device 500 includes:

[0077] The memory 510 and the processor 520, a bus 530 connecting different components (including the memory 510 and the processor 520), the memory 510 stores a computer program, and when the processor 520 executes the program, the low-power verification method described in the embodiment of the present disclosure is implemented.

[0078] Bus 530 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnect (PCI) bus.

[0079] The electronic device 500 typically includes a variety of electronic device readable media. These media can be any available media that can be accessed by the electronic device 500, including volatile and non-volatile media, removable and non-removable media.

[0080] The memory 510 may also include computer system readable media in the form of volatile memory, such as random access memory (RAM) 540 and / or cache memory 550. The electronic device 500 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 560 may be used to read and write non-removable, non-volatile magnetic media ( Figure 5 not shown, usually called a "hard drive"). Although Figure 5 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 530 via one or more data medium interfaces. The memory 510 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0081] A program / utility 580 having a set (at least one) of program modules 570 may be stored, for example, in the memory 510, such program modules 570 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 570 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0082] The electronic device 500 may also communicate with one or more external devices 590 (e.g., keyboard, pointing device, display 591, etc.), one or more devices that enable a user to interact with the electronic device 500, and / or any device that enables the electronic device 500 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 592. Furthermore, the electronic device 500 may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 593. Figure 5 As shown, the network adapter 1193 communicates with other modules of the electronic device 500 via the bus 530. It should be understood that although Figure 5 Not shown, other hardware and / or software modules may be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0083] The processor 520 executes various functional applications and data processing by running the programs stored in the memory 510 .

[0084] It should be noted that the implementation process and technical principles of the electronic device of this embodiment refer to the aforementioned explanation of the low power consumption verification method of the embodiment of the present disclosure, and will not be repeated here.

[0085] In order to implement the above embodiment, the present application also proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute Figures 1 to 3 The low power consumption verification method described in the embodiment.

[0086] In order to implement the above embodiment, the present disclosure also provides a computer program product. When the instruction processor in the computer program product executes, Figures 1 to 3 The low power consumption verification method described in the embodiment.

[0087] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0088] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0089] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0090] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0091] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0092] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0094] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A low power consumption verification method, characterized in that: include: Determine the register transfer level RTL model of the system-level chip and the control logic test cases in low power mode; According to the control logic test case and the RTL model, the system-level chip is simulated and verified in the RTL simulation stage to determine whether the verification is successful in the RTL simulation stage; When the verification succeeds in the RTL simulation stage, a unified power format UPF model of the system-level chip is generated according to the RTL model, and the system-level chip is simulated in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification succeeds in the RTL+UPF simulation stage; When the verification succeeds in the RTL+UPF simulation stage, a PG netlist of the system-level chip is generated according to the UPF model, and the system-level chip is simulated in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification succeeds in the PG netlist simulation stage; The generating of a unified power format UPF model of the system-level chip according to the RTL model, and simulating the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model, includes: For each power domain, control the input value of the register in the UPF model according to the test case corresponding to the power domain, so as to obtain the actual voltage value of the circuit pin of each circuit unit in the UPF model; The actual voltage value of each circuit pin is compared with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage.

2. The method according to claim 1, characterized in that: The control logic test cases include: test cases corresponding to each power domain in low power consumption mode; The performing simulation verification of the system-level chip at the RTL simulation stage according to the control logic test case and the RTL model includes: For each power domain, controlling the input value of the register in the RTL model according to the test case corresponding to the power domain, so as to obtain the actual output value of each circuit unit in the RTL model; The actual output value of each circuit unit is compared with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage.

3. The method according to claim 2, characterized in that The step of controlling the input value of the register in the RTL model according to the test case corresponding to each power domain to obtain the actual output value of each circuit unit in the RTL model includes: For each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to perform a simulation process; During the simulation process, each circuit unit in the RTL model is called to obtain the actual output value of each circuit unit during the simulation process.

4. The method according to claim 2, characterized in that: Each circuit unit in the RTL model includes at least one of the following units: a power domain switch, a gated clock, a reset unit, an isolation and logic circuit signal switch.

5. The method according to claim 1, characterized in that The UPF model is provided with a reinitialization logic to adjust the values ​​of each circuit unit in the UPF model to a preset initial value after the reinitialization logic is triggered.

6. The method according to claim 5, characterized in that The re-initialization logic is configured in at least one of the following ways: Adding the reinitialization logic to the UPF model; An outer logic is nested outside the UPF model, wherein the outer logic includes the reinitialization logic.

7. The method according to claim 1, characterized in that The PG netlist is a netlist that is not provided with a standard delay format file and is used to perform netlist function simulation on the system-level chip.

8. A low power consumption verification device, characterized in that: include: A determination module, used to determine a register transfer level RTL model of a system-level chip and a control logic test case in a low power mode; A first simulation module, used to perform simulation verification of the system-level chip in the RTL simulation stage according to the control logic test case and the RTL model, so as to determine whether the verification is successful in the RTL simulation stage; A second simulation module is used to generate a unified power format UPF model of the system-level chip according to the RTL model when the verification is successful in the RTL simulation stage, and simulate the system-level chip in the RTL+UPF simulation stage according to the control logic test case and the UPF model to determine whether the verification is successful in the RTL+UPF simulation stage; The third simulation module is used to generate a PG netlist of the system-level chip according to the UPF model when the verification is successful in the RTL+UPF simulation stage, and simulate the system-level chip in the PG netlist simulation stage according to the control logic test case and the PG netlist to determine whether the verification is successful in the PG netlist simulation stage; The second simulation module is specifically used for: For each power domain, control the input value of the register in the UPF model according to the test case corresponding to the power domain, so as to obtain the actual voltage value of the circuit pin of each circuit unit in the UPF model; The actual voltage value of each circuit pin is compared with the theoretical voltage range of each circuit pin to determine whether the verification is successful in the RTL+UPF simulation stage.

9. The device according to claim 8, characterized in that The control logic test case includes: a test case corresponding to each power domain in the low power consumption mode; the first simulation module is specifically used for: For each power domain, controlling the input value of the register in the RTL model according to the test case corresponding to the power domain, so as to obtain the actual output value of each circuit unit in the RTL model; The actual output value of each circuit unit is compared with the theoretical output range of each circuit unit under the input value to determine whether the verification is successful in the RTL simulation stage.

10. The device according to claim 9, characterized in that The first simulation module is further used for: For each power domain, the input value of the register in the RTL model is controlled according to the test case corresponding to the power domain to perform a simulation process; During the simulation process, each circuit unit in the RTL model is called to obtain the actual output value of each circuit unit during the simulation process.

11. The device according to claim 9, characterized in that Each circuit unit in the RTL model includes at least one of the following units: a power domain switch, a gated clock, a reset unit, an isolation and logic circuit signal switch.

12. The device according to claim 8, characterized in that The UPF model is provided with a reinitialization logic to adjust the values ​​of each circuit unit in the UPF model to a preset initial value after the reinitialization logic is triggered.

13. The device according to claim 12, characterized in that The re-initialization logic is configured in at least one of the following ways: Adding the reinitialization logic to the UPF model; An outer logic is nested outside the UPF model, wherein the outer logic includes the reinitialization logic.

14. The device according to claim 8, characterized in that: The PG netlist is a netlist that is not provided with a standard delay format file and is used to perform netlist function simulation on the system-level chip.

15. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

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