semiconductor packaging

Abstract

A semiconductor package is disclosed. The semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first underfill layer filling a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity therein and a first vent extending from the top surface of the package substrate and in fluid communication with the cavity. The first underfill layer extends along the first vent to fill the cavity.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package and / or a method of manufacturing the same, and more particularly, to a stacked semiconductor package and / or a method of manufacturing the same. Background Art

[0002] With the development of the electronics industry, the demand for high performance, high speed and compact size of electronic products has been increasing. In order to cater to this trend, packaging technology for mounting multiple semiconductor chips in a single package has been developed recently.

[0003] In the recent electronic product market, the demand for portable devices has been increasing. As a result, it has become desirable to reduce the size and weight of electronic components mounted on portable devices. In order to achieve the reduction in size and weight of electronic components, it is desirable not only to reduce the size of the mounted components but also to integrate many individual devices on a single package. Summary of the Invention

[0004] Some example embodiments of the inventive concepts provide a compact-sized semiconductor package and / or a method of manufacturing the semiconductor package.

[0005] Some example embodiments of the inventive concepts provide a semiconductor package having improved structural stability and / or a method of manufacturing the semiconductor package.

[0006] Some example embodiments of the inventive concepts provide a method of manufacturing a semiconductor package that reduces the occurrence of defects.

[0007] The features and effects of the inventive concept are not limited to those mentioned above, and other features and effects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] According to some example embodiments of the inventive concepts, a semiconductor package may include: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; and a first underfill layer filling a space between the package substrate and the first semiconductor chip. The package substrate may include a first vent and a cavity within the package. The first vent may extend from the top surface of the package substrate to the cavity and may be in fluid communication with the cavity. The first underfill may extend along the first vent to fill the cavity.

[0009] According to some example embodiments of the inventive concepts, a semiconductor package may include: a package substrate including a cavity therein; a first semiconductor chip mounted on the package substrate via a first chip terminal; a second semiconductor chip mounted on a top surface of the first semiconductor chip via a second chip terminal; a first underfill layer filling the cavity and a space between the package substrate and the first semiconductor chip; a second underfill layer filling the space between the first and second semiconductor chips; and a mold layer on the package substrate. The mold layer may surround the first and second semiconductor chips. The width of the first underfill layer between the package substrate and the first semiconductor chip may be smaller than the width of the second underfill layer between the first and second semiconductor chips.

[0010] According to some example embodiments of the inventive concepts, a method for manufacturing a semiconductor package may include: providing a package substrate including a cavity therein and a first vent extending from a top surface of the package substrate and in fluid communication with the cavity; forming a first underfill layer on the package substrate; providing a first semiconductor chip on the first underfill layer to mount the first semiconductor chip on the package substrate; forming a second underfill layer on the first semiconductor chip; and providing a second semiconductor chip on the second underfill layer to mount the second semiconductor chip on the first semiconductor chip. When mounting the first semiconductor chip, the first underfill layer may be introduced into the cavity through the first vent. When mounting the second semiconductor chip, the second underfill layer may protrude from a side of the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0012] Figure 2 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0013] Figure 3 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0014] Figure 4 and Figure 5 Illustrated are plan views showing semiconductor packages according to some example embodiments of the inventive concepts.

[0015] Figure 6 and Figure 7 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0016] Figure 8Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0017] Figures 9 to 18 sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0018] Figures 19 to 22 sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated. DETAILED DESCRIPTION

[0019] Hereinafter, a semiconductor package according to the inventive concept will now be described with reference to the accompanying drawings.

[0020] Figure 1 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated. Figure 2 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0021] Reference Figure 1 , a package substrate 100 may be provided. The package substrate 100 may include a core portion 110 , an upper buildup portion 120 disposed on a top surface of the core portion 110 , and a lower buildup portion 130 disposed on a bottom surface of the core portion 110 .

[0022] The core 110 may extend in one direction. When viewed in a plane, the core 110 may include a core pattern. In some example embodiments of the inventive concept, the core 110 is shown as having a core pattern as an example, but the inventive concept is not limited thereto. According to some example embodiments, the core 110 may include two or more core patterns. For example, the package substrate 100 may include a plurality of core patterns spaced apart from each other when viewed in a plane. The core 110 may include a dielectric material. For example, the core 110 may include one of fiberglass, a ceramic plate, an epoxy resin, and a resin. For another example, the core 110 may include one selected from stainless steel, aluminum (Al), nickel (Ni), magnesium (Mg), zinc (Zn), tantalum (Ta), and any combination thereof.

[0023] The core 110 may have therein vertical connection terminals 112 vertically penetrating the core 110. The vertical connection terminals 112 may electrically connect the upper stacking part 120 to the lower stacking part 130.

[0024] The upper and lower accumulation parts 120 and 130 may be disposed on the top and bottom surfaces of the core 110 , respectively.

[0025] The upper buildup portion 120 may cover the top surface of the core portion 110. The upper buildup portion 120 may include a plurality of upper dielectric layers 122 and a plurality of upper wirings 124 alternately stacked on the top surface of the core portion 110. The uppermost one of the upper dielectric layers 122 may expose upper wirings among the upper wirings 124, and the exposed upper wirings 124 may correspond to first substrate pads 124a through which semiconductor chips 200 and 300, to be discussed below, are mounted on the package substrate 100. For example, the uppermost one of the upper dielectric layers 122 may include a recess, and the first substrate pads 124a may be exposed to the recess.

[0026] The lower buildup part 130 may cover the bottom surface of the core part 110. The lower buildup part 130 may include a plurality of lower dielectric layers 132 and a plurality of lower wirings 134 alternately stacked on the bottom surface of the core part 110.

[0027] The upper dielectric layer 122 and the lower dielectric layer 132 may include prepreg, Ajinomoto built-up film (ABF), FR-4, or bismaleimide triazine (BT). The upper wiring 124 and the lower wiring 134 may include circuit patterns. The lower wiring 134 may be electrically connected to the upper wiring 124 via the vertical connection terminals 112. The upper wiring 124 and the lower wiring 134 may include one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and any combination thereof.

[0028] The package substrate 100 may have a cavity CV and a first ventilation hole VH1 .

[0029] The cavity CV may be a recess where the core 110 is partially removed from the package substrate 100. The cavity CV may be located inside the core 110. For example, the cavity CV may be defined as representing an area where the core 110 is partially removed and surrounded by the core 110. When viewed in a plane, the cavity CV may be located at the center of the package substrate 100. For example, the cavity CV may be provided between the vertical connection terminals 112.

[0030] According to some example embodiments, the cavity CV may be a region in which one of the upper and lower accumulation portions 120 and 130 is partially removed. Figure 2 As shown, the core 110 may have a cavity CV' formed thereunder by partially removing the lower buildup portion 130. For example, the cavity CV' may be defined as representing a region in which the lower buildup portion 130 is partially removed and which is surrounded by the core 110 and the lower buildup portion 130. Figure 2 Unlike what is shown, the cavity CV may be a region in which the upper accumulation portion 120 is partially removed.

[0031] According to some example embodiments, cavity CV may be a region in which core 110, upper buildup portion 120, and lower buildup portion 130 are partially removed. For example, cavity CV may be defined as a region in which each of core 110, upper buildup portion 120, and lower buildup portion 130 is partially removed and surrounded by core 110, upper buildup portion 120, and lower buildup portion 130.

[0032] Reference Figure 1 , the first ventilation hole VH1 can be formed on the upper part of the packaging substrate 100. When viewed in a plane, the first ventilation hole VH1 can be set on the central part of the packaging substrate 100. For example, the first ventilation hole VH1 can be located between the recesses formed in the upper dielectric layer 122 of the upper stacking portion 120. The first ventilation hole VH1 can be placed above the cavity CV. The first ventilation hole VH1 can extend from the cavity CV toward the top surface of the packaging substrate 100. For example, the first ventilation hole VH1 can be formed to penetrate a portion of the core 110 and the upper stacking portion 120. The cavity CV can be spatially connected to the outside (e.g., fluidically connected) through the first ventilation hole VH1. The first ventilation hole VH1 can have a width D1 of about 2 μm to about 10 μm. The first ventilation hole VH1 can have an aspect ratio of about 0.1 to about 2.0. The aspect ratio and width D1 of the first ventilation hole VH1 can depend on the material of the molding layer 600 to be discussed below. Figure 1 An example in which one first ventilation hole VH1 is included is depicted, but the inventive concept is not limited thereto.

[0033] The first ventilation hole VH1 may be provided in plural, as shown below Figure 3 shown. Figure 3 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated. Figure 4 and Figure 5 FIG2 shows a plan view of a semiconductor package according to some example embodiments of the inventive concept. Figure 3 As shown, each of the plurality of first ventilation holes VH1 may penetrate a portion of the core 110 and the upper stacking portion 120, thereby being spatially connected to the cavity CV. The first ventilation holes VH1 may be arranged to be spaced apart from each other when viewed in a plane, and the first ventilation holes VH1 may be arranged at regular intervals. The first ventilation holes VH1 may be arranged along a first direction X and a second direction Y parallel to the top surface of the package substrate 100. In this case, the first ventilation holes VH1 may constitute a plurality of rows and a plurality of columns when viewed in a plane. For example, as Figure 4 As shown, the first direction X and the second direction Y may be orthogonal to each other, and the first ventilation holes VH1 may be arranged in a quadrilateral lattice shape. Figure 5As shown, the first direction X and the second direction Y may intersect each other at an angle of about 60°, and the first ventilation holes VH1 may be arranged in a hexagonal lattice shape. However, the inventive concept is not limited thereto, and the first ventilation holes VH1 may be arranged in various shapes.

[0034] Refer again Figure 1 , the external terminal 140 may be provided below the lower buildup portion 130. The external terminal 140 may be provided on the bottom surface of the lower buildup portion 130. For example, the external terminal 140 may be placed on the second substrate pad 134a provided on the bottom surface of the lower buildup portion 130. In this case, the second substrate pad 134a may be a lower wiring 134 exposed from the lower dielectric layer 132 of the lower buildup portion 130, or a separate pad provided on the lower dielectric layer 132 of the lower buildup portion 130 and connected to the lower wiring 134. The external terminal 140 may include a solder ball or a solder bump.

[0035] The first semiconductor chip 200 can be mounted on the package substrate 100. The first semiconductor chip 200 can be a memory chip or a logic chip. The first semiconductor chip 200 may include a semiconductor material such as silicon (Si). The first semiconductor chip 200 may have a front surface and a rear surface. In this specification, the word "front surface" may be defined as representing the active surface of an integrated device in a semiconductor chip or the surface on which a pad of a semiconductor chip is formed, and the word "rear surface" may be defined as representing the surface opposite to the front surface. The first semiconductor chip 200 may include a first base layer 210, a first chip pad 220 arranged on the front surface of the first semiconductor chip 200, a first lower passivation layer 230 covering the front surface of the first semiconductor chip 200, a second chip pad 240 arranged on the rear surface of the first semiconductor chip 200, and a first upper passivation layer 250 covering the rear surface of the first semiconductor chip 200.

[0036] The first chip pad 220 can be electrically connected to an integrated device or integrated circuit in the first semiconductor chip 200. According to some example embodiments, a redistribution line can be provided between the first chip pad 220 and the integrated device in the first semiconductor chip 200. The second chip pad 240 can be electrically connected to the first chip pad 220 through a first through electrode 260 that vertically penetrates the first base layer 210. Alternatively, the second chip pad 240 can be connected to a separate wiring electrically floating from the integrated device in the first semiconductor chip 200 through the first through electrode 260. The first chip pad 220 and the second chip pad 240 may include a conductive material such as a metal. For example, the first chip pad 220 and the second chip pad 240 may include copper (Cu).

[0037] The first chip pad 220 may be surrounded by a first lower passivation layer 230 on the front surface of the first semiconductor chip 200. For example, the first lower passivation layer 230 may cover the bottom surface of the first base layer 210 and may contact the side surface of the first chip pad 220. The first lower passivation layer 230 may have a lowermost end at the same level as the bottom surface of the first chip pad 220. The second chip pad 240 may be surrounded by a first upper passivation layer 250 on the rear surface of the first semiconductor chip 200. For example, the first upper passivation layer 250 may cover the top surface of the first base layer 210 and may contact the side surface of the second chip pad 240. The first upper passivation layer 250 may have an uppermost end at the same level as the top surface of the second chip pad 240. The first lower passivation layer 230 and the first upper passivation layer 250 may include oxide or nitride. For example, the first lower passivation layer 230 and the first upper passivation layer 250 may include silicon oxide (SiO), silicon nitride (SiN), or silicon carbon nitride (SiCN).

[0038] The first semiconductor chip 200 may vertically overlap the cavity CV. For example, the cavity CV and the first ventilation hole VH1 may be located below the central portion of the first semiconductor chip 200. The first semiconductor chip 200 may have a width greater than that of the cavity CV. For example, the width of the cavity CV may be approximately 1 / 5 to approximately 1 / 2 of the width of the first semiconductor chip 200.

[0039] The first semiconductor chip 200 may be mounted on the package substrate 100. The front surface of the first semiconductor chip 200 may be directed toward the package substrate 100, and the first semiconductor chip 200 may be mounted on the package substrate 100 in a flip-chip manner. For example, the first connection terminal 202 may be provided on the first chip pad 220 of the first semiconductor chip 200, and the first connection terminal 202 may be coupled to the first substrate pad 124a of the package substrate 100. The first connection terminal 202 may include a solder ball or a solder bump.

[0040] The first bottom fill layer 400 can be inserted between the package substrate 100 and the first semiconductor chip 200. The first bottom fill layer 400 can fill the space between the package substrate 100 and the first semiconductor chip 200 and can surround the first connection terminal 202. The first bottom fill layer 400 can be formed by a molding member or by a flux containing a resin, an activator and a solvent. The solvent may include a glycol ether ester compound, a glycol ether compound, an ester compound, a ketone compound or a cyclic ester compound. Alternatively, the first bottom fill layer 400 may include a non-conductive film (NCF) such as an Ajinomoto built-up film (ABF). The first bottom fill layer 400 can protrude outward from the side surface of the first semiconductor chip 200. For example, the first bottom fill layer 400 may have a width greater than the width of the first semiconductor chip 200.

[0041] The first underfill layer 400 may fill the cavity CV of the package substrate 100. For example, the first underfill layer 400 may have a first extension portion 402 that extends along the first ventilation hole VH1 and protrudes into the cavity CV from the space between the package substrate 100 and the first semiconductor chip 200. The first extension portion 402 of the first underfill layer 400 may fill both the first ventilation hole VH1 and the cavity CV.

[0042] The second semiconductor chips 300 may be stacked on the first semiconductor chip 200. The second semiconductor chip 300 may be a memory chip. The second semiconductor chip 300 may be substantially the same as or similar to the first semiconductor chip 200. Alternatively, the second semiconductor chip 300 may be of a different type than the first semiconductor chip 200. Each second semiconductor chip 300 may include a second base layer 310, a third chip pad 320 disposed on the front surface of the second semiconductor chip 300, a second lower passivation layer 330 covering the front surface of the second semiconductor chip 300, a fourth chip pad 340 disposed on the rear surface of the second semiconductor chip 300, a second upper passivation layer 350 covering the rear surface of the second semiconductor chip 300, and a second through electrode 360 ​​connecting the third chip pad 320 to the fourth chip pad 340.

[0043] The lowermost of the second semiconductor chips 300 may be mounted on the first semiconductor chip 200. The front surface of the lowermost second semiconductor chip 300 may point toward the first semiconductor chip 200, and the lowermost second semiconductor chip 300 may be mounted on the first semiconductor chip 200 in a flip-chip manner. For example, a second connection terminal 302 may be provided on the third chip pad 320 of the lowermost second semiconductor chip 300, and the second connection terminal 302 may be coupled to the second chip pad 240 of the first semiconductor chip 200. The second connection terminal 302 may include a solder ball or a solder bump. The distance between the first semiconductor chip 200 and the lowermost second semiconductor chip 300 may be greater than the distance between the first semiconductor chip 200 and the package substrate 100. According to some example embodiments of the inventive concept, since a small distance is provided between the first semiconductor chip 200 and the package substrate 100, a semiconductor package having a small height and a compact size may be provided.

[0044] In addition, each of the second semiconductor chips 300 may be mounted on another second semiconductor chip 300 below it. For example, each of the second semiconductor chips 300 may be mounted on the fourth chip pad 340 of the second semiconductor chip 300 below it through the second connection terminal 302. The distance between the second semiconductor chips 300 may be substantially the same as the distance between the first semiconductor chip 200 and the lowermost second semiconductor chip 300, and greater than the distance between the package substrate 100 and the first semiconductor chip 200.

[0045] According to some example embodiments, the uppermost one of the second semiconductor chips 300 may not include the fourth chip pad 340, the second upper passivation layer 350, or the second through electrode 360. Alternatively, unlike what is shown, the uppermost second semiconductor chip 300 may be the same as the other second semiconductor chips 300 and may include the fourth chip pad 340, the second upper passivation layer 350, and the second through electrode 360.

[0046] The second underfill layer 500 may be interposed between the second semiconductor chips 300 and between the first semiconductor chip 200 and the lowermost second semiconductor chip 300. The second underfill layer 500 may fill the space between the first semiconductor chip 200 and the lowermost second semiconductor chip 300 and the space between the second semiconductor chips 300, and may surround the second connection terminal 302. The second underfill layer 500 may be formed by a molding member or by a flux containing a resin, an activator, and a solvent. Alternatively, the second underfill layer 500 may include a non-conductive film (NCF) such as an Ajinomoto built-up film (ABF). The second underfill layer 500 may protrude outward from the side surface of the second semiconductor chip 300. For example, the second underfill layer 500 may have a width greater than that of the second semiconductor chip 300. In addition, the width of the second underfill layer 500 may be greater than that of the first underfill layer 400. Alternatively, the width of the second underfill layer 500 may be equal to the width of the first underfill layer 400.

[0047] A molding layer 600 may be provided on the packaging substrate 100. The molding layer 600 may cover the top surface of the packaging substrate 100. The molding layer 600 may surround the first semiconductor chip 200 and the second semiconductor chip 300. For example, the molding layer 600 may cover the side surfaces of the first semiconductor chip 200 and the side surfaces of the second semiconductor chip 300. In this case, the distance between the outer surface of the molding layer 600 and the distal end of the first underfill layer 400 may be greater than the distance between the outer surface of the molding layer 600 and the distal end of the second underfill layer 500. The distance between the outer surface of the molding layer 600 and the distal end of the first underfill layer 400 may be in a range from about 100 μm to about 500 μm. The molding layer 600 may protect the first semiconductor chip 200 and the second semiconductor chip 300. The molding layer 600 may include a dielectric material. For example, the molding layer 600 may include an epoxy molding compound (EMC). The mold layer 600 may be formed to cover the first and second semiconductor chips 200 and 300. For example, the mold layer 600 may cover the rear surface of the uppermost second semiconductor chip 300. Alternatively, unlike shown, the mold layer 600 may expose the rear surface of the uppermost second semiconductor chip 300.

[0048] According to some example embodiments of the inventive concept, a small width may be provided to the first underfill layer 400, and a large contact area may be provided between the mold layer 600 and the package substrate 100. Therefore, the mold layer 600 and the package substrate 100 may have strong adhesion therebetween, and the semiconductor package may improve structural stability.

[0049] Figure 6 and Figure 7sectional views showing semiconductor packages according to some example embodiments of the inventive concept are shown. For ease of explanation, the following description will focus on Figures 1 to 5 The difference in description.

[0050] Reference Figure 6 , the encapsulation substrate 100 may further include a second ventilation hole VH2. The second ventilation hole VH2 may be formed in the lower portion of the encapsulation substrate 100. When viewed in a plane, the second ventilation hole VH2 may be provided on the central portion of the encapsulation substrate 100. For example, the second ventilation hole VH2 may be placed below the cavity CV. The second ventilation hole VH2 may extend from the cavity CV to the bottom surface of the encapsulation substrate 100. For example, the second ventilation hole VH2 may be formed to penetrate a portion of the core 110 and the lower stacking portion 130. The cavity CV may be spatially connected to the outside through the second ventilation hole VH2. The second ventilation hole VH2 may have a width D2 of approximately 2 μm to approximately 10 μm. The second ventilation hole VH2 may have an aspect ratio of approximately 0.1 or higher. The aspect ratio and width D2 of the second ventilation hole VH2 may depend on the material of the molding layer 600. Figure 6 It is depicted that one second ventilation hole VH2 is provided, but the inventive concept is not limited thereto.

[0051] For example, Figure 7 As shown, the second ventilation holes VH2 can be provided in plurality. The second ventilation holes VH2 can all penetrate a portion of the core 110 and the lower stacking portion 130, thereby being spatially connected to the cavity CV. The second ventilation holes VH2 can be arranged to be spaced apart from each other when viewed in a plane, and the second ventilation holes VH2 can be arranged at regular intervals. The second ventilation holes VH2 can be arranged along a first direction and a second direction parallel to the bottom surface of the package substrate 100. In this case, when viewed in a plane, the second ventilation holes VH2 can constitute a plurality of rows and a plurality of columns. For example, the second ventilation holes VH2 can be arranged in a quadrilateral lattice shape. For another example, the second ventilation holes VH2 can be arranged in a hexagonal lattice shape. However, the inventive concept is not limited thereto, and the second ventilation holes VH2 can be arranged in various shapes.

[0052] Reference Figure 6 and Figure 7 , the first underfill layer 400 may extend downward from the package substrate 100. For example, the first underfill layer 400 may have a second extension 404 that extends along the second ventilation hole VH2 and protrudes from the first extension 402 in the cavity CV onto the bottom surface of the package substrate 100. The second extension 404 of the first underfill layer 400 may partially cover the bottom surface of the package substrate 100. In this case, the distance between the bottom surface of the package substrate 100 and the lowermost end of the second extension 404 may be less than the thickness of the external terminal 140.

[0053] Figure 8 Cross-sectional views showing semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0054] Reference Figure 8 , the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked on the package substrate 100. The package substrate 100 and the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked on the package substrate 100. Figure 1 The same or similar ones discussed.

[0055] The first underfill layer 400 may be provided between the package substrate 100 and the first semiconductor chip 200, and the second underfill layer 500 may be provided between the second semiconductor chips 300 and between the first semiconductor chip 200 and the second semiconductor chip 300. The first underfill layer 400 and the second underfill layer 500 may be provided with reference to Figure 1 For example, the first underfill layer 400 may have a first extension 402 that fills the first ventilation hole VH1 and the first cavity CV1 .

[0056] The third semiconductor chip 700 may be provided on the package substrate 100. The third semiconductor chip 700 and the first semiconductor chip 200 may be spaced apart from each other in a direction parallel to the top surface of the package substrate 100. For example, the spacing distance between the first semiconductor chip 200 and the third semiconductor chip 700 may be in a range from about 50 μm to about 100 μm. The first semiconductor chip 200 and the third semiconductor chip 700 may be electrically connected to each other through the circuit line 126 in the upper stacking portion 120 of the package substrate 100. The first semiconductor chip 200 and the second semiconductor chip 300 may be memory chips such as DRAM, SRAM, MRAM, or flash memory, and the third semiconductor chip 700 may be a logic chip.

[0057] A third underfill layer 800 may be interposed between the package substrate 100 and the third semiconductor chip 700. The third underfill layer 800 may fill the space between the package substrate 100 and the third semiconductor chip 700. The third underfill layer 800 may protrude outward from the side surface of the third semiconductor chip 700. For example, the third underfill layer 800 may have a width greater than that of the third semiconductor chip 700. The third underfill layer 800 may fill the second cavity CV2 formed in the package substrate 100.

[0058] Figures 9 to 18 sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0059] Reference Figure 9, a first core layer 1010, a second core layer 1020 and a third core layer 1030 may be provided. The first core layer 1010, the second core layer 1020 and the third core layer 1030 may constitute a reference Figure 1 Components of the core portion 110 of the discussed package substrate 100. The first core layer 1010, the second core layer 1020, and the third core layer 1030 may each include a dielectric material.

[0060] A first hole H1 may be formed in the first core layer 1010. The first hole H1 may be formed on the corresponding package region PR. The first hole H1 may be formed to vertically penetrate the first core layer 1010. The package regions PR may be separated from each other by separation regions SR. In this specification, the package region PR may be defined as a zone on each of which a semiconductor package is formed, and the separation region SR may be defined as a zone along which a sawing process is performed to separate the formed semiconductor packages from each other.

[0061] Reference Figure 10 , the second core layer 1020 may be coupled to the top surface of the first core layer 1010, and the third core layer 1030 may be coupled to the bottom surface of the first core layer 1010. The first core layer 1010, the second core layer 1020, and the third core layer 1030 may constitute the core portion 110. The first hole H1 of the first core layer 1010 may be surrounded by the first core layer 1010, the second core layer 1020, and the third core layer 1030. The first hole H1 surrounded by the first core layer 1010, the second core layer 1020, and the third core layer 1030 may constitute a cavity CV.

[0062] Reference Figure 11 , vertical connection terminals 112 may be formed in the core 110. For example, the vertical connection terminals 112 may be formed by forming a hole penetrating the core 110 and then filling the hole with a conductive material. On the packaging region PR, the vertical connection terminals 112 may be formed spaced apart from the cavity CV.

[0063] The upper stacking portion 120 may be formed on the core portion 110. For example, a dielectric layer may be formed on the top surface of the core portion 110, and then the dielectric layer may be patterned to form an upper dielectric layer 122. Patterning of the upper dielectric layer 122 may expose the vertical connection terminals 112. A conductive layer may be formed on the upper dielectric layer 122, and then the conductive layer may be patterned to form an upper wiring 124. The formation of the upper dielectric layer 122 and the upper wiring 124 may be repeatedly performed. A plurality of upper dielectric layers 122 and a plurality of upper wirings 124 may constitute a reference Figure 1The upper buildup portion 120 discussed above may include a portion of an uppermost one of the upper wirings 124 buried in the upper dielectric layer 122 , and another portion of the uppermost one of the upper wirings 124 exposed to a recess formed in the uppermost one of the upper dielectric layers 122 .

[0064] The lower buildup portion 130 may be formed below the core portion 110. For example, a dielectric layer may be formed on the bottom surface of the core portion 110, and then the dielectric layer may be patterned to form a lower dielectric layer 132. A conductive layer may be formed on the lower dielectric layer 132, and then the conductive layer may be patterned to form a lower wiring 134. The formation of the lower dielectric layer 132 and the lower wiring 134 may be repeatedly performed. A plurality of lower dielectric layers 132 and a plurality of lower wirings 134 may constitute a reference Figure 1 The lower accumulation section 130 is discussed.

[0065] Reference Figure 12 , a first ventilation hole VH1 may be formed in the package substrate 100. The first ventilation hole VH1 may be formed by etching a portion of the core portion 110 and the upper stacking portion 120. The first ventilation hole VH1 may be formed to be spatially connected to the cavity CV. The formation of the first ventilation hole VH1 may include a drilling process such as laser drilling. The first ventilation hole VH1 may be spaced apart from the upper wiring 124.

[0066] According to some example embodiments, Figure 13 As shown, a second ventilation hole VH2 may be additionally formed in the package substrate 100. The second ventilation hole VH2 may be formed by etching a portion of the core portion 110 and the lower accumulation portion 130. The second ventilation hole VH2 may be formed to be spatially connected to the cavity CV. The formation of the second ventilation hole VH2 may be performed simultaneously with or separately from the formation of the first ventilation hole VH1. The formation of the second ventilation hole VH2 may include a drilling process. Figure 13 As shown, when the second ventilation hole VH2 is formed in the package substrate 100, the following can be manufactured: Figure 6 The following content will focus on the semiconductor packaging discussed in Figure 12 implementation method.

[0067] Reference Figure 14 , the package substrate 100 may be provided on a carrier substrate 900. The package substrate 100 may be attached to the carrier substrate 900. For example, as shown in the figure, the carrier substrate 900 may include an adhesive member 910 provided on a top surface thereof. For another example, the carrier substrate 900 may include an adhesive tape 910.

[0068] A first bottom filler member 410 may be provided on the packaging substrate 100. For example, the first bottom filler member 410 may be a non-conductive adhesive or a non-conductive film. When the first bottom filler member 410 is a non-conductive adhesive, the first bottom filler member 410 may be formed by a dispensing method of coating the packaging substrate 100 with a liquid non-conductive adhesive. When the first bottom filler member 410 is a non-conductive film, the first bottom filler member 410 may be formed by attaching the non-conductive film to the packaging substrate 100. The first bottom filler member 410 may be provided on the packaging region PR of the packaging substrate 100. For example, the first bottom filler member 410 may be positioned above the cavity CV while covering the first ventilation hole VH1. The first bottom filler member 410 may be spaced apart from the separation region SR.

[0069] Reference Figure 15 , thermocompression bonding may be performed to couple the first semiconductor chip 200 to the package substrate 100. The first semiconductor chip 200 may be electrically connected to the package substrate 100 through the first connection terminal 202. For example, the first connection terminal 202 may be coupled to the upper wiring 124 provided in the recess of the upper buildup portion 120. Thus, a small space may be provided between the package substrate 100 and the first semiconductor chip 200. When the first semiconductor chip 200 is pressed in a direction toward the package substrate 100, the first bottom filling member 410 may protrude outward from the side surface of the first semiconductor chip 200. In addition, as Figure 15 As indicated by the arrows, the first underfill member 410 may pass through the first ventilation hole VH1 to fill the cavity CV. The compressed first underfill member 410 may constitute the first underfill layer 400. As the first underfill members 410 are introduced into the cavity CV, each of the first underfill members 410 may protrude outward from the side surface of the first semiconductor chip 200 by a small distance. Therefore, none of the first underfill members 400 may protrude into the separation region SR, and the occurrence of defects in the subsequent sawing process may be reduced.

[0070] Reference Figure 16 A second underfill member 510 may be provided on the first semiconductor chip 200. For example, the second underfill member 510 may be a non-conductive adhesive or a non-conductive film. When the second underfill member 510 is a non-conductive adhesive, the second underfill member 510 may be formed by a dispensing method of coating the first semiconductor chip 200 with a liquid non-conductive adhesive. When the second underfill member 510 is a non-conductive film, the second underfill member 510 may be formed by attaching the non-conductive film to the first semiconductor chip 200.

[0071] Reference Figure 17, thermocompression bonding may be performed to couple the second semiconductor chip 300 to the first semiconductor chip 200. The second semiconductor chip 300 may be electrically connected to the first semiconductor chip 200 through the second connection terminal 302. For example, the second connection terminal 302 may be coupled to the second chip pad 240 of the first semiconductor chip 200. When the second semiconductor chip 300 is pressed in a direction toward the first semiconductor chip 200, as shown in FIG. Figure 17 As indicated by the arrows, the second underfill member 510 may protrude outward from the side surface of the second semiconductor chip 300. The compressed second underfill member 510 may constitute a second underfill layer 500. The protrusion distance of the second underfill layer 500 from the side surface of the second semiconductor chip 300 may be greater than the protrusion distance of the first underfill layer 400 from the side surface of the first semiconductor chip 200. The distance between the first semiconductor chip 200 and the second semiconductor chip 300 may be greater than the distance between the package substrate 100 and the first semiconductor chip 200.

[0072] Reference Figure 18 , other second semiconductor chips 300 can be stacked. The stacking process of the second semiconductor chips 300 can be the same as that of the reference Figure 16 and Figure 17 The process discussed is the same.

[0073] A mold layer 600 may be formed on the package substrate 100. For example, the package substrate 100 may be provided with a dielectric material surrounding the first and second semiconductor chips 200 and 300 on its top surface, and then the dielectric material may be cured to form the mold layer 600. The dielectric material may include a dielectric polymer or a thermosetting resin.

[0074] Afterwards, a singulation process such as a sawing process may be performed to form a semiconductor package. The sawing process may be performed on the separation region SR. Thus, the first semiconductor chips 200 may be separated from each other, and a plurality of semiconductor packages may be formed.

[0075] When the cavity CV is not formed in the package substrate 100, the first underfill layer 400 may be provided between the package substrate 100 and the first semiconductor chip 200 at a small interval and may each protrude a large distance outward from the side surface of the first semiconductor chip 200. For example, because the distance between the package substrate 100 and the first semiconductor chip 200 is smaller than the distance between the first semiconductor chip 200 and the second semiconductor chip 300, the protruding distance of the first underfill layer 400 may be greater than the protruding distance of the second underfill layer 500. In this case, the first underfill layer 400 may be formed adjacent to the separation region SR, and defects such as delamination of the mold layer 600 may occur in a subsequent sawing process.

[0076] According to some example embodiments of the inventive concepts, because the first underfill members 410 are introduced into the cavity CV, the first underfill layers 400 may each protrude a small distance outward from the side surface of the first semiconductor chip 200. As a result, none of the first underfill members 410 may protrude into the separation region SR, and the occurrence of defects may be reduced in a sawing process.

[0077] Reference Figure 1 , the carrier substrate 900 may be removed. For example, the carrier substrate 900 may be removed by applying shear stress or by chemically treating the adhesive member 910. Removal of the carrier substrate 900 may expose the bottom surface of the package substrate 100. External terminals 140 may be formed on the exposed bottom surface of the package substrate 100.

[0078] The above process can produce Figure 1 The semiconductor package shown.

[0079] Figures 19 to 22 sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0080] Reference Figure 19 , a core 110 may be provided. Vertical connection terminals 112 may be formed in the core 110. For example, the vertical connection terminals 112 may be formed by forming a hole penetrating the core 110 on the package region PR and then filling the hole with a conductive material.

[0081] The upper buildup portion 120 may be formed on the core portion 110. For example, a dielectric layer may be formed on the top surface of the core portion 110, and then the dielectric layer may be patterned to form an upper dielectric layer 122. A conductive layer may be formed on the upper dielectric layer 122, and then the conductive layer may be patterned to form an upper wiring 124. The formation of the upper dielectric layer 122 and the upper wiring 124 may be repeatedly performed. A plurality of upper dielectric layers 122 and a plurality of upper wirings 124 may constitute a reference Figure 1 The upper accumulation section 120 is discussed.

[0082] Reference Figure 20 , a dielectric layer may be formed on the bottom surface of the core 110, and then the dielectric layer may be patterned to form a lower dielectric layer 132. A conductive layer may be formed on the lower dielectric layer 132, and then the conductive layer may be patterned to form a lower wiring 134. The formation of the lower dielectric layer 132 and the lower wiring 134 may be repeatedly performed.

[0083] The second hole H2 may be formed in the lower dielectric layer 132. The second hole H2 may be formed on the corresponding package region PR. The second hole H2 may be formed to vertically penetrate the lower dielectric layer 132. The second hole H2 may be spaced apart from the lower wiring 134.

[0084] Reference Figure 21 , another lower dielectric layer 132 and another lower wiring 134 may be further formed on the bottom surface of the package substrate 100. The additional lower dielectric layer 132 may cover the second hole H2. Therefore, the second hole H2 may be surrounded by the lower dielectric layer 132. The second hole H2 surrounded by the lower dielectric layer 132 may constitute a cavity CV'.

[0085] Reference Figure 22 , a first ventilation hole VH1 may be formed in the package substrate 100. The first ventilation hole VH1 may be formed by etching a portion of the core portion 110 and the upper stacking portion 120. The first ventilation hole VH1 may be formed to be spatially connected to the cavity CV'. The formation of the first ventilation hole VH1 may include a drilling process such as laser drilling. The first ventilation hole VH1 may be spaced apart from the upper wiring 124.

[0086] Afterwards, you can execute the reference Figures 14 to 18 The process discussed is to manufacture Figure 2 semiconductor packaging.

[0087] In semiconductor packages according to some example embodiments of the present inventive concepts, a small distance can be provided between the first semiconductor chip and the package substrate, thereby providing advantages of reduced height and size for the semiconductor package. Furthermore, the underfill layer can be provided with a small width, thereby providing a large contact area between the mold layer and the package substrate. Consequently, the mold layer and the package substrate can have strong adhesion therebetween, and the semiconductor package can be improved in structural stability.

[0088] In a method of manufacturing a semiconductor package according to some example embodiments of the inventive concept, an underfill member may be introduced into a cavity of a package substrate, so that the underfill layer may protrude outwardly from the side surfaces of the semiconductor chip by a small distance. Consequently, the underfill layer may not protrude into the separation region, and the occurrence of defects during sawing may be reduced.

[0089] Although the inventive concept has been described in conjunction with some example embodiments thereof shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and characteristics of the inventive concept. Therefore, the embodiments disclosed above should be considered as illustrative rather than restrictive.

[0090] This application claims the benefit of Korean Patent Application No. 10-2020-0061467 filed on May 22, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising: Package substrate, The package substrate includes a first vent hole and a cavity in the package substrate, The first vent hole extends from the top surface of the package substrate to the cavity so that the first vent hole is in fluid communication with the cavity; A first semiconductor chip is mounted on the packaging substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; as well as a first bottom filling layer filling a space between the package substrate and the first semiconductor chip, wherein the first bottom filling layer extends along the first ventilation hole to fill the cavity; Wherein, the width of the cavity is greater than the width of the first ventilation hole.

2. The semiconductor package according to claim 1, further comprising: A second bottom filling layer fills the space between the first semiconductor chip and the second semiconductor chip, wherein A width of the first underfill layer between the package substrate and the first semiconductor chip is the same as or smaller than a width of the second underfill layer between the first semiconductor chip and the second semiconductor chip.

3. The semiconductor package according to claim 1, wherein The first ventilation hole is one of a plurality of first ventilation holes included in the package substrate, and The plurality of first ventilation holes are arranged along a first direction and a second direction parallel to the top surface of the package substrate. 4 . The semiconductor package according to claim 1 , wherein a width of the first ventilation hole is in a range of 2 μm to 10 μm.

5. The semiconductor package according to claim 1, wherein The package substrate includes a core portion, a first accumulation portion, and a second accumulation portion. The core has a first surface and a second surface opposite to the first surface, The first accumulation portion and the second accumulation portion are respectively on the first surface and the second surface, Each of the first and second build-up sections includes a plurality of dielectric layers and a plurality of wirings stacked alternately, and The cavity is in the core portion or the second accumulation portion. 6 . The semiconductor package according to claim 1 , wherein a distance between the package substrate and the first semiconductor chip is smaller than a distance between the first semiconductor chip and the second semiconductor chip. 7 . The semiconductor package according to claim 1 , wherein the package substrate further comprises a second vent hole extending from a bottom surface of the package substrate to the cavity and in fluid communication with the cavity. 8 . The semiconductor package according to claim 7 , wherein the first underfill layer extends from the inside of the cavity along the second ventilation hole onto the bottom surface of the package substrate.

9. The semiconductor package according to claim 7, wherein The second ventilation hole is one of a plurality of second ventilation holes in the package substrate, and The plurality of second ventilation holes are arranged along a first direction and a second direction parallel to the bottom surface of the package substrate.

10. The semiconductor package according to claim 1, further comprising: a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip and the second semiconductor chip, The distance between the outer surface of the molding layer and the distal end of the first underfill layer is in a range of 100 μm to 500 μm.

11. The semiconductor package according to claim 1, wherein the package substrate comprising a plurality of substrate pads in a plurality of recesses on the top surface of the package substrate, The plurality of substrate pads are exposed on the top surface of the package substrate, The package substrate includes a plurality of connection terminals thereon, and The first semiconductor chip is coupled to the plurality of substrate pads through the plurality of connection terminals.

12. A semiconductor package comprising: a package substrate including a cavity therein; a first semiconductor chip mounted on the package substrate via a first connection terminal; a second semiconductor chip mounted on a top surface of the first semiconductor chip via second connection terminals; a first bottom filling layer, filling the cavity and the space between the packaging substrate and the first semiconductor chip; a second underfill layer, filling the space between the first semiconductor chip and the second semiconductor chip, wherein a width of the first underfill layer between the package substrate and the first semiconductor chip is smaller than a width of the second underfill layer between the first semiconductor chip and the second semiconductor chip; as well as A molding layer is formed on the package substrate, and the molding layer surrounds the first semiconductor chip and the second semiconductor chip.

13. The semiconductor package according to claim 12, wherein The package substrate further includes a first vent hole extending from the cavity to a top surface of the package substrate, and The first underfill layer extends along the first vent hole to fill the cavity.

14. The semiconductor package according to claim 12, wherein The package substrate further includes a second vent hole extending from a bottom surface of the package substrate to the cavity and in fluid communication with the cavity, and The first underfill layer extends from the inside of the cavity along the second ventilation hole to the bottom surface of the package substrate.

15. The semiconductor package according to claim 12, wherein The package substrate includes a core portion, a first buildup portion on a top surface of the core portion, and a second buildup portion on a bottom surface of the core portion. The semiconductor package of claim 15 , wherein the cavity is in the core portion of the package substrate.

17. The semiconductor package according to claim 15, wherein The cavity is in the second accumulation portion of the package substrate, and The cavity is spaced apart from the wiring of the second stacking section.

18. A semiconductor package comprising: a package substrate including a cavity therein; A first semiconductor chip is mounted on the packaging substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a first underfill layer, filling a space between the package substrate and the first semiconductor chip and extending into the cavity of the package substrate; a second bottom filling layer, filling the space between the first semiconductor chip and the second semiconductor chip; as well as a molding layer on the package substrate, the molding layer surrounding the first semiconductor chip and the second semiconductor chip, The protrusion distance of the second bottom filling layer from the side surface of the second semiconductor chip is greater than the protrusion distance of the first bottom filling layer from the side surface of the first semiconductor chip.

19. The semiconductor package according to claim 18, wherein the package substrate further comprises a first vent hole extending from the cavity to a top surface of the package substrate, and The first underfill layer extends along the first vent hole to fill the cavity.

20. The semiconductor package according to claim 18, wherein A width of the first underfill layer between the package substrate and the first semiconductor chip is smaller than a width of the second underfill layer between the first semiconductor chip and the second semiconductor chip.

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