Power semiconductor device and method for manufacturing the same

Abstract

A power semiconductor device is provided, including: a semiconductor layer of silicon carbide (SiC); at least one trench extending in one direction; a gate insulating layer formed on at least the inner wall of the at least one trench; at least one gate electrode layer formed on the gate insulating layer; a drift region formed in the semiconductor layer on at least one side of the at least one gate electrode layer; a well region formed deeper than the at least one gate electrode layer in the semiconductor layer; a source region formed in the well region; and at least one channel region formed in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer. The power semiconductor device according to the present application can provide improved high breakdown voltage characteristics and improved operation reliability.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application Nos. 10 - 2020 - 0063131, filed on May 26, 2020, 10 - 2020 - 0064148, filed on May 28, 2020, 10 - 2020 - 0066309, filed on Jun. 2, 2020, 10 - 2020 - 0068205, filed on Jun. 5, 2020, 10 - 2020 - 0069417, filed on Jun. 9, 2020, 10 - 2020 - 0070701, filed on Jun. 11, 2020, 10 - 2020 - 0071310, filed on Jun. 12, 2020, and 10 - 2020 - 0144559, filed on Nov. 2, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same. Background art

[0004] Power semiconductor devices are semiconductor devices that operate in high - voltage and high - current environments. Power semiconductor devices are used in fields that require high - power switching, such as power conversion, power converters, inverters, etc. For example, power semiconductor devices may include insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), etc. Power semiconductor devices basically require high breakdown voltage characteristics, and nowadays, power semiconductor devices also require high - speed switching operations.

[0005] Thus, power semiconductor devices using silicon carbide (SiC) instead of silicon (Si) are being developed. Compared with silicon, silicon carbide (SiC), a wide-gap semiconductor material with a bandgap larger than that of silicon, can maintain stability even at high temperatures. Additionally, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, silicon carbide enables stable operation at high temperatures through the following characteristics: a breakdown voltage higher than that of silicon and excellent heat dissipation.

[0006] To increase the channel density of power semiconductor devices using this silicon carbide, a trench gate structure with a vertical channel structure is being developed. In the trench gate structure, since the electric field is concentrated at the trench edge, there are limitations in reducing the channel density by using a structure for protecting the lower part of the trench. Additionally, since the source contact structure is provided between the gate electrodes, it is also difficult to reduce the distance between the gate electrodes. Thus, there are limitations in reducing the channel density.

[0007] Prior Art References

[0008] Patent References

[0009] Patent Document 1: Korean Patent Application with Publication No. 2011-0049249 (May 12, 2011) Summary of the Invention

[0010] The present disclosure has been made to solve the above problems that occur in the prior art while fully maintaining the advantages achieved by the prior art.

[0011] One aspect of the present disclosure provides a silicon carbide-based power semiconductor device and a method of manufacturing the same that can mitigate electric field concentration and increase channel density. However, the above objectives are examples, and the scope of the present invention is not limited thereto.

[0012] The technical problems to be solved by the present disclosure are not limited to the above problems, and those skilled in the art to which the present disclosure pertains will clearly understand any other technical problems not mentioned herein from the following description.

[0013] According to one aspect of the present disclosure, a power semiconductor device includes: a semiconductor layer of silicon carbide (SiC); at least one trench extending in one direction and formed to recess from the surface of the semiconductor layer into the semiconductor layer to a given depth; a gate insulating layer formed on at least the inner walls of the at least one trench; at least one gate electrode layer formed on the gate insulating layer to bury the at least one trench; a drift region formed in the semiconductor layer on at least one side of the at least one gate electrode layer and having a first conductivity type; a well region formed in the semiconductor layer, the well region being formed deeper in the semiconductor layer than the at least one gate electrode layer to contact at least a part of the drift region and at least surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, the well region having a second conductivity type; a source region formed in the well region and having the first conductivity type; and at least one channel region formed in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer and having the second conductivity type, an inversion channel being formed in the at least one channel region along the one direction.

[0014] The source region includes a source contact region connected to a source electrode layer outside one end of the at least one gate electrode layer.

[0015] The power semiconductor device may include: a well contact region extending from the well region through the source region in the source contact region and connected to the source electrode layer, the well contact region having the second conductivity type, wherein the doping concentration of the well contact region is higher than that of the well region.

[0016] The drift region may include a vertical portion vertically extending in the semiconductor layer on one side of the at least one gate electrode layer, wherein the at least one channel region is formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0017] The well region, the source region, and the channel region are formed in the semiconductor layer to be located on the opposite side of the vertical portion of the drift region.

[0018] The drift region may include a vertical portion vertically extending in the semiconductor layer on the opposite side of the at least one gate electrode layer, wherein the at least one channel region includes a channel region formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0019] The at least one channel region may be a part of the well region.

[0020] The at least one trench may include a plurality of trenches formed in parallel in the semiconductor layer along the one direction, wherein the at least one gate electrode layer includes a plurality of gate electrode layers formed by burying the plurality of trenches, wherein the well region and the source region extend across the plurality of gate electrode layers, and wherein the at least one channel region includes a plurality of channel regions formed in the semiconductor layer on one side of the plurality of gate electrode layers.

[0021] The source region may include a source contact region connected to a source electrode layer outside one end of the plurality of gate electrode layers.

[0022] The drift region may include a vertical portion extending vertically in the semiconductor layer between the plurality of gate electrode layers, and wherein the channel region is formed in the semiconductor layer between the vertical portion of the drift region and the source region.

[0023] The at least one trench may include a plurality of trenches arranged in a straight line and spaced apart from each other along the one direction, wherein the at least one gate electrode layer includes a plurality of gate electrode layers formed by burying the plurality of trenches, and wherein the well region and the source region are at least formed in the semiconductor layer between the plurality of trenches.

[0024] The power semiconductor device may further include a drain region formed in the semiconductor layer below the drift region and having the first conductivity type, wherein the doping concentration of the drain region is higher than the doping concentration of the drift region.

[0025] According to another aspect of the present disclosure, a power semiconductor device includes: a semiconductor layer of silicon carbide (SiC); a plurality of trenches extending in parallel in one direction and formed to recess from the surface of the semiconductor layer into the semiconductor layer to a given depth; a gate insulating layer formed on at least an inner wall of the trenches; a plurality of gate electrode layers formed on the gate insulating layer to bury the plurality of trenches; a drift region including a plurality of vertical portions formed in the semiconductor layer between the plurality of gate electrode layers; the drift region having a first conductivity type; a well region formed in the semiconductor layer, the well region being formed deeper in the semiconductor layer than the plurality of gate electrode layers to contact the plurality of vertical portions of the drift region and surround a bottom surface of the plurality of gate electrode layers at opposite ends of the plurality of gate electrode layers, the well region having a second conductivity type; a source region formed in the well region and having the first conductivity type; and a plurality of channel regions formed in the semiconductor layer on opposite sides of the plurality of gate electrode layers between the plurality of vertical portions of the drift region and the source region, an inversion channel being respectively formed in the plurality of channel regions along the one direction, the plurality of channel regions having the second conductivity type.

[0026] According to another aspect of the present disclosure, a method of manufacturing a power semiconductor device includes: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in the semiconductor layer and in contact with at least a portion of the drift region; forming a source region having the first conductivity type in the well region; forming at least one channel region having the second conductivity type in the semiconductor layer between the drift region and the source region, and forming an inversion channel in the channel region in one direction; forming at least one trench shallower than the well region to recess from the surface of the semiconductor layer into the semiconductor layer to a given depth and extending across the drift region in the one direction; forming a gate insulating layer on at least an inner wall of the at least one trench; and forming at least one gate electrode layer on the gate insulating layer to bury the at least one trench, wherein the well region is formed deeper in the semiconductor layer than the at least one gate electrode layer to surround a bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer; wherein the channel region is formed in the semiconductor layer on one side of the at least one gate electrode layer between the drift region and the source region.

[0027] The formation of the source region may include forming a source contact region connected to a source electrode layer outside one end of the at least one gate electrode layer.

[0028] The method may further include: forming a well contact region in the source contact region, the well contact region extending from the well region through the source region and connected to the source electrode layer, the well contact region having the second conductivity type, wherein a doping concentration of the well contact region is higher than a doping concentration of the well region.

[0029] The formation of the well region may be performed by implanting impurities of the second conductivity type into the semiconductor layer, wherein the formation of the source region may be performed by implanting impurities of the first conductivity type into the well region.

[0030] The drift region may be formed on a drain region having the first conductivity type, wherein a doping concentration of the drain region is higher than a doping concentration of the drift region.

[0031] The drain region may be formed of a substrate of the first conductivity type, wherein the drift region is formed as an epitaxial layer on the substrate. Description of the Drawings

[0032] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings:

[0033] Figure 1is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0034] Figure 2 is a plan view showing the power semiconductor device taken along line II-II of Figure 1 ;

[0035] Figure 3 is a cross-sectional view showing the power semiconductor device taken along line III-III of Figure 1 ;

[0036] Figure 4 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0037] Figure 5 is a cross-sectional view showing the power semiconductor device taken along line V-V of Figure 4 ;

[0038] Figure 6 is a cross-sectional view showing the power semiconductor device taken along line VI-VI of Figure 4 ;

[0039] Figures 7 to 9 is a schematic perspective view showing a manufacturing method of a power semiconductor device according to an embodiment of the present disclosure;

[0040] Fig.10 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0041] Fig.11 is a plan view showing the power semiconductor device taken along line II-II of Fig.10 ;

[0042] Fig.12 is a cross-sectional view showing the power semiconductor device taken along line III-III of Fig.11 ;

[0043] Fig.13 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0044] Fig.14 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0045] Fig.15 is a plan view showing the power semiconductor device taken along line VI-VI of Fig.14 ;

[0046] Fig.16 is a cross-sectional view showing the power semiconductor device taken along line VI-VI of Fig.15Cross-sectional view of a power semiconductor device taken along line VII-VII;

[0047] Fig.17 is a cross-sectional view of a power semiconductor device taken along line VIII-VIII; Fig.15 Cross-sectional view of a power semiconductor device taken along line VIII-VIII;

[0048] Fig.18 and Fig.19 are cross-sectional views of power semiconductor devices according to other embodiments of the present disclosure;

[0049] Figure 20 to Figure 22 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0050] Fig.23 is a graph showing the variation of the electric field according to the depth of a power semiconductor device according to an embodiment of the present disclosure;

[0051] Fig.24 is a schematic perspective view of a power semiconductor device according to an embodiment of the present disclosure;

[0052] Fig.25 is a plan view of a power semiconductor device taken along line II-II; Fig.24 Plan view of a power semiconductor device taken along line II-II;

[0053] Fig.26 is a cross-sectional view of a power semiconductor device taken along line III-III; Fig.25 Cross-sectional view of a power semiconductor device taken along line III-III;

[0054] Fig. 27 is a cross-sectional view of a power semiconductor device taken along line IV-IV; Fig.25 Cross-sectional view of a power semiconductor device taken along line IV-IV;

[0055] Fig.28 and Fig.29 are cross-sectional views of power semiconductor devices according to another embodiment of the present disclosure;

[0056] Fig.30 are cross-sectional views of power semiconductor devices according to another embodiment of the present disclosure;

[0057] Fig.31 is a schematic perspective view of a power semiconductor device according to another embodiment of the present disclosure;

[0058] Fig.32 is a plan view of a power semiconductor device taken along line IX-IX; Fig.31 Plan view of a power semiconductor device taken along line IX-IX;

[0059] Fig.33 is a cross-sectional view taken along line Fig.32Cross-sectional view of a power semiconductor device taken along line X-X;

[0060] Fig.34 Is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0061] Figure 35 to Figure 37 Is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0062] Fig.38 Is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0063] Fig.39 Is showing along Fig.38 Plan view of a power semiconductor device taken along line II-II;

[0064] Fig.40 Is showing along Fig.39 Cross-sectional view of a power semiconductor device taken along line III-III;

[0065] Fig.41 Is showing along Fig.39 Cross-sectional view of a power semiconductor device taken along line IV-IV;

[0066] Fig.42 And Fig.43 Is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0067] Fig.44 Is a schematic cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure;

[0068] Figure 45 to Figure 47 Is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0069] Fig.48 Is a graph showing the characteristics of the diode of a power semiconductor device according to an embodiment of the present disclosure;

[0070] Fig.49 Is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0071] Fig.50 Is showing along Fig.49 Plan view of a power semiconductor device taken along line II-II;

[0072] Fig.51 Is showing along Fig.50 Cross-sectional view of a power semiconductor device taken along line III-III;

[0073] Fig.52 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0074] Fig.53 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0075] Fig.54 is a plan view showing a power semiconductor device taken along line Fig.53 VI-VI;

[0076] Fig.55 is a cross-sectional view showing a power semiconductor device taken along line Fig.54 VII-VII;

[0077] Fig.56 is a cross-sectional view showing a power semiconductor device taken along line Fig.54 VIII-VIII;

[0078] Fig.57 and Fig.58 are cross-sectional views showing power semiconductor devices according to other embodiments of the present disclosure;

[0079] Figure 59 to Figure 61 is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0080] Fig.62 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0081] Fig.63 is a plan view showing a power semiconductor device taken along line Fig.62 II-II;

[0082] Fig.64 is a cross-sectional view showing a power semiconductor device taken along line Fig.63 III-III;

[0083] Fig.65 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0084] Fig.66 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0085] Fig.67 is a plan view showing a power semiconductor device taken along line Fig.66 VI-VI;

[0086] Fig.68 is a cross-sectional view showing a power semiconductor device taken along line Fig.67 Cross-sectional view of a power semiconductor device taken along line VII-VII;

[0087] Fig.69 is a cross-sectional view of a power semiconductor device taken along Fig.67 line VIII-VIII;

[0088] Fig.70 and Fig.71 are cross-sectional views of power semiconductor devices according to other embodiments of the present disclosure;

[0089] Figure 72 to Figure 74 is a schematic perspective view of a method for manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0090] Fig.75 is a schematic perspective view of a power semiconductor device according to an embodiment of the present disclosure;

[0091] Fig.76 is a plan view of a power semiconductor device taken along Fig.75 line II-II;

[0092] Fig.77 is a cross-sectional view of a power semiconductor device taken along Fig.76 line III-III;

[0093] Fig.78 is a cross-sectional view of a power semiconductor device taken along Fig.76 line IV-IV;

[0094] Fig.79 is a schematic perspective view of a power semiconductor device according to another embodiment of the present disclosure;

[0095] Fig.80 is a plan view of a power semiconductor device taken along Fig.79 line VI-VI;

[0096] Fig.81 is a cross-sectional view of a power semiconductor device taken along Fig.80 line VII-VII;

[0097] Fig.82 is a cross-sectional view of a power semiconductor device taken along Fig.80 line VIII-VIII;

[0098] Figure 83 to Figure 86 are cross-sectional views of power semiconductor devices according to other embodiments of the present disclosure;

[0099] Figure 87 to Figure 89is a schematic perspective view showing a method of manufacturing a power semiconductor device according to an embodiment of the present disclosure;

[0100] Fig.90 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure;

[0101] Fig.91 is showing along Fig.90 a plan view of the power semiconductor device taken along line II-II;

[0102] Fig.92 is showing along Fig.91 a cross-sectional view of the power semiconductor device taken along line III-III;

[0103] Fig.93 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0104] Fig.94 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present disclosure;

[0105] Fig.95 is showing a plan view of the power semiconductor device taken along line VI-VI along Fig.94 ;

[0106] Fig.96 is showing along Fig.95 a cross-sectional view of the power semiconductor device taken along line VII-VII;

[0107] Fig.97 is showing along Fig.95 a cross-sectional view of the power semiconductor device taken along line VIII-VIII;

[0108] Fig.98 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present disclosure; and

[0109] Fig.99 is a perspective view showing a power semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0110] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure can be implemented in various different forms and should not be construed as limited to the embodiments disclosed below. Instead, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. Additionally, for ease of description, the dimensions of at least some of the components or elements shown in the drawings may be enlarged or reduced. In the drawings, the same reference numerals refer to the same elements.

[0111] Unless otherwise defined, all terms used herein shall be construed as those commonly understood by one of ordinary skill in the art. In the drawings, the dimensions of layers and regions are exaggerated for description purposes, and thus the dimensions of the layers and regions are provided to describe the normal structure of the present disclosure.

[0112] Like reference numerals indicate like components. When a first component such as a layer, a region, or a substrate is described as being on a second component, it can be understood that the first component is directly on the second component or a third component is interposed therebetween. On the other hand, when the first component is described as being "directly" on the second component, it should be understood that no intermediate component is interposed therebetween.

[0113] Figure 1 is a schematic perspective view showing a power semiconductor device according to an embodiment of the present disclosure. Figure 2 is showing along Figure 1 a plan view of the power semiconductor device taken along line II-II. Figure 3 is showing along Figure 1 a cross-sectional view of the power semiconductor device taken along line III-III.

[0114] Referring to Figures 1 to 3 , the power semiconductor device 100-1 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-1 may have a power MOSFET structure.

[0115] The semiconductor layer 105 may refer to one semiconductor material layer or a plurality of semiconductor material layers. For example, it may refer to one epitaxial layer or a plurality of epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0116] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one silicon carbide epitaxial layer.

[0117] Silicon carbide (SiC) may have a wider bandgap than silicon, and thus may maintain stability even at high temperatures compared to silicon. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-1 including the semiconductor layer 105 formed of silicon carbide may have a high breakdown voltage and may provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0118] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0119] A well region 110 may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of the second conductivity type, which is opposite to the first conductivity type, in the drift region 107.

[0120] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, and at least a portion of the vertical portion 107a is surrounded by the well region 110. During the operation of the power semiconductor device 100-1, the vertical portion 107a may provide a vertical movement path for charges.

[0121] The well region 110 is Figure 1 shown as including two regions spaced apart from each other and a vertical portion 107a inserted between the two regions, but the well region 110 may be subject to various changes or modifications. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110 at one time.

[0122] A source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0123] At least one channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type such that an inversion channel is formed along one direction.

[0124] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when a working voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, thereby allowing charge movement.

[0125] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be formed to be continuously connected to the well region 110. The doping concentration of the impurity of the second conductivity type in the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for threshold voltage adjustment.

[0126] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetric with respect to the vertical portion 107a of the drift region 107. For example, each of the well region 110, the channel region 110a, and the source region 112 may include a left portion and a right portion formed symmetric with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the left portion and the right portion may be separated from each other or may be connected to each other.

[0127] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0128] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or may be understood as a substrate independent of the semiconductor layer 105.

[0129] At least one trench 116 may be formed to recess into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to the length direction of the trench 116, rather than the depth direction, and may refer to Figure 1 the direction of line II-II or III-III.

[0130] The gate insulating layer 118 may be formed on at least the inner walls of the trench 116. For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof. The thickness of the gate insulating layer 118 may be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a part of the gate insulating layer 118 formed on the sidewalls of the trench 116.

[0131] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0132] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120.

[0133] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that extends vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120.

[0134] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0135] This structure can reduce the concentration of the electric field on the bottom surface of the trench 116, that is, at the lower part of the gate electrode layer 120. Therefore, in the power semiconductor device 100-1 according to the embodiment, the well region 110 can be formed deeper than the gate electrode layer 120 without additionally forming a deep well, so that the concentration of the electric field on the bottom surface of the trench 116 can be reduced. The problem with the conventional vertical channel structure is that as the distance between the deep well and the trench becomes shorter, the junction resistance and the threshold voltage increase. However, this problem may not occur in the power semiconductor device 100-1 according to the embodiment.

[0136] The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0137] The above structure of the channel region 110a may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0138] Additionally, the channel region 110a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0139] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and in addition, may be formed to further extend outside the trench 116.

[0140] In some embodiments, one or more trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0141] For example, multiple trenches 116 may be formed in the semiconductor layer 105 parallel to one direction. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0142] In this case, multiple gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trenches 116. In this way, trench-type gate electrode layers 120 may be formed in the semiconductor layer 105 and may be arranged to extend in parallel in the one direction like the trenches 116.

[0143] Furthermore, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. Multiple channel regions 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0144] In some embodiments, the well region 110 may be formed in the semiconductor layer 105 deeper than the gate electrode layer 120 so as to contact the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at the opposite ends of the gate electrode layer 120.

[0145] The interlayer insulating layer 130 may be formed on the gate electrode layer 120.

[0146] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0147] For clarity, different from Figure 2 and Figure 3 the interlayer insulating layer 130 and the source electrode layer 140 are not shown in Figure 1 .

[0148] In the above-described power semiconductor device 100-1, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of n-type and p-type. For example, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0149] More specifically, when the power semiconductor device 100-1 is an N-type MOSFET, the drift region 107 can be an N-region, the source region 112, the source contact region 112a, and the drain region 102 can be N+ regions, the well region 110 and the channel region 110a can be P-regions, and the well contact region 114 can be a P+ region.

[0150] During the operation of the power semiconductor device 100-1, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then can flow along the side surface of the gate electrode layer 120 through the channel region 110a to the source region 112.

[0151] In the above-described power semiconductor device 100-1, the gate electrode layers 120 can be arranged densely and parallel to each other in a stripe shape, and the channel region 110a can be arranged on the side surface of the gate electrode layer 120. In this way, the channel density can be increased.

[0152] In addition, in the power semiconductor device 100-1, since the bottom surface of the gate electrode layer 120 is surrounded by the well region 110, the breakdown phenomenon caused by the electric field concentrating on the edge of the trench 116 can be alleviated. Therefore, the high breakdown voltage characteristics of the power semiconductor device 100-1 can be improved. This may mean that the reliability of the operation of the power semiconductor device 100-1 is improved.

[0153] Figure 4 is a schematic perspective view showing a power semiconductor device 100a-1 according to another embodiment of the present disclosure. Figure 5 is shown along Figure 4 A cross-sectional view of the power semiconductor device 100a-1 taken along line V-V. Figure 6 is shown along Figure 4 A cross-sectional view of the power semiconductor device 100a-1 taken along line VI-VI.

[0154] The power semiconductor device 100a-1 according to this embodiment can be implemented by using or partially modifying Figures 1 to 3 The power semiconductor device 100-1 in. Therefore, additional descriptions will be omitted to avoid repetition.

[0155] Referring to Figures 4 to 6 , the source region 112 can include a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, can refer to the portion connected to the source electrode layer 140.

[0156] The well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source region 112, and may have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 may be formed in the source contact region 112a.

[0157] For example, the well contact region 114 may be connected to the source electrode layer 140 and may be doped with a second conductivity type impurity having a higher concentration than that of the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0158] In Figures 4 to 6 an example is shown in which the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0159] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other along one direction. Thus, the gate electrode layers 120 may also be arranged to be linearly spaced apart from each other along the trenches 116 in one direction. In this case, the well region 110 and the source region 112 may be formed in the semiconductor layer 105 such that the well region 110 and the source region 112 are located between the plurality of trenches 116 linearly spaced apart from each other along one direction.

[0160] For example, Figures 1 to 3 the structure of the power semiconductor device 100-1 shown may be arranged in plurality along one direction, and the well region 110 and the source region 112 may be formed therebetween.

[0161] For clarity, different from Figure 5 and Figure 6 the interlayer insulating layer 130 and the source electrode layer 140 are not shown in Figure 4 .

[0162] In the power semiconductor device 100a-1 according to an embodiment, the source contact region 112a and the well contact region 114 may be provided outside the gate electrode layer 120 instead of between the gate electrode layers 120. Thus, the gate electrode layers 120 may be arranged more densely. In this way, the channel density of the power semiconductor device 100a-1 may be significantly increased. Additionally, according to the power semiconductor device 100a-1, the breakdown phenomenon caused by the electric field concentration on the edge of the trench 116 may be alleviated. Thus, the high breakdown voltage characteristic of the power semiconductor device 100a-1 may be improved. This may mean that the reliability of the operation of the power semiconductor device 100a-1 is improved.

[0163] Figures 7 to 9 is a schematic perspective view showing a manufacturing method of a power semiconductor device 100a-1 according to an embodiment of the present disclosure.

[0164] Referring Figure 7 , a drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented with a substrate having a first conductivity type, and the drift region 107 can be formed as one or more epitaxial layers on the substrate.

[0165] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with at least a part of the drift region 107. For example, the formation of the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0166] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. More specifically, the well region 110 can be formed by doping impurities having a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0167] Then, a source region 112 having a first conductivity type can be formed in the well region 110. For example, the source region 112 can be formed by implanting impurities of the first conductivity type into the well region 110.

[0168] In addition to forming the source region 112, at least one channel region 110a having a second conductivity type can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, and an inversion channel is formed in the channel region 110a in one direction. For example, the channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0169] In the above manufacturing method, impurity implantation or impurity doping can be performed such that impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern can be used to implant impurities in a selected region.

[0170] Optionally, a heat treatment process for activating or diffusing impurities can be performed after the ion implantation.

[0171] Referring Figure 8 , at least one trench 116 can be formed to recess from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0172] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110.

[0173] In addition, a plurality of trenches 116 may be formed in parallel in the semiconductor layer 105 in one direction.

[0174] For example, the trench 116 may be formed by using photolithography to form a photomask and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0175] Referring to Fig. 9 , a gate insulating layer 118 may be formed on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0176] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities in polysilicon or may be formed to include a conductive metal or a metal silicide.

[0177] The patterning process may be performed by using photolithography and etching processes. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process may include a process of selectively etching the underlying structure by using the photoresist pattern.

[0178] In this way, the well region 110 may be arranged deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and a channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0179] In addition, referring to Figure 2 and Figure 3 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120.

[0180] Next, a source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0181] Meanwhile, Figures 4 to 6The power semiconductor device 100a-1 can be manufactured by adding some processes to, or changing or modifying, the manufacturing method of the above-mentioned power semiconductor device 100-1.

[0182] For example, when manufacturing the power semiconductor device 100a-1, the formation of the source region 112 can include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may not be separated from the source region 112.

[0183] In addition, before forming the trench 116, a well contact region 114 can be formed in the source contact region 112a. For example, the well contact region 114 can be formed by implanting impurities of a second conductivity type having a higher concentration than the well region 110 into a part of the well region 110.

[0184] When manufacturing the power semiconductor device 100a-1, the trenches 116 can be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer between the trenches 116.

[0185] According to the above manufacturing method, the power semiconductor device 100-1 using the semiconductor layer 105 of silicon carbide can be economically manufactured by using the processes applied to a conventional silicon substrate.

[0186] Fig.10 is a schematic perspective view showing a power semiconductor device 100-2 according to an embodiment of the present disclosure. Fig.11 is shown along Fig.10 The plan view of the power semiconductor device 100-2 taken along line II-II. Fig.12 is shown along Fig.11 The cross-sectional view of the power semiconductor device 100-2 taken along line III-III.

[0187] Referring to Figures 10 to 12 , the power semiconductor device 100-2 can at least include a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-2 can have a power MOSFET structure.

[0188] The semiconductor layer 105 can refer to one semiconductor material layer or multiple semiconductor material layers. For example, it can refer to one epitaxial layer or multiple epitaxial layers. In addition, the semiconductor layer 105 can refer to one or more epitaxial layers on a semiconductor substrate.

[0189] For example, the semiconductor layer 105 can be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 can include at least one epitaxial layer of silicon carbide.

[0190] The bandgap of silicon carbide (SiC) can be wider than that of silicon, so it maintains stability even at high temperatures compared to silicon. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can be stably operated even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-2 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0191] More specifically, the semiconductor layer 105 can include a drift region 107. The drift region 107 can have a first conductivity type and can be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 can be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0192] The well region 110 can be formed in the semiconductor layer 105 to contact the drift region 107 and can have a second conductivity type. For example, the well region 110 can be formed by doping impurities of the second conductivity type opposite to the first conductivity type in the drift region 107.

[0193] For example, the well region 110 can be formed to surround at least a part of the drift region 107. In this way, the drift region 107 can include a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. During the operation of the power semiconductor device 100-2, the vertical portion 107a can provide a vertical movement path for charges.

[0194] In Fig.10 the well region 110 shown includes two regions spaced apart from each other and a vertical portion 107a inserted between the two regions, but the well region 110 can be variously changed or modified. For example, the vertical portion 107a can have a shape in which its side surfaces are surrounded by the well region 110 at one time.

[0195] The pillar region 111 can be formed in the semiconductor layer 105 under the well region 110 to contact the drift region 107. In this way, a superjunction with the drift region 107 can be formed. For example, the pillar region 111 can be disposed below the well region 110 to contact the well region 110, and the opposite side surfaces of the pillar region 111 can be disposed to contact the drift region 107.

[0196] The column region 111 may have a conductivity type different from that of the drift region 107 and may be formed in the semiconductor layer 105 to form a super junction with the drift region 107. For example, the column region 111 may have a second conductivity type opposite to that of the drift region 107 and the same as that of the well region 110. For example, the doping concentration of the impurities of the second conductivity type in the column region 111 may be the same as or lower than the doping concentration of the impurities of the second conductivity type in the well region 110.

[0197] In some embodiments, the column region 111 may be formed to have a width narrower than that of the well region 110 based on one direction. One direction may refer to Fig.11 the direction of line III-III. In addition, the opposite ends of the column region 111 may be arranged to be inwardly offset from the opposite ends of the well region 110 based on one direction.

[0198] In this way, under the well region 110, the column region 111 may be formed to retract inward from the opposite ends of the well region 110 in a state of being in contact with the well region 110. For example, the column region 111 is formed in two spaced-apart regions like the well region 110, and the spacing distance between the two column regions 111 may be greater than the spacing distance between the two well regions 110.

[0199] In some embodiments, the side surfaces and the lower surface of the column region 111 may be in contact with the drift region 107. For example, the plurality of column regions 111 and the plurality of drift regions 107 may be alternately arranged such that the side surfaces of the column region 111 and the side surfaces of the drift region 107 are in contact with each other, and thus, a super junction structure may be formed. In addition, the plurality of column regions 111 and the plurality of drift regions 107 may be alternately provided under one well region 110.

[0200] The source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0201] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type, and an inversion channel may be formed in the channel region 110a along one direction during the operation of the power semiconductor device 100-2.

[0202] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when a working voltage is applied to the gate electrode layer 120, an inversion channel can be formed therein, thereby allowing charge movement.

[0203] In some embodiments, the channel region 110a can be part of the well region 110. In this case, the channel region 110a can be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurities of the second conductivity type in the channel region 110a can be the same as or different from the doping concentration of the rest of the well region 110 to adjust the threshold voltage.

[0204] In some embodiments, the well region 110, the pillar region 111, the channel region 110a, and the source region 112 can be formed symmetric with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the pillar region 111, the channel region 110a, and the source region 112 can be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the pillar region 111, the channel region 110a, and the source region 112 can include a first portion and a second portion formed symmetric with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the pillar region 111, the channel region 110a, and the source region 112, the first portion and the second portion can be separated from each other or can be connected to each other.

[0205] In addition, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and can have a first conductivity type. For example, compared with the drift region 107, the drain region 102 can be doped with a high concentration of impurities.

[0206] In some embodiments, the drain region 102 can be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 can be understood as part of the semiconductor layer 105 or can be understood as a substrate independent of the semiconductor layer 105.

[0207] At least one trench 116 can be formed that recesses into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth. The trench 116 can extend in one direction within the semiconductor layer 105. One direction can refer to the length direction of the trench 116, rather than the depth direction, and can refer to Fig.11 the direction of line III-III.

[0208] The gate insulating layer 118 can be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 can be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 can be thicker than a part of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0209] For example, the gate insulating layer 118 can include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or can include a stacked structure thereof.

[0210] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 can include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or can include a stacked structure thereof.

[0211] The drift region 107 can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 can vertically extend in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a can be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 can include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0212] In some embodiments, the drift region 107 can be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 can include a vertical portion 107a that vertically extends in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110a can be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0213] The above structure of the channel region 110a can be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0214] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end portion of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 to surround the bottom surface of the gate electrode layer 120 at the opposite end portion of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0215] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and further, may be formed to extend outside the trench 116.

[0216] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of the trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0217] For example, a plurality of trenches 116 may be formed in parallel in one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0218] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trench 116. In this way, the gate electrode layer 120 may be formed in a trench type in the semiconductor layer 105 and may be arranged to extend in parallel in one direction like the trench 116.

[0219] Additionally, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0220] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0221] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0222] In the above-mentioned power semiconductor device 100-2, the first conduction type and the second conduction type may be opposite to each other, and each of the first conduction type and the second conduction type may be one of n-type and p-type. For example, when the first conduction type is n-type, the second conduction type is p-type, and vice versa.

[0223] More specifically, when the power semiconductor device 100-2 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110, the pillar region 111, and the channel region 110a may be P- regions.

[0224] During the operation of the power semiconductor device 100-2, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then can flow along the side surface of the gate electrode layer 120 through the channel region 110a to the source region 112.

[0225] In the above-mentioned power semiconductor device 100-2, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe type or a line type, and the channel region 110a may be provided on the side surface of the gate electrode layer 120. In this way, the channel density can be increased.

[0226] In addition, in the above-mentioned power semiconductor device 100-2, the well (110) structure can relieve the concentration of the electric field at the bottom surface of the trench 116, that is, at the lower part of the gate electrode layer 120. Thus, the margin of the electric field covering the gate insulating layer 118 of the power semiconductor device 100-2 can be increased, and therefore, the reliability of the operation of the power semiconductor device 100-2 can be improved. In addition, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field at the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0227] At the same time, since the power semiconductor device 100-2 is used for high-power switching, the power semiconductor device 100-2 requires high breakdown voltage characteristics. When a high voltage is applied to the drain region 102, the depletion region can expand from the semiconductor layer 105 adjacent to the drain region 102, so that the voltage barrier of the channel is reduced. This phenomenon is called "drain induced barrier lowering (DIBL)".

[0228] DIBL may cause abnormal conduction in the channel region 110a, and in addition, may cause a punch-through phenomenon, that is, as it expands, the depletion region from the drain side reaches the source side.

[0229] However, the above power semiconductor device 100-2 can ensure appropriate high breakdown voltage characteristics by suppressing abnormal current and punch-through phenomenon caused by DIBL through the use of the pillar region 111 that forms a superjunction with the drift region 107.

[0230] By adjusting the charge amount of the pillar region 111 and the charge amount of the drift region 107, the high breakdown voltage characteristics can be further improved.

[0231] Fig.23 is a graph showing the variation of the electric field according to the depth of the power semiconductor device 100-2.

[0232] Referring to Fig.23 , when the charge amount Qp of the pillar region 111 is greater than the charge amount Qn of the drift region 107, during the operation of the power semiconductor device 100-2, the breakdown voltage can be increased by allowing the maximum electric field to be formed in the drift region 107 on the same line as the bottom surface of the pillar region 111. Fig.23 The slope of the electric field strength between position A and position B in

[0233] For example, by making the doping concentration of the impurity of the second conductivity type in the pillar region 111 higher than the doping concentration of the impurity of the first conductivity type in the drift region 107, the charge amount Qp of the pillar region 111 can be made greater than the charge amount Qn of the drift region 107. Therefore, the high breakdown voltage characteristics of the power semiconductor device 100-2 can be improved.

[0234] Fig.13 is a perspective view showing a power semiconductor device 100a-2 according to another embodiment of the present disclosure.

[0235] The power semiconductor device 100a-2 according to the embodiment can be implemented by using or partially modifying the Figures 10 to 12 power semiconductor device 100-2 in. Therefore, additional description will be omitted to avoid repetition.

[0236] Referring to Fig.13 , in the power semiconductor device 100a-2, a channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have the first conductivity type, and during the operation of the power semiconductor device 100a-2, an accumulation channel can be formed in the channel region 107b.

[0237] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0238] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band of the channel region 107b bends upward. Thus, an accumulation channel can be formed that allows charges or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120.

[0239] Therefore, the threshold voltage applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b can be much lower than the threshold voltage applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a in Figures 10 to 12 this case.

[0240] In some embodiments, the channel region 107b can be a part of the drift region 107. More specifically, the channel region 107b can be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b can be formed integrally with the drift region 107. In this case, the drift region 107 can be connected to the source region 112 through the channel region 107b. That is, in the portion of the channel region (107b), the drift region 107 and the source region 112 can be in contact with each other.

[0241] The doping concentration of the impurity of the first conductivity type in the channel region 107b can be the same as or different from the doping concentration of the remaining portion of the drift region 107 to adjust the threshold voltage.

[0242] As a modified example of the embodiment, the well region 110 can be formed to protrude farther toward the vertical portion 107a of the drift region 107 than a part of the source region 112, and the channel region 107b can be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0243] In addition, the well region 110 can further include a tap portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b can be formed in a curved shape on the protruding portion and the tap portion of the well region 110.

[0244] In addition, the vertical portion 107a of the drift region 107 can further extend between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed to further extend between the lower part of the source region 112 and the well region 110.

[0245] The above structure can allow the channel region 107b to be more restricted between the gate electrode layer 120 and the well region 110.

[0246] The power semiconductor device 100a-2 can include Figures 10 to 12The advantages of the power semiconductor device 100-2 shown, and furthermore, the threshold voltage can be made low.

[0247] Fig.14 FIG. is a schematic perspective view showing a power semiconductor device 100b-2 according to another embodiment of the present disclosure. Fig.15 FIG. is showing along Fig.14 a plan view of the power semiconductor device 100b-2 taken along line VI-VI. Fig.16 FIG. is showing along Fig.15 a cross-sectional view of the power semiconductor device 100b-2 taken along line VII-VII. Fig.17 FIG. is showing along Fig.15 a cross-sectional view of the power semiconductor device 100b-2 taken along line VIII-VIII.

[0248] The power semiconductor device 100b-2 according to an embodiment can be implemented by using or partially modifying the power semiconductor device 100-2 in Figures 10 to 12 . Therefore, additional descriptions will be omitted to avoid repetition.

[0249] Referring to Figures 14 to 17 , in the power semiconductor device 100b-2, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, may refer to the portion connected to the source electrode layer 140.

[0250] The well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source region 112 and may have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 may be formed in the source contact region 112a.

[0251] For example, the well contact region 114 may be doped with second conductivity type impurities having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0252] The source electrode layer 140 may be commonly connected to the source contact region 112a and the well contact region 114.

[0253] In Figures 14 to 17 an example is shown in which the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0254] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other along one direction. In this way, the gate electrode layers 120 may also be arranged to be linearly spaced apart from each other along the trenches 116 in this one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from each other along this one direction.

[0255] For example, the power semiconductor device 100b-2 may be formed by arranging a plurality of Figures 10 to 12 in the structure of the power semiconductor device 100-2 in one direction, and by providing the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 therebetween.

[0256] For example, when the power semiconductor device 100-2 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0257] According to the power semiconductor device 100b-2, the source contact region 112a and the well contact region 114 may be provided outside the gate electrode layer 120, rather than between the gate electrode layers 120, so that the gate electrode layers 120 may be arranged more densely. In this way, the channel density of the power semiconductor device 100a-2 may be significantly increased.

[0258] Fig.18 and Fig.19 are cross-sectional views showing the power semiconductor devices 100c-2 and 100d-2 according to other embodiments of the present disclosure. Each of the power semiconductor devices 100c-2 and 100d-2 may be implemented by modifying Figures 14 to 17 part of the configuration of the power semiconductor device 100b-2. Therefore, additional descriptions will be omitted to avoid repetition.

[0259] Referring to Fig.18 , the power semiconductor device 100c-2 may include at least one groove 138 in the source contact region 112a of the source region 112, which is formed to penetrate the source region 112 and recess into the well region 110. The well contact region 114a may be formed on at least the bottom surface of the groove 138 so as to contact the well region 110.

[0260] The source electrode layer 140a may be formed to fill the groove 138, so that the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110, as well as the contact area between the source electrode layer 140a and the source region 112, so that the contact resistance therebetween is reduced.

[0261] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Accordingly, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0262] Referring to Fig.19 , replacing Fig.14 and 17 the channel region 110a of the power semiconductor device 100b-2, the power semiconductor device 100d-2 may include a channel region 107b that forms an accumulation channel. The structure of the power semiconductor device 100d-2 including the channel region 107b may refer to the description given in Fig.13 .

[0263] Accordingly, the power semiconductor device 100d-2 may correspond to a structure in which Fig.13 the power semiconductor devices 100a-2 are connected in multiple numbers, and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 are provided therebetween.

[0264] Figure 20 to Figure 22 is a schematic perspective view showing a method of manufacturing a power semiconductor device 100-2 according to an embodiment of the present disclosure.

[0265] Referring to Fig. 20 , a drift region 107 having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be implemented with a substrate of the first conductivity type, and the drift region 107 may be formed with one or more epitaxial layers on the substrate.

[0266] Next, a well region 110 having a second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105. The well region 110 may be formed from the surface of the semiconductor layer 105 to a given depth substantially.

[0267] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. More specifically, the well region 110 may be formed by doping impurities of a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0268] Next, a column region 111 of a second conductivity type can be formed in the semiconductor layer 105 below the well region 110 such that the column region 111 contacts the drift region 107 to form a superjunction with the drift region 107. The column region 111 can be formed by implanting impurities of the same second conductivity type as the well region 110. The well region 110 and the column region 111 can be formed in any order.

[0269] Then, a source region 112 of a first conductivity type can be formed in the well region 110. For example, the source region 112 can be formed by implanting impurities of the first conductivity type into the well region 110. The source region 112 can be formed in the well region 110 to extend substantially from the surface of the semiconductor layer 105 to a given depth.

[0270] In addition to forming the source region 112, a channel region 110a can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, and an inversion channel is formed in the channel region 110a in one direction. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a can be a part of the well region 110 and can be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0271] In a modification of the embodiment, the order of forming the well region 110, the column region 111, the source region 112, and the channel region 110a or the order of impurity doping can be changed to any order.

[0272] In the above manufacturing method, impurity implantation or impurity doping can be performed such that when impurities are implanted into the semiconductor layer 105, the impurities are mixed or an epitaxial layer is formed. However, an ion implantation method using a mask pattern can be used to implant impurities in a selected region.

[0273] Optionally, a heat treatment process for activating or diffusing impurities can be performed after the ion implantation.

[0274] Referring to Fig.21 , at least one trench 116 can be formed to recess from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0275] For example, the trench 116 can extend across the drift region 107 in one direction and can be formed shallower than the well region 110.

[0276] In addition, the at least one trench 116 can include a plurality of trenches 116, and the trenches 116 can be formed simultaneously, for example, parallel to each other in one direction in the semiconductor layer 105. The channel region 110a can be further restricted by the trenches 116.

[0277] For example, a photomask can be formed by using photolithography, and then trenches 116 can be formed by etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0278] Referring Fig. 22 , a gate insulating layer 118 can be formed on the bottom and inner walls of the trenches 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0279] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trenches 116. For example, the gate electrode layer 120 can be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 can be formed by doping impurities in polysilicon, or can be formed to include a conductive metal or a metal silicide.

[0280] The patterning process can be performed by using a photolithography process and an etching process. The photolithography process can include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process can include a process of selectively etching a lower layer structure by using the photoresist pattern.

[0281] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0282] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120.

[0283] Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0284] Meanwhile, Fig.13 the power semiconductor device 100a-2 can be manufactured by adding some processes to or changing or modifying the manufacturing method of the above power semiconductor device 100-2. For example, a channel region 107b can be formed with a part of the drift region 107 so as to form an accumulation channel.

[0285] Figures 14 to 17 the power semiconductor device 100b-2 can be manufactured by adding some processes to or changing or modifying the manufacturing method of the above power semiconductor device 100-2.

[0286] For example, when manufacturing the power semiconductor device 100b-2, the formation of the source region 112 may include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be a part of the source region 112.

[0287] In addition, before forming the trench 116, a well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may be formed by implanting impurities of a second conductivity type having a higher concentration than the well region 110 into a part of the well region 110.

[0288] When manufacturing the power semiconductor device 100b-2, the trenches 116 may be arranged to be spaced apart linearly from each other in one direction. In addition, the well region 110, the channel region 110a, and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116.

[0289] Referring to Fig.18 The manufacturing method of the power semiconductor device 100c-2 described above may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and recess into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 to contact the well region 110, and forming a source electrode layer 140 to connect to the well contact region 114.

[0290] According to the above manufacturing method, a power semiconductor device 100-2 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0291] Fig.24 is a schematic perspective view showing a power semiconductor device 100-3 according to an embodiment of the present disclosure. Fig.25 is showing along Fig.24 A plan view of the power semiconductor device 100-3 taken along line II-II of. Referring to Fig.24 . Fig.26 is showing along Fig.25 A cross-sectional view of the power semiconductor device 100-3 taken along line III-III of. Fig. 27 is showing a cross-sectional view of the power semiconductor device 100-3 taken along line IV-IV of Fig.25 .

[0292] Referring to Figure 24 to Figure 27 , the power semiconductor device 100-3 may include a semiconductor layer 105, a gate insulating layer 118, and at least one gate electrode layer 120. For example, the power semiconductor device 100-3 may have a power MOSFET structure.

[0293] The semiconductor layer 105 may refer to a single semiconductor material layer or multiple semiconductor material layers. For example, it may refer to a single epitaxial layer or multiple epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0294] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0295] The bandgap of silicon carbide (SiC) may be wider than that of silicon, so it can maintain stability better than silicon even at high temperatures. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-3 including the semiconductor layer 105 formed of silicon carbide may have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0296] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0297] A well region 110 may be formed in the semiconductor layer 105 to contact the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the drift region 107.

[0298] For example, the well region 110 may be formed to surround at least a part of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. During the operation of the power semiconductor device 100-3, the vertical portion 107a may provide a vertical movement path for charges.

[0299] Fig.24 The well region 110 shown includes two regions spaced apart from each other and a vertical portion 107a inserted between the two regions, but the well region 110 may be variously changed or modified. For example, the vertical portion 107a may have a shape in which its side is surrounded by the well region 110 at once.

[0300] The field reduction region 111 may be formed to be spaced apart from the well region 110 at a given depth of the semiconductor layer 105 and may have a second conductivity type. The field reduction region 111 may be formed by implanting impurities of the second conductivity type, and the doping concentration of the field reduction region 111 may be the same as or lower than the doping concentration of the well region 110.

[0301] The source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0302] The channel region 110a may be formed in the semiconductor layer 105 between the drift layer 107 and the source region 112. For example, the channel region 110a may have a second conductivity type, and in the operation of the power semiconductor device 100-3, an inversion channel may be formed in the channel region 110a along one direction.

[0303] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when a working voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, allowing charge movement.

[0304] In some embodiments, the channel region 110a may be a part of the well region 110. In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurities of the second conductivity type in the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 to adjust the threshold voltage.

[0305] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first part and a second part, which are formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first part and the second part may be separated from each other or may be connected to each other.

[0306] Alternatively, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0307] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or may be understood as a substrate independent of the semiconductor layer 105.

[0308] At least one trench 116 may be formed that recesses from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and may refer to Fig.25 the direction of line III-III.

[0309] The gate insulating layer 118 may be formed on at least the inner walls of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a part of the gate insulating layer 118 formed on the sidewalls of the trench 116 such that the electric field is reduced at the bottom of the trench 116.

[0310] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof.

[0311] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0312] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may vertically extend in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0313] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on opposite sides of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that extends vertically in the semiconductor layer 105 on opposite sides of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120, between the vertical portion 107a of the drift region 107 and the source region 112.

[0314] The above structure of the channel region 110a may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewalls of the gate electrode layer 120.

[0315] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end portion of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end portion of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0316] The field reduction region 111 may be formed in the semiconductor layer 105 below the bottom surface of the gate electrode layer 120 and spaced apart from the well region 110. More specifically, the field reduction region 111 may be formed in contact with the gate insulating layer 118 below the bottom surface of the gate electrode layer 120 and formed to surround the bottom surface of the trench 116 or the gate electrode layer 120. The field reduction region 111 may have a floating structure in which an external power supply is not directly applied.

[0317] According to this floating structure, the well region 110 may surround the bottom surface of the gate electrode layer 120 at its opposite end portions, and the field reduction region 111 may surround the bottom surface at the central portion of the gate electrode layer 120. Therefore, the structure of the well region 110 and the arrangement of the field reduction region 111 may further alleviate the concentration of the electric field on the bottom surface of the trench 116, i.e., the concentration at the lower portion of the gate electrode layer 120.

[0318] In this way, the electric field margin of the gate insulating layer 118 covering the power semiconductor device 100-3 can be increased, and thus, the operation reliability of the power semiconductor device 100-3 can be improved. Additionally, the junction resistance of the vertical portion 107a of the drift region 107 can be reduced by reducing the electric field on the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0319] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and in addition, may be formed to further extend outside the trench 116.

[0320] In some embodiments, a trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0321] For example, a plurality of trenches 116 may be formed in the semiconductor layer 105 parallel to one direction. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0322] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trenches 116. In this way, the gate electrode layers 120 may be formed in a trench type in the semiconductor layer 105 and may be arranged to extend in parallel in one direction like the trenches 116.

[0323] In addition, the field reduction regions 111 may be respectively provided to contact the gate insulating layer 118 below the bottom surface of the trenches 116 or below the bottom surface of the gate electrode layers 120. In this case, the field reduction regions 111 may collectively refer to a plurality of island regions.

[0324] Additionally, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be arranged in the semiconductor layer 105 between the gate electrode layers 120. The channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0325] The interlayer insulating layer 130 may be formed on the gate electrode layers 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0326] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0327] In the above-mentioned power semiconductor device 100-3, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of n-type and p-type. For example, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0328] More specifically, when the power semiconductor device 100-3 is an N-type MOSFET, the drift region 107 can be an N- region, the source region 112 and the drain region 102 can be N+ regions, and the well region 110, the field reduction region 111, and the channel region 110a can be P- regions.

[0329] In the operation of the power semiconductor device 100-3, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then can flow along the side surface of the gate electrode layer 120 through the channel region 110a to the source region 112.

[0330] In the above-described power semiconductor device 100-3, the gate electrode layers 120 in the trenches 116 can be densely arranged in parallel in a stripe pattern or a linear pattern, and the channel region 110a can be provided on the side surface of the gate electrode layer 120. Therefore, the channel density can be increased.

[0331] Fig.28 and Fig.29 is a cross-sectional view showing a power semiconductor device 100a-3 according to another embodiment of the present disclosure. The power semiconductor device 100a-3 can be implemented by modifying part of the configuration of the power semiconductor device 100-3 in Figure 24 to Figure 27 , and thus, additional description will be omitted to avoid repetition.

[0332] Referring to Fig.28 and 29 , the field reduction region 111a can be provided below the bottom surface of the gate electrode layer 120, that is, can be formed to be spaced apart from the gate insulating layer 118 below the bottom surface of the gate electrode layer 120. In addition, the field reduction region 111a can be arranged in an island structure or a floating structure so as to be surrounded by the drift region 107 below the gate electrode layer 120.

[0333] When a plurality of trenches 116 are provided, the field reduction regions 111a can be respectively provided below the bottom surface of the trenches 116 or below the bottom surface of the gate electrode layer 120 in a floating structure or an island structure.

[0334] Even in the floating structure or the island structure, the field reduction region 111a can be provided below the bottom surface of the trench 116, thereby reducing the electric field concentration on the gate insulating layer 118 on the bottom surface of the trench 116.

[0335] Fig.30 is a cross-sectional view showing a power semiconductor device 100b-3 according to another embodiment of the present disclosure. The power semiconductor device 100b-3 can be implemented by using or partially modifying the power semiconductor device 100-3 or 100a-3 in Figure 24 to Figure 29 , and thus, additional description will be omitted to avoid repetition.

[0336] Reference Fig.30 In the power semiconductor device 100b-3, a channel region 107b may be formed in a semiconductor layer 105 between a drift region 107 and a source region 112. For example, the channel region 107b may have a first conductivity type. During operation of the power semiconductor device 100b-3, an accumulation channel may be formed in the channel region 107b.

[0337] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and a vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0338] In this case, the source region 112, the channel region 107b, and the drift region 107 may be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band of the channel region 107b bends upward. Thus, an accumulation channel that allows charge or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120 may be formed.

[0339] Therefore, the threshold voltage applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be much lower than the threshold voltage applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a in Figures 24 to 28 .

[0340] In some embodiments, the channel region 107b may be a part of the drift region 107. More specifically, the channel region 107b may be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107. In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, the drift region 107 and the source region 112 may be in contact with each other at the channel region (107b) portion.

[0341] The doping concentration of the impurity of the first conductivity type in the channel region 107b may be the same as or different from the doping concentration of the rest of the drift region 107 to adjust the threshold voltage.

[0342] As a modified example of the embodiment, a well region 110 may be formed to protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112, and the channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0343] In addition, the well region 110 may further include a tap portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b may be formed in a curved shape on the protruding portion and the tap portion of the well region 110.

[0344] In addition, the vertical portion 107a of the drift region 107 may further extend between the lower portion of the source region 112 and the well region 110. In this case, the channel region 107b may be formed to further extend between the lower portion of the source region 112 and the well region 110.

[0345] The above structure may allow the channel region 107b to be more restricted between the gate electrode layer 120 and the well region 110.

[0346] The power semiconductor device 100b-3 may include Figures 24 to 28 the advantages of the power semiconductor devices 100-3 and 100a-3 in , and in addition, the threshold voltage may be made lower.

[0347] Fig.31 is a schematic perspective view showing a power semiconductor device 100c-3 according to another embodiment of the present disclosure. Fig.32 is showing along Fig.31 a plan view of the power semiconductor device 100c-3 taken along the line IX-IX of . Fig.33 is showing along Fig.32 a cross-sectional view of the power semiconductor device 100c-3 taken along the line X-X of .

[0348] The power semiconductor device 100c-3 according to an embodiment may be implemented by using or partially modifying the Figure 24 to Figure 27 power semiconductor device 100-3 in . Therefore, additional descriptions will be omitted to avoid repetition.

[0349] Referring to Figure 31 to Figure 33 , in the power semiconductor device 100c-3, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is a part of the source region 112, may refer to the portion connected to the source electrode layer 140.

[0350] A well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source region 112 and may have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 may be formed in the source contact region 112a.

[0351] For example, the well contact region 114 may be doped with a second conductivity type impurity having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0352] The source electrode layer 140 may be commonly connected to the source contact region 112a and the well contact region 114.

[0353] The source contact region 112a and the well contact region 114 may be formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. In a modified example of the embodiment, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0354] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other along one direction. In this way, the gate electrode layers 120 may also be arranged to be linearly spaced apart from each other along the trenches 116 in this one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from each other along this one direction.

[0355] For example, the power semiconductor device 100c-3 may be formed by arranging the structure of the power semiconductor device 100-3 in Figure 24 to Figure 27 one direction and arranging the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 therebetween.

[0356] For example, when the power semiconductor device 100-3 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0357] According to the power semiconductor device 100c-3, the source contact region 112a and the well contact region 114 may be provided outside the gate electrode layer 120, rather than between the gate electrode layers 120, so that the gate electrode layers 120 may be arranged more densely. In this way, the channel density of the power semiconductor device 100a-3 can be significantly increased.

[0358] Meanwhile, the structure of the power semiconductor device 100c-3 may be applied to Fig.28 and Fig.29 the power semiconductor device 100a-3 in Fig.30 and the power semiconductor device 100b-3 in

[0359] Fig.34It is a cross-sectional view showing a power semiconductor device 100d-3 according to another embodiment of the present disclosure. It can be achieved by modifying Figure 31 to Figure 33 a partial configuration of the power semiconductor device 100c-3 in . Therefore, additional descriptions will be omitted to avoid repetition.

[0360] Referring to Fig.34 , the power semiconductor device 100d-3 may include at least one groove 138 in a source contact region 112a of a source region 112. The groove 138 is formed to penetrate the source region 112 and recess into a well region 110. A well contact region 114a may be formed to contact the well region 110 on at least a bottom surface of the groove 138.

[0361] A source electrode layer 140a may be formed to fill the groove 138 and may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure can widen a contact area between the source electrode layer 140a and the well region 110 and a contact area between the source electrode layer 140a and the source region 112, so that a contact resistance therebetween is reduced.

[0362] In some embodiments, the well contact region 114a may be formed on an entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a may be formed on the well region 110 exposed from a bottom surface and sidewalls of the groove 138. The above structure of the well contact region 114a can allow a contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0363] Meanwhile, a field reduction region 111 may be set to contact a gate insulating layer 118, but may be modified to be spaced apart from the gate insulating layer 118 downward.

[0364] Figure 35 to Figure 37 It is a schematic perspective view showing a method of manufacturing a power semiconductor device 100-3 according to an embodiment of the present disclosure.

[0365] Referring to Fig.35 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be implemented with a substrate of the first conductivity type, and the drift region 107 may be formed on the substrate with one or more epitaxial layers.

[0366] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 can be performed by implanting impurities having a second conductivity type into the semiconductor layer 105. The well region 110 can be formed substantially from the surface of the semiconductor layer 105 to a given depth.

[0367] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a part of which is surrounded by the well region 110. More specifically, the well region 110 can be formed by doping impurities having a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0368] Before or after the formation of the well region 110, a field reduction region 111 having a second conductivity type can be formed at a given depth of the semiconductor layer 105 so that the field reduction region 111 is spaced apart from the well region 110. For example, the field reduction region 111 can be formed by implanting impurities of a second conductivity type into the semiconductor layer 105.

[0369] Then, a source region 112 having a first conductivity type can be formed in the well region 110. For example, the source region 112 can be formed by implanting impurities of a first conductivity type into the well region 110. The source region 112 can be formed in the well region 110 substantially from the surface of the semiconductor layer 105 to a given depth.

[0370] In addition to the formation of the source region 112, a channel region 110a having an inverted channel formed in one direction can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a can be a part of the well region 110 and can be formed by implanting impurities of a second conductivity type into the semiconductor layer 105.

[0371] In a modified example of the embodiment, the order of doping impurities in the well region 110, the source region 112, the channel region 110a, and the field reduction region 111 can be arbitrarily changed.

[0372] In the above manufacturing method, impurity implantation or impurity doping can be performed such that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern can be used to implant impurities in a selected region.

[0373] Optionally, a heat treatment process for activating or diffusing the impurities can be performed after the ion implantation.

[0374] Refer to Fig.36, at least one trench 116 can be formed to recess into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth.

[0375] For example, the trench 116 can extend across the drift region 107 in one direction and can be formed shallower than the well region 110.

[0376] In addition, the at least one trench 116 can include a plurality of trenches 116, and for example, the trenches 116 can be formed in parallel in the semiconductor layer 105 in one direction at the same time. The channel region 110a can be further restricted by the trenches 116.

[0377] For example, the trench 116 can be formed by: forming a photomask by using photolithography and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0378] Referring to Fig.37 , a gate insulating layer 118 can be formed on the bottom and inner walls of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0379] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 can be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 can be formed by doping impurities in polysilicon or can be formed to include a conductive metal or a metal silicide.

[0380] The patterning process can be performed by using a photolithography process and an etching process. The photolithography process can include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process can include a process of selectively etching a lower layer structure by using the photoresist pattern.

[0381] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120. And, the field reduction region 111 can be arranged to contact the gate insulating layer 118 below the bottom surface of the gate electrode layer 120.

[0382] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120.

[0383] Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer (e.g., a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0384] Meanwhile, Fig.30 the power semiconductor device 100b-3 in

[0384] can be manufactured by adding some processes to or changing or modifying the manufacturing method of the above power semiconductor device 100-3. For example, the channel region 107b can be formed with a part of the drift region 107 to form an accumulation channel.

[0385] Figure 31 to Figure 33 the power semiconductor device 100c-3 of Figure 31 to Figure 33 can be manufactured by adding some processes to or changing or modifying the manufacturing method of the above power semiconductor device 100-3.

[0386] For example, when manufacturing the power semiconductor device 100c-3, the formation of the source region 112 can include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a can be a part of the source region 112.

[0387] In addition, before forming the trench 116, a well contact region 114 can be formed in the source contact region 112a. For example, the well contact region 114 can be formed by implanting impurities of a second conductivity type with a concentration higher than that of the well region 110 into a part of the well region 110.

[0388] When manufacturing the power semiconductor device 100c-3, the trenches 116 can be arranged to be spaced apart linearly from each other in one direction. In addition, the well region 110, the channel region 110a, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116.

[0389] Referring to Fig.34 the method of manufacturing the power semiconductor device 100d-3 described, it can further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and recess into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 to contact the well region 110, and forming a source electrode layer 140 to connect to the well region 114.

[0390] According to the above manufacturing method, a power semiconductor device 100-3 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using processes applied to a conventional silicon substrate.

[0391] Fig.38 is a schematic perspective view showing a power semiconductor device 100-4 according to an embodiment of the present disclosure. Fig.39 is a plan view of the power semiconductor device 100-4 taken along line II-II shown in Fig.38 . Fig.38 . Fig.40 is a cross-sectional view of the power semiconductor device 100-4 taken along line III-III shown in Fig.39 . Fig.41 is a cross-sectional view of the power semiconductor device 100-4 taken along line IV-IV shown in Fig.39 .

[0392] Referring to Figures 38 to 41 , the power semiconductor device 100-4 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-4 may have a power MOSFET structure.

[0393] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers. For example, it may refer to one epitaxial layer or multiple epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0394] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0395] The bandgap of silicon carbide (SiC) may be wider than that of silicon, so it maintains stability better than silicon even at high temperatures. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-4 including the semiconductor layer 105 formed of silicon carbide may have a high breakdown voltage and may provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0396] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0397] A well region 110 may be formed in the semiconductor layer 105 to contact the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of the second conductivity type opposite to the first conductivity type in the drift region 107.

[0398] For example, the well region 110 may be formed to surround at least a portion of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, at least a portion of which is surrounded by the well region 110. During the operation of the power semiconductor device 100-4, the vertical portion 107a may provide a vertical movement path for charges.

[0399] In Fig.38 the well region 110 shown includes two regions spaced apart from each other and a vertical portion 107a inserted therebetween, but the well region 110 may be variously changed or modified. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110 at once.

[0400] The source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0401] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type, and during the operation of the power semiconductor device 100-4, an inversion channel may be formed in the channel region 110a along one direction.

[0402] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not normally allow charges to move; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, allowing charges to move.

[0403] In some embodiments, the channel region 110a may be a part of the well region 110. In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurities of the second conductivity type in the channel region 110a may be the same as or different from that of the rest of the well region 110 for threshold voltage adjustment.

[0404] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be symmetrically formed with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0405] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107, and the drain region 102 may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0406] In some embodiments, the drain region 102 may be implemented with a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105, or may be understood as a substrate independent of the semiconductor layer 105.

[0407] At least one trench 116 may be formed that recesses from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and may refer to Fig.39 the direction of line III-III or line IV-IV.

[0408] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a part of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0409] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof.

[0410] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0411] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may vertically extend in the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Accordingly, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0412] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that vertically extends in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0413] The above structure of the channel region 110a may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0414] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0415] This well (110) structure may further alleviate the electric field concentration on the bottom surface of the trench 116 (i.e., below the gate electrode layer 120). In addition, a deep well region 111 may be provided below the well region 110 so as to further reduce the electric field covering the gate insulating layer 118 and the electric field on the bottom surface of the trench 116. In this way, the margin of the electric field covering the gate insulating layer 118 of the power semiconductor device 100-4 may be increased, and thus, the reliability of the operation of the power semiconductor device 100-4 may be improved. Additionally, the junction resistance of the vertical portion 107a of the drift region 107 may be reduced by reducing the electric field on the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0416] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and in addition, may be formed to further extend to the outside of the trench 116.

[0417] In some embodiments, one or more trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0418] For example, multiple trenches 116 may be formed parallel to each other in the semiconductor layer 105 in one direction. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0419] In this case, multiple gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trenches 116. In this way, trench-type gate electrode layers 120 may be formed in the semiconductor layer 105 and may be arranged to extend in parallel in the one direction, similar to the trenches 116.

[0420] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0421] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120, so as to contact the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at the opposite ends of the gate electrode layer 120.

[0422] An interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0423] A source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0424] In addition, the source electrode layer 140 may contact a portion of the drift region 107 to form a Schottky barrier diode (SBD). The Schottky barrier diode SBD may refer to a diode that uses a Schottky barrier through the junction of a semiconductor and a metal.

[0425] In addition to the Schottky barrier diode (SBD), a parasitic diode can be formed in the power semiconductor device 100-4. For example, a body diode can be formed between the well region 110 and the drift region 107. The body diode can be a PN diode formed when different types of semiconductor materials are combined together.

[0426] From Fig.48 It can be understood that, compared with the PN diode, the Schottky barrier diode (SBD) has a low forward voltage VF and fast switching characteristics.

[0427] In the operation of the power semiconductor device 100-4, the Schottky barrier diode (SBD) can reduce the switching loss together with the body diode. For example, the Schottky barrier diode (SBD) and the body diode can be used as freewheeling diodes in the operation of the power semiconductor device 100-4.

[0428] In some embodiments, the source region 112 can include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a can refer to the region of the semiconductor layer 105 connected to the source electrode layer 140.

[0429] For example, the source contact region 112a can include a part of the source region 112 outside at least one end of the gate electrode layer 120, a part of the well region 110, and a protruding portion 107c of the drift region 107 exposed from the well region 110.

[0430] A well contact region 114 can be formed on a part of the well region 110 in the source contact region 112a and can have a second conductivity type. For example, one well contact region 114 or multiple well contact regions 114 can be formed in the source contact region 112a. In addition, the well contact region 114 can be doped with impurities of the second conductivity type having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0431] The source electrode layer 140 can be connected to the source contact region 112a and thus can be commonly connected to the source region 112, the well contact region 114, and the protruding portion 107c of the drift region 107.

[0432] In some embodiments, a plurality of trenches 116 can be arranged to be linearly spaced apart from each other along one direction. In this way, the gate electrode layers 120 can also be arranged to be linearly spaced apart from each other along the trenches 116 in this one direction. In this case, the well region 110, the source region 112, the source contact region 112a, the Schottky barrier diode (SBD), and the well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from each other along this one direction.

[0433] In the above-mentioned power semiconductor device 100-4, the first conduction type and the second conduction type can be opposite to each other, and each of the first conduction type and the second conduction type can be one of n-type and p-type. For example, when the first conduction type is n-type, the second conduction type is p-type, and vice versa.

[0434] More specifically, when the power semiconductor device 100-4 is an N-type MOSFET, the drift region 107 can be an N- region, the source region 112 and the drain region 102 can be N+ regions, the well region 110 and the channel region 110a can be P- regions, and the well contact region 114 can be a P+ region.

[0435] In the operation of the power semiconductor device 100-4, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then flow through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0436] In the above-mentioned power semiconductor device 100-4, the gate electrode layers 120 in the trenches 116 can be densely arranged in parallel in a stripe pattern or a linear pattern, and the channel region 110a can be disposed on the side surface of the gate electrode layer 120. Therefore, the channel density can be increased.

[0437] According to the power semiconductor device 100-4, the source contact region 112a and the well contact region 114 can be arranged outside the gate electrode layer 120 instead of between the gate electrode layers 120, so that the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100-4 can be significantly increased.

[0438] Fig.42 and Fig.43 is a cross-sectional view showing a power semiconductor device 100a-4 according to another embodiment of the present disclosure. The power semiconductor device 100a-4 according to the embodiment can be implemented by modifying Figures 38 to 41 a part of the configuration of the power semiconductor device 100-4 in. Therefore, additional descriptions will be omitted to avoid repetition.

[0439] Referring to Fig.42 and Fig.43 , the power semiconductor device 100a-4 can include at least one groove 138, which is formed by etching a part of the drift region 107 (e.g., the protruding portion 107c), a part of the source region 112, and a part of the well region 110. For example, the groove 138 can be formed by etching Figures 38 to 41 the source contact region 112a in the power semiconductor device 100-4 of.

[0440] A well contact region 114a may be formed on a portion of the well region 110 exposed from the groove 138. For example, the well contact region 114a may be formed on a portion of the well region 110 corresponding to the bottom surface of the groove 138. The well contact region 114a may have a second conductivity type and may be more heavily doped than the well contact region 114.

[0441] A source electrode layer 140a may be formed to fill the groove 138 and may commonly contact the well contact region 114a, the protruding portion 107c of the drift region 107, and the source region 112 within the groove 138. The contact between the protruding portion 107c of the drift region 107 and the source electrode layer 140 may form a Schottky barrier diode SBD.

[0442] The above structure may widen the contact area between the source electrode layer 140a and the source region 112 and the well contact region 114a, such that the contact resistance therebetween is reduced.

[0443] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0444] Fig.44 is a schematic cross-sectional view showing a power semiconductor device 100b-4 according to another embodiment of the present disclosure. The power semiconductor device 100b-4 according to the embodiment may be implemented by modifying Figures 38 to 41 a partial configuration of the power semiconductor device 100-4 in. Thus, additional description will be omitted to avoid repetition.

[0445] Referring to Fig.44 , replacing Figures 38 to 41 the channel region 110a of the power semiconductor device 100-4 in, the power semiconductor device 100b-4 may include a channel region 107b that forms an accumulation channel.

[0446] In the power semiconductor device 100b-4, the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type, and during operation of the power semiconductor device 100b-4, an accumulation channel may be formed in the channel region 107b.

[0447] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0448] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band in the channel region 107b bends upward. Thus, an accumulation channel that allows charges or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120 can be formed.

[0449] Therefore, the threshold voltage applied to the gate electrode layer 120 to form the accumulation channel in the channel region 107b can be much lower than the threshold voltage applied to the gate electrode layer 120 to form the Figures 38 to 41 inversion channel of the channel region 110a.

[0450] In some embodiments, the channel region 107b can be a part of the drift region 107. More specifically, the channel region 107b can be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b can be formed integrally with the drift region 107. In this case, the drift region 107 can be connected to the source region 112 through the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 can be in contact with each other.

[0451] The doping concentration of the impurity of the first conductivity type in the channel region 107b can be the same as or different from the doping concentration of the rest of the drift region 107 to adjust the threshold voltage.

[0452] As a modified example of the embodiment, the well region 110 can be formed to protrude farther toward the vertical portion 107a of the drift region 107 than a part of the source region 112, and the channel region 107b can be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0453] In addition, the well region 110 can further include a tap portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b can be formed in a curved shape on the protruding portion and the tap portion of the well region 110.

[0454] Furthermore, the vertical portion 107a of the drift region 107 can extend further between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed to extend further between the lower part of the source region 112 and the well region 110.

[0455] The above structure can allow the channel region 107b to be more restricted between the gate electrode layer 120 and the well region 110.

[0456] The power semiconductor device 100b-4 can include Figures 38 to 41 In addition, the power semiconductor device 100-4 in has the advantage that the threshold voltage can be made lower.

[0457] Figure 45 to Figure 47 FIG. 5 is a schematic perspective view showing a method of manufacturing a power semiconductor device 100-4 according to an embodiment of the present disclosure.

[0458] Referring to Fig.45 , a drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented with a substrate of the first conductivity type, and the drift region 107 can be formed with one or more epitaxial layers on the substrate.

[0459] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to be in contact with the drift region 107. For example, the formation of the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0460] For example, the well region 110 can be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. More specifically, the well region 110 can be formed by doping impurities of a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0461] Then, a source region 112 having a first conductivity type can be formed in the well region 110. For example, the source region 112 can be formed by implanting impurities of the first conductivity type into the well region 110.

[0462] In addition to forming the source region 112, a channel region 110a having an inversion channel formed in one direction can be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110a can be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a is a part of the well region 110, and can be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0463] In addition, when the source region 112 is formed, a source contact region 112a including a part of the source region 112, a part of the well region 110, and a protruding portion 107c of the drift region 107 exposed from the well region 110 can be formed at least outside one end of the gate electrode layer 120.

[0464] Alternatively, a well contact region 114 having a second conductivity type and being more highly doped than the well region 110 may be formed on a part of the well region 110. For example, the well contact region 114 may be formed by implanting impurities of the second conductivity type having a higher concentration than the well region 110 into a part of the well region 110.

[0465] In the above steps, impurity implantation or impurity doping may be performed such that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selected region.

[0466] Optionally, a heat treatment process for activating or diffusing the impurities may be performed after the ion implantation.

[0467] Referring to Fig.46 , at least one trench 116 may be formed to recess into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth.

[0468] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110.

[0469] Alternatively, the at least one trench 116 may include a plurality of trenches 116, and for example, the trenches 116 may be formed in parallel in the semiconductor layer 105 in one direction at the same time. The channel region 110a may be further restricted by the trenches 116.

[0470] For example, the trench 116 may be formed by using photolithography to form a photomask and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0471] In some embodiments, the trenches 116 may be arranged to be linearly spaced apart from each other in one direction. Additionally, the well region 110, the channel region 110a, and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116.

[0472] Referring to Fig.47 , a gate insulating layer 118 may be formed at least on the inner walls of the trenches 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0473] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trenches 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities in polysilicon or may be formed to include a conductive metal or a metal silicide.

[0474] The patterning process can be performed by using a photolithography process and an etching process. The photolithography process can include a process of forming a photoresist pattern as a mask layer by using a light process and a development process, and the etching process can include a process of selectively etching an underlying structure by using the photoresist pattern.

[0475] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0476] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120.

[0477] Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0478] For example, the source electrode layer 140 can be connected to the source region 112 and can be in contact with a part of the drift region 107. Therefore, a Schottky barrier diode SBD can be formed. In some embodiments, the source electrode layer 140 can be connected to the source contact region 112a, so as to be in common contact with the source region 112, the well contact region 114, and the protruding part 107c of the drift region 107.

[0479] Fig.42 and Fig.43 The power semiconductor device 100a-4 can be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-4 or changing or modifying the manufacturing method. For example, the manufacturing method of the power semiconductor device 100a-4 can further include: forming at least one groove 138 by etching a part of the drift region 107 (such as the protruding part 107a of the drift region 107), a part of the source region 112, and a part of the well region 110; forming a well contact region 114 on a part of the well region 110 corresponding to the bottom surface of the groove 138, and forming a source electrode layer 140 connected to the source region 112, the protruding part 107c of the drift region 107, and the well contact region 114 by filling the groove 138.

[0480] Meanwhile, Fig.44 the power semiconductor device 100b-4 can be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-4 or changing or modifying the manufacturing method. For example, a channel region 107b can be formed with a part of the drift region 107 so as to form an accumulation channel.

[0481] According to the above manufacturing method, a power semiconductor device 100-4 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0482] Fig.49 FIG. 6 is a schematic perspective view showing a power semiconductor device 100-5 according to an embodiment of the present disclosure. Fig.50 FIG. 7 is a plan view showing the power semiconductor device 100-5 taken along line II-II. Fig.49 FIG. 8 is a plan view showing the power semiconductor device 100-5 taken along line II-II. Fig.51 FIG. 9 is a cross-sectional view showing the power semiconductor device 100-5 taken along line III-III. Fig.50 FIG. 10 is a cross-sectional view showing the power semiconductor device 100-5 taken along line III-III.

[0483] Referring to FIGS. 11 to 13, the power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure. Figures 49 to 51 Referring to FIGS. 11 to 13, the power semiconductor device 100-5 may include at least a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-5 may have a power MOSFET structure.

[0484] The semiconductor layer 105 may refer to one semiconductor material layer or a plurality of semiconductor material layers. For example, it may refer to one epitaxial layer or a plurality of epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0485] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0486] The bandgap of silicon carbide (SiC) may be wider than that of silicon, so it maintains stability better than silicon even at high temperatures. Additionally, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-5 including the semiconductor layer 105 formed of silicon carbide may have a high breakdown voltage and may provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0487] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type into an epitaxial layer of silicon carbide.

[0488] A well region 110 may be formed in the semiconductor layer 105 to contact the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of the second conductivity type opposite to the first conductivity type into the drift region 107.

[0489] For example, the well region 110 may be formed to surround at least a part of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. During the operation of the power semiconductor device 100-5, the vertical portion 107a may provide a vertical movement path for charges.

[0490] The well region 110 is Fig.49 shown in as including two regions separated from each other and a vertical portion 107a inserted between the two regions, but the well region 110 may be variously changed or modified. For example, the vertical portion 107a may have a shape in which its sides are surrounded by the well region 110 at once.

[0491] A deep well region 111 may be formed below the well region 110 to contact the well region 110 and the drift region 107. Like the well region 110, the deep well region 111 may have a second conductivity type. The doping concentration of the impurities of the second conductivity type in the deep well region 111 may be equal to or lower than the doping concentration of the impurities of the second conductivity type in the well region 110.

[0492] For example, the deep well region 111 may be formed to have a width narrower than the width of the well region 110 based on one direction. One direction may refer to the Fig.50 direction of line III-III. In addition, the opposite ends of the deep well region 111 may be arranged to be inwardly offset from the opposite ends of the well region 110 based on one direction.

[0493] In this way, below the well region 110, the deep well region 111 may be arranged to retreat inward from the opposite ends of the well region 110 in a state of contacting the well region 110. The lower surface and the side surface of the deep well region 111 may contact the drift region 107.

[0494] For example, when the deep well region 111 is formed in two regions spaced apart from each other like the well region 110, the spacing distance between the two deep well regions 111 may be greater than the spacing distance between the two well regions 110.

[0495] The source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0496] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type, and during the operation of the power semiconductor device 100-5, an inversion channel may be formed in the channel region 110a along one direction.

[0497] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when a working voltage is applied to the gate electrode layer 120, an inversion channel can be formed therein, thereby allowing charge movement.

[0498] In some embodiments, the channel region 110a can be part of the well region 110. In this case, the channel region 110a can be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurities of the second conductivity type in the channel region 110a can be the same as or different from that of the rest of the well region 110 to adjust the threshold voltage.

[0499] In some embodiments, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 can be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the deep well region 111, the channel region 110a, and the source region 112 can be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the deep well region 111, the channel region 110a, and the source region 112 can include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the deep well region 111, the channel region 110a, and the source region 112, the first portion and the second portion can be separated from each other or can be connected to each other.

[0500] In addition, the drain region 102 can be formed in the semiconductor layer 105 below the drift region 107 and can have a first conductivity type. For example, compared with the drift region 107, the drain region 102 can be doped with a high concentration of impurities.

[0501] In some embodiments, the drain region 102 can be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 can be understood as part of the semiconductor layer 105 or can be understood as a substrate independent of the semiconductor layer 105.

[0502] At least one trench 116 can be formed that recesses into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth. The trench 116 can extend in one direction within the semiconductor layer 105. One direction can refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and can refer to Fig.50 the direction of line III-III.

[0503] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench. The thickness of the gate insulating layer 118 may be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a part of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0504] For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof.

[0505] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0506] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. A channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0507] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that extends vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0508] The above structure of the channel region 110a may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0509] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0510] This well (110) structure may further alleviate the electric field concentration on the bottom surface of the trench 116 (i.e., below the gate electrode layer 120). In addition, a deep well region 111 may be provided below the well region 110, thereby further reducing the electric field covering the gate insulating layer 118 and the electric field of the bottom surface of the trench 116. In this way, the margin of the electric field covering the gate insulating layer 118 of the power semiconductor device 100-5 may be increased, and thus, the reliability of the operation of the power semiconductor device 100-5 may be improved. Additionally, the junction resistance of the vertical portion 107a of the drift region 107 may be reduced by reducing the electric field of the bottom surface of the trench 116 and reducing the electric field covering the gate insulating layer 118.

[0511] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and in addition, may be formed to further extend to the outside of the trench 116.

[0512] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0513] For example, a plurality of trenches 116 may be formed in parallel in one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0514] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trench 116. In this way, a trench-type gate electrode layer 120 may be formed in the semiconductor layer 105 and may be arranged to extend in parallel in the one direction as the trench 116.

[0515] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be arranged in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0516] In some embodiments, the well region 110 may be formed deeper than the gate electrode layer 120 in the semiconductor layer 105, so as to contact the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at opposite ends of the gate electrode layer 120.

[0517] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0518] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0519] In the above-described power semiconductor device 100-5, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of n-type and p-type. For example, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0520] More specifically, when the power semiconductor device 100-5 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110, the deep well region 111, and the channel region 110a may be P- regions.

[0521] In the operation of the power semiconductor device 100-5, current may generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then may flow through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0522] In the above-described power semiconductor device 100-5, the gate electrode layers 120 in the trenches 116 may be densely arranged in parallel in a stripe type or a line type, and the channel region 110a may be provided on the side surface of the gate electrode layer 120. Therefore, the channel density can be increased.

[0523] Fig.52 is a perspective view showing a power semiconductor device 100a-5 according to another embodiment of the present disclosure.

[0524] The power semiconductor device 100a-5 according to an embodiment may be implemented by using or partially modifying Figures 49 to 51 the power semiconductor device 100-5 therein. Therefore, additional description will be omitted to avoid repetition.

[0525] Refer to Fig.52, in the power semiconductor device 100a-5, the channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type, and an accumulation channel can be formed in the channel region 107b during the operation of the power semiconductor device 100a-5.

[0526] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0527] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of the negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band in the channel region 107b bends upward. Thus, an accumulation channel can be formed that allows charge or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120.

[0528] Therefore, the threshold voltage applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b can be much lower than the threshold voltage applied to the gate electrode layer 120 to form Figures 49 to 51 an inversion channel in the channel region 110a.

[0529] In some embodiments, the channel region 107b can be a part of the drift region 107. More specifically, the channel region 107b can be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b can be formed integrally with the drift region 107. In this case, the drift region 107 can be connected to the source region 112 through the channel region 107b. That is, in the channel region (107b) part, the drift region 107 and the source region 112 can be in contact with each other.

[0530] The doping concentration of the first conductivity type impurity in the channel region 107b can be the same as or different from the doping concentration of the rest of the drift region 107 to adjust the threshold voltage.

[0531] As a modified example of the embodiment, the well region 110 can be formed to protrude further into the vertical portion 107a of the drift region 107 than a part of the source region 112, and the channel region 107b can be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0532] In addition, the well region 110 can further include a tap portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b can be formed in a curved shape on the protruding portion and the tap portion of the well region 110.

[0533] In addition, the vertical portion 107a of the drift region 107 can further extend between the lower portion of the source region 112 and the well region 110. In this case, the channel region 107b can be formed to further extend between the lower portion of the source region 112 and the well region 110.

[0534] The above structure can allow for more confinement of the channel region 107b between the gate electrode layer 120 and the well region 110.

[0535] The power semiconductor device 100a-5 can include Figures 49 to 51 the advantages of the power semiconductor device 100-5, and in addition, the threshold voltage can be made low.

[0536] Fig.53 is a schematic perspective view showing a power semiconductor device 100b-5 according to another embodiment of the present disclosure. Fig.54 is showing along Fig.53 a plan view of the power semiconductor device 100b-5 taken along line VI-VI. Fig.55 is showing along Fig.54 a cross-sectional view of the power semiconductor device 100b-5 taken along line VII-VII. Figure 56 is showing along Figure 54 a cross-sectional view of the power semiconductor device 100b-5 taken along line VIII-VIII.

[0537] The power semiconductor device 100b-5 according to an embodiment can be implemented by using or partially modifying Figures 49 to 51 the power semiconductor device 100-5 in. Therefore, additional description will be omitted to avoid repetition.

[0538] Referring to Figures 53 to 56 , in the power semiconductor device 100b-5, the source region 112 can include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, can refer to the portion connected to the source electrode layer 140.

[0539] A well contact region 114 can be formed in the source contact region 112a. For example, the well contact region 114 can extend from the well region 110 to penetrate the source region 112 and can have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 can be formed in the source contact region 112a.

[0540] For example, the well contact region 114 can be doped with impurities of the second conductivity type having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0541] The source electrode layer 140 may be commonly connected to the source contact region 112a and the well contact region 114.

[0542] In Figures 53 to 56 an example is shown where the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0543] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other in one direction. Thus, the gate electrode layers 120 may also be arranged to be linearly spaced apart from each other in the one direction along the trenches 116. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from each other in the one direction.

[0544] For example, the power semiconductor device 100b-5 may be formed by arranging the structure of the power semiconductor device 100-5 in one direction and by arranging the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 therebetween. Figures 49 to 51

[0545] For example, when the power semiconductor device 100-5 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0546] According to the power semiconductor device 100b-5, the source contact region 112a and the well contact region 114 may be provided outside the gate electrode layer 120 instead of between the gate electrode layers 120. Thus, the gate electrode layers 120 may be arranged more densely. In this way, the channel density of the power semiconductor device 100b-5 may be significantly increased.

[0547] Figure 57 and Figure 58 are cross-sectional views showing power semiconductor devices 100c-5 and 100d-5 according to other embodiments of the present disclosure.

[0548] Referring to Figure 57 , the power semiconductor device 100c-5 may include at least one groove 138 in the source contact region 112a of the source region 112, the groove 138 being formed to penetrate the source region 112 and recessed into the well region 110. The well contact region 114a may be formed on at least the bottom surface of the groove 138 so as to contact the well region 110.

[0549] ​A source electrode layer 140a can be formed to fill the groove 138 and can be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure can widen the contact area between the source electrode layer 140a and the well region 110, as well as the contact area between the source electrode layer 140a and the source region 112, so that the contact resistance therebetween is reduced.

[0550] In some embodiments, the well contact region 114a can be formed on the entire surface of the well region 110 exposed by the groove 138. Therefore, the well contact region 114a can be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above structure of the well contact region 114a can allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0551] Referring to Figure 58 , replacing Figures 53 to 56 the channel region 110a of the power semiconductor device 100b-5, the power semiconductor device 100d-5 can include a channel region 107b that forms an accumulation channel. The above structure of the structure of the power semiconductor device 100d-5 including the channel region 107b can refer to the description given in Figure 52 .

[0552] Therefore, the power semiconductor device 100d-5 can correspond to the following structure: wherein Figure 52 the power semiconductor device 100a-5 is connected in multiple and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 are provided therebetween.

[0553] Figures 59 to 61 is a schematic perspective view showing a method of manufacturing a power semiconductor device 100-5 according to an embodiment of the present disclosure.

[0554] Referring to Figure 59 , a drift region 107 having a first conductivity type can be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 can be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 can be implemented with a substrate of the first conductivity type, and the drift region 107 can be formed on the substrate with one or more epitaxial layers.

[0555] Next, a well region 110 having a second conductivity type can be formed in the semiconductor layer 105 so as to contact the drift region 107. For example, the formation of the well region 110 can be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0556] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. More specifically, the well region 110 may be formed by doping impurities of a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0557] Next, below the well region 110, a deep well region 111 of a second conductivity type may be formed in contact with the well region 110 and the drift region 107. The deep well region 111 may be formed by implanting impurities of the same second conductivity type as the well region 110. The well region 110 and the deep well region 111 may be formed in any order.

[0558] Then, a source region 112 of a first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0559] In addition to forming the source region 112, a channel region 110a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110a may be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be a part of the well region 110 and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0560] In the above manufacturing method, impurity implantation or impurity doping may be performed such that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selected region.

[0561] Optionally, a heat treatment process for activating or diffusing the impurities may be performed after the ion implantation.

[0562] Referring to Figure 60 , at least one trench 116 may be formed to recess from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0563] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110.

[0564] In addition, at least one trench 116 may include a plurality of trenches 116, and for example, the trenches 116 may be formed in parallel in one direction in the semiconductor layer 105 at the same time. The channel region 110a may be further restricted by the trenches 116.

[0565] For example, a trench 116 can be formed by forming a photomask using photolithography and then etching the semiconductor layer 105 using the photomask as an etching protection layer.

[0566] Referring to Figure 61 , a gate insulating layer 118 can be formed on the bottom and inner wall of the trench 116. For example, the gate insulating layer 118 can be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0567] Next, a gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 can be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 can be formed by doping impurities in polysilicon or can be formed to include a conductive metal or a metal silicide.

[0568] The patterning process can be performed by using a photolithography and an etching process. The photolithography process can include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process can include a process of selectively etching an underlying structure by using the photoresist pattern.

[0569] In this way, the well region 110 can be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0570] Next, an interlayer insulating layer 130 can be formed on the gate electrode layer 120.

[0571] Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0572] Meanwhile, Figure 52 the power semiconductor device 100a-5 in can be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-5 or by changing or modifying the manufacturing method. For example, the channel region 107b can be formed with a part of the drift region 107 so as to form an accumulation channel.

[0573] Figures 53 to 56 the power semiconductor device 100b-5 in can be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-5 or by changing or modifying the manufacturing method.

[0574] For example, when manufacturing the power semiconductor device 100b-5, forming the source region 112 may include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be a part of the source region 112.

[0575] In addition, before forming the trench 116, a well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may be formed by implanting impurities of a second conductivity type having a higher concentration than the well region 110 into a part of the well region 110.

[0576] When manufacturing the power semiconductor device 100b-5, the trenches 116 may be arranged to be spaced apart linearly from each other in one direction. In addition, the well region 110, the channel region 110a, and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116.

[0577] Referring to Figure 57 the description, the manufacturing method of the power semiconductor device 100c-5 may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and recess into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 such that the well contact region 114 contacts the well region 110, and forming a source electrode layer 140 to be connected to the well contact region 114.

[0578] According to the above manufacturing method, a power semiconductor device 100-5 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0579] Figure 62 is a schematic perspective view showing a power semiconductor device 100-6 according to an embodiment of the present disclosure. Figure 63 is showing along Figure 62 the plan view of the power semiconductor device 100-6 taken along line II-II. Figure 64 is showing along Figure 63 the cross-sectional view of the power semiconductor device 100-6 taken along line III-III.

[0580] Referring to Figures 62 to 64 , the power semiconductor device 100-6 may at least include a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-6 may have a power MOSFET structure.

[0581] The semiconductor layer 105 may refer to a single semiconductor material layer or multiple semiconductor material layers. For example, it may refer to a single epitaxial layer or multiple epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0582] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0583] Silicon carbide (SiC) may have a wider bandgap than silicon, and thus can maintain stability even at high temperatures compared to silicon. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared to the case of using silicon, the power semiconductor device 100-6 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0584] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0585] A well region 110 may be formed in the semiconductor layer 105 to contact the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of the second conductivity type, which is opposite to the first conductivity type, in the drift region 107.

[0586] For example, the well region 110 may be formed to surround at least a part of the drift region 107. In this way, the drift region 107 may include a vertical portion 107a, and at least a part of the vertical portion 107a is surrounded by the well region 110. During the operation of the power semiconductor device 100-6, the vertical portion 107a may provide a vertical movement path for charges.

[0587] The well region 110 is shown in Figure 62 as including two regions spaced apart from each other and a vertical portion 107a inserted between the two regions, but the well region 110 may be variously changed or modified. For example, the vertical portion 107a may have a shape in which its side is surrounded by the well region 110 once.

[0588] A source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0589] The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 110a may have a second conductivity type, and during the operation of the power semiconductor device 100-6, an inversion channel may be formed in the channel region 110a along one direction. One direction may refer to Figure 63 the direction of line III-III.

[0590] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a may form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when an operating voltage is applied to the gate electrode layer 120, an inversion channel may be formed therein, allowing charge movement.

[0591] In some embodiments, the channel region 110a may be part of the well region 110. In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurities of the second conductivity type in the channel region 110a may be the same as or different from the doping concentration of the rest of the well region 110 for threshold voltage adjustment.

[0592] In some embodiments, the well region 110, the channel region 110a, and the source region 112 may be formed symmetrically with respect to the vertical portion 107a of the drift region 107. For example, the well region 110, the channel region 110a, and the source region 112 may be formed at opposite ends of the vertical portion 107a of the drift region 107, or each of the well region 110, the channel region 110a, and the source region 112 may include a first portion and a second portion formed symmetrically with respect to the vertical portion 107a of the drift region 107. In each of the well region 110, the channel region 110a, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0593] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0594] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as part of the semiconductor layer 105 or may be understood as a substrate independent of the semiconductor layer 105.

[0595] At least one trench 116 can be formed that recesses from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth. The trench 116 can extend in one direction within the semiconductor layer 105. One direction can refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and can refer to Figure 63 the direction of line III-III of

[0596] A gate insulating layer 118 can be formed on the bottom surface and inner walls of the trench 116. For example, the gate insulating layer 118 can include a first portion 118a formed with a first thickness from the bottom surface of the trench 116 and a second portion 118b formed with a second thickness on the inner walls of the trench 116.

[0597] For example, the first portion 118a can be formed to have a first thickness from the bottom surface of the trench 116 so as to partially bury the trench 116. Thus, the second portion 118b can be substantially formed on the first portion 118a and can be formed on the sidewalls of the trench 116 without burying the trench 116. Therefore, the second thickness of the second portion 118b can be less than the first thickness of the first portion 118a. For example, the first thickness can be 1 / 5 or more and 1 / 2 or less of the depth of the trench 116, and the second thickness can be in the range of 1 / 5 to 1 / 30 of the first thickness.

[0598] For example, the gate insulating layer 118 can include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or can include a stacked structure thereof.

[0599] As described above, by forming the first portion 118a of the gate insulating layer 118 thicker than the second portion 118b at the bottom of the trench 116, the electric field concentration on the bottom of the trench 116 during the operation of the power semiconductor device 100-6 can be alleviated.

[0600] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 can include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or can include a stacked structure thereof.

[0601] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may extend vertically in the semiconductor layer 105 on one side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Accordingly, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0602] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that extends vertically in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. The channel region 110a may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112.

[0603] The above structure of the channel region 110a may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0604] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0605] This well (110) structure may further alleviate the electric field concentration on the bottom surface of the trench 116 (i.e., below the gate electrode layer 120). Accordingly, according to the power semiconductor device 100-6, the well region 110 may be formed deeper than the gate electrode layer 120 without additionally forming a deep well, and thus, the electric field concentration on the bottom surface of the trench 116 may be alleviated. The problem with the conventional vertical channel structure is that as the distance between the deep well and the trench becomes shorter, the junction resistance and the threshold voltage increase. However, in the power semiconductor device 100-6 according to the embodiment, this problem may not occur.

[0606] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116, and in addition, may be formed to further extend outside the trench 116.

[0607] In some embodiments, one trench 116 or multiple trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0608] For example, multiple trenches 116 may be formed in the semiconductor layer 105 parallel to one direction. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0609] In this case, multiple gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the interior of the trenches 116. In this way, the gate electrode layers 120 may be formed in a trench type in the semiconductor layer 105 and may be arranged to extend in parallel in the one direction like the trenches 116.

[0610] In addition, each of the well region 110 and the source region 112 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be arranged in the semiconductor layer 105 between the gate electrode layers 120. A channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0611] In some embodiments, the well region 110 may be formed deeper in the semiconductor layer 105 than the gate electrode layer 120 so as to contact the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at the opposite ends of the gate electrode layer 120.

[0612] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0613] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0614] In the above-mentioned power semiconductor device 100-6, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of n-type and p-type. For example, when the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

[0615] More specifically, when the power semiconductor device 100-6 is an N-type MOSFET, the drift region 107 may be an N- region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 and the channel region 110a may be P- regions.

[0616] In the operation of the power semiconductor device 100-6, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then can flow through the channel region 110a along the side surface of the gate electrode layer 120 to the source region 112.

[0617] In the above-mentioned power semiconductor device 100-6, the gate electrode layers 120 can be densely arranged in parallel in a stripe or linear pattern, and the channel region 110a can be provided on the side surface of the gate electrode layer 120. In this way, the channel density can be increased.

[0618] In addition, in the power semiconductor device 100-6, since the gate insulating layer 118 is formed thicker at the bottom of the trench 116 and the bottom surface of the gate electrode layer 120 is surrounded by the well region 110, the breakdown phenomenon caused by the electric field concentrating on the edge of the trench 116 can be alleviated. Therefore, the high breakdown voltage characteristics of the power semiconductor device 100-6 can be improved. This may mean that the reliability of the operation of the power semiconductor device 100-6 is improved.

[0619] Figure 65 is a perspective view showing a power semiconductor device 100a-6 according to another embodiment of the present disclosure.

[0620] The power semiconductor device 100a-6 according to the embodiment can be implemented by using or partially modifying Figures 62 to 64 the power semiconductor device 100-6 therein. Therefore, additional descriptions will be omitted to avoid repetition.

[0621] Referring to Figure 65 , in the power semiconductor device 100a-6, a channel region 107b can be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b can have a first conductivity type. In the operation of the power semiconductor device 100a-6, an accumulation channel can be formed in the channel region 107b.

[0622] For example, the channel region 107b can be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b can have the same doping type as the source region 112 and the drift region 107.

[0623] In this case, the source region 112, the channel region 107b, and the drift region 107 can be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of the negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band of the channel region 107b bends upward. Thus, an accumulation channel that allows charges or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120 can be formed.

[0624] Therefore, the threshold voltage applied to the gate electrode layer 120 to form the accumulation channel in the channel region 107b can be much lower than the threshold voltage applied to the gate electrode layer 120 to form the Figures 62 to 64 inversion channel of the channel region 110a.

[0625] In some embodiments, the channel region 107b can be a part of the drift region 107. More specifically, the channel region 107b can be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b can be formed integrally with the drift region 107. In this case, the drift region 107 can be connected to the source region 112 through the channel region 107b. That is, in the channel region (107b) part, the drift region 107 and the source region 112 can be in contact with each other.

[0626] The doping concentration of the impurity of the first conductivity type in the channel region 107b can be the same as or different from the doping concentration of the rest of the drift region 107 for threshold voltage adjustment.

[0627] As a modified example of the embodiment, the well region 110 can be formed to protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112, and the channel region 107b can be formed in the semiconductor layer 105 on the protruding portion of the well region 110.

[0628] In addition, the well region 110 can further include a tap portion extending toward the gate electrode layer 120 at the end of the protruding portion. The channel region 107b can be formed in a curved shape on the protruding portion and the tap portion of the well region 110.

[0629] In addition, the vertical portion 107a of the drift region 107 can further extend between the lower part of the source region 112 and the well region 110. In this case, the channel region 107b can be formed to further extend between the lower part of the source region 112 and the well region 110.

[0630] The above structure can allow the channel region 107b to be more restricted between the gate electrode layer 120 and the well region 110.

[0631] The power semiconductor device 100a-6 can include Figures 62 to 64The advantages of the power semiconductor device 100-6 shown, and furthermore, the threshold voltage can be made low.

[0632] Figure 66 FIG. is a schematic perspective view showing a power semiconductor device 100b-6 according to another embodiment of the present disclosure. Figure 67 is shown along Figure 66 A plan view of the power semiconductor device 100b-6 taken along line VI-VI. Figure 68 is shown along Figure 67 A cross-sectional view of the power semiconductor device 100b-6 taken along line VII-VII. Figure 69 is shown along Figure 67 A cross-sectional view of the power semiconductor device 100b-6 taken along line VIII-VIII.

[0633] The power semiconductor device 100b-6 according to an embodiment can be implemented by using or partially modifying Figures 62 to 64 the power semiconductor device 100-6 in. Therefore, additional description will be omitted to avoid repetition.

[0634] Referring to Figures 66 to 69 , in the power semiconductor device 100b-6, the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, may refer to the portion connected to the source electrode layer 140.

[0635] The well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source region 112 and may have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 may be formed in the source contact region 112a.

[0636] For example, the well contact region 114 may be doped with impurities of the second conductivity type having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0637] The source electrode layer 140 may be commonly connected to the source contact region 112a and the well contact region 114.

[0638] In Figures 66 to 69 , an example is shown in which the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. However, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0639] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other along one direction. In this way, the gate electrode layers 120 may also be arranged to be linearly spaced apart from each other along the trenches 116 in this one direction. In this case, the well regions 110, source regions 112, source contact regions 112a, and well contact regions 114 may be formed in the semiconductor layer 105 between the trenches 116 arranged to be linearly spaced apart from each other along this one direction.

[0640] For example, the power semiconductor device 100b-6 may be formed by arranging a plurality of Figures 62 to 64 in the structure of the power semiconductor device 100-6 in one direction and by providing well regions 110, source regions 112, source contact regions 112a, and well contact regions 114 therebetween.

[0641] For example, when the power semiconductor device 100-6 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

[0642] According to the power semiconductor device 100b-6, the source contact region 112a and the well contact region 114 may be provided outside the gate electrode layer 120, rather than between the gate electrode layers 120, so that the gate electrode layers 120 may be arranged more densely. In this way, the channel density of the power semiconductor device 100b-6 may be significantly increased.

[0643] Figure 70 and Figure 71 are cross-sectional views showing power semiconductor devices 100c-6 and 100d-6 according to other embodiments of the present disclosure.

[0644] Referring to Figure 70 , the power semiconductor device 100c-6 may include at least one groove 138 in the source contact region 112a of the source region 112, and the groove 138 is formed to penetrate the source region 112 and recess into the well region 110. A well contact region 114a may be formed on at least the bottom surface of the groove 138 so as to contact the well region 110.

[0645] A source electrode layer 140a may be formed to fill the groove 138, so that the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110, as well as the contact area between the source electrode layer 140a and the source region 112, so that the contact resistance therebetween is reduced.

[0646] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Accordingly, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and sidewalls of the groove 138. The above structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0647] Referring to Figure 71 , instead of Figures 66 to 69 the channel region 110a of the power semiconductor device 100b-6, the power semiconductor device 100d-6 may include a channel region 107b that forms an accumulation channel. The structure of the power semiconductor device 100d-6 including the channel region 107b may refer to Figure 65 the description given.

[0648] Accordingly, the power semiconductor device 100d-6 may correspond to the following structure: wherein Figure 65 the power semiconductor devices 100a-6 are connected in multiple numbers, and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 are provided therebetween.

[0649] Figures 72 to 74 is a schematic perspective view showing a method of manufacturing a power semiconductor device 100-6 according to an embodiment of the present disclosure.

[0650] Referring to Figure 72 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be implemented with a substrate having a first conductivity type, and the drift region 107 may be formed on the substrate with one or more epitaxial layers.

[0651] Next, a well region 110 having a second conductivity type may be formed in the semiconductor layer 105 so as to contact the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities having a second conductivity type into the semiconductor layer 105.

[0652] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a part of which is surrounded by the well region 110. More specifically, the well region 110 may be formed by doping impurities having a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0653] Then, a source region 112 having a first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities having a first conductivity type into the well region 110.

[0654] In addition to forming the source region 112, a channel region 110a having an inversion channel formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107. The channel region 110a may be formed between the source region 112 and the vertical portion 107a of the drift region 107. For example, the channel region 110a may be a part of the well region 110 and may be formed by implanting impurities of a second conductivity type into the semiconductor layer 105.

[0655] In the above manufacturing method, impurity implantation or doping may be performed such that the impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selected region.

[0656] Optionally, a heat treatment process for activating or diffusing the impurities may be performed after the ion implantation.

[0657] Referring to Figure 73 , at least one trench 116 may be formed to recess from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0658] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110.

[0659] In addition, the at least one trench 116 may include a plurality of trenches 116, and the trenches 116 may be formed simultaneously, for example, parallel to each other in one direction in the semiconductor layer 105. The channel region 110a may be further restricted by the trenches 116.

[0660] For example, the trench 116 may be formed by using photolithography to form a photomask and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0661] Referring to Figure 74 , a gate insulating layer 118 may be formed on the bottom and inner walls of the trench 116. For example, the formation of the gate insulating layer 118 may include forming a first portion 118a having a first thickness from the bottom surface of the trench, and forming a second portion 118b having a second thickness on the inner walls of the trench 116.

[0662] For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105. In some embodiments, the first portion 118a may be formed by depositing an insulating material, and the second portion 118b may be formed by oxidizing the semiconductor layer 105 or depositing an insulating material.

[0663] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities in polysilicon, or may be formed to include a conductive metal or a metal silicide.

[0664] The patterning process may be performed by using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process may include a process of selectively etching the underlying structure by using the photoresist pattern.

[0665] In this way, the well region 110 may be arranged to be deeper than the gate electrode layer 120, so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0666] Next, an interlayer insulating layer 130 may be formed on the gate electrode layer 120.

[0667] Next, a source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0668] Meanwhile, Figure 65 The power semiconductor device 100a-6 may be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-6 or changing or modifying the manufacturing method. For example, the channel region 107b may be formed with a part of the drift region 107 to form an accumulation channel.

[0669] Figures 66 to 69 The power semiconductor device 100b-6 may be manufactured by adding some processes to the manufacturing method of the above power semiconductor device 100-6 or changing or modifying the manufacturing method.

[0670] For example, when manufacturing the power semiconductor device 100b-6, the formation of the source region 112 may include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may be a part of the source region 112.

[0671] In addition, before forming the trench 116, a well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may be formed by implanting impurities of a second conductivity type having a higher concentration than the well region 110 into a part of the well region 110.

[0672] When manufacturing the power semiconductor device 100b-6, the trenches 116 may be arranged to be spaced apart linearly from each other in one direction. Additionally, the well region 110, the channel region 110a, and the source region 112 may be formed in the semiconductor layer 105 between the trenches 116.

[0673] Reference Figure 70 The method of manufacturing the power semiconductor device 100c-6 described with reference to may further include: forming at least one groove 138 in the source region 112 to penetrate the source region 112 and recess into the well region 110; forming a well contact region 114 on the bottom surface of the groove 138 to contact the well region 110, and forming a source electrode layer 140 to connect to the well contact region 114.

[0674] According to the above manufacturing method, a power semiconductor device 100-6 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using a process applied to a conventional silicon substrate.

[0675] Figure 75 is a schematic perspective view showing a power semiconductor device 100-7 according to an embodiment of the present disclosure. Figure 76 is shown along Figure 75 A plan view of the power semiconductor device 100-7 taken along line II-II. Figure 77 is shown along Figure 76 A cross-sectional view of the power semiconductor device 100-7 taken along line III-III. Figure 78 is shown along Figure 76 A cross-sectional view of the power semiconductor device 100-7 taken along line IV-IV.

[0676] Referring to Figures 75 to 78 , the power semiconductor device 100-7 may at least include a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-7 may have a power MOSFET structure.

[0677] The semiconductor layer 105 may refer to one semiconductor material layer or multiple semiconductor material layers. For example, it may refer to one epitaxial layer or multiple epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0678] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0679] The bandgap of silicon carbide (SiC) can be wider than that of silicon, so it can maintain stability better than silicon even at high temperatures. Additionally, since the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can be stably operated even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-7 including the semiconductor layer 105 formed of silicon carbide can have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0680] More specifically, the semiconductor layer 105 can include a drift region 107. The drift region 107 can have a first conductivity type and can be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 can be formed by doping impurities of the first conductivity type in an epitaxial layer of silicon carbide.

[0681] A well region 110 can be formed in the semiconductor layer 105 to contact at least a part of the drift region 107 and can have a second conductivity type. For example, the well region 110 can be formed by doping impurities of the second conductivity type opposite to the first conductivity type in the drift region 107.

[0682] For example, the well region 110 can be formed to surround at least a part of the drift region 107. More specifically, the well region 110 can include a vertical portion 107a vertically extending in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, at least a part of the vertical portion 107a of the drift region 107 can include the vertical portion 107a, which can be surrounded and restricted by the well region 110. During the operation of the power semiconductor device 100-7, the vertical portion 107a can provide a vertical movement path for charges.

[0683] Figure 75 The well region 110 shown includes two regions separated from each other and the vertical portion 107a inserted between the two regions, but the well region 110 can be variously changed or modified. For example, the vertical portion 107a can have a shape in which its side is surrounded by the well region 110 at one time.

[0684] A source region 112 can be formed in the well region 110 and can have a first conductivity type. For example, the source region 112 can be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 can be higher than the concentration doped in the drift region 107.

[0685] The channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112. For example, the channel region 107b may have a first conductivity type, and in the operation of the power semiconductor device 100-7, an accumulation channel may be formed in the channel region 107b.

[0686] For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107. The channel region 107b may have the same doping type as the source region 112 and the drift region 107.

[0687] In this case, the source region 112, the channel region 107b, and the drift region 107 may be electrically connected normally. However, in the structure of the semiconductor layer 105 of silicon carbide, due to the influence of the negative charges generated by the formation of carbon clusters in the gate insulating layer 118, a potential barrier is formed while the energy band of the channel region 107b bends upward. Thus, an accumulation channel that allows charge or current to flow in the channel region 107b only when a working voltage is applied to the gate electrode layer 120 may be formed.

[0688] Therefore, the threshold voltage applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b may be much lower than the threshold voltage applied to the gate electrode layer 120 to form a normal inversion channel.

[0689] In some embodiments, the channel region 107b may be a part of the drift region 107. More specifically, the channel region 107b may be a part of the vertical portion 107a of the drift region 107. For example, the channel region 107b may be formed integrally with the drift region 107.

[0690] In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, in the portion of the channel region (107b), the drift region 107 and the source region 112 may be in contact with each other.

[0691] For example, the doping concentration of the impurities of the first conductivity type in the channel region 107b may be the same as or different from the doping concentration of the rest of the drift region 107 for threshold voltage adjustment.

[0692] In some embodiments, the well region 110, the channel region 107b, and the source region 112 may be formed symmetric with respect to the vertical portion 107a of the drift region 107. The well region 110, the channel region 107b, and the source region 112 may be formed in the semiconductor layer 105 on opposite sides of the vertical portion 107a, or each of the well region 110, the channel region 107b, and the source region 112 may include a first portion and a second portion formed symmetric with respect to the vertical portion 107a. In each of the well region 110, the channel region 107b, and the source region 112, the first portion and the second portion may be separated from each other or may be connected to each other.

[0693] In addition, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0694] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or may be understood as a substrate independent of the semiconductor layer 105.

[0695] At least one trench 116 may be formed to recess into the semiconductor layer 105 from the surface of the semiconductor layer 105 to a given depth. The trench 116 may extend in one direction within the semiconductor layer 105. One direction may refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and may refer to Figure 76 the direction of line III-III or line IV-IV.

[0696] The gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof. The thickness of the gate insulating layer 118 may be uniform, or a part of the gate insulating layer 118 formed on the bottom surface of the trench 116 may be thicker than a part of the gate insulating layer 118 formed on the sidewall of the trench 116, so that the electric field is reduced at the bottom of the trench 116.

[0697] At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

[0698] The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120. For example, the vertical portion 107a of the drift region 107 may vertically extend in the semiconductor layer 105 on one side of the gate electrode layer 120.

[0699] In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120. For example, the drift region 107 may include a vertical portion 107a that vertically extends in the semiconductor layer 105 on the opposite side of the gate electrode layer 120.

[0700] The well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120. Additionally, the well region 110 may be formed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at the opposite end of the gate electrode layer 120. In this way, the opposite end portions of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110.

[0701] This structure may alleviate the concentration of the electric field on the bottom surface of the trench 116, i.e., at the lower part of the gate electrode layer 120. Therefore, in the power semiconductor device 100-7 according to the embodiment, the well region 110 may be formed deeper than the gate electrode layer 120 without additionally forming a deep well, and thus the concentration of the electric field on the bottom surface of the trench 116 may be alleviated. The problem of the conventional vertical channel structure is that as the distance between the deep well and the trench becomes shorter, the junction resistance and the threshold voltage increase. However, this problem may not occur in the power semiconductor device 100-7 according to the embodiment.

[0702] The channel region 107b may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. Therefore, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 107b, and the vertical portion 107a of the drift region 107 are connected in one direction.

[0703] The above structure of the channel region 107b may be referred to as a "lateral channel structure" because the channel region 110a is formed along the sidewall of the gate electrode layer 120.

[0704] Additionally, the channel region 107b may be formed in the semiconductor layer 105 on the opposite side of the gate electrode layer 120 between the vertical portion 107a of the drift region 107 and the source region 112. In the above embodiment, the channel region 107b may be a part of the vertical portion 107a of the drift region 107.

[0705] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed in the trench 116 and, in addition, may be formed to further extend outside the trench 116.

[0706] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0707] For example, a plurality of trenches 116 may be formed in parallel in one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0708] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trench 116. In this way, the gate electrode layer 120 may be formed in a trench type in the semiconductor layer 105 and may be arranged to extend in parallel in the one direction like the trench 116.

[0709] In addition, the gate insulating layer 118 and the gate electrode layer 120 may further extend to the outside of the trench 116, and thus may be widely formed on the semiconductor layer 105 across the trench 116.

[0710] In addition, the well region 110 may extend across the gate electrode layer 120. The vertical portion 107a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120. The channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portion 107a of the drift region 107 on one side or the opposite side of each gate electrode layer 120.

[0711] In some embodiments, the source region 112 may be connected across the gate electrode layer 120 while surrounding the end portion of the gate electrode layer 120.

[0712] In some embodiments, the well region 110 may be formed deeper than the gate electrode layer 120 in the semiconductor layer 105 so as to contact the vertical portion 107a of the drift region 107 and surround the bottom surface of the gate electrode layer 120 at the opposite ends of the gate electrode layer 120.

[0713] The interlayer insulating layer 130 may be formed on the gate electrode layer 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0714] The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material, metal, etc.

[0715] In the above-described power semiconductor device 100-7, the first conduction type and the second conduction type may be opposite to each other, and each of the first conduction type and the second conduction type may be one of n-type and p-type. For example, when the first conduction type is n-type, the second conduction type is p-type, and vice versa.

[0716] More specifically, when the power semiconductor device 100-7 is an N-type MOSFET, the drift region 107 and the channel region 107b may be N- regions, and the source region 112 and the drain 102 may be N+ regions. The well region 110 may be a P- region.

[0717] In the operation of the power semiconductor device 100-7, current can generally flow in the vertical direction from the drain region 102 along the vertical portion 107a of the drift region 107, and then can flow through the channel region 107b along the side surface of the gate electrode layer 120 to the source region 112.

[0718] In the above-described power semiconductor device 100-7, the gate electrode layers 120 may be arranged densely and parallel to each other in a stripe shape, and the channel region 110a may be arranged on the side surface of the gate electrode layer 120. In this way, the channel density may increase.

[0719] In addition, in the power semiconductor device 100-7, since the bottom surface of the gate electrode layer 120 is surrounded by the well region 110, the breakdown phenomenon caused by the electric field concentrating on the edge of the trench 116 may be alleviated. Therefore, the high breakdown voltage characteristics of the power semiconductor device 100-7 can be improved. This may mean that the reliability of the operation of the power semiconductor device 100-7 is improved.

[0720] Figure 79 is a schematic perspective view showing a power semiconductor device 100a-7 according to another embodiment of the present disclosure. Figure 80 is shown along Figure 79 a plan view of the power semiconductor device 100a-7 taken along line VI-VI. Figure 81 is shown along Figure 80 a cross-sectional view of the power semiconductor device 100a-7 taken along line VII-VII. Figure 82 is shown along Figure 80 a cross-sectional view of the power semiconductor device 100a-7 taken along line VIII-VIII.

[0721] The power semiconductor device 100a-7 according to the embodiment can be implemented by using or partially modifying Figures 75 to 78 the power semiconductor device 100-7 in. Therefore, additional description will be omitted to avoid repetition.

[0722] Referring toFigures 79 to 82 The source region 112 may include a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, may refer to the part connected to the source electrode layer 140.

[0723] The well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source region 112 and may have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 may be formed in the source contact region 112a.

[0724] For example, the well contact region 114 may be connected to the source electrode layer 140 and may be doped with impurities of the second conductivity type having a concentration higher than that of the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0725] In Figures 79 to 82 the example shown, the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side of the vertical portion 107a of the drift region 107. However, the source contact region 112a and the well contact region 114 may be formed on opposite sides of each vertical portion 107a of the drift region 107. Alternatively, when each of the source region 112 and the well region 110 is divided into a plurality of regions, each of the source contact region 112a and the well contact region 114 may be formed in each corresponding region.

[0726] In some embodiments, a plurality of trenches 116 may be arranged to be linearly spaced apart from each other along one direction. In this way, the gate electrode layer 120 may also be arranged to be linearly spaced apart from each other along the trenches 116 in this one direction. In this case, the well region 110 and the source region 112 may be formed in the semiconductor layer 105 such that the well region 110 and the source region 112 are located between the plurality of trenches 116 arranged to be linearly spaced apart from each other along this one direction.

[0727] For example, Figures 75 to 77 the structure of the power semiconductor device 100-7 shown may be arranged in a plurality along one direction, and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 may be formed therebetween.

[0728] For example, when the power semiconductor device 100-7 is an N-type MOSFET, the source contact region 112a may be an N+ region, while the well contact region 114 may be a P+ region.

[0729] In the power semiconductor device 100a-7 according to an embodiment, the source contact region 112a and the well contact region 114 may be arranged outside the gate electrode layer 120, rather than between the gate electrode layers 120. Therefore, the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100a-7 can be significantly increased.

[0730] In addition, in the power semiconductor device 100a-7, since the threshold voltage is reduced by using the channel region 107b in which an accumulated channel is formed and the breakdown phenomenon caused by the concentration of the electric field at the edge of the trench 116 is alleviated, the high breakdown voltage characteristic of the power semiconductor device 100a-7 is improved. This may mean that the reliability of the operation of the power semiconductor device 100a-7 is improved.

[0731] Figures 83 to 86 FIG. is a cross-sectional view showing power semiconductor devices 100b-7, 100c-7, 100d-7, and 100e-7 according to other embodiments of the present disclosure. Each of the power semiconductor devices 100b-7, 100c-7, 100d-7, and 100e-7 can be implemented by modifying Figures 75 to 82 a partial configuration of the power semiconductor device 100-7 or 100a-7. Therefore, additional descriptions will be omitted to avoid repetition.

[0732] Referring to Figure 83 , in the power semiconductor device 100b-7, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112.

[0733] A channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the well region 110. For example, the vertical portion 107a of the drift region 107 may further extend to a groove portion formed between the well region 110 and the gate electrode layer 120 as the protruding portion of the well region 110, and the channel region 107b1 may be formed on the vertical portion 107a. The above structure can make the channel region 107b1 more restricted between the gate electrode layer 120 and the well region 110.

[0734] Referring to Figure 84 , in the power semiconductor device 100c-7, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112. In addition, the well region 110 may include a tap portion extending toward the gate electrode layer 120 at its end. For example, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112 and may include a tap portion at its end.

[0735] The channel region 107b2 may be formed in the semiconductor layer 105 on the protruding portion of the well region 110. For example, the channel region 107b2 may be formed in a curved shape on the protruding portion and the tap portion of the well region 110. The above structure may confine the channel region 107b2 more between the gate electrode layer 120 and the well region 110.

[0736] Referring Figure 85 , in the power semiconductor device 100d-7, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112. In addition, the well region 110 may include a tap portion extending toward the gate electrode layer 120 at its end. For example, the well region 110 may protrude further toward the vertical portion 107a of the drift region 107 than a part of the source region 112 and may include a tap portion at its end. Additionally, the vertical portion 107a of the drift region 107 may further extend between the lower part of the source region 112 and the well region 110.

[0737] The channel region 107b3 may be formed to further extend between the lower part of the source region 112 and the well region 110. For example, the channel region 107b3 may be formed in a curved shape from the tap portion of the well region 110 to the lower part of the source region 112. This structure may widen the contact area between the channel region 107b3 and the source region 112.

[0738] Referring Figure 86 , the power semiconductor device 100e-7 may include at least one groove 138 in the source contact region 112a of the source region 112, and the groove 138 is formed to penetrate the source region 112 and recess into the well region 110. The contact region 114a may be formed on at least the bottom surface of the groove 138 to contact the well region 110.

[0739] The source electrode layer 140a may be formed to fill the groove 138, so the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110 and the source region 112, reducing the contact resistance therebetween.

[0740] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and the sidewall of the groove 138. The above structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0741] Figures 87 to 89is a schematic perspective view showing a method of manufacturing a power semiconductor device 100a-7 according to an embodiment of the present disclosure.

[0742] Referring Figure 87 , a drift region 107 having a first conductivity type may be formed in a semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be implemented with a substrate of the first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on the substrate.

[0743] Next, a well region 110 having a second conductivity type may be formed in the semiconductor layer 105 so as to be in contact with at least a part of the drift region 107. For example, the formation of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105.

[0744] For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a, at least a part of which is surrounded by the well region 110. More specifically, the well region 110 may be formed by doping impurities of a conductivity type opposite to that of the drift region 107 in the drift region 107.

[0745] Then, a source region 112 having a first conductivity type may be formed in the well region 110. For example, the source region 112 may be formed by implanting impurities of the first conductivity type into the well region 110.

[0746] In addition to the formation of the source region 112, at least one channel region 107b having a second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107, and an accumulation channel may be formed in the channel region 107b in one direction. For example, the channel region 107b may be formed between the source region 112 and the vertical portion 107a of the drift region 107.

[0747] For example, when the channel region 107b is a part of the drift region 107, the source region 112 may be formed to be in contact with the drift region 107 through the channel region 107b.

[0748] In the above manufacturing method, impurity implantation or impurity doping may be performed such that impurities are mixed or an epitaxial layer is formed when the impurities are implanted into the semiconductor layer 105. However, an ion implantation method using a mask pattern may be used to implant impurities in a selected region.

[0749] Optionally, a heat treatment process for activating or diffusing impurities may be performed after the ion implantation.

[0750] Referring Figure 88, at least one trench 116 may be formed to recess from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth.

[0751] For example, the trench 116 may extend across the drift region 107 in one direction and may be formed shallower than the well region 110.

[0752] In addition, a plurality of trenches 116 may be formed in parallel in the semiconductor layer 105 in one direction.

[0753] For example, the trench 116 may be formed by using photolithography to form a photomask and then etching the semiconductor layer 105 by using the photomask as an etching protection layer.

[0754] Referring to Figure 89 , the gate insulating layer 118 may be formed at least on the inner wall of the trench 116. For example, the gate insulating layer 118 may be formed by oxidizing the semiconductor layer 105 to form an oxide or by depositing an insulating material such as an oxide or a nitride on the semiconductor layer 105.

[0755] Next, a gate electrode layer 120 may be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and patterning the conductive layer. The gate electrode layer 120 may be formed by doping impurities in polysilicon or may be formed to include a conductive metal or a metal silicide.

[0756] For example, the gate insulating layer 118 and the gate electrode layer 120 may be formed to further protrude outside the trench 116. In addition, the gate insulating layer 118 and the gate electrode layer 120 may be widely formed on the semiconductor layer 105 covering the trench 116.

[0757] The patterning process may be performed by using a photolithography process and an etching process. The photolithography process may include a process of forming a photoresist pattern as a mask layer by using a light process and a developing process, and the etching process may include a process of selectively etching the underlying structure by using the photoresist pattern.

[0758] In this way, the well region 110 may be arranged to be deeper than the gate electrode layer 120, so as to at least surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120, and the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112, on one side or the opposite side of the gate electrode layer 120.

[0759] In addition, an interlayer insulating layer 130 may be formed on the gate electrode layer 120.

[0760] Next, a source electrode layer 140 can be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 can be formed by forming a conductive layer (such as a metal layer) on the interlayer insulating layer 130 and patterning the conductive layer.

[0761] Meanwhile, Figures 79 to 82 The power semiconductor device 100a-7 shown can be manufactured by adding some processes to or changing or modifying the manufacturing method of the above power semiconductor device 100-7.

[0762] For example, when manufacturing the power semiconductor device 100a-7, the formation of the source region 112 can include forming a source contact region 112a connected to the source electrode layer 140 outside at least one end of the gate electrode layer 120. In some embodiments, the source contact region 112a may not be separated from the source region 112.

[0763] In addition, a well contact region 114 can be formed in the source contact region 112a before forming the trench 116. For example, the well contact region 114 can be formed by implanting second-conductive-type impurities with a concentration higher than that of the well region 110 into a part of the well region 110.

[0764] When manufacturing the power semiconductor device 100a-7, the trenches 116 can be arranged to be linearly spaced apart from each other in one direction. In addition, the well region 110, the channel region 107b, and the source region 112 can be formed in the semiconductor layer 105 between the trenches 116.

[0765] According to the above manufacturing method, a power semiconductor device 100-7 using a semiconductor layer 105 of silicon carbide can be economically manufactured by using processes applied to a conventional silicon substrate.

[0766] Figure 90 is a schematic perspective view showing a power semiconductor device 100-8 according to an embodiment of the present disclosure. Figure 91 is a plan view showing the power semiconductor device 100-8 taken along the line II-II Figure 90 of. Figure 92 is a sectional view showing the power semiconductor device 100-8 taken along the line III-III Figure 91 of.

[0767] Referring to Figures 90 to 92 , the power semiconductor device 100-8 can at least include a semiconductor layer 105, a gate insulating layer 118, and a gate electrode layer 120. For example, the power semiconductor device 100-8 can have a power MOSFET structure.

[0768] The semiconductor layer 105 may refer to a single semiconductor material layer or multiple semiconductor material layers. For example, it may refer to a single epitaxial layer or multiple epitaxial layers. Additionally, the semiconductor layer 105 may refer to one or more epitaxial layers on a semiconductor substrate.

[0769] For example, the semiconductor layer 105 may be formed of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

[0770] The bandgap of silicon carbide (SiC) may be wider than that of silicon, so it can maintain stability better than silicon even at high temperatures. Additionally, because the breakdown electric field of silicon carbide is higher than that of silicon, silicon carbide can operate stably even at high temperatures. Therefore, compared with the case of using silicon, the power semiconductor device 100-8 including the semiconductor layer 105 formed of silicon carbide may have a high breakdown voltage and can provide excellent heat dissipation characteristics and stable operating characteristics at high temperatures.

[0771] More specifically, the semiconductor layer 105 may include a drift region 107. The drift region 107 may have a first conductivity type and may be formed by implanting impurities of the first conductivity type into a part of the semiconductor layer 105. For example, the drift region 107 may be formed by doping impurities of the first conductivity type in the epitaxial layer of silicon carbide.

[0772] A well region 110 may be formed in the semiconductor layer 105 to contact the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of the second conductivity type opposite to the first conductivity type in the drift region 107. More specifically, the well region 110 may be disposed on the drift region 107.

[0773] A source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping impurities of the first conductivity type in the well region 110. The concentration of the impurities of the first conductivity type doped in the source region 112 may be higher than the concentration doped in the drift region 107.

[0774] Additionally, a drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may have a first conductivity type. For example, compared with the drift region 107, the drain region 102 may be doped with a high concentration of impurities.

[0775] In some embodiments, the drain region 102 may be implemented with a silicon carbide substrate having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or may be understood as a substrate independent of the semiconductor layer 105.

[0776] At least one trench 116 can be formed that recesses from the surface of the semiconductor layer 105 into the semiconductor layer 105 to a given depth. The trench 116 can extend in one direction within the semiconductor layer 105. One direction can refer to the length direction of the trench 116, rather than the depth direction of the trench 116, and can refer to Figure 91 the direction of line III-III.

[0777] The gate insulating layer 118 can be formed at least on the inner walls of the trench 116. For example, the gate insulating layer 118 can be formed on the inner surface of the trench 116 and on the semiconductor layer 105 outside the trench 116. The thickness of the gate insulating layer 118 can be uniform, or a portion of the gate insulating layer 118 formed on the bottom surface of the trench 116 can be thicker than a portion of the gate insulating layer 118 formed on the sidewalls of the trench 116, such that the electric field is reduced at the bottom of the trench 116.

[0778] For example, the gate insulating layer 118 can include an insulating material such as silicon oxide, silicon carbide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or can include a stacked structure thereof.

[0779] At least one gate electrode layer 120 can be formed on the gate insulating layer 118 to bury the trench 116. For example, the gate electrode layer 120 can include a suitable conductive material such as polysilicon, metal, metal nitride, or metal silicide, or can include a stacked structure thereof.

[0780] In some embodiments, a drift region 107 can be formed in the semiconductor layer 105 below the gate electrode layer 120. In the semiconductor layer 105 over the drift region 107, a well region 110 can be formed deeper than the gate electrode layer 120 to at least surround the opposite sidewalls and bottom edge of the gate electrode layer 120.

[0781] A junction resistance reduction region 108 can be formed in the semiconductor layer 105 to connect with the drift region 107 below the bottom surface of the gate electrode layer 120. The junction resistance reduction region 108 can have a first conductivity type and can be formed by implanting impurities of the first conductivity type into the semiconductor layer 105.

[0782] In some embodiments, the well region 110 can be formed to surround the sidewalls and bottom surface of the gate electrode layer 120, and the junction resistance reduction region 108 can be formed between the bottom surface of the gate electrode layer 120 and the drift region 107 to penetrate the well region 110. In this case, the junction resistance reduction region 108 can be formed by doping impurities of the first conductivity type in the well region 110.

[0783] The well (110) structure can further alleviate the electric field concentration at the bottom surface of the trench 116 (i.e., the lower end edge of the gate electrode layer 120). The above structure can increase the electric field margin of the gate insulating layer 118 of the power semiconductor device 100-8, and thus, the reliability of the operation of the power semiconductor device 100-8 can be improved.

[0784] The channel region 110a can be formed in the semiconductor layer 105 between the junction resistance reduction region 108 and the source region 112. For example, the channel region 110a can be formed in the semiconductor layer 105 between the junction resistance reduction region 108 and the source region 112 along the sidewall of the gate electrode layer 120. For example, the channel region 110a can have a second conductivity type, and in the operation of the power semiconductor device 100-8, an inversion channel can be formed in the channel region 110a along one direction.

[0785] Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107, the channel region 110a can form a diode junction with the source region 112 and the drift region 107. Therefore, the channel region 110a may not allow charge movement under normal circumstances; however, when a working voltage is applied to the gate electrode layer 120, an inversion channel can be formed therein, allowing charge movement.

[0786] In some embodiments, the channel region 110a can be a part of the well region 110. In this case, the channel region 110a can be integrally formed to be continuously connected to the well region 110. The doping concentration of the impurity of the second conductivity type in the channel region 110a can be the same as or different from the doping concentration of the rest of the well region 110 for adjusting the threshold voltage.

[0787] The doping concentration of the impurity of the first conductivity type in the junction resistance reduction region 108 can be equal to or higher than the doping concentration of the drift region 107. In some embodiments, the doping concentration of the impurity of the first conductivity type in the junction resistance reduction region 108 can be higher than the doping concentration of the drift region 107, such that the junction resistance is reduced. In this case, since the junction resistance reduction region 108 with a resistance smaller than that of the drift region 107 is joined to the channel region 110a, the junction resistance can be reduced.

[0788] In addition, the doping concentration of the impurity of the first conductivity type in the junction resistance reduction region 108 can be equal to or lower than the doping concentration of the impurity of the first conductivity type in the source region 112 and the drain region 102.

[0789] In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 can be formed in the trench 116, and in addition, can be formed to further extend to the outside of the trench 116.

[0790] In some embodiments, one trench 116 or a plurality of trenches 116 may be provided in the semiconductor layer 105. The number of trenches 116 may be appropriately selected without limiting the scope of the embodiments.

[0791] For example, a plurality of trenches 116 may be formed parallel to each other in one direction in the semiconductor layer 105. When the trenches 116 extend in one direction and are spaced apart from each other in a direction perpendicular to the one direction, the trenches 116 may be arranged in parallel.

[0792] In this case, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trenches 116. In this way, trench-type gate electrode layers 120 may be formed in the semiconductor layer 105, and the gate electrode layers 120 may be arranged to extend in parallel in the one direction in the same manner as the trenches 116.

[0793] An interlayer insulating layer 130 may be formed on the gate electrode layers 120. For example, the interlayer insulating layer 130 may include a suitable insulating material such as an oxide or a nitride, or may include a stacked structure thereof.

[0794] A source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112. For example, the source electrode layer 140 may be formed of a suitable conductive material (such as a metal).

[0795] In the above-described power semiconductor device 100-8, the first conductivity type and the second conductivity type may be opposite to each other, and each of the first conductivity type and the second conductivity type may be one of an n-type and a p-type. For example, when the first conductivity type is an n-type, the second conductivity type is a p-type, and vice versa.

[0796] More specifically, when the power semiconductor device 100-8 is an N-type MOSFET, the drift region 107 may be an N- region, the junction resistance reduction region 108 may be an N- region, the source region 112 and the drain region 102 may be N+ regions, and the well region 110 and the channel region 110a may be P- regions.

[0797] In the operation of the power semiconductor device 100-8, current may generally flow from the drain region 102 to the drift region 107 and the junction resistance reduction region 108 in the vertical direction, and then may flow to the source region 112 along the sidewalls of the gate electrode layer 120 on which the channel region is formed.

[0798] In the above-described power semiconductor device 100-8, the gate electrode layers 120 in the trenches 116 may be densely arranged in a stripe type or a linear type in parallel, and the channel region may be provided on the sides of the gate electrode layers 120. In this way, the channel density may be increased.

[0799] Figure 93 is a perspective view showing a power semiconductor device 100a-8 according to another embodiment of the present disclosure. The power semiconductor device 100a-8 according to the embodiment can be implemented by using or partially modifying Figures 90 to 92 the power semiconductor device 100-8 in . Therefore, additional descriptions will be omitted to avoid repetition.

[0800] Referring to Figure 93 , in the power semiconductor device 100a-8, the source region 112 can be continuously formed along the extending direction of the gate electrode layer 120. For example, the source region 112 can be widely formed to surround the upper region of the gate electrode layer 120. As described above, when the source region 112 is widely formed, the charge movement path from the drain region 102 to the source region 112 can be widened.

[0801] Figure 94 is a schematic perspective view showing a power semiconductor device 100b-8 according to another embodiment of the present disclosure. Figure 95 is a plan view showing the power semiconductor device 100b-8 taken along the line VI-VI of Figure 94 . Figure 96 is a cross-sectional view showing the power semiconductor device 100b-8 taken along the line VII-VII of Figure 95 . Figure 97 is a cross-sectional view showing the power semiconductor device 100b-8 taken along the line VIII-VIII of Figure 95 .

[0802] The power semiconductor device 100b-8 according to the embodiment can be implemented by using or partially modifying Figures 90 to 92 the power semiconductor device 100-8 in . Therefore, additional descriptions will be omitted to avoid repetition.

[0803] Referring to Figures 94 to 97 , in the power semiconductor device 100b-8, the source region 112 can include a source contact region 112a outside at least one end of the gate electrode layer 120. For example, the source contact region 112a, which is part of the source region 112, can refer to the part connected to the source electrode layer 140.

[0804] A well contact region 114 can be formed in the source contact region 112a. For example, the well contact region 114 can extend from the well region 110 to penetrate the source region 112 and can have a second conductivity type. One well contact region 114 or a plurality of well contact regions 114 can be formed in the source contact region 112a.

[0805] For example, the well contact region 114 can be doped with impurities of the second conductivity type having a higher concentration than the well region 110 to reduce the contact resistance when connected to the source electrode layer 140.

[0806] The source electrode layer 140 can be commonly connected to the source contact region 112a and the well contact region 114.

[0807] In some embodiments, a plurality of trenches 116 can be arranged to be spaced apart linearly from each other along one direction. In this way, the gate electrode layers 120 can also be arranged to be spaced apart linearly from each other along the trenches 116 in this one direction. In this case, the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 can be formed in the semiconductor layer 105 between the trenches 116 arranged to be spaced apart linearly from each other along this one direction.

[0808] For example, the power semiconductor device 100b-8 can be formed by arranging a plurality of Figures 90 to 92 structures of the power semiconductor device 100-8 along one direction and by arranging the well region 110, the source region 112, the source contact region 112a, and the well contact region 114 therebetween.

[0809] For example, when the power semiconductor device 100-8 is an N-type MOSFET, the source contact region 112a can be an N+ region, and the well contact region 114 can be a P+ region.

[0810] According to the power semiconductor device 100b-8, the source contact region 112a and the well contact region 114 can be provided outside the gate electrode layer 120 instead of between the gate electrode layers 120, so that the gate electrode layers 120 can be arranged more densely. In this way, the channel density of the power semiconductor device 100b-8 can be significantly increased.

[0811] Figure 98 is a cross-sectional view showing a power semiconductor device 100c-8 according to another embodiment of the present disclosure. The power semiconductor device 100c-8 can be implemented by modifying Figures 94 to 97 part of the configuration of the power semiconductor device 100b-8 in. Therefore, additional descriptions will be omitted to avoid repetition because they can refer to each other.

[0812] Referring to Figure 98 , the power semiconductor device 100c-8 can include at least one groove 138 in the source contact region 112a of the source region 112. The groove 138 is formed to penetrate the source region 112 and recess into the well region 110. The well contact region 114a can be formed on at least the bottom surface of the groove 138 to contact the well region 110.

[0813] A source electrode layer 140a may be formed to fill the groove 138, and the source electrode layer 140a may be connected to the well contact region 114a, the well region 110, and / or the source region 112. The above structure may widen the contact area between the source electrode layer 140a and the well region 110 and the contact area between the source electrode layer 140a and the source region 112, reducing the contact resistance therebetween.

[0814] In some embodiments, the well contact region 114a may be formed on the entire surface of the well region 110 exposed by the groove 138. Thus, the well contact region 114a may be formed on the well region 110 exposed from the bottom surface and the sidewalls of the groove 138. The above structure of the well contact region 114a may allow the contact resistance between the source electrode layer 140a and the well region 110 to be further reduced.

[0815] Figure 99 is a cross-sectional view showing a power semiconductor device 100d-8 according to another embodiment of the present disclosure. The power semiconductor device 100d-8 may be implemented by modifying Figures 94 to 97 the partial configuration of the power semiconductor device 100b-8 in. Therefore, additional descriptions will be omitted to avoid repetition as they may refer to each other.

[0816] Referring to Figure 99 , in the power semiconductor device 100d-8, the source region 112 may be formed to be continuous along the extending direction of the gate electrode layer 120. For example, the source region 112 may extend along the upper portion of the gate electrode layer 120, and in addition, may extend further between the gate electrode layers 120 arranged in a straight line.

[0817] The source region 112 may be widely formed to surround the upper region of the gate electrode layer 120. As described above, when the source region 112 is widely formed, the charge movement path from the drain region 102 to the source region 112 may be widened.

[0818] As described above, according to the embodiments of the present disclosure, the power semiconductor device and its manufacturing method may alleviate the concentration of the electric field and may increase the channel density, thereby improving the integration degree.

[0819] Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

[0820] In the above, although the present disclosure has been described with reference to exemplary embodiments and the drawings, the present disclosure is not limited thereto, and those skilled in the art to which the present disclosure pertains may make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A power semiconductor device, comprising: a semiconductor layer of silicon carbide (SiC); at least one trench extending in a first direction and recessed from the surface of the semiconductor layer into the semiconductor layer, the trench including a first trench; a gate insulating layer provided on at least the inner wall of the at least one trench; at least one gate electrode layer provided on the gate insulating layer and in at least one of the at least one trench; a drift region provided in the semiconductor layer on at least one side of the at least one gate electrode layer and having a first conductivity type; a well region provided in the semiconductor layer, the well region being provided deeper in the semiconductor layer than the at least one gate electrode layer to contact at least a part of the drift region and at least surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, the well region having a second conductivity type; a source region provided in the well region and having the first conductivity type; and at least one channel region provided in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer and having the second conductivity type; wherein the drift region includes a vertical portion extending vertically to the surface of the semiconductor layer and surrounding the bottom surface of the at least one trench, and wherein both sides of the vertical portion of the drift region are in contact with the well region, wherein the source region includes a source contact region spaced apart from the first trench in the first direction, and wherein the well region is in contact with a well contact region, the well contact region being in contact with the source contact region in the first direction; wherein the at least one trench includes a plurality of trenches provided in parallel in the semiconductor layer along the first direction, the trench including a second trench, wherein the at least one gate electrode layer includes a plurality of gate electrode layers provided in the plurality of trenches, wherein the well region and the source region extend across the plurality of gate electrode layers, wherein the at least one channel region includes a plurality of channel regions provided in the semiconductor layer on one side of the plurality of gate electrode layers, wherein the second trench is separated from the first trench in the first direction, and wherein the source contact region is located between the first trench and the second trench.

2. The power semiconductor device according to claim 1, wherein, the source contact region is connected to a source electrode layer outside one end of the at least one gate electrode layer.

3. The power semiconductor device according to claim 2, wherein, the well contact region extends through the source region from the well region in the source contact region, is connected to the source electrode layer, and has the second conductivity type, wherein the doping concentration of the well contact region is higher than that of the well region.

4. The power semiconductor device according to claim 1, wherein, the at least one channel region is provided in the semiconductor layer between the vertical portion of the drift region and the source region.

5. The power semiconductor device according to claim 4, wherein, The well region, the source region, and the channel region are disposed in the semiconductor layer to be on opposite sides of the vertical portion of the drift region.

6. The power semiconductor device according to claim 1, wherein, the vertical portion of the drift region extends vertically in the semiconductor layer on the opposite side of the at least one gate electrode layer, wherein the at least one channel region includes a channel region disposed in the semiconductor layer between the vertical portion of the drift region and the source region.

7. The power semiconductor device according to claim 1, wherein, the at least one channel region is part of the well region.

8. The power semiconductor device according to claim 1, wherein, the source contact region is connected to the source electrode layer outside one end of the plurality of gate electrode layers.

9. The power semiconductor device according to claim 1, wherein, the vertical portion of the drift region extends vertically in the semiconductor layer between the plurality of gate electrode layers, wherein the channel region is disposed in the semiconductor layer between the vertical portion of the drift region and the source region, wherein the drift region extends along the bottom surface of the well region.

10. The power semiconductor device according to claim 1, wherein, the at least one trench includes a plurality of trenches that are arranged to be spaced apart from each other in a straight line along a second direction different from the first direction, wherein the at least one gate electrode layer includes a plurality of gate electrode layers disposed in the plurality of trenches, and wherein the well region and the source region are formed at least in the semiconductor layer between the plurality of trenches, wherein the plurality of gate electrode layers extend above the surface of the semiconductor layer.

11. The power semiconductor device according to claim 1, further comprises: a drain region formed in the semiconductor layer below the drift region and having the first conductivity type, wherein the doping concentration of the drain region is higher than the doping concentration of the drift region.

12. A power semiconductor device, comprises: a semiconductor layer of silicon carbide (SiC); a plurality of trenches that extend parallel to each other in one direction and are recessed from the surface of the semiconductor layer into the semiconductor layer; a gate insulating layer disposed on at least the inner walls of the trenches; a plurality of gate electrode layers disposed on the gate insulating layer and in the plurality of trenches; a drift region including a plurality of vertical portions disposed in the semiconductor layer between the plurality of gate electrode layers, the drift region having the first conductivity type; a well region disposed in the semiconductor layer, the well region being disposed deeper in the semiconductor layer than the plurality of gate electrode layers to contact both sides of each of the plurality of vertical portions of the drift region and surround the bottom surface of the plurality of gate electrode layers at opposite ends of the plurality of gate electrode layers, the well region having the second conductivity type; a source region disposed in the well region and having the first conductivity type; and a plurality of channel regions disposed in the semiconductor layer on the opposite side of the plurality of gate electrode layers between the plurality of vertical portions of the drift region and the source region, the plurality of channel regions having the second conductivity type; Among them, a plurality of vertical portions of the drift region vertically extend to the surface of the semiconductor layer and surround the bottom surface of each of the plurality of trenches; Among them, the source region includes a source contact region spaced apart from the plurality of trenches in the one direction, and Among them, the well region is in contact with a well contact region, and the well contact region is in contact with the source contact region in the one direction; Among them, the trenches include a first trench and a second trench, and among them, the well region and the source region extend across the plurality of gate electrode layers, Among them, the second trench is separated from the first trench in the one direction, and Among them, the source contact region is located between the first trench and the second trench.

13. A method of manufacturing a power semiconductor device, including: forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in contact with at least a part of the drift region in the semiconductor layer; forming a source region having the first conductivity type in the well region; forming at least one channel region having the second conductivity type in the semiconductor layer between the drift region and the source region; forming at least one trench shallower than the well region to recess from the surface of the semiconductor layer into the semiconductor layer and extend across the drift region in one direction; forming a gate insulating layer on at least an inner wall of the at least one trench; and forming at least one gate electrode layer on the gate insulating layer and in the at least one trench, forming a source contact region having the first conductivity type away from the at least one trench in the one direction; and forming a well contact region having the second conductivity type in contact with the source contact region in one direction, wherein the well region is formed deeper in the semiconductor layer than the at least one gate electrode layer to surround the bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer; and wherein the channel region is formed in the semiconductor layer between the drift region and the source region and on one side of the at least one gate electrode layer; wherein the drift region includes a vertical portion vertically extending to the surface of the semiconductor layer and surrounding the bottom surface of the at least one trench, and wherein both sides of the vertical portion of the drift region are in contact with the well region; wherein the at least one trench includes a plurality of trenches arranged parallel to each other in the one direction in the semiconductor layer, and the trenches include a first trench and a second trench, wherein the at least one gate electrode layer includes a plurality of gate electrode layers provided in the plurality of trenches, wherein the well region and the source region extend across the plurality of gate electrode layers, wherein the at least one channel region includes a plurality of channel regions provided in the semiconductor layer on one side of the plurality of gate electrode layers, wherein the second trench is separated from the first trench in the one direction, and wherein the source contact region is located between the first trench and the second trench.

14. The method according to claim 13, wherein, The source contact region is formed to be connected to the source electrode layer outside one end of the at least one gate electrode layer.

15. The method according to claim 14, wherein, the well contact region extends from the well region through the source region, is connected to the source electrode layer, and has the second conductivity type, wherein the doping concentration of the well contact region is higher than that of the well region.

16. The method according to claim 13, wherein, the formation of the well region is performed by implanting impurities of the second conductivity type into the semiconductor layer, wherein the formation of the source region is performed by implanting impurities of the first conductivity type into the well region.

17. The method according to claim 13, wherein, the drift region is formed on the drain region having the first conductivity type, wherein the doping concentration of the drain region is higher than that of the drift region.

18. The method according to claim 17, wherein, the drain region is formed of a substrate of the first conductivity type, wherein the drift region is formed as an epitaxial layer on the substrate.

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