Semiconductor device and method for forming the same

Abstract

In an embodiment, the device includes: a gate dielectric located above a substrate; a gate electrode located above the gate dielectric, the gate electrode including: a work function adjustment layer located above the gate dielectric; a glue layer located above the work function adjustment layer; a filling layer located above the glue layer; and a gap defined by an inner surface of at least one of the filling layer, the glue layer and the work function adjustment layer, wherein the material of the gate electrode at the inner surface includes a work function adjustment element. Embodiments of the present application also relate to semiconductor devices and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of individual electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a gate dielectric located above a substrate; a gate electrode located above the gate dielectric, the gate electrode comprising: a work function adjustment layer located above the gate dielectric; a glue layer located above the work function adjustment layer; a filling layer located above the glue layer; and a gap defined by an inner surface of at least one of the filling layer, the glue layer and the work function adjustment layer, the material of the gate electrode at the inner surface comprising a work function adjustment element.

[0005] Other embodiments of the present application provide a semiconductor device, including: a first transistor, including: a first channel region, the first channel region having a first length; and a first gate structure, located above the first channel region, the first gate structure including a first gate electrode, the first gate electrode having a gap therein; and a second transistor, including: a second channel region, the second channel region having a second length, the second length being greater than the first length; and a second gate structure, located above the second channel region, the second gate structure including a second gate electrode, the second gate electrode having no gap, and the second gate electrode having a work function different from that of the first gate electrode.

[0006] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: removing a dummy gate to form a groove between gate spacers; depositing a gate dielectric layer in the groove; depositing a gate electrode layer on the gate dielectric layer, the inner surface of the gate electrode layer defining a gap; flattening the top surface of the gate electrode layer until the gap is exposed at the top surface of the gate electrode layer; and performing a first gate processing process in the gap, the first gate processing process increasing the concentration of a work function adjustment element at the inner surface of the gate electrode layer defining the gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown.

[0009] Figures 2 to 19B are various views of intermediate stages in the fabrication of a FinFET according to some embodiments.

[0010] Fig. 20A and Fig. 20B is a cross-sectional view of a FinFET according to some embodiments.

[0011] FIG. 21A to FIG. 22B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments.

[0012] Fig.23A and Fig. 23B is a cross-sectional view of a FinFET according to some other embodiments.

[0013] FIG. 24A to FIG. 25B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments.

[0014] Fig.26A and Fig.26B is a cross-sectional view of a FinFET according to some other embodiments.

[0015] Fig. 27 is a spectrum graph showing the composition of a gate electrode according to some embodiments.

[0016] Fig.28 is a graph showing threshold voltages of devices according to some embodiments.

[0017] FIG. 29A to FIG. 29C is a cross-sectional view of a gate structure film stack according to some embodiments.

[0018] Fig. 30A , Fig. 30B and Fig. 30C are various 3D and cross-sectional views of the results of an etching step according to some embodiments.

[0019] Fig.31A , Fig.31B and Fig.31C According to some embodiments, FIG. 30A to FIG. 30C Various 3D and cross-sectional views of the structures formed by the etching steps. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] According to various embodiments, the device will form a short length channel region and a long length channel region. A gate electrode is formed above the channel region. The gate electrode above the short length channel region is formed to have a gap, and the gate electrode above the long length channel region is formed to have no gap (or at least have a smaller gap). One or more gate processing processes are implemented to modify the work function of the device. The gate processing process has a greater effect on the gate electrode with a gap (e.g., those above the short length channel region) than on the gate electrode without a gap (e.g., those above the long length channel region). Therefore, the gate processing process can also be used to selectively adjust the threshold voltage of some devices, even when the gate processing process is implemented across the entire substrate.

[0023] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, some other components of the FinFET (discussed below) are omitted. The FinFET shown can be electrically connected or coupled in a manner to operate as, for example, one transistor or multiple transistors (such as two transistors).

[0024] The FinFET includes a fin 52 extending from a substrate 50. A shallow trench isolation (STI) region 56 is disposed above the substrate 50, and the fin 52 is above and protrudes from adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single, continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to the portion extending between adjacent STI regions 56.

[0025] The gate dielectric 112 is along the sidewalls of the fin 52 and is located above the top surface of the fin 52, and the gate electrode 114 is located above the gate dielectric 112. The source / drain region 88 is disposed in the opposite side of the fin 52 relative to the gate dielectric 112 and the gate electrode 114. The gate spacer 82 separates the source / drain region 88 from the gate dielectric 112 and the gate electrode 114. An interlayer dielectric (ILD) 92 is disposed above the source / drain region 88 and the STI region 56. In embodiments where multiple transistors are formed, the source / drain region 88 can be shared between the respective transistors. In embodiments where a transistor is formed from multiple fins 52, adjacent source / drain regions 88 can be electrically connected, such as by merging the source / drain regions 88 by epitaxial growth, or by coupling the source / drain regions 88 to the same source / drain contact.

[0026] Figure 1 Several reference cross sections are also shown. Cross section AA is along the longitudinal axis of the fin 52 and in the direction of current flow, for example, between the source / drain regions 88 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the gate electrode 114 and in a direction, for example, perpendicular to the direction of current flow, for example, between the source / drain regions 88 of the FinFET. Cross section CC is parallel to cross section BB and extends through the source / drain regions 88 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0027] Figures 2 to 19B are various views of intermediate stages in the fabrication of a FinFET according to some embodiments. Figure 2 , Figure 3 and Figure 4 is a three-dimensional view. Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.18A and Fig.19A is along with Figure 1 A cross-sectional view similar to the cross-section shown in reference section AA. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18B and Fig.19B is along with Figure 1 A cross-sectional view similar to the cross-sectional view shown in reference section BB. Figure 6C and Fig.6D is along with Figure 1 A cross-sectional view similar to the cross-section shown in reference section CC.

[0028] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0029] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. The p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0030] Fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0031] The fin 52 may be patterned by any suitable method. For example, the fin 52 may be patterned using one or more photolithography processes including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin 52. In some embodiments, a mask (or other layer) may remain on the fin 52.

[0032] STI regions 56 are formed over the substrate 50 and between adjacent fins 52. As an example of forming the STI regions 56, an insulating material may be formed over the substrate 50 and between adjacent fins 52. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the fins 52. Although the STI regions 56 are shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material, such as those discussed above, may be formed over the liner. A removal process is then applied to the insulating material to remove excess insulating material over the fins 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 52 so that the top surface of the fin 52 is coplanar with the insulating material after the planarization process is completed (within process variations). In an embodiment where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surface of the mask or the fin 52 is coplanar with the insulating material, respectively (within process variations). The insulating material is then recessed to form the STI region 56. The insulating material is recessed so that the upper portion of the fin 52 located in the n-type region 50N and the p-type region 50P protrudes from between adjacent STI regions 56. In addition, the top surface of the STI region 56 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof as shown. The top surface of the STI region 56 may be formed to be flat, convex, and / or concave by appropriate etching. STI regions 56 may be recessed using an acceptable etch process, such as an etch process that is selective to the material of the insulating material (eg, etches the material of the insulating material at a faster rate than the material of fins 52). For example, oxide removal (using, for example, dilute hydrofluoric (dHF) acid) may be used.

[0033] about Figure 2The process described is only one example of how to form the fin 52. In some embodiments, the fin 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In addition, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, the fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown above the recessed material. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material disposed above the recessed material. In a further embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer. Then a heteroepitaxial structure can be epitaxially grown in the groove using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, although in situ and implant doping may be used together.

[0034] Furthermore, it may be advantageous to epitaxially grow a different material in the n-type region 50N (eg, NMOS region) than in the p-type region 50P (eg, PMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0035] In addition, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a p-type well may be formed in the n-type region 50N, and an n-type well may be formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in the n-type region 50N and the p-type region 50P.

[0036] In embodiments with different well types, different implantation steps for n-type region 50N and p-type region 50P may be implemented using photoresist and / or other masks (not shown). For example, a photoresist may be formed over fin 52 and STI region 56 in n-type region 50N. The photoresist is patterned to expose p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in p-type region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity may be implanted in a region with a concentration equal to or less than about 10 18 cm -3 Phosphorus, arsenic, antimony, etc., such as about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0037] After implanting the p-type region 50P, a photoresist is formed over the fin 52 and the STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be implanted in a region with a concentration equal to or less than 10 18 cm -3 Boron, boron fluoride, indium, etc., such as about 10 16 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0038] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and to activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0039] exist Figure 3In the embodiment of the present invention, a pseudo dielectric layer 62 is formed on the fin 52. The pseudo dielectric layer 62 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 64 is formed above the pseudo dielectric layer 62, and a mask layer 66 is formed above the pseudo gate layer 64. The pseudo gate layer 64 may be deposited above the pseudo dielectric layer 62 and then planarized, such as by CMP. The mask layer 66 may be deposited above the pseudo gate layer 64. The pseudo gate layer 64 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The pseudo gate layer 64 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 64 may be made of other materials having high etch selectivity to the etching of the isolation region (e.g., STI region 56 and / or pseudo dielectric layer 62). The mask layer 66 may include one or more layers of, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. In the embodiment shown, the dummy dielectric layer 62 covers the STI region 56, extends over the STI region 56, and between the dummy gate layer 64 and the STI region 56. In another embodiment, the dummy dielectric layer 62 only covers the fin 52.

[0040] exist Figure 4 In the embodiment of the present invention, the mask layer 66 may be patterned using acceptable photolithography and etching techniques to form a mask 76. The pattern of the mask 76 may then be transferred to the dummy gate layer 64 to form a dummy gate 74. In some embodiments, the pattern of the mask 76 is also transferred to the dummy dielectric layer 62 by an acceptable etching technique to form a dummy dielectric 72. The dummy gates 74 cover the corresponding channel regions 58 of the fins 52. The pattern of the mask 76 may be used to physically separate each of the dummy gates 74 from the adjacent dummy gates 74. The dummy gates 74 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the fins 52.

[0041] FIG. 5A to FIG. 19B Various additional steps in the fabrication of example devices are shown. FIG. 5A to FIG. 19B Components in either the n-type region 50N or the p-type region 50P are shown. For example, FIG. 5A to FIG. 19B The structure shown in FIG. 5 may be applicable to both the n-type region 50N and the p-type region 50P. The differences, if any, in the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

[0042] exist Figure 5A and Figure 5B, a gate spacer 82 is formed on the sidewalls of the dummy gate 74 and the mask 76. The gate spacer 82 can be formed by conformally depositing one or more insulating materials and then etching the insulating material. The insulating material can be formed of a low-k dielectric material, such as silicon oxide, silicon nitride, silicon carbonitride, silicon carbon nitride oxide, combinations thereof, and the like, which can be formed by a conformal deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like. The insulating material (when etched) has a portion that remains on the sidewalls of the dummy gate 74 and the mask 76 (thus forming the gate spacer 82). After etching, the gate spacer 82 may have straight sidewalls (as shown) or may have curved sidewalls (not shown). In some embodiments, the insulating material of the gate spacer 82 is silicon carbon nitride oxide (e.g., SiO x N y C 1-x-y , where x and y are in the range of 0 to 1). For example, each layer of insulating material may have a similar or different composition of silicon oxycarbon nitride.

[0043] Implantation for lightly doped source / drain (LDD) regions 86 may also be performed. In embodiments having different device types, similar to the implantation for the well discussed previously, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of the appropriate type (e.g., p-type) may be implanted into the exposed fins 52 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of the appropriate type (e.g., n-type) may be implanted into the exposed fins 52 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The LDD region 86 may have a thickness of approximately 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implantation damage and to activate implanted impurities.

[0044] exist Fig. 6A and Figure 6BIn the embodiment of the present invention, epitaxial source / drain regions 88 are formed in the fin 52. The epitaxial source / drain regions 88 are formed in the fin 52 so that each dummy gate 74 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 88. In some embodiments, the epitaxial source / drain regions 88 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, the gate spacer 82 is used to separate the epitaxial source / drain regions 88 from the dummy gate 74 by an appropriate lateral distance so that the epitaxial source / drain regions 88 do not short-circuit the subsequently formed gate of the resulting FinFET. The material of the epitaxial source / drain regions 88 may be selected to exert stress in the corresponding channel region 58, thereby improving performance.

[0045] The epitaxial source / drain regions 88 in the n-type region 50N may be formed by masking the p-type region 50P and etching the source / drain regions of the fin 52 in the n-type region 50N to form recesses in the fin 52. The recesses may extend through the LDD region 86 (see FIG. Figure 5A ). Then, epitaxial source / drain regions 88 in the n-type region 50N are epitaxially grown in the recesses. The epitaxial source / drain regions 88 may include any acceptable material, such as suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 88 in the n-type region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 88 in the n-type region 50N may have surfaces that protrude from corresponding surfaces of the fin 52 and may have small facets.

[0046] The epitaxial source / drain regions 88 in the p-type region 50P may be formed by masking the n-type region 50N and etching the source / drain regions of the fin 52 in the p-type region 50P to form recesses in the fin 52. The recesses may extend through the LDD region 86 (see FIG. Figure 5A ). Then, epitaxial source / drain regions 88 in the p-type region 50P are epitaxially grown in the recesses. The epitaxial source / drain regions 88 may include any acceptable material, such as suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 88 in the p-type region 50P may include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 88 in the p-type region 50P may have surfaces that protrude from corresponding surfaces of the fin 52 and may have small facets.

[0047] The epitaxial source / drain regions 88 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming the LDD regions 86, followed by annealing. The source / drain regions may have a surface area of ​​about 10 19 cm-3 and about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 88 may be doped in situ during growth.

[0048] Due to the epitaxial process used to form epitaxial source / drain regions 88 in n-type region 50N and p-type region 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets allow adjacent epitaxial source / drain regions 88 to merge, such as Figure 6C In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 88 remain separated, as shown in FIG. Fig.6D As shown. The spacer etch used to form the gate spacer 82 can be adjusted to also form the fin spacer 84 on the sidewalls of the fin 52. In the embodiment shown, the fin spacer 84 covers the portion of the sidewall of the fin 52 that extends over the STI region 56, thereby preventing epitaxial growth. The fin spacers 84 between adjacent fins 52 can be merged (as shown), or can be separated. In another embodiment, the spacer etch used to form the gate spacer 82 is adjusted to not form the fin spacer 84 on the STI region 56, so as to allow the epitaxial growth region to extend to the surface of the STI region 56.

[0049] exist Fig. 7A and Figure 7B In the embodiment of the present invention, a first ILD 92 is deposited over the epitaxial source / drain regions 88, the gate spacers 82, the STI regions 56, and the mask 76 (if present) or the dummy gate 74. The first ILD 92 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0050] In some embodiments, a contact etch stop layer (CESL) 90 is formed between the first ILD 92 and the epitaxial source / drain regions 88, the gate spacers 82, the STI regions 56, and the mask 76 (if present) or the dummy gate 74. The CESL 90 may include a dielectric material having a lower etch rate than the material of the first ILD 92, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0051] exist Fig. 8A and Figure 8BIn the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 92 flush with the top surface of the mask 76 (if present) or the dummy gate 74. The planarization process may also remove the mask 76 on the dummy gate 74 and the portion of the gate spacer 82 along the sidewall of the mask 76. After the planarization process, the top surfaces of the dummy gate 74, the gate spacer 82, and the first ILD 92 are coplanar (within process variations). Therefore, the top surface of the dummy gate 74 is exposed through the first ILD 92. In some embodiments, the mask 76 may remain, in which case the planarization process makes the top surface of the first ILD 92 flush with the top surface of the mask 76.

[0052] exist Fig. 9A and Fig. 9B During the process, mask 76 (if present) and dummy gate 74 and optional dummy dielectric 72 are removed and replaced with a replacement gate structure. The replacement gate structure includes gate dielectric 112 and gate electrode 114. As will be discussed in more detail below, replacement gate structures having different channel lengths are formed in different regions, and various processing processes are performed during the gate replacement process to form devices having different threshold voltages in different regions.

[0053] FIG. 10A to FIG. 15B is a cross-sectional view of an intermediate stage in the formation of a replacement gate structure according to some embodiments. Fig. 9A Components in the region 50R in the region 50R. In the process shown, the pseudo dielectric 72 and the pseudo gate 74 are replaced. In some embodiments, the pseudo dielectric 72 is removed in a first region of the die (e.g., the core logic region) and retained in a second region of the die (e.g., the input / output region). In other words, the gate replacement process shown can be implemented in the first region of the die (e.g., the core logic region), and the gate replacement process without removing the pseudo dielectric 72 can be implemented in the second region of the die (e.g., the input / output region).

[0054] Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A A dense region 50D is shown where a replacement gate structure is formed. The gate structure in the dense region 50D has a short length channel region 58, such as a channel length of less than about 10 nm. For some types of devices, such as devices that operate at high speeds, a short channel length is desirable. Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14BA sparse region 50S is shown, in which a replacement gate structure is formed. The gate structure in the sparse region 50S has a long length of channel region 58, such as a channel length greater than about 18nm. For some types of devices, such as devices running at high power or applications requiring low leakage, a long channel length is ideal. More generally, the channel length of the device in the dense region 50D is shorter than the channel length of the device in the sparse region 50S. Therefore, the gate spacer 82 in the dense region 50D is arranged to be closer to each other than the gate spacer 82 in the sparse region 50S. In addition, the gate structure in the dense region 50D has a greater density than the gate structure in the sparse region 50S. Regions 50D and 50S are processed and discussed together at the same time. A single fin 52 is shown in each of regions 50D and 50S, but it should be understood that each of regions 50D and 50S can include fins 52 from both regions 50N and 50P. In other words, the dense region 50D and the sparse region 50S can each include an n-type device and a p-type device.

[0055] exist Fig. 10A and Fig. 10B In one embodiment, the mask 76 (if present) and the dummy gate 74 are removed in one or more etching steps, thereby forming a groove 94 between the opposing portions of the gate spacer 82. The groove 94 exposes the sidewalls of the gate spacer 82. In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 74 at a faster rate than the first ILD 92 or the gate spacer 82. Each groove 94 is located above the channel region 58 of the corresponding fin 52. During removal, when etching the dummy gate 74, the dummy dielectric 72 can be used as an etch stop layer. The dummy dielectric 72 can then be optionally removed after removing the dummy gate 74.

[0056] During patterning of the dummy gate 74, the pattern loading effect may cause the sidewalls of the portion of the dummy gate 74 close to the fin 52 to be etched less than the sidewalls of the portion of the dummy gate 74 far from the fin 52. The pattern loading effect is more significant in the dense region 50D than in the sparse region 50S, and is exacerbated as the technology shrinks (e.g., as the aspect ratio of the dummy gate 74 increases). Therefore, the groove 94D in the dense region 50D may have a bottle profile shape, while the groove 94S in the sparse region 50S may have a quadrilateral profile shape. In some embodiments, the sidewalls of the gate spacer 82 located in the dense region 50D are arched sidewalls, while the sidewalls of the gate spacer 82 located in the sparse region 50S are straight sidewalls (or at least less arched than the sidewalls of the gate spacer 82 located in the dense region 50D).

[0057] The bottle profile shape of the groove 94D is composed of Fig. 10ASpecifically, each of the grooves 94D has a main portion 94D with a first width W1. M and a neck portion 94D having a second width W2 N The width W1 may be in a range of about 5 nm to about 30 nm, and the width W2 may be in a range of about 3 nm to about 20 nm. The first width W1 is greater than the second width W2. In addition, the first width W1 extends through the main portion 94D in a direction D1 extending away from the top surface of the fin 52. M increases until it reaches a maximum width and then passes through the main portion 94D in direction D1 M The second width W2 may be along the direction D1 through the neck portion 94D N of constant width.

[0058] The quadrilateral outline shape of the groove 94S is composed of Fig. 10B . Specifically, each of the grooves 94S has a single portion having a third width W3. The third width W3 may be in the range of about 20 nm to about 80 nm. The third width W3 is greater than the first width W1 and the second width W2. The third width W3 may be a constant width along a direction D1 extending away from the top surface of the fin 52.

[0059] exist Fig.11A and Fig. 11B In the embodiment, a gate dielectric layer 102 and a gate electrode layer 104 are deposited in the recess 94. The gate dielectric layer 102 and the gate electrode layer 104 include a plurality of sub-layers. According to various embodiments, an exemplary film stack for the gate dielectric layer 102 and the gate electrode layer 104 is FIG. 29A to FIG. 29C shown in, and combined with Fig.11A and Fig. 11B describe.

[0060] The gate dielectric layer 102 is deposited in the recess 94, such as on the top surface of the fin 52 and the sidewalls of the gate spacer 82. The gate dielectric layer 102 may also be formed on the top surface of the first ILD 92. In some embodiments, the gate dielectric layer 102 includes one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. Although the gate dielectric layer 102 is shown as a single layer in this embodiment, in some embodiments the gate dielectric layer 102 may include multiple sub-layers. For example, the gate dielectric layer 102 may include an interfacial layer 102A (102A) of silicon oxide formed by thermal oxidation or chemical oxidation. FIG. 29A to FIG. 29C ) and the high-k dielectric material 102B above ( FIG. 29A to FIG. 29C), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Gate dielectric layer 102 may include a dielectric layer having a k value greater than about 7.0. The formation method of gate dielectric layer 102 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of pseudo dielectric 72 remains in recess 94, gate dielectric layer 102 includes the material of pseudo dielectric 72 (e.g., silicon oxide).

[0061] Optionally, a portion of the gate dielectric layer 102 is doped with a dipole-inducing element. For example, a dipole-dipole-inducing doping layer may be formed above the gate dielectric layer 102, and annealing may be performed to drive the dipole-dipole induction from the doping layer into the gate dielectric layer 102. The doping layer may be formed of an oxide, nitride, or carbide of a dipole-inducing element (such as lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, etc.), which may be formed by ALD, CVD, PVD, or other suitable deposition methods. In some embodiments, the doping layer is formed of an oxide of lanthanum, such as LaO x . Some embodiments may utilize multiple doped layers. For example, a first doped layer may be formed in a first region (e.g., a dense region 50D), and a second doped layer may be formed in a second region (e.g., a sparse region 50S). The doped layers in different regions may have different thicknesses and / or include different dipole-inducing elements. The presence, thickness, and materials of the doped layers may vary based on the desired threshold voltage of the device to be formed. For example, doped portions of the gate dielectric layer 102 with lanthanum may reduce the threshold voltage of a device formed with those doped portions of the gate dielectric layer 102. Once annealing is completed, the gate dielectric layer 102 is doped with the dipole-inducing element (e.g., lanthanum), and the doped layers may then be removed, such as by an acceptable etching process.

[0062] The process described above is only one example of how the gate dielectric layer 102 can be formed and doped with a dipole inducing element. Other techniques can be used to form the doped gate dielectric layer. For example, a first gate dielectric sublayer can be formed, a doped layer deposited over the first gate dielectric sublayer, and an anneal performed to drive the dipole dipole induction from the doped layer into the first gate dielectric sublayer. The doped layer can then be removed, and a second gate dielectric sublayer can be deposited over the first gate dielectric sublayer. Thus, the first gate dielectric sublayer can be doped, while the second gate dielectric sublayer is undoped.

[0063] A gate electrode layer 104 is deposited over the gate dielectric layer 102 and in the recess 94. The gate electrode layer 104 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. More specifically, the gate electrode layer 104 includes any number of work function adjustment layers 104A, any number of glue layers 104B, and a filler layer 104C.

[0064] The work function adjustment layer 104A includes any acceptable material to adjust the work function of the device to a desired amount given the application of the device to be formed, and can be deposited using any acceptable deposition process. For example, the work function adjustment layer 104A can be formed of aluminum, aluminum nitride, titanium aluminide, tantalum aluminum, titanium carbonitride, etc., which can be deposited by ALD, CVD, PVD, etc. In some embodiments, the work function adjustment layer 104A is deposited by a conformal process such as ALD, which allows for a more consistent film thickness. In some embodiments, the work function adjustment layer 104A is deposited by a non-conformal process such as PVD, which allows for greater manufacturing yields. Although the work function adjustment layer 104A is shown as a single layer in this embodiment, in some embodiments the work function adjustment layer 104A may include multiple sub-layers. For example, the work function adjustment layer 104A may include a first adjustment layer 104A1 (see FIG. 29A to FIG. 29C ), may include a second adjustment layer 104A2 (see Fig.29B and Fig.29C ), and may further include a third adjustment layer 104A3 (see Fig.29C In some embodiments, only a single work function adjustment layer 104A is formed between the glue layer 104B and the filling layer 104C (see Fig.29A In some embodiments, a plurality of work function adjustment layers 104A are formed between the glue layer 104B and the filling layer 104C (see Fig.29B and Fig.29C ). The work function adjustment layer 104A may be formed based on a desired threshold voltage of the device.

[0065] Different structures of the work function adjustment layer 104A may be formed in different regions. As an example of forming the work function adjustment layer 104A, the first adjustment layer 104A1 may be deposited in all regions and then etched to remove the portion of the first adjustment layer 104A1 located in the undesired region. The second adjustment layer 104A2 may then be deposited in all regions (and on the first adjustment layer 104A1) and then etched to remove the portion of the second adjustment layer 104A2 located in the undesired region. The third adjustment layer 104A3 may then be deposited in all regions (and on the second adjustment layer 104A2) and then etched to remove the portion of the third adjustment layer 104A3 located in the undesired region. Therefore, some regions may include the first adjustment layer 104A1, other regions may include the first adjustment layer 104A1 and the second adjustment layer 104A2, and still other regions may include the first adjustment layer 104A1, the second adjustment layer 104A2, and the third adjustment layer 104A3.

[0066] One or more capping layers may be formed prior to the work function adjustment layer 104A. In some embodiments, the capping layer is deposited, removed (e.g., by etching), and redeposited, which helps remove residual dipole-inducing elements (e.g., lanthanum) that may remain on the top surface of the gate dielectric layer 102. Annealing may be performed after removing the capping layer and before redepositing the capping layer to help remove the residual dipole-inducing elements.

[0067] Glue layer 104B includes any acceptable material to promote adhesion and prevent diffusion. For example, glue layer 104B may be formed of a metal or metal nitride, such as titanium nitride, titanium aluminide, aluminum titanium nitride, silicon-doped titanium nitride, tantalum nitride, etc., which may be deposited by ALD, CVD, PVD, etc. In some embodiments, glue layer 104B is deposited by a conformal process such as ALD, which allows for a more consistent film thickness. In some embodiments, glue layer 104B is deposited by a non-conformal process such as PVD, which allows for greater manufacturing yields.

[0068] Filling layer 104C includes any acceptable low resistance material. For example, filling layer 104C can be formed of a metal, such as tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), combinations thereof, etc., which can be deposited by ALD, CVD, PVD, etc. In some embodiments, filling layer 104C is deposited by a conformal process such as ALD, which allows for a more consistent film thickness. In some embodiments, filling layer 104C is deposited by a non-conformal process such as PVD, which allows for greater manufacturing yields. As will be discussed in more detail below, filling layer 104C completely fills the remainder of recess 94S, but filling layer 104C only partially fills the remainder of recess 94D, thereby forming void 104D.

[0069] During the deposition of the gate electrode layer 104, the neck portion 94D of the groove 94D N The gate electrode layer 104 completely fills the neck portion 94D of the groove 94D. N , but the gate electrode layer 104 only partially fills the main portion 94D of the groove 94D M The gap 104D is defined. The gap 104D includes the remaining portion of the recess 94D that is not filled by the gate electrode layer 104. Pinching may occur during the deposition of any of the work function adjustment layers 104A (e.g., adjustment layers 104A1, 104A2, 104A3), the glue layer 104B, or the fill layer 104C. The layer where pinching occurs depends on the width of the recess 94D, the number of layers deposited, and the conformality of the deposition process used to deposit the layers. For example, when less work function adjustment layer 104A is formed (e.g., Fig.29A In the case of an embodiment of the present invention, or in the case of a conformal deposition process, pinching off may occur later in the process, such as during the deposition of the fill layer 104C. In contrast, when more work function adjustment layer 104A is formed (e.g., Fig.29B and Fig.29C ) or in the case of a non-conformal deposition process, pinch-off may occur earlier in the process, such as during deposition of one of the glue layer 104B or the work function adjustment layer 104A.

[0070] In this embodiment, some fill layer 104C is deposited in the main portion 94D of the groove 94D. M After that, pinch-off occurs during the deposition of fill layer 104C. This pinch-off may occur in embodiments where a work function adjustment layer is formed (e.g., Fig.29A 104D) or in an embodiment using a conformal deposition process. Therefore, the void 104D exposes the surface of the filling layer 104C, and the filling layer 104C separates the void 104D from the glue layer 104B and the work function adjustment layer 104A. In such an embodiment, the void 104D is initially formed to have a teardrop profile shape. The teardrop profile shape of the void 104D can have a height in the range of about 5 nm to about 80 nm and a maximum width in the range of about 2 nm to about 8 nm.

[0071] exist Fig. 12A and Fig. 12BIn the embodiment of the present invention, a gate treatment process 106 is performed to modify the work function of the gate electrode layer 104. The gate treatment process 106 incorporates one or more work function adjustment elements into one or more of the gate electrode layers 104, which can increase the work function of the gate electrode 114. The work function adjustment element can also penetrate the gate electrode layer 104 and be incorporated into the gate dielectric layer 102. The gate treatment process 106 includes a fluorination process (which incorporates fluorine), a nitridation process (which incorporates nitrogen), an oxidation process (which incorporates oxygen), a deposition process (which incorporates chlorine, boron and / or silicon), combinations thereof, and the like. The type and amount of work function adjustment elements incorporated by the gate treatment process 106 can be controlled based on the desired threshold voltage of the device to be formed. For example, the incorporation of fluorine can increase the work function of the gate electrode layer 104 for a p-type device, thereby reducing the threshold voltage of the device.

[0072] In some embodiments, the gate treatment process 106 includes a fluorination process, wherein the gate dielectric layer 102 and / or the gate electrode layer 104 are exposed to fluorine. The fluorination process can be implemented in a chamber such as an etching chamber. A gas source is distributed in the chamber. The gas source includes a fluorine source gas and a carrier gas. The fluorine source gas can be fluorine (F2) gas, nitrogen trifluoride (NF3), tungsten fluoride (VI) (WF6), a combination thereof, etc. The carrier gas can be an inert gas such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), radon (Rn), a combination thereof, etc. In some embodiments, the fluorine source gas is about 10% to about 50% of the gas source, and the carrier gas is about 50% to about 90% of the gas source. The gas source can be distributed at a flow rate of about 50sccm to about 1000sccm. The fluorine in the gas source is incorporated into the gate electrode layer 104 (e.g., the work function adjustment layer 104A, the glue layer 104B and / or the filling layer 104C), thereby changing the work function of the affected gate electrode layer 104. The fluorine in the gas source can also be incorporated into the gate dielectric layer 102, thereby improving the quality of the gate dielectric layer 102. For example, fluorine can passivate oxygen vacancies in the gate dielectric layer 102, reduce its leakage and increase the reliability of the device. The gas source is maintained in the chamber until the gate dielectric layer 102 and / or the gate electrode layer 104 have been fluorinated by the desired amount. In some embodiments, the fluorination process is performed at a temperature of about 25° C. to about 550° C. and lasts for about 10 seconds to about 2700 seconds.

[0073] In some embodiments, the gate treatment process 106 includes a nitridation process, wherein the gate dielectric layer 102 and / or the gate electrode layer 104 are exposed to nitrogen. The nitridation process can be implemented in a chamber such as an etching chamber. A gas source is distributed in the chamber. The gas source includes a nitrogen source gas and a carrier gas. The nitrogen source gas can be a combination of ammonia (NH3), cracked ammonia, nitrogen (N2) and hydrogen (H2) gas, a combination thereof, and the like. The carrier gas can be an inert gas such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), radon (Rn), a combination thereof, and the like. In some embodiments, the nitrogen source gas is about 10% to about 50% of the gas source, and the carrier gas is about 50% to about 90% of the gas source. The gas source can be distributed at a flow rate of about 500 sccm to about 5000 sccm. In some embodiments, such as when the nitrogen source gas is a combination of N2 and H2, a plasma is generated from the gas source to generate nitrogen radicals and corresponding ions. The nitrogen in the source gas / plasma is incorporated into the gate electrode layer 104 (e.g., the work function adjustment layer 104A, the glue layer 104B, and / or the filling layer 104C), thereby changing the work function of the affected gate electrode layer 104. The source gas / plasma is maintained in the chamber until the gate dielectric layer 102 and / or the gate electrode layer 104 have been nitrated by a desired amount. In some embodiments, the nitridation process is performed at a temperature of about 100° C. to about 650° C. and lasts for about 10 seconds to about 2700 seconds.

[0074] In some embodiments, the gate treatment process 106 includes an oxidation treatment process, in which the gate dielectric layer 102 and / or the gate electrode layer 104 are exposed to oxygen. For example, a low temperature annealing can be performed in an environment containing oxygen and an inert gas. The inert gas can be argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), radon (Rn), combinations thereof, and the like. In some embodiments, oxygen is about 1% to about 10% of the environment, and the inert gas is about 90% to about 99% of the environment. The low temperature annealing can be performed at a temperature of about 150° C. to about 500° C. and lasts for about 10 seconds to about 2700 seconds. The oxidation treatment process can also increase the reliability of the device to be formed, such as by densifying the gate electrode layer 104.

[0075] In some embodiments, the gate treatment process 106 includes a deposition process, wherein the gate dielectric layer 102 and / or the gate electrode layer 104 are exposed to chlorine, boron and / or silicon. For example, a thin layer containing chlorine, boron and / or silicon can be deposited on the gate electrode layer 104 by CVD. The deposition process can be implemented in a chamber such as a deposition chamber. A gas source is distributed in the chamber. The gas source includes a precursor gas and a carrier gas. The precursor gas can be boron trichloride (BCl3), silane (SiH4), disilane (Si2H6), diborane (B2H6), combinations thereof, etc. The carrier gas can be an inert gas such as argon (Ar), helium (He), xenon (Xe), neon (Ne), krypton (Kr), radon (Rn), combinations thereof, etc. In some embodiments, the precursor gas is about 1% to about 10% of the gas source, and the carrier gas is about 90% to about 99% of the gas source. The gas source can be distributed at a flow rate of about 50sccm to about 500sccm. The precursor gases may be combined to deposit a layer including a desired element (e.g., chlorine, boron, silicon, etc.) on the gate electrode layer 104, thereby changing the work function of the affected gate electrode layer 104. The gas source is maintained in the chamber until the desired amount of the element has been deposited on the gate dielectric layer 102 and / or the gate electrode layer 104. In some embodiments, the deposition process is performed at a temperature of about 300° C. to about 650° C. and lasts for about 10 seconds to about 1000 seconds.

[0076] exist Fig.13A and Fig. 13B In the process, a planarization process such as CMP is performed to remove excess portions of the gate dielectric layer 102 and the gate electrode layer 104, which are located above the top surface of the first ILD 92. The remaining portion of the gate dielectric layer 102 located in the recess 94 forms a gate dielectric 112. The remaining portion of the gate electrode layer 104 located in the recess 94 forms a gate electrode 114. After the planarization process is completed, the top surfaces of the gate electrode 114, the gate dielectric 112, the first ILD 92, and the gate spacer 82 are coplanar (within process variations). The gate dielectric 112 and the gate electrode 114 form a replacement gate structure of the FinFET. The gate dielectric 112 and the gate electrode 114 can each be collectively referred to as a "gate stack". The gate structure extends along the sidewalls of the channel region 58 of the fin 52.

[0077] The gate electrode 114D in the dense region 50D has a void 104D disposed therein. After the gate structure reaches the desired height, a timed planarization process can be used to stop planarizing the gate dielectric layer 102 and the gate electrode layer 104. In the embodiment shown, the height of the gate structure is controlled so that the void 104D is destroyed by the planarization process, which effectively reforms the recess 94D (see FIG. Fig. 10A and Fig.11A For example, the planarization process may be performed until the neck portion 94D of the gate electrode layer 104 located in the groove 94D is removed.N Part of (see Fig.13A ) and the void 104D is exposed at the top surface of the gate electrode 114D, so that the top surface of the gate electrode 114D extends discontinuously between the sidewalls of the gate electrode 114D. In another embodiment, the height of the gate structure is controlled so that the void 104D is not destroyed by the planarization process. For example, the planarization process can be stopped while the neck portion 94D of the gate electrode layer 104 located in the groove 94D is N Part of (see Fig.13A ) remains and the void 104D is not exposed at the top surface of the gate electrode 114S, so that the top surface of the gate electrode 114D extends continuously between the sidewalls of the gate electrode 114D.

[0078] The gate electrode 114S in the sparse region 50S may not have a void disposed therein. Therefore, no void is exposed at the top surface of the gate electrode 114S, so that the top surface of the gate electrode 114S extends continuously between the sidewalls of the gate electrode 114S. In another embodiment, the gate electrode 114S also has a void, but has a smaller void than the gate electrode 114D.

[0079] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a gate treatment process 116 is performed to modify the work function of the gate electrode 114. The gate treatment process 116 incorporates one or more work function adjustment elements into one or more of the gate electrode layers 104, which can increase the work function of the gate electrode 114. The gate treatment process 116 may include a process selected from the above for Fig. 12A and Fig. 12B The gate treatment process 106 and the gate treatment process 116 may be the same process or may include different processes. For example, performing the gate treatment process 116 may include repeating the gate treatment process 106 or may include performing a different gate treatment process. The type and amount of work function adjustment elements incorporated by the gate treatment process 116 may be controlled based on the desired threshold voltage of the device to be formed. For example, the incorporation of fluorine may increase the work function of the gate electrode 114 for a p-type device, thereby lowering the threshold voltage of the device.

[0080] As noted above, the gate electrode 114D has a void 104D that may be exposed at the top surface of the gate electrode 114D, while the gate electrode 114S may not have a void (or at least have a smaller void). When the void 104D is exposed at the top surface of the gate electrode 114D, the void 104D exposes the inner surface of the gate electrode 114D, and the gate treatment process 116 is performed in the void 104D. Therefore, the gate electrode 114D has more surface area exposed to the gate treatment process 116 than the gate electrode 114S. Therefore, the gate treatment process 116 modifies the work function of the gate electrode 114D more than it modifies the work function of the gate electrode 114S. Specifically, the gate treatment process 116 increases the concentration of the work function adjustment element in the gate electrode 114D and the gate electrode 114S, but it increases the concentration of the work function adjustment element in the gate electrode 114D more than it increases the concentration of the work function adjustment element in the gate electrode 114S. In some embodiments, the gate treatment process 116 modifies the work function of the gate electrode 114D, while substantially no modification of the work function of the gate electrode 114S occurs due to the absence of voids in the gate electrode 114S. In addition, the gate treatment process 116 introduces (or at least increases the concentration of) the work function adjustment element 104E at the inner surface of the gate electrode 114D, such that the inner surface includes the work function adjustment element 104E. For example, a portion of the gate electrode 114D proximate to the inner surface of the gate electrode 114D may include the material of the gate electrode 114D and the work function adjustment element 104E. The gate electrode 114S may be substantially free of the work function adjustment element 104E.

[0081] FIG. 15A to FIG. 17B is a cross-sectional view of a further intermediate stage in the formation of a replacement gate structure according to some embodiments. Fig. 9B The components in the area are shown in addition to the four gate structures. Fig.15A , Fig.16A and Fig.17A A dense region 50D is shown, while Fig. 15B , Fig. 16B and Fig. 17B Sparse regions 50S are shown. In the process shown, isolation regions are formed to divide the gate electrodes 114. The isolation regions thus separate gate electrodes 114 having the same longitudinal axis. The isolation regions provide physical and electrical isolation between gate electrodes 114 of different devices.

[0082] exist Fig.15A and Fig. 15BIn the embodiment of the present invention, an opening 122 is formed through the gate electrode 114. The opening 122 may also be formed through the gate dielectric 112, in which case the STI region 56 is exposed. The opening 122 may be formed using acceptable photolithography and etching techniques. The etching may be any acceptable etching process using an etching mask (such as a photoresist) having a pattern of the opening 122, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

[0083] exist Fig.16A and Fig. 16B In the embodiment of the present invention, a gate treatment process 126 is performed to modify the work function of the gate electrode 114. The gate treatment process 126 incorporates one or more work function adjustment elements into one or more of the gate electrode layers 104, which can increase the work function of the gate electrode 114. The gate treatment process 126 may include a process selected from the above for Fig. 12A and Fig. 12B The gate treatment process 106 and the gate treatment process 126 may be the same process or may include different processes. For example, implementing the gate treatment process 126 may include repeating the gate treatment process 106 or may include implementing a different gate treatment process. The type and amount of work function adjustment elements incorporated by the gate treatment process 126 may be controlled based on the desired threshold voltage of the device to be formed. For example, the incorporation of fluorine may increase the work function of the gate electrode 114 for a p-type device, thereby reducing the threshold voltage of the device.

[0084] As noted above, gate electrode 114D has void 104D, while gate electrode 114S may not have a void (or at least have a smaller void). Void 104D exposes the inner surface of gate electrode 114D (see Fig.14A ), so that gate electrode 114D has more surface area exposed to gate treatment process 126 than gate electrode 114S. Opening 122 provides additional access to void 104D at the end of gate electrode 114D. Therefore, void 104D can be exposed at the top surface and / or sidewall of gate electrode 114D, thereby increasing the opportunity for gate treatment process 126 to process the inner surface of gate electrode 114D. In addition, when void 104D is not exposed at the top surface of gate electrode 114D, forming opening 122 can allow void 104D to be exposed at the sidewall of gate electrode 114D. Similar to the above for Fig.14A and Fig. 14BIn discussing the gate treatment process 116, the gate treatment process 126 modifies the work function of the gate electrode 114D more than it modifies the work function of the gate electrode 114S. Specifically, the gate treatment process 126 increases the concentration of the work function adjusting element in both the gate electrode 114D and the gate electrode 114S, but it increases the concentration of the work function adjusting element in the gate electrode 114D more than it increases the concentration of the work function adjusting element in the gate electrode 114S. In some embodiments, the gate treatment process 126 modifies the work function of the gate electrode 114D, while substantially no modification of the work function of the gate electrode 114S occurs due to the absence of voids in the gate electrode 114S. In addition, the gate treatment process 126 introduces (or at least increases the concentration of) the work function adjusting element 104E (see FIG. 1 ) at the inner surface of the gate electrode 114D. Fig.14A ). For example, a portion of the gate electrode 114D near the inner surface of the gate electrode 114D may include materials of the gate electrode 114D and the work function adjustment element 104E. The gate electrode 114S may be substantially free of the work function adjustment element 104E.

[0085] In the illustrated embodiment, gate treatment processes 116, 126 are performed. One of gate treatment processes 116, 126 may be omitted. In some embodiments, gate treatment process 116 is performed and gate treatment process 126 is omitted. In some embodiments, gate treatment process 126 is performed and gate treatment process 116 is omitted. Gate treatment processes 116, 126 may be included or omitted based on whether void 104D is exposed at the top surface of gate electrode 114D. For example, when void 104D is exposed at the top surface of gate electrode 114D, gate treatment process 116 may be performed and gate treatment process 126 may be omitted, or when void 104D is not exposed at the top surface of gate electrode 114D, gate treatment process 126 may be performed and gate treatment process 116 may be omitted. Gate treatment processes 116, 126 may also be included or omitted based on adjusting element concentrations (and therefore threshold voltages) of the desired work function of the device to be formed. As noted above, substantially no modification of the work function of gate electrode 114S occurs as a result of gate treatment processes 116, 126. In embodiments where both gate treatment processes 116 and 126 are implemented, the gate electrode 114D may have a concentration of a work function adjustment element (e.g., fluorine, nitrogen, oxygen, chlorine, boron, silicon, etc.) in a range of about 1 at.% to about 28 at.%, such as at least 5×10 16 cm -3In some embodiments, the gate electrode 114D, 114S may have a concentration of the work function adjustment element that is substantially zero. Including the work function adjustment element in the gate electrodes 114D, 114S at a concentration within such a range may allow for the formation of devices with sufficiently different (e.g., distinguishable) threshold voltages. Including the work function adjustment element in the gate electrodes 114D, 114S at a concentration outside of such a range may not allow for the formation of devices with sufficiently different (e.g., distinguishable) threshold voltages.

[0086] exist Fig.17A and Fig. 17B In the embodiment shown, an insulating material is formed in the opening 122 to form an isolation region 128. The isolation region 128 provides isolation between the gate electrodes 114. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by HDP-CVD, FCVD (for example, CVD-based material deposition in a remote plasma system and post-curing to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. The insulating material of the isolation region 128 can be the same as the insulating material of the STI region 56, or can be a different insulating material. In the embodiment shown, the insulating material is silicon nitride.

[0087] exist Fig.18A and Fig.18B In the embodiment of the present invention, a second ILD 132 is deposited over the gate spacer 82, the CESL 90, the first ILD 92, the gate dielectric 112, and the gate electrode 114. In some embodiments, the second ILD 132 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 132 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD and PECVD.

[0088] In some embodiments, an etch stop layer (ESL) 130 is formed between the second ILD 132 and the gate spacers 82, CESL 90, first ILD 92, gate dielectric 112, and gate electrode 114. The ESL 130 may include a dielectric material having a high etch selectivity to the second ILD 132, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0089] exist Fig.19A and Fig.19B, source / drain contacts 134 and gate contacts 136 are formed to contact the epitaxial source / drain regions 88 and the gate electrode 114, respectively. An opening for the source / drain contact 134 is formed through the CESL 90, the first ILD 92, the ESL 130, and the second ILD 132. An opening for the gate contact 136 is formed through the ESL 130 and the second ILD 132. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be implemented to remove excess material from the surface of the second ILD 132. The remaining liner and conductive material form the source / drain contact 134 and the gate contact 136 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 88 and the source / drain contacts 134. The source / drain contacts 134 are physically and electrically coupled to the epitaxial source / drain regions 88, and the gate contacts 136 are physically and electrically coupled to the gate electrode 114. The source / drain contacts 134 and the gate contacts 136 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contacts 134 and the gate contacts 136 may be formed in different cross sections, which may avoid shorting of the contacts.

[0090] Fig. 20A and Fig. 20B is a cross-sectional view of a FinFET according to some embodiments. Figures 2 to 19B The steps of the process produce a device. Fig. 20A and Fig. 20B Shows something like Fig.19A The components in the region 50R in the region (with FIG. 10A to FIG. 14B The gate electrode 114D has a gap 104D which is sealed at the top (and thus defined) by the ESL 130 and / or the gate contact 136 and which is sealed at the side (and thus defined) by the sidewalls of the isolation region 128 (see FIG. Fig.17A and Fig. 17B). The work function adjustment element 104E is located in the void 104D, such as at the inner surface of the gate electrode 114D that defines the void 104D. The work function adjustment element 104E may not be located at the inner surface of the ESL 130 and / or the gate contact 136 that defines the void 104D. In addition, the gate electrode 114S may not have a void (or at least have a smaller void). Due to the gate processing processes 116, 126, the gate electrode 114D has a higher work function adjustment element concentration than the gate electrode 114S. Therefore, the FinFET in the dense area 50D has a different threshold voltage than the FinFET in the dense area 50S. For example, when the FinFET is a p-type device, the FinFET in the dense area 50D has a smaller threshold voltage than the FinFET in the dense area 50S.

[0091] FIG. 21A to FIG. 22B is a cross-sectional view of an intermediate stage in the formation of a replacement gate structure according to some other embodiments. Fig.21A and Fig.21B Shown with Fig.11A and Fig. 11B Similar processing steps. Fig.22A and Fig. 22B Shown with Fig.13A and Fig. 13B Similar processing steps. In this embodiment, any fill layer 104C is deposited in the main portion 94D of the groove 94D. M Prior to this, pinch-off occurred during the deposition of the fill layer 104C (see Fig.21A and Fig.21B ). This pinch-off may be useful in embodiments where multiple work function adjustment layers are formed (e.g., Fig.29B and Fig.29C In the embodiment of the present invention, or in the embodiment using a non-conformal deposition process, the gap 104D exposes the surface of the filling layer 104C and the surface of the glue layer 104B. In this embodiment, the height of the gate structure is controlled so that the neck portion 94D of the gate electrode layer 104 located in the groove 94D is N Part of (see Fig.21A ) remains and the gate electrode 114D still includes some filling layer 104C after planarization (see Fig.22A and Fig. 22B ). Therefore, the gate electrode 114S includes the conformal filling layer 104C, and the gate electrode 114D includes the neck portion 94D of the groove 94D. NIn such an embodiment, the void 104D is formed to have a bottle profile shape. The bottle profile shape of the void 104D may have a height in the range of about 5 nm to about 80 nm, a main portion with a width in the range of about 2 nm to about 8 nm, and a neck portion with a width in the range of about 1 nm to about 7 nm. The width of the neck portion may be up to about 88% smaller than the width at the bottom of the main portion, and the maximum width of the main portion may be up to about 33% greater than the width at the bottom of the main portion. In another embodiment, the height of the gate structure is controlled so that the void 104D is destroyed by the planarization process. Therefore, the gate electrode 114S includes the filling layer 104C, but the gate electrode 114D does not include the filling layer.

[0092] Fig.23A and Fig. 23B is a cross-sectional view of a FinFET according to some other embodiments. FIG. 21A to FIG. 22B The steps of the process produce a device. Fig.23A and Fig. 23B Shows something like Fig.19A The components in the region 50R in the region (with FIG. 10A to FIG. 14B in a similar way).

[0093] FIG. 24A to FIG. 25B is a cross-sectional view of an intermediate stage in the formation of a replacement gate structure according to some other embodiments. Fig.24A and Fig. 24B Shown with Fig.11A and Fig. 11B Similar processing steps. Fig.25A and Fig.25B Shown with Fig.13A and Fig. 13B Similar processing steps. In this embodiment, any glue layer 104B is deposited on the main portion 94D of the groove 94D. M Prior to this, pinch-off occurred during the deposition of the glue layer 104B (see Fig.24A and Fig. 24B ). This pinch-off may be useful in embodiments where multiple work function adjustment layers are formed (e.g., Fig.29B and Fig.29C In the embodiment of the present invention, or in the embodiment using a non-conformal deposition process, the gap 104D exposes the surface of the glue layer 104B and the surface of the work function adjustment layer 104A. In this embodiment, the height of the gate structure is controlled so that the neck portion 94D of the gate electrode layer 104 located in the groove 94D is N Part of (see Fig.24A ) remains, and the gate electrode 114D still includes some glue layer 104B after planarization (see Fig.25A and Fig.25B). Therefore, the gate electrode 114S includes the conformal glue layer 104B and the conformal filling layer 104C, and the gate electrode 114D includes a neck portion 94D located in the groove 94D. N 104B in the gate electrode 114D. The gate electrode 114D does not include a filling layer. In such an embodiment, the gap 104D is formed to have a bottle profile shape. The bottle profile shape of the gap 104D can have a height in the range of about 5nm to about 80nm, a main portion with a width in the range of about 2nm to about 8nm, and a neck portion with a width in the range of about 1nm to about 7nm. The width of the neck portion can be up to about 88% smaller than the width at the bottom of the main portion. The maximum width of the main portion can be up to about 33% larger than the width at the bottom of the main portion. In another embodiment, the height of the gate structure is controlled so that the gap 104D is destroyed by the planarization process. Therefore, the gate electrode 114S includes the glue layer 104B and the filling layer 104C, but the gate electrode 114D does not include a glue layer or a filling layer.

[0094] Fig.26A and Fig.26B is a cross-sectional view of a FinFET according to some other embodiments. FIG. 24A to FIG. 25B The steps of the process produce a device. Fig.26A and Fig.26B Shows something like Fig.19A The components in the region 50R in the region (with FIG. 10A to FIG. 14B in a similar way).

[0095] Fig. 27 2 is a spectrum diagram showing the composition of the gate electrode 114 after the gate treatment processes 116, 126. The first set of data 202 shows the composition of the filling layer of the gate electrode formed without the gate treatment processes 116, 126. The second set of data 204 shows the composition of the filling layer of the gate electrode formed using the gate treatment processes 116, 126. As shown in the figure, the amount of the work function adjustment element 104E measured in the gate electrode is significantly increased by the gate treatment processes 116, 126.

[0096] Fig.28 30 is a graph showing the threshold voltage of the resulting device. The first set of data 302 shows the threshold voltage of the device formed without the gate processing process 116, 126. The second set of data 304 shows the threshold voltage of the device formed using the gate processing process 116, 126. It can be seen that the gate processing process 116, 126 causes the device with a shorter channel length to experience a larger threshold voltage increase than the device with a longer channel length. This increase is due to the formation of a gap in the gate electrode of the device with a shorter channel length. In one example, the threshold voltage of the device with a shorter channel length increases by about 20mV to about 100mV.

[0097] The disclosed FinFET embodiments may also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacks of alternating layers of patterned channel layers and sacrificial layers. A dummy gate structure and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate structure, the sacrificial layer may be partially or completely removed in the channel region. A replacement gate structure is formed in a manner similar to the embodiments described above, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. An ILD and contacts to the replacement gate structure and source / drain regions may be formed in a manner similar to the embodiments described above. The nanostructured device may be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0098] The formation of nanostructured devices is introduced below using No. 2016 / 0365414 as an example.

[0099] exist Fig. 30A , Fig. 30B and Fig. 30C In the embodiment, substantially only the second layer 28 of the superlattice 24 is etched. Due to this etching step, the sidewalls of the etched second layer 28d are offset inwardly toward the fin from the sidewalls of the first layer 26 on the corresponding side. This etching produces a fourth modified superlattice 24d. In some embodiments, as Fig. 30A , Fig. 30B and Fig. 30C The results of the etching shown may be a function of the material of the first layer 26 and the second layer 28, the orientation of the sidewalls, and the etchant used for etching. For example, continuing with this specific example, where each first layer 26 is Si 0.50 Ge 0.50 The buffer layer 22, the first layer 26 and the second layer 28 are each a layer of Si, the buffer layer 22, the first layer 26 and the second layer 28 are epitaxially grown on the (110) surface of the bulk Si substrate, and the sidewalls of the first layer 26 and the second layer 28 are (111) crystal surfaces. In addition, the etchant can be a wet etchant, such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) and the like, which are selective to the (111) crystal surface of the Si second layer 28. These conditions can produce a etchant from Si. 0.50 Ge 0.50 The (111) crystal side wall surfaces of the first layer 26 are shifted inwardly toward the (111) crystal side wall surfaces of the etched Si second layer 28d.

[0100] Fig.31A , Fig.31B and Fig.31C Shown in undergoing Fig. 30A , Fig. 30B and Fig. 30C 4 and after continuing with other processing steps (such as forming a gate dielectric 42 and a gate electrode 44 in the opening through ILD0 40, depositing an ILD (ILD1) 46 over ILD0 40 and gate electrode 44, and forming a contact 48 through ILD1 46 and ILD0 40 to the epitaxial source / drain region 38). Fig.31C As shown, gate dielectric 42 conforms to the etched sidewalls in fourth modified superlattice 24d. In addition, since etched second layer 28d has been etched, gate electrode 44 may at least partially extend between or closer to the surface of first layer 26.

[0101] Embodiments can achieve advantages. Due to the nature of the increased surface area of ​​the gate electrode 114D exposed by the void 104D, forming the void 104D in the gate electrode 114D allows the gate treatment processes 116, 126 to affect the gate electrode 114D more than the gate electrode 114S. Therefore, the gate treatment processes 116, 126 can incorporate more work function adjustment elements (e.g., fluorine, nitrogen, oxygen, chlorine, boron, silicon, etc.) into the gate electrode 114D relative to the gate electrode 114S. Therefore, the gate treatment processes 116, 126 can be used to selectively adjust the threshold voltage of the device in the dense region 50D, even when the gate treatment processes 116, 126 are implemented in the dense region 50D and the sparse region 50S. Therefore, the FinFET formed with the gate electrode 114D has a different threshold voltage than the FinFET formed with the gate electrode 114S. For example, when the FinFET is a p-type device, the FinFET formed with the gate electrode 114D may have a smaller threshold voltage than the FinFET formed with the gate electrode 114S.

[0102] In an embodiment, a device includes: a gate dielectric located above a substrate; a gate electrode located above the gate dielectric, the gate electrode including: a work function adjustment layer located above the gate dielectric; a glue layer located above the work function adjustment layer; a fill layer located above the glue layer; and a void defined by an inner surface of at least one of the fill layer, the glue layer, and the work function adjustment layer, the material of the gate electrode at the inner surface including a work function adjustment element. In some embodiments of the device, the inner surface is an inner surface of the fill layer, and the work function adjustment layer is the only work function adjustment layer between the glue layer and the gate dielectric. In some embodiments of the device, the inner surface is an inner surface of the glue layer, and the work function adjustment layer is one of a plurality of work function adjustment layers located between the glue layer and the gate dielectric. In some embodiments of the device, the inner surface is an inner surface of the work function adjustment layer, and the work function adjustment layer is one of a plurality of work function adjustment layers located between the glue layer and the gate dielectric. In some embodiments of the device, the work function adjustment element is fluorine, nitrogen, oxygen, chlorine, boron, or silicon. In some embodiments of the device, the material of the gate electrode at the inner surface includes a work function adjustment element with a concentration in the range of 1 at.% to 28 at.%. In some embodiments, the device further includes: a contact located above the gate electrode, and the gap is further defined by the bottom surface of the contact. In some embodiments, the device further includes: an isolation region adjacent to an end of the gate electrode, and the gap is further defined by the sidewall of the isolation region.

[0103] In an embodiment, a device includes: a first transistor including: a first channel region, the first channel region having a first length; and a first gate structure located above the first channel region, the first gate structure including a first gate electrode, the first gate electrode having a void therein; and a second transistor including: a second channel region, the second channel region having a second length, the second length being greater than the first length; and a second gate structure located above the second channel region, the second gate structure including a second gate electrode, the second gate electrode having no void, and the second gate electrode having a different work function than the first gate electrode. In some embodiments of the device, the first gate electrode includes a metal and a work function adjustment element, and the second gate electrode includes a metal and no work function adjustment element. In some embodiments of the device, the metal is tungsten, and the work function adjustment element is fluorine, nitrogen, oxygen, chlorine, boron, or silicon. In some embodiments, the device also includes: a first gate spacer adjacent to the first gate structure, the first gate spacer having an arched sidewall; and a second gate spacer adjacent to the second gate structure, the second gate spacer having a straight sidewall. In some embodiments, the device further includes: a first gate mask located above the first gate structure; and an isolation region adjacent to an end of the first gate structure, the gap being defined by surfaces of the isolation region, the first gate mask, and the first gate electrode.

[0104] In an embodiment, the method includes: removing the dummy gate to form a groove between the gate spacers; depositing a gate dielectric layer in the groove; depositing a gate electrode layer on the gate dielectric layer, the inner surface of the gate electrode layer defining a void; planarizing the top surface of the gate electrode layer until the void is exposed at the top surface of the gate electrode layer; and performing a first gate treatment process in the void, the first gate treatment process increasing the concentration of the work function adjustment element at the inner surface of the gate electrode layer defining the void. In some embodiments of the method, the groove has a main portion and a neck portion, the gate electrode layer completely fills the neck portion of the groove, and the gate electrode layer partially fills the main portion of the groove to define the void. In some embodiments of the method, the work function adjustment element is fluorine, and the first gate treatment process is a fluorination treatment process. In some embodiments of the method, the work function adjustment element is nitrogen, and the first gate treatment process is a nitridation treatment process. In some embodiments of the method, the work function adjustment element is oxygen, and the first gate treatment process is an oxidation treatment process. In some embodiments of the method, the work function adjustment element is chlorine, boron or silicon, and the first gate treatment process is a deposition process. In some embodiments, the method also includes: forming an opening in the gate electrode layer, after the opening is formed, the void is exposed at the side wall of the gate electrode layer; and performing a second gate processing process in the void, the second gate processing process increasing the concentration of the work function adjustment element at the inner surface of the gate electrode layer that defines the void.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a gate dielectric disposed above the substrate; A gate electrode, located above the gate dielectric, the gate electrode comprising: a work function adjustment layer, located above the gate dielectric; A glue layer, located above the work function adjustment layer; a filling layer, located above the glue layer; and A void is defined by an inner surface of at least one of the filling layer, the glue layer and the work function adjustment layer, and the material of the gate electrode at the inner surface includes a work function adjustment element, wherein the semiconductor device also includes a gate spacer adjacent to the gate dielectric, and wherein the void is exposed from a horizontal plane where a top surface of the gate spacer is located.

2. The semiconductor device according to claim 1, wherein The inner surface is an inner surface of the filling layer, and wherein the work function adjusting layer is the only work function adjusting layer between the glue layer and the gate dielectric.

3. The semiconductor device according to claim 1, wherein The inner surface is an inner surface of the glue layer, and wherein the work function adjusting layer is one of a plurality of work function adjusting layers located between the glue layer and the gate dielectric.

4. The semiconductor device according to claim 1, wherein: The inner surface is an inner surface of the work function adjusting layer, and wherein the work function adjusting layer is one of a plurality of work function adjusting layers located between the glue layer and the gate dielectric.

5. The semiconductor device according to claim 1, wherein The work function adjustment element is fluorine, nitrogen, oxygen, chlorine, boron or silicon.

6. The semiconductor device according to claim 1, wherein The material of the gate electrode at the inner surface includes a work function adjustment element at a concentration in the range of 1 at. % to 28 at. %.

7. The semiconductor device according to claim 1, further comprising: A contact is located above the gate electrode, and the gap is further defined by a bottom surface of the contact.

8. The semiconductor device according to claim 1, further comprising: An isolation region is adjacent to an end of the gate electrode, and the gap is further defined by a sidewall of the isolation region.

9. A semiconductor device comprising: A first transistor comprising: a first channel region having a first length; a first gate structure located above the first channel region, the first gate structure comprising a first gate electrode, the first gate electrode having a void therein, the first gate electrode having an inner surface defining the void, the material of the gate electrode at the inner surface comprising a work function adjustment element; and a first gate spacer adjacent to the first gate structure, the first gate spacer having an arcuate sidewall; and The second transistor comprises: a second channel region, the second channel region having a second length, the second length being greater than the first length; a second gate structure located above the second channel region, the second gate structure comprising a second gate electrode, the second gate electrode having no gap, and the second gate electrode having a different work function from the first gate electrode; and The second gate spacer is adjacent to the second gate structure, and the second gate spacer has a straight sidewall.

10. The semiconductor device according to claim 9, wherein The first gate electrode further comprises a metal, and wherein the second gate electrode comprises a metal and is free of the work function adjusting element.

11. The semiconductor device according to claim 10, wherein: The metal is tungsten, and the work function adjusting element is fluorine, nitrogen, oxygen, chlorine, boron or silicon.

12. The semiconductor device according to claim 9, wherein: The void is exposed from a level where a top surface of the first gate spacer is located.

13. The semiconductor device according to claim 9, further comprising: A first gate mask, located above the first gate structure; as well as An isolation region is adjacent to an end of the first gate structure, and the gap is defined by the isolation region, the first gate mask, and a surface of the first gate electrode.

14. A method of forming a semiconductor device, comprising: removing the dummy gate to form a recess between the gate spacers; depositing a gate dielectric layer in the groove; depositing a gate electrode layer on the gate dielectric layer, an inner surface of the gate electrode layer defining a void; planarizing a top surface of the gate electrode layer until the void is exposed at the top surface of the gate electrode layer; as well as A first gate treatment process is performed in the void, the first gate treatment process increasing a concentration of a work function adjustment element at the inner surface of the gate electrode layer defining the void.

15. The method according to claim 14, wherein: The groove has a main portion and a neck portion, the gate electrode layer completely fills the neck portion of the groove, and the gate electrode layer partially fills the main portion of the groove to define the gap.

16. The method according to claim 14, wherein: The work function adjustment element is fluorine, and the first gate treatment process is a fluorination treatment process.

17. The method according to claim 14, wherein: The work function adjustment element is nitrogen, and the first gate treatment process is a nitridation process.

18. The method according to claim 14, wherein: The work function adjustment element is oxygen, and the first gate treatment process is an oxidation treatment process.

19. The method according to claim 14, wherein: The work function adjustment element is chlorine, boron or silicon, and the first gate treatment process is a deposition process.

20. The method of claim 14, further comprising: forming an opening in the gate electrode layer, wherein after the opening is formed, the void is exposed at a sidewall of the gate electrode layer; as well as A second gate treatment process is performed in the void, the second gate treatment process increasing a concentration of the work function adjusting element at the inner surface of the gate electrode layer defining the void.

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