Power semiconductor devices and power semiconductor chips

Abstract

The present application provides a power semiconductor device and a power semiconductor chip. The power semiconductor device includes: a semiconductor layer; a trapezoidal groove, which is recessed from the surface of the semiconductor layer to a specific depth into the semiconductor layer, and the groove includes a pair of wires with a first depth and a plurality of connectors connected between the pair of wires and having a second depth shallower than the first depth; a well region, which is defined in the semiconductor layer, between the pair of wires and between the plurality of connectors in the groove; a floating region, which is defined in the semiconductor layer, outside the pair of wires in the groove; a gate insulating layer, which is arranged on the inner wall of the groove; and a gate electrode layer, which is arranged on the gate insulating layer to fill the groove, and the gate electrode layer includes a first portion filling the pair of wires and a second portion filling the plurality of connectors. The depth of the second portion of the gate electrode layer is shallower than the depth of the first portion of the gate electrode layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0058261 filed on May 15, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices, and more particularly, to a power semiconductor device and a power semiconductor chip for switching power transmission. Background Art

[0004] Power semiconductor devices are semiconductor devices that work under high voltage and high current environments. Power semiconductor devices are used in fields that require high power switching, such as inverter devices. For example, power semiconductor devices may include insulated gate bipolar transistors (IGBTs), power MOSFETs, and the like. Power semiconductor devices require essentially high voltage breakdown characteristics, and recently also require high-speed switching operations.

[0005] Semiconductor devices work when electrons injected from the channel and holes injected from the collector flow. However, in trench gate power semiconductor devices, when holes accumulate excessively in the trench gate, a negative gate charge (NGC) phenomenon occurs, and a displacement current is generated in the gate direction. Trench gate power semiconductor devices have a large gate-to-collector capacitance (Cgc), which is greatly affected by negative gate charge (NGC), resulting in problems with switching stability.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Korean Patent Application Publication No. 20140057630 (published on May 13, 2014) Summary of the invention

[0009] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0010] In one general aspect, a power semiconductor device includes: a semiconductor layer; a trapezoidal trench recessed from a surface of the semiconductor layer into the semiconductor layer to a specific depth and including a pair of wires having a first depth and a plurality of connectors connected between the pair of wires and having a second depth shallower than the first depth; a well region defined in the semiconductor layer, between the pair of wires and between the plurality of connectors of the trench; a floating region defined in the semiconductor layer, outside the pair of wires of the trench; a gate insulating layer arranged on an inner wall of the trench; and a gate electrode layer arranged on the gate insulating layer to fill the trench and including a first portion filling the pair of wires and a second portion filling the plurality of connectors. The depth of the second portion of the gate electrode layer is shallower than the depth of the first portion of the gate electrode layer.

[0011] A width of each of the connections may be greater than a width of each of the pair of lines, and a width of the second portion of the gate electrode layer may be greater than a width of the first portion of the gate electrode layer.

[0012] The floating region may extend under the pair of lines to surround a bottom surface of the first portion of the gate electrode layer, and a bottom surface of the second portion of the gate electrode layer may be exposed relative to the floating region.

[0013] The second portion of the gate electrode layer may have a depth deeper than a depth of the well region.

[0014] The power semiconductor device may include a source region or an emitter region adjacent to the second portion of the gate electrode layer in the well region and spaced apart from each other in an extension direction of the first portion of the gate electrode layer.

[0015] The power semiconductor device may include a drift region defined in the semiconductor layer below the well region.

[0016] The drift region, and the source region or the emitter region may be doped with impurities of a first conductivity type, and the well region and the floating region may be doped with impurities of a second conductivity type opposite to the first conductivity type.

[0017] In another general aspect, a power semiconductor chip includes: a semiconductor layer including a main unit area and a sensor area; a power semiconductor transistor arranged in the main unit area and including a power semiconductor device; a current sensor transistor arranged in the sensor area to monitor the current of the power semiconductor transistor; an emitter terminal connected to an emitter electrode of the power semiconductor transistor; a current sensor terminal connected to the emitter electrode of the current sensor transistor; and a gate terminal connected to a gate electrode of the power semiconductor transistor and a gate electrode of the current sensor transistor.

[0018] Other features and aspects will become apparent from the following detailed description, the accompanying drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings:

[0020] Figure 1 is a schematic plan view showing a power semiconductor chip according to an embodiment of the present disclosure;

[0021] Figure 2 is a circuit diagram showing a power semiconductor chip according to an embodiment of the present disclosure;

[0022] Figure 3 It is shown Figure 2 A circuit diagram of a portion of a power semiconductor chip;

[0023] Figure 4 is a plan view showing a power semiconductor device according to an embodiment of the present disclosure;

[0024] Figure 5 It is along Figure 4 A cross-sectional view of a power semiconductor device taken along line VV; and

[0025] Figure 6 It is along Figure 4 A cross-sectional view of the power semiconductor device taken along line VI-VI. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. The following examples are used to complete the disclosure of the present disclosure and fully inform the ordinary technicians in the scope of the present disclosure. In addition, for ease of description, the size of at least some constituent elements in the accompanying drawings may be exaggerated or reduced. In the accompanying drawings, the same reference numerals represent the same elements.

[0027] Unless otherwise defined, all terms used herein have the same meanings as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for explanation, and are thus provided to explain the general structure of the present disclosure.

[0028] Like reference numerals denote like elements. When a configuration such as a layer, region, or substrate is referred to as being on another configuration, it is understood that it is in the directly upper trench of the other configuration, or there may be other intermediate configurations between the two. On the other hand, when a configuration is referred to as being "directly on" another configuration, it is understood that there is no intervening configuration.

[0029] Figure 1 is a schematic plan view showing a power semiconductor chip 50 according to an embodiment of the present disclosure, Figure 2 is a circuit diagram showing a power semiconductor chip 50 according to an embodiment of the present disclosure, and Figure 3 It is shown Figure 2 Circuit diagram of a part of a power semiconductor chip.

[0030] Reference Figure 1 , a power semiconductor chip 50 may be formed using the semiconductor layer 105 including the main cell region MC and the sensor region SA. The power semiconductor chip 50 may include a wafer die or a package structure.

[0031] Multiple power semiconductor transistors ( Figure 3 A plurality of current sensor transistors ( Figure 3 A sensor region SA may be formed to monitor the current of the power semiconductor transistor PT.

[0032] For example, the power semiconductor transistor PT and the current sensor transistor ST may include an insulated gate bipolar transistor (IGBT) or a power MOSFET structure. The IGBT may include a gate electrode, an emitter electrode, and a collector electrode. Figures 2 to 3 Hereinafter, a case where the power semiconductor transistor PT and the current sensor transistor ST are IGBTs will be described as an example.

[0033] Reference Figures 1 to 3 , the power semiconductor chip 50 may include a plurality of terminals for connecting with the outside.

[0034] For example, the power semiconductor chip 50 may include: an emitter terminal 69, which is connected to the emitter electrode of the power semiconductor transistor PT; a Kelvin emitter terminal 66, which is connected to the Kelvin emitter electrode of the power semiconductor transistor PT; a current sensor terminal 64, which is connected to the emitter electrode of the current sensor transistor ST for monitoring current; a gate terminal 62, which is connected to the gate electrode of the power semiconductor transistor PT and the gate electrode of the current sensor transistor ST; temperature sensor terminals 67 and 68, which are connected to the temperature sensor TC for monitoring temperature; and / or a collector terminal 61, which is connected to the collector of the power semiconductor transistor PT and the collector of the current sensor transistor ST.

[0035] exist Figure 2 In the embodiment, the collector terminal 61 may be formed at Figure 1 on the rear surface of the semiconductor layer 105, and Figure 2 The emitter terminal 69 in the Figure 1 On the main unit area MC.

[0036] The temperature sensor TC may include a junction diode connected to the temperature sensor terminals 67 and 68. The junction diode may include a junction structure between at least one n-type impurity region and at least one p-type impurity region, such as a PN junction structure, a PNP junction structure, an NPN junction structure, etc.

[0037] This structure exemplarily describes a structure in which the temperature sensor TC is embedded in the power semiconductor chip 50 , but the temperature sensor TC may be omitted in a modified example of the present embodiment.

[0038] The power semiconductor transistor PT is connected between the emitter terminal 69 and the collector terminal 61, and the current sensor transistor ST is partially connected in parallel with the power semiconductor transistor PT between the current sensor terminal 64 and the collector terminal 61. The gate electrode of the current sensor transistor ST and the gate electrode of the power semiconductor transistor PT are commonly connected to the gate terminal 62 through a specific resistor.

[0039] The current sensor transistor ST may be formed in substantially the same structure as the power semiconductor transistor PT, but may be reduced to a certain ratio. Therefore, the output current of the power semiconductor transistor PT may be indirectly monitored by monitoring the output current of the current sensor transistor ST.

[0040] For example, the power semiconductor transistor PT and / or the current sensor transistor ST may include Figures 4 to 6 In some embodiments, the power semiconductor transistor PT and the power semiconductor device 100 may be used interchangeably.

[0041] Figure 4 is a plan view showing a power semiconductor device 100 according to an embodiment of the present disclosure, Figure 5 It is along Figure 4 A cross-sectional view of a power semiconductor device taken along line VV, and Figure 6 It is along Figure 4 A cross-sectional view of the power semiconductor device taken along line VI-VI.

[0042] Reference Figures 4 to 6 The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, may refer to a portion of a semiconductor substrate and / or one or more epitaxial layers.

[0043] At least one trench 116 may be recessed from the surface of semiconductor layer 105 to a certain depth to be formed into semiconductor layer 105. The number of trenches 116 may be appropriately selected according to the performance of power semiconductor device 100 and does not limit the scope of this embodiment.

[0044] The groove 116 may have a trapezoidal shape, including a pair of wires 116a and a plurality of connectors 116b connected between the pair of wires 116a. The connectors 116b may be formed to be spaced at regular intervals between the wires 116a.

[0045] For example, in the groove 116, the line 116a may have a first depth D1, and the connector 116b may have a second depth D2. The second depth D2 may be less than the first depth D1, and therefore, the depth of the connector 116b may be shallower than the depth of each line 116a. In addition, the width W2 of each connector 116b of the groove 116 may be greater than the width W1 of each line 116a. This structure can alleviate the electric field stress near the connector 116b.

[0046] Furthermore, the trench 116 may have rounded edges, such as a bottom edge of the trench 116 , to suppress concentration of the electric field.

[0047] For example, the semiconductor layer 105 may include a drift region 107 and a well region 110. In addition, the semiconductor layer 105 may further include an emitter region 112 in the well region 110. Here, the emitter region 112 may be referred to as a source region, and hereinafter, the emitter region 112 may represent a source region. In addition, the semiconductor layer 105 may further include a floating region 125.

[0048] More specifically, the well region 110 may be defined in the semiconductor layer 105 between the lines 116a of the trenches 116 and between the connectors 116b of the trenches 116. That is, the well region 110 may be a region of the semiconductor layer 105 that is rectangular and surrounded by the trapezoidal trenches 116.

[0049] The floating region 125 may be defined in the semiconductor layer 105 outside the line 116a of the trench 116. For example, the floating region 125 may be formed in the semiconductor layer 105 outside the trench 116 in a trapezoidal shape.

[0050] The floating region 125 may also extend below the line 116a to surround the bottom surface of the line 116a of the groove 116 for mitigating the electric field. However, the floating region 125 may not extend below the connector 116b. Figure 6 As shown, along Figure 4 The floating region 125 may not exist under the well region 110 and the connection member 116 b in the VI-VI line.

[0051] exist Figure 4 In the embodiment, well regions 110 may be separated by connectors 116b in the extension direction of line 116a (ie, along line VI-VI). Floating regions 125 and well regions 110 may be alternately arranged along line VV, wherein line 116a is located between floating regions 125 and well regions 110.

[0052] For example, the well region 110 and the floating region 125 may be doped with the same type of dopant.

[0053] The emitter region 112 may be formed adjacent to the trench 116 at a specific depth within the well region 110. For example, the emitter region 112 may not be formed in a portion of the well region 110 adjacent to the line 116a, but may be formed in a portion of the well region 110 adjacent to the connector 116b. Therefore, the emitter region 112 may be formed adjacent to the connector 116b in the well region 110 along the extension direction of the line 116a (i.e., along the line VI-VI).

[0054] For example, the emitter region 112 and the well region 110 may be doped with opposite types of dopants.

[0055] The drift region 107 may be defined in the semiconductor layer 105 below the well region 110 . For example, the drift region 107 may be defined between the trenches 116 , contacting the well region 110 , and may extend to the lower surface of the semiconductor layer 105 below the floating region 125 .

[0056] For example, the drift region 107 and the emitter region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, when the first conductivity type may be n-type, the second conductivity type may be p-type, and vice versa.

[0057] In some embodiments, the drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be doped with impurities of a second conductivity type into the epitaxial layer, or may be formed with an epitaxial layer of the second conductivity type. The emitter region 112 may be formed by doping impurities of the first conductivity type in the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

[0058] In addition, when the power semiconductor device 100 is an IGBT, a collector region (not shown) may be disposed below the drift region 107, and a collector (not shown) may be disposed below the collector region to be connected to the collector region. For example, the collector region may be disposed below the drift region 107 as an epitaxial layer having a second conductivity type different from that of the drift region 107.

[0059] As another example, when the power semiconductor device 100 is a power MOSFET, the drain electrode may be connected below the drift region 107 .

[0060] The gate insulating layer 118 may be formed on the inner wall of the at least one trench 116. For example, the gate insulating layer 118 may be formed to have a uniform thickness on the inner wall of the trench 116.

[0061] The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the at least one trench 116. For example, the gate electrode layer 120 may be formed to be recessed into the semiconductor layer 105, and in this case, the gate electrode layer 120 may be understood to have a recess type or a trench type.

[0062] For example, the gate electrode layer 120 may include a first portion 120 a formed by filling the line 116 a and a second portion 120 b formed by filling the connector 116 b .

[0063] The shape of the gate electrode layer 120 in the trench 116 may correspond to the structure of the trench 116. Therefore, since the second depth D2 of the connector 116b of the trench 116 is less than the first depth D1 of the line 116a, the depth of the second portion 120b of the gate electrode layer 120 may be shallower than the depth of the first portion 120a. The depth of the second portion 120b of the gate electrode layer 120 may be greater than the depth of the well region 110. In addition, the width of the second portion 120b of the gate electrode layer 120 may be greater than the width of the first portion 120a.

[0064] The arrangement of the gate electrode layer 120 on the plane may follow the arrangement of the trench 116, and thus the gate electrode layer 120 may be arranged on the Figure 4 Like the trenches 116 , the number of the gate electrode layers 120 may be appropriately selected according to the operating specifications of the power semiconductor device 100 , and the scope of the present embodiment is not limited thereto.

[0065] In addition, an emitter electrode (not shown) may be formed on the emitter region 112. The emitter electrode may be commonly connected to the emitter region 112 and the well region 110. An insulating layer 130 may be interposed between the semiconductor layer 105 and the emitter electrode.

[0066] According to the above structure, the floating region 125 may extend below the line 116a of the trench 116 to surround the bottom surface of the first portion 120a of the gate electrode layer 120. However, the bottom surface of the second portion 120b of the gate electrode layer 120 may be exposed from the floating region 125 without being surrounded by the floating region 125.

[0067] Furthermore, the emitter region 112 may be adjacent to the second portion 120 b of the gate electrode layer 120 in the well region 110 , and may be spaced apart from each other in an extension direction of the first portion 120 a of the gate electrode layer 120 .

[0068] The lower portion of the trench 116 can be protected by the trapezoidal strip portion (i.e., the structure of the line 116a through the trench 116 and the first portion 120a of the gate electrode layer 120 and the structure of the floating region 125), so the power semiconductor device 100 can maintain a high internal breakdown voltage during shutdown.

[0069] In addition, the emitter region 112 may be arranged in a portion adjacent to the connector 116b of the trench 116 and the second portion 120b of the gate electrode layer 120, and may not be arranged in a portion adjacent to the line 116a of the trench 116 and the first portion 120a of the gate electrode layer 120, and therefore, when the power semiconductor device 100 operates, the value of the gate-collector capacitance Cgc may be reduced by changing the moving path of holes. Therefore, the negative gate charging (NGC) phenomenon may be reduced, and the switching stability may be improved.

[0070] In addition, the depth of the second portion 120b of the gate electrode layer 120 may be reduced and the width of the second portion 120b of the gate electrode layer 120 may be increased, thereby reducing the electric field under the second portion 120b of the gate electrode layer 120 and the value of the gate-collector capacitance (Cgc).

[0071] Furthermore, as the distance between the first portions 120 a of the gate electrode layer 120 narrows, the influence of the charge sharing phenomenon increases, and thus, as equipotential surfaces under adjacent first portions 120 a are connected, the electric field stress under the gate electrode layer 120 may be further alleviated.

[0072] The above description has been made for the case where the power semiconductor device is an IGBT, but the same is applicable to the case where it is a power MOSFET.

[0073] exist Figures 1 to 3 In the embodiment, the power semiconductor chip 50 can be used Figures 4 to 6 The power semiconductor device 100 shown is used as a power semiconductor transistor PT and / or a current sensor transistor ST, and thus the characteristics of the power semiconductor device 100 described above can be applied to the power semiconductor chip 50 as they are.

[0074] Therefore, shape changes of the trapezoidal trench 116 and the gate electrode layer 120 can be provided, and therefore, the above-mentioned power semiconductor device 100 and the power semiconductor chip 50 using the power semiconductor device 100 can maintain the breakdown voltage at a high voltage, suppress the negative gate charging phenomenon, and improve the switching stability.

[0075] According to the power semiconductor device and the power semiconductor chip according to the embodiments of the present disclosure made as described above, switching stability can be improved by suppressing the negative gate charging (NGC) phenomenon while maintaining the breakdown characteristics to a high voltage.

[0076] The effects are illustrative, and the scope of the present disclosure is not limited thereby.

[0077] Although the present disclosure has been described above with reference to the exemplary embodiments and the accompanying drawings, the present disclosure is not limited thereto but may be variously modified and changed by those skilled in the art without departing from the spirit and scope of the present disclosure as claimed in the appended claims.

Claims

1. A power semiconductor device, comprising: Semiconductor layer; a trapezoidal trench recessed from a surface of the semiconductor layer into the semiconductor layer by a specific depth, and comprising a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth; a well region defined in the semiconductor layer, between the pair of lines and between the plurality of connections of the trench; a floating region defined in the semiconductor layer outside the pair of lines of the trench; A gate insulating layer, arranged on an inner wall of the trench; as well as a gate electrode layer disposed on the gate insulating layer to fill the trench, and the gate electrode layer includes a first portion filling the pair of lines and a second portion filling the plurality of connections, wherein a depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer, and wherein the floating region extends below the pair of lines to surround a bottom surface of the first portion of the gate electrode layer, and Wherein, a bottom surface of the second portion of the gate electrode layer is exposed relative to the floating region.

2. The power semiconductor device according to claim 1, wherein: The width of each of the connecting members of the groove is greater than the width of each of the pair of lines, and Wherein, a width of the second portion of the gate electrode layer is greater than a width of the first portion of the gate electrode layer.

3. The power semiconductor device according to claim 1, wherein: A depth of the second portion of the gate electrode layer is deeper than a depth of the well region.

4. The power semiconductor device according to claim 1, further comprising: A source region or an emitter region is adjacent to the second portion of the gate electrode layer in the well region and is spaced apart from each other in an extending direction of the first portion of the gate electrode layer.

5. The power semiconductor device according to claim 4, further comprising: A drift region is defined in the semiconductor layer and is located below the well region.

6. The power semiconductor device according to claim 5, wherein: The drift region and the source region or the emitter region are doped with impurities of a first conductivity type, and The well region and the floating region are doped with impurities of a second conductivity type opposite to the first conductivity type.

7. A power semiconductor chip, comprising: A semiconductor layer including a main unit region and a sensor region; a power semiconductor transistor arranged in the main cell region and comprising the power semiconductor device according to claim 1; a current sensor transistor arranged in the sensor region to monitor a current of the power semiconductor transistor; an emitter terminal connected to an emitter electrode of the power semiconductor transistor; a current sensor terminal connected to an emitter electrode of the current sensor transistor; as well as A gate terminal is connected to a gate electrode of the power semiconductor transistor and a gate electrode of the current sensor transistor.

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