Semiconductor structure and method

Abstract

This disclosure relates to a semiconductor structure (100) including a crystalline silicon substrate (110) having a surface (111) and a crystalline silicon oxide superstructure (120) on the surface (111) of the silicon substrate (110), the silicon oxide superstructure (120) having a thickness of at least two molecular layers and a (1x1) planar structure using Wood's notation.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures and methods for forming them. In particular, this disclosure relates to silicon oxide structures for surface passivation of silicon-based semiconductor devices. Background Technology

[0002] Silicon is the most common substrate material in traditional semiconductor devices, such as transistors, capacitors, diodes, photodiodes, and other types of microelectronic and photonic components. In all such devices, the interface quality of the substrate is of paramount importance.

[0003] In conventional devices, the surface of a silicon substrate is typically passivated by forming a layer of thermal oxide. However, known oxidation methods result in an amorphous silicon oxide layer. The amorphous nature of this oxide layer leads to defect states on the passivated silicon surface. This inevitably degrades the performance of devices fabricated on conventionally passivated substrates. Furthermore, conventional oxidation processes rely on relatively high processing temperatures, which can degrade the properties of the silicon substrate and / or structures fabricated on it. Given these challenges, there is an urgent need to develop new solutions related to the passivation of silicon surfaces.

[0004] US 20060003500 A1 discloses a method in which a layer of oxygen atoms is self-limitedly deposited on an existing silicon surface to form a molecular layer of crystalline silicon dioxide. Summary of the Invention

[0005] The present invention provides a simplified overview of some concepts, which will be further described in the specific embodiments below. This summary is not intended to identify any key or essential features claimed, nor is it intended to limit the scope of the claimed patent.

[0006] According to a first aspect, a semiconductor structure is provided. The semiconductor structure includes a crystalline silicon substrate having a surface, and a crystalline silicon oxide superstructure on the surface of the silicon substrate, the silicon oxide superstructure having a thickness of at least two molecular layers and a (1 x 1) planar structure using Wood's notation.

[0007] According to a second aspect, a method for forming a semiconductor structure is provided, the semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate. The method includes: providing the silicon substrate in a vacuum chamber, the silicon substrate having a substantially clean deposition surface; and heating the silicon substrate to an oxidation temperature T of 100°C to 530°C. O ; and while keeping the silicon substrate at the oxidation temperature, molecular oxygen (O2) is introduced at a rate of 1 x 10⁻⁶. -8 millibars to 1 x 10 -4 oxidation pressure (P) per millibar O And oxygen doses ranging from 0.1 to 10,000 Langmuirs. O It is supplied to the vacuum chamber.

[0008] Accordingly, a crystalline silica superstructure is formed on the deposition surface, the silica superstructure having a thickness of at least two molecular layers and a (1 x 1) planar structure using Wood's representation.

[0009] According to a third aspect, this disclosure relates to the use of a crystalline silicon oxide superstructure having a (1 x 1) planar structure using Wood's representation for surface passivation of a crystalline silicon substrate in a semiconductor structure.

[0010] In one embodiment of the third aspect, the semiconductor structure is a semiconductor structure according to the first aspect or any embodiment of the first aspect. It is particularly understood that, according to the third aspect, a crystalline silicon oxide superstructure can be used for surface passivation of a crystalline silicon substrate in a semiconductor structure according to the first aspect or any embodiment of the first aspect. Attached Figure Description

[0011] This disclosure can be better understood by referring to the following specific embodiments and accompanying drawings, wherein:

[0012] Figure 1 A cross-sectional view of a semiconductor structure is shown.

[0013] Figure 2 A method for forming a semiconductor structure is shown, and

[0014] Figure 3 a) Figure 3 b) and Figure 3 c) shows a scanning tunneling microscopy image of the silicon sample.

[0015] Figure 4 a) and Figure 4b) shows a scanning tunneling microscope image of another silicon sample.

[0016] Unless otherwise expressly stated to the contrary, any of the above figures may not be drawn to scale, and therefore any element in the figures may be drawn at an incorrect scale relative to the other elements in the figures, in order to emphasize certain structural aspects of the embodiments of the figures.

[0017] Furthermore, corresponding elements in the embodiments of any two of the foregoing figures may be disproportionate to each other in the two figures in order to emphasize certain structural aspects of the embodiments of the two figures. Detailed Implementation

[0018] Figure 1 A partial cross-sectional view of a semiconductor structure 100 according to one embodiment is schematically shown.

[0019] In this specification, "semiconductor" may refer to a material such as silicon (Si), whose conductivity is between that of conductive materials such as metals and that of insulating materials such as various plastics and glasses. Semiconductors, such as silicon, may or may not have a crystalline structure.

[0020] Here, the “crystalline” structure of a material can refer to the orderly formation of a three-dimensional crystal lattice by the constituent elements of the material (such as atomic nuclei).

[0021] Furthermore, "semiconductor structure" can refer to all or only a portion of a structural part, layer, and / or other element comprising a complete, operable semiconductor component, element, or device, such as a transistor (e.g., a power transistor or phototransistor), capacitor, diode (e.g., a photodiode or power diode), microprocessor, or photonic device (e.g., a display, a photodetector, or a solar cell). When forming only a part of such a component, element, or device, the term "structure" means a structure "for" such a component, element, or device, or a building block of such a component, element, or device. In particular, in addition to semiconductor materials, semiconductor structures may also typically include non-semiconductor materials, such as conductors and / or insulators.

[0022] exist Figure 1 In one embodiment, the semiconductor structure 100 includes a crystalline silicon substrate 110.

[0023] Throughout this disclosure, "substrate" can refer to a solid providing a surface, which may be flat or slightly curved, allowing materials to be disposed, deposited, etched, and / or engraved on the surface. For example, a substrate may include a wafer comprising a semiconductor material such as silicon suitable for fabricating various semiconductor structures and / or devices, such as integrated circuits, solar cells, or photodetectors.

[0024] Here, "surface" can refer to a finite portion of a plane in a general sense, which may have non-zero curvature that may depend on location, and preferably may be smooth. Furthermore, a surface can be connected, i.e., indivisible into two non-intersecting subsurfaces, or path-connected. Some surfaces may simply be connected. Additionally or alternatively, a surface can refer to a portion of the outer boundary of a subject or element. Specifically, a surface can refer to a portion, or a part thereof, of the outer boundary of a subject or element observable from a particular viewing direction.

[0025] Figure 1 The silicon substrate 110 in this embodiment has a surface 111. In other embodiments, the silicon substrate may typically include a surface.

[0026] Figure 1 Surface 111 in this embodiment is a crystalline surface. In other embodiments, the silicon substrate may have at least a partially crystalline surface, i.e., a partially or fully crystalline surface.

[0027] Throughout this specification, "crystalline surface" may refer to the surface of a crystalline material, which, based on its translational symmetry, can be defined as a two-dimensional lattice and / or a two-dimensional unit cell. Alternatively or alternatively, crystalline surface may refer to the surface of a crystal, which may or may not (substantially) extend along the crystallographic plane of the bulk lattice of that crystal.

[0028] Although the surface 111 of the silicon substrate 110 is Figure 1 While the surface of a silicon substrate is typically depicted as a single line segment, it can generally include any number and type of typical features of a crystalline surface, such as adatoms, step adatoms, kink atoms, step atoms, and / or surface vacancy.

[0029] exist Figure 1 In some embodiments, the semiconductor structure 100 further includes a crystalline silicon oxide superstructure 120 on the surface 111 of the silicon substrate 110.

[0030] In this disclosure, "superstructure" can refer to any structure, such as a layer, disposed on a crystalline structure, component, or element. Furthermore, "layer" can refer to a generally sheet-like element disposed on a surface or body. Additionally or alternatively, a layer can refer to one of a series of stacked, overlapping, or piled generally sheet-like elements.

[0031] Furthermore, "silicon oxide" can refer to binary compounds comprising silicon and oxygen (O). Silicon oxide can refer to ideally proportioned silicon dioxide (SiO2) and / or non-ideally proportioned silicon oxide (SiO2). x ). Silica may or may not contain trace amounts of elements other than silicon or oxygen as impurities.

[0032] Figure 1 The silicon oxide superstructure 120 of the embodiments has a thickness of at least two molecular layers. Specifically, the silicon oxide superstructure 120 has a thickness of approximately 3 nanometers (nm). Generally, a higher thickness of the silicon oxide superstructure can reduce pinhole density and / or other defects in the silicon oxide superstructure, while a lower thickness can improve the performance of semiconductor devices including the silicon oxide superstructure. In other embodiments, the silicon oxide superstructure can have any thickness of at least two molecular layers, for example, a thickness greater than or equal to 1 nanometer, 2 nanometer, or 3 nanometers and / or less than or equal to 10 nanometers, 7 nanometers, or 5 nanometers.

[0033] Throughout this specification, "thickness" can refer to the element dimension measured perpendicular to the surface of the silicon substrate. Furthermore, "thickness of at least two molecular layers" can refer to the combined thickness of at least two units of a repeating structural theme of a crystalline polymorph of silicon dioxide, such as quartz, for example, α-quartz (α-... (quartz). Alternatively or alternatively, the thickness of at least two molecular layers may refer to a thickness greater than or equal to approximately 0.5 nanometers, 0.7 nanometers, or 1 nanometer.

[0034] Despite Figure 1 The silicon oxide superstructure 120 is shown as having a constant thickness, but silicon oxide superstructures can typically have a substantially constant or constant thickness that depends on the location.

[0035] Figure 1 The silicon oxide superstructure 120 of this embodiment has a (1 x 1) planar structure using Wood's notation. This structure of the silicon oxide superstructure typically improves the surface quality of the silicon substrate by reducing surface defect density. In other embodiments, the silicon oxide superstructure may typically have this structure.

[0036] As those skilled in the art to which this disclosure pertains, "Wood's representation" is a method for specifying the crystalline structure of an ordered superstructure (e.g., a layer) on the surface of a crystalline substrate using surface lattice vectors derived from the host lattice vector of the substrate. Wood's representation can be used if the microstructure of the superstructure has symmetry properties related to the symmetry properties of the crystalline substrate.

[0037] Here, "(1x1) planar structure" can refer to the crystalline microstructure of a superstructure, for example, an epitaxial-like superstructure having a crystalline plane extending (substantially) parallel to the surface of a crystalline substrate. The crystalline plane may have a unit cell, such as a primitive unit cell, having two lattice vectors of length (1 x 1) using Wood's notation. Specifically, a (1 x 1) planar structure can refer to a (1 x 1) R0° structure. In particular, a (1 x 1) silicon oxide superstructure may or may not refer to a (1 x 1) R0°-SiO2 structure.

[0038] Typically, for example, the presence of a (1 x 1) silica superstructure on the surface of a crystalline silicon substrate can be directly and definitively verified by combining three types of standard surface characterization methods. First, if necessary, the superstructure to be detected (e.g., layers) must be exposed. Then, the presence of silica at the surface can be confirmed using X-ray photoelectron spectroscopy (XPS). Following XPS, low-energy electron diffraction (LEED) analysis can be performed. If the LEED analysis shows a (1 x 1) pattern, scanning tunneling microscopy (STM) can be used. If the STM does not show the characteristics of a typical reconstruction pattern indicating a clean, unoxidized silicon surface, but rather the distances between the patterns (e.g., columns) are similar to and / or substantially equal to (e.g., within 25%, 20%, or 10% of the same) the relevant lattice constant of the surface of the crystalline silicon substrate, then a (1 x 1) silica superstructure exists on the surface.

[0039] exist Figure 1In one embodiment, the semiconductor structure 100 further includes a dielectric capping layer 130 on the silicon oxide superstructure 120. This capping layer typically passivates the silicon oxide superstructure, thereby extending its lifetime. Alternatively or additionally, this capping layer can facilitate the use of semiconductor structures, such as field-effect transistors or capacitors, in semiconductor devices where a dielectric layer with sufficiently high thickness and / or relative permittivity is required. In other embodiments, the semiconductor structure may or may not include a capping layer on the silicon oxide superstructure.

[0040] Here, "capping layer" can refer to a layer disposed on the silicon oxide superstructure, which can at least partially cover the silicon oxide superstructure, that is, partially or completely cover the silicon oxide superstructure.

[0041] Figure 1 The capping layer 130 in one embodiment may be amorphous. In other embodiments of the semiconductor structure including the capping layer, the capping layer may have any suitable at least partially ordered structure (e.g., crystalline, semi-crystalline, or quasi-crystalline) or disordered structure (e.g., amorphous).

[0042] Figure 1 The capping layer 130 in one embodiment may have a thickness of, for example, about 10 nanometers. A higher capping layer thickness can increase the passivation effect imparted by the capping layer, while a lower thickness can provide other advantageous features in a semiconductor device. In other embodiments where the semiconductor structure includes a capping layer, the capping layer may have any suitable thickness, such as greater than or equal to 1 nanometer, 2 nanometers, or 5 nanometers and / or less than or equal to 500 nanometers, 250 nanometers, or 100 nanometers.

[0043] Figure 1 The capping layer 130 in one embodiment may include a dielectric material having a relative permittivity (κ) greater than or equal to 10. Examples of such materials include hafnium oxide (HfO2), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), titanium dioxide (TiO2), strontium titanate (SrTiO3), barium titanate (BaTiO3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), cerium oxide (CeO2), yttrium oxide (Y2O3), or mixtures thereof. In other embodiments, the capping layer may include any suitable dielectric material, such as oxides, nitrides, oxynitrides, silicates, and / or titanates, which may or may not have a relative permittivity greater than or equal to 10, greater than or equal to 20, or greater than or equal to 50.

[0044] It should be understood that any of the foregoing embodiments of the first aspect can be used in combination with each other. In other words, the foregoing embodiments can be combined to form another embodiment of the first aspect.

[0045] The above mainly describes the structural and material aspects of semiconductor structures. The following text will focus more on the methods for forming semiconductor structures. The aforementioned implementation methods, definitions, details, and advantages regarding structure and materials, while requiring modifications to account for different situations, generally apply to the methodological aspects described below, and vice versa.

[0046] Specifically, it should be understood that the method according to the second aspect can be used to provide a semiconductor structure according to the first aspect and any embodiment thereof. Accordingly, the method according to the second aspect can be used to manufacture any semiconductor structure according to any embodiment of the first aspect.

[0047] Figure 2 A method 200 for forming a semiconductor structure according to an embodiment is shown, the semiconductor structure including a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate.

[0048] exist Figure 2 In one embodiment, method 200 includes: in process 201, providing the silicon substrate in a vacuum chamber, the silicon substrate having a substantially clean deposition surface. In other embodiments, methods for forming a semiconductor structure typically include providing the silicon substrate, the semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate.

[0049] In this specification, "process" can refer to a series of one or more steps leading to a result. Thus, a process can be a single-step or multi-step process. Furthermore, a process can be divided into multiple sub-processes, wherein each of these sub-processes may or may not share common steps. Here, "operation" can refer to the means taken to achieve a predetermined result.

[0050] Throughout this disclosure, "providing" can mean arranging the said element or component in a usable state, which may include at least partially forming, producing, or manufacturing the said element or component. Additionally or alternatively, providing may include arranging ready-made, pre-produced, or manufactured elements or components in a usable state. For example, the process of providing the silicon substrate may or may not include one or more steps taken to form a substantially clean deposition surface of the silicon substrate.

[0051] Throughout this specification, "deposited surface" can refer to the surface of a silicon substrate on which other materials may be introduced and / or adsorbed. Regarding crystal orientation, the deposited surface can be, for example, a silicon {100} surface, a silicon {111} surface, or a silicon {110} surface. In some embodiments, the deposited surface can be a relaxed surface and / or a reconstructed surface, such as a silicon (100) (2x1) or silicon (111) (7x7) surface. In some embodiments, the deposited surface can be an adsorbate-terminated surface, such as a hydrogen-terminated surface, such as silicon (100) (1x1). H.

[0052] Additionally, a "substantially clean" deposited surface can mean, for example, that the deposited surface is substantially free of any native silicon dioxide or any other type of impurity atoms. Here, "substantially free" can mean that the concentration of foreign atoms and molecules on the silicon surface does not exceed 3 x 10⁻⁶. 13 cm -2 This substantially clean deposition surface can be provided in a pre-cleaning manner, i.e., before the method of forming the semiconductor structure. Alternatively, this method may include cleaning of the deposition surface. Such cleaning can be performed by any suitable cleaning process.

[0053] In providing Figure 2 In the processing of the silicon substrate 201 in this embodiment, the deposition surface may be a silicon {100} surface. In other embodiments, the deposition surface may be, for example, a silicon {100} surface, a silicon {111} surface, or a silicon {110} surface.

[0054] exist Figure 2 In one embodiment, the process of providing the silicon substrate 201 includes a selective process of cleaning the deposited surface 202 to remove possible natural oxides and / or other impurities prior to the process of supplying molecular oxygen. In other embodiments, the process of providing the silicon substrate may or may not include such a process of cleaning the deposited surface. In some embodiments, for example, the deposited surface of the crystalline silicon substrate may be pre-cleaned by another party.

[0055] Figure 2 The treatment of the deposited surface 202 in one embodiment includes an RCA cleaning step 203. This RCA cleaning step typically facilitates the treatment of the deposited surface and / or enables the cleaning of the deposited surface at lower temperatures. In other embodiments, the treatment of the deposited surface may or may not include an RCA cleaning step.

[0056] Here, "RCA cleaning operation" can refer to a cleaning step that exposes the deposited surface to an aqueous solution of SC-1 and / or SC-2, wherein the SC-1 aqueous solution contains water (H2O), hydrogen peroxide (H2O2), and ammonium hydroxide (NH4OH), and the SC-2 aqueous solution contains H2O, H2O2, and hydrochloric acid (HCl). In the RCA cleaning step, after SC-1 immersion and / or SC-2 immersion, the silica can be stripped from the deposited surface, with or without stripping, by immersing the deposited surface in an aqueous solution of hydrofluoric acid (HF) and / or exposing the deposited surface to hydrofluoric acid vapor. This hydrofluoric acid treatment typically removes silica impurities efficiently at relatively low processing temperatures.

[0057] Figure 2 The treatment of the cleaned deposited surface 202 in this embodiment, following the RCA cleaning step 203, further includes a pre-annealing step 204. In the pre-annealing step 204, the crystalline silicon substrate is pre-annealed at a temperature (T0) in the range of 200 °C to 300 °C. A ) and in less than or equal to 1 x 10 -4 Pre-annealing pressure (P) in millibars (mbar) A Annealing is performed in a pre-annealing period, the pre-annealing duration of which is t. A The pre-annealing time should be greater than or equal to 1 minute. Such a pre-annealing step can reduce the defect density on the deposition surface of the silicon substrate. Specifically, this can be achieved by using a sufficiently low T0 for the metallized sample. A This is to achieve a reduction in defect density. In other embodiments, the process of cleaning the deposited surface may or may not include such a pre-annealing step. In embodiments where the process of cleaning the deposited surface includes such a pre-annealing step, the crystalline silicon substrate may or may not be annealed in a hydrogen (H2) or oxygen (O2) environment. In some embodiments, the process of cleaning the deposited surface may include using... Figure 2 In the example, the T in the pre-annealing step 204 A P A and t A Different T A P A and / or t A The pre-annealing step. In these embodiments, for example, a T range of 210°C to 290°C, 220°C to 280°C, or 230°C to 270°C may be used. A Less than or equal to 1x10 -5 millibars, 1x10 -6 millibars, or 1x10 -7 millibars of P A ; and / or t greater than or equal to 5 minutes, 10 minutes, or 30 minutes AIn some embodiments, the treatment to clean the deposited surface after the pre-annealing step may include hydrofluoric acid immersion and / or hydrofluoric acid vapor treatment.

[0058] exist Figure 2 In an embodiment, method 200 includes heating the silicon substrate to an oxidation temperature T of 100 °C to 530 °C in process 205. O Such a T O This can promote the formation of crystalline silicon oxide superstructures on a crystalline silicon substrate. In particular, such T... O This can result in sufficiently low diffusivity of silicon and / or oxygen nuclei to suppress the formation of a buried oxide layer within the silicon substrate. In other embodiments, methods for forming semiconductor structures typically include processes comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate. In these other embodiments, a T value in the range of 100 °C to 530 °C, 150 °C to 520 °C, 200 °C to 500 °C, 250 °C to 480 °C, 300 °C to 460 °C, or 350 °C to 450 °C can be used. O .

[0059] exist Figure 2 In an embodiment, method 200 includes, in process 206, maintaining the silicon substrate in a T O At the same time, molecular oxygen (O2) is produced at a rate of 1 x 10 -8 millibars to 1 x 10 -4 Oxidative stress of millibars (P) O ) and oxygen doses from 0.1 Langmuir (L) to 10,000 Langmuir D O The material is supplied to the vacuum chamber. In this manner, a crystalline silicon oxide superstructure having a (1x1) planar structure using Wood's representation can be formed on the deposition surface. In other embodiments, methods for forming semiconductor structures typically include a process comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on that silicon substrate. In these other embodiments, a 1x10 planar structure can be used. -8 millibars to 1x10 -5 millibars, 1x10 -7 millibars to 1x10 -6 millibars, or 5 x 10 -7 millibars to 5x10 -5 P in the range of millibars O In the other embodiments, D can be in the range of 1 Langmuir to 1000 Langmuir, 5 Langmuir to 500 Langmuir, or 10 Langmuir to 100 Langmuir.O .

[0060] exist Figure 2 In the molecular oxygen supply process 206 of the embodiment, molecular oxygen O2 is supplied to the vacuum chamber for a continuous oxidation period, the oxidation duration of which is (t) O The duration of oxidation can range from 0.5 seconds to 30 minutes. In other embodiments, the oxidation time for which O2 is supplied to the vacuum chamber can be any suitable duration. For example, in some embodiments, a duration of t can be used that ranges from 0.5 seconds to 30 minutes, 30 seconds to 15 minutes, or 1 minute to 10 minutes. O .

[0061] exist Figure 2 In some embodiments, method 200 further includes a selective process 207 for depositing a dielectric capping layer on the silicon oxide superstructure. This deposition of the capping layer can be achieved, at least in part, by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and / or evaporation.

[0062] It is worth noting that, Figure 2 The method 200 of the embodiment is used as a maximum processing temperature T less than or equal to 500°C. max One particular embodiment of a method for forming a semiconductor structure includes a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate. Typically, lower T... max This could encourage the use of this approach in situations requiring a more stringent thermal budget. In particular, lower T... max The formation of silicon carbide (SiC) can be suppressed, which in turn reduces the density of grain boundaries and / or dislocations on the deposited surface after processing. Alternatively or concurrently, certain structures fabricated on a substrate, such as metallized structures, may require lower processing temperatures. In other embodiments, the method for forming the semiconductor structure can have any suitable processing temperature. max The semiconductor structure includes a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate, for example, at a T value less than or equal to 1200 °C, less than or equal to 500 °C, less than or equal to 480 °C, less than or equal to 460 °C, or less than or equal to 450 °C. max .

[0063] In one embodiment, a method for forming a semiconductor structure includes... Figure 2The methods 200 of the embodiment correspond to processes 201, 205, and 206, and the semiconductor structure includes a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate.

[0064] Typically, in methods for forming semiconductor structures, the method used to achieve... Figure 2 The steps of any corresponding process in method 201, process 202, process 205, process 206, and process 207 of the embodiment method 200 need not be performed in a fixed order, and the semiconductor structure includes a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate. Additionally, a method for forming a semiconductor structure may include related... Figure 2 The method 200 of the embodiments and any number of additional processing or steps not disclosed herein, wherein the semiconductor structure includes a crystalline silicon substrate and a crystalline silicon oxide superstructure on the silicon substrate.

[0065] Several embodiments will be described below.

[0066] In the first embodiment, a 6 mm x 12 mm rectangular silicon sample was cut from an n-type silicon (100) wafer to serve as a crystalline silicon substrate with a silicon (100) deposited surface. The silicon sample was secured to a sample holder made of molybdenum (Mo) by its shorter edges, allowing direct current to pass through the silicon sample. The sample holder was transferred to a manipulator located in one of the vacuum chambers of a multi-chamber vacuum system, and the silicon sample was then repeatedly and rapidly heated to a cleaning temperature of 1100°C to 1200°C to remove any native oxides and carbon contaminants from the silicon (100) deposited surface. LEED analysis revealed a clear (2x1) + (1x2) reconstruction from the inherent double-domain surface structure. STM images obtained after surface cleaning supported the existence of double-domain reconstruction on a large two-dimensional terrace.

[0067] Following the cleaning stage, O2 gas, introduced into the vacuum chamber through a leak valve, is used to oxidize the silicon sample with a clean silicon (100) deposition surface in the same vacuum system. Before opening the leak valve, the silicon sample is heated to an oxidation temperature (T00) of approximately 450 °C. O Then, the oxidation pressure (P) in the vacuum chamber is... O Increased to 1x10 -6Millibars, this pressure can be measured using an ion gauge pressure meter, and the silicon sample is placed in a T... O Oxidation lasts for 200 seconds, resulting in an oxidation dose of 200 Langmuirs. Afterward, the leakage valve is closed, and silicon heating is simultaneously stopped.

[0068] Following oxidation of the silicon sample, XPS confirmed that the deposited surface of the silicon sample contained silicon oxide. Furthermore, LEED analysis of the silicon sample revealed a simple (1x1) pattern. Typically, such results indicate the formation of an amorphous silicon oxide layer on the silicon (100), causing (1x1) LEED diffraction spots to emerge from the blocky silicon (100) plane beneath this amorphous layer.

[0069] However, as Figure 3 As shown in a), the STM image obtained after oxidation reveals a smooth island-like structure on the silicon sample. Consistent with previous XPS and LEED results, no columnar structure of silicon dimers (Si-dimers) was detected on top of the smooth island-like structures. Instead, as shown in a diagram... Figure 3 b) and Figure 3 As shown in c), a high-resolution STM image of the smooth island structure reveals a column structure with an inter-row distance of approximately 0.39 nm, close to the silicon (100) lattice constant. Figure 3 In b), these columns extend substantially along the direction indicated by the white double-headed arrows on the surface of the oxidized silicon sample.

[0070] Overall, the results indicate the formation of an epitaxial crystalline silicon oxide superstructure on the deposited surface of the silicon sample, which conforms to the lattice structure of the silicon substrate. The crystalline structure of this silicon oxide superstructure follows the periodicity of the silicon (100) (1x1) plane. Thus, the silicon oxide superstructure possesses a (1x1) planar structure using Wood's notation.

[0071] Furthermore, the (1x1) LEED pattern of the silicon sample is denser than the typical pattern on a silicon (100) surface covered by an amorphous silicon oxide layer, especially at a surface-sensitive electron binding energy of around 100 electron volts (eV). This high-density LEED pattern is consistent with the STM images, indicating the formation of an epitaxial crystalline silicon oxide superstructure.

[0072] In the second embodiment, n-type floating-zone (FZ) silicon wafers and p-type FZ silicon wafers with a resistivity of 3 ohms (Ωm) and a diameter of 102 mm (4 inches) are used as crystalline silicon substrates with silicon (100) deposition surfaces. The deposition surfaces of the silicon wafers are cleaned in a standard RCA cleaning procedure (including RCA-1 and RCA-2 sections), and then subjected to a T444-T ... A A pre-annealing step is performed. This pre-annealing step results in the formation of an amorphous silicon oxide layer, which is etched using a buffered aqueous solution of hydrofluoric acid (HF) before the wafer is introduced into the vacuum chamber of an industrial-grade ultra-high vacuum (UHV) system. To complete the cleaning of the deposited surface, the silicon wafer is subjected to a T244°C process. A The pre-annealing step is then carried out until degassing stops.

[0073] Following cleaning, the wafer is oxidized by introducing O2 gas into a vacuum chamber through a leak valve using oxidation parameters similar to those in the first embodiment. This results in the formation of a crystalline silicon oxide superstructure on the deposition surface of the wafer. After oxidation, the wafer is cooled and transferred to an ALD instrument used to generate an Al2O3 capping layer approximately 20 nanometers thick on the silicon oxide superstructure using trimethylaluminium (TMA) and water as precursors.

[0074] Finally, the defect density at the interface between the crystalline silicon wafer and the crystalline silicon oxide superstructure on it was evaluated using corona oxide characterization of semiconductor (COCOS) technology. According to the results of this COCOS measurement, the interface exhibits a reduced interface defect density. This result is consistent with the results of separate carrier lifetime measurement, which shows an increase in the minority carrier lifetime of the substrate with the crystalline silicon oxide superstructure.

[0075] In the third embodiment, a 6 mm x 12 mm silicon sample is cut from an adjacent, i.e., a cut silicon (111) wafer, to be used as a crystalline silicon substrate. The silicon sample is cleaned and oxidized using a process and processing parameters similar to those of the first embodiment, except that the oxidation uses a different To. O It is relatively low, around 400 °C.

[0076] Scanning tunneling spectroscopy (STS) of the adjacent diced silicon (111) surface revealed a surface band gap of approximately 5 eV after oxidation, indicating the formation of a silicon oxide superstructure on this surface. Additionally, as... Figure 4 a) and Figure 4 As shown in b), the STM image obtained after oxidation shows the presence of column structures that follow the hexagonal lattice structure of the silicon substrate.

[0077] Overall, the results of STS and STM measurements indicate the formation of a crystalline silicon oxide superstructure on the adjacent silicon (111) surface of the silicon sample. Based on these results, the crystalline structure of the silicon oxide superstructure follows the periodicity of the silicon (111) (1x1) planar structure.

[0078] It will be apparent to those skilled in the art to which this disclosure pertains that, with advancements in technology, the basic ideas of this invention can be implemented in various ways. Therefore, this invention and its embodiments are not limited to the embodiments described above, but can be varied within the scope of this patent application.

[0079] It should be understood that any of the benefits and advantages described above may apply to one embodiment or multiple embodiments. The embodiments are not limited to embodiments that solve any or all of the described problems, or embodiments that have any or all of the described benefits and advantages.

[0080] In this specification, the term "comprising" means including the features or actions that follow it, without excluding the presence of one or more additional features or actions. It should also be understood that "a" object refers to one or more of the same object.

[0081] Explanation of reference numerals in the attached figures

[0082] 100: Semiconductor Structure

[0083] 110: Silicon substrate

[0084] 111: Surface

[0085] 120: Silica Superstructure

[0086] 130: Overlay

[0087] 200: Method

[0088] 201: Provide silicon substrate

[0089] 202: Clean the deposited surface

[0090] 203: RCA Cleaning Steps

[0091] 204: Pre-annealing step

[0092] 205: Heating the silicon substrate

[0093] 206: Supply of molecular oxygen

[0094] 207: Depositional medium overburden

Claims

1. A method (200) of forming a semiconductor structure, the semiconductor structure comprising a crystalline silicon substrate and a crystalline silicon oxide superstructure on the crystalline silicon substrate, the method (200) comprising the following processes: providing the crystalline silicon substrate (201) having a substantially clean deposition surface in a vacuum chamber; heating the crystalline silicon substrate to an oxidation temperature T of 100 °C to 450 °C O (205); and while keeping the crystalline silicon substrate at the oxidation temperature T O of 1 x 10 -8 -4 millibar to 1 x 10 -4 -4 millibar oxidation pressure P O and an oxygen dose D O of 0.1 Langmuir to 10,000 Langmuir is supplied to the vacuum chamber (206); wherein forming the crystalline silicon oxide superstructure on the deposition surface, the crystalline silicon oxide superstructure having a thickness of at least two molecular layers and a (1 x 1) plane structure in Wood notation.

2. The method (200) of claim 1, wherein The deposition surface is a silicon {100} surface, a silicon {111} surface or a silicon {110} surface.

3. The method (200) of claim 1 or 2, wherein The oxidation temperature T O in the range of 200 to 450 °C.

4. The method (200) of claim 1 or 2, wherein, The oxidation pressure P O in the range of 1 x 10 -8 in the range of 1 x 10 -5 in the range of 1 x 10 5. The method (200) of claim 1 or 2, wherein, The oxygen dose D O In the range of 1 to 1000 Langmuir.

6. The method (200) of claim 1 or 2, wherein, The molecular oxygen O2 is supplied into the vacuum chamber for an oxidation period, the oxidation period having an oxidation time length t O In the range of 0.5 seconds to 30 minutes.

7. The method (200) of claim 1 or 2, wherein, The process (201) of providing the crystalline silicon substrate comprises cleaning the deposition surface (202) to remove possible native oxides and / or other impurities prior to the process of supplying the molecular oxygen O2.

8. The method (200) of claim 7, wherein, The cleaning process for the deposited surface (202) includes an RCA cleaning step (203) and a pre-annealing step (204) following the RCA cleaning step (203), wherein the pre-annealing step (204) is performed at a pre-annealing temperature T in the range of 200 °C to 300 °C. A and less than or equal to 1 x 10 -4 Pre-annealing pressure P in millibars A The pre-annealing step is carried out during a pre-annealing period, the duration of which is t. A Greater than or equal to 1 minute.

9. The method (200) according to claim 1 or 2, further comprising depositing a dielectric capping layer (207) on the crystalline silicon oxide superstructure.

10. The method (200) according to claim 1 or 2, having a maximum processing temperature T max , the maximum processing temperature T max being less than or equal to 500 °C.

11. A semiconductor structure (100) formed by using the method of any one of claims 1 to 10, comprising: a crystalline silicon substrate (110) having a surface (111); and a crystalline silicon oxide superstructure (120) on the surface (111) of the crystalline silicon substrate (110), the crystalline silicon oxide superstructure (120) having a thickness of at least two molecular layers and a (1 x 1) plane structure in Wood notation.

12. The semiconductor structure (100) according to claim 11, wherein The surface (111) is a silicon {100} surface, a silicon {111} surface or a silicon {110} surface.

13. The semiconductor structure (100) according to claim 11 or 12, wherein The crystalline silicon oxide superstructure (120) has a thickness greater than or equal to 1 nanometer and / or less than or equal to 10 nanometers.

14. The semiconductor structure (100) according to claim 11 or 12, further comprising a dielectric capping layer (130), the dielectric capping layer (130) being located on the crystalline silicon oxide superstructure.

15. The semiconductor structure (100) according to claim 14, wherein The dielectric capping layer (130) comprises a dielectric material having a relative dielectric constant K greater than or equal to 10.

16. Use of a crystalline silicon oxide superstructure having a (1 x 1) plane structure in Wood notation for surface passivation of a crystalline silicon substrate in a semiconductor structure, wherein The semiconductor structure is the semiconductor structure (100) according to any one of claims 11 to 15.

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