Solar cell having a hybrid structure including separate P-type and N-type regions and bias contacts

Abstract

The present invention discloses a solar cell and a method for manufacturing the solar cell. The solar cell may include a first emitter region on a substrate, the first emitter region having a perimeter surrounding a portion of the substrate. A first conductive contact is electrically connected to the first emitter region at a position outside the perimeter of the first emitter region.

Description

[0001] Cross-references to related patent applications

[0002] This application claims priority to U.S. Non-Provisional Application No. 16 / 832,762, filed on March 27, 2020, which claims the benefit of U.S. Provisional Application No. 62 / 826,699, filed on March 29, 2019, the entire contents of which are hereby incorporated by reference herein. Background Art

[0003] Photovoltaic (PV) cells, often called solar cells, are devices used to convert solar radiation into electrical energy. Generally speaking, solar radiation impinging on the surface of a solar cell substrate and entering the substrate forms electron and hole pairs in the bulk of the substrate. The electron and hole pairs migrate to p-type doped regions and n-type doped regions in the substrate, thereby forming a voltage difference between the doped regions. The doped regions are connected to conductive regions on the solar cell to conduct current from the cell to an external circuit. When PV cells are combined in an array such as a PV module, the electrical energy collected from all of the PV cells can be combined in series and parallel arrangements to provide a power source with a certain voltage and current. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A cross-sectional view of a portion of a solar cell is shown according to some embodiments.

[0005] Figure 2A and Figure 2B A plan view and a cross-sectional view respectively illustrate a portion of a solar cell according to some embodiments.

[0006] Figure 3 A cross-sectional view of a portion of a solar cell is shown according to some embodiments.

[0007] Figure 4 A cross-sectional view of a portion of a solar cell is shown according to some embodiments.

[0008] Figure 5 A cross-sectional view of a portion of a solar cell is shown according to some embodiments.

[0009] Figure 6 A cross-sectional view of a portion of a solar cell according to some embodiments is shown.

[0010] Figure 7 An exemplary plan view showing a portion of a solar cell according to some embodiments.

[0011] Figure 8 FIG. 1 is a flow chart illustrating a method of manufacturing a solar cell according to some embodiments.

[0012] Fig. 9A cross-sectional view of a portion of a solar cell is shown for comparison purposes. DETAILED DESCRIPTION

[0013] Efficiency is an important characteristic of solar cells because it is directly related to the ability of the solar cell to generate electricity. Likewise, the efficiency of producing solar cells is directly related to the cost-effectiveness of such solar cells. Therefore, techniques for improving the efficiency of solar cells or techniques for improving the efficiency of manufacturing solar cells are generally needed. Some embodiments of the present disclosure allow for improving the manufacturing efficiency of solar cells by providing new processes for manufacturing solar cell structures. Some embodiments of the present disclosure allow for improving the efficiency of solar cells by providing new solar cell structures.

[0014] The following specific embodiments are merely exemplary in nature and are not intended to limit the application and use of these embodiments or such embodiments. As used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as exemplary is not necessarily preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, summary of the invention or the following specific embodiments.

[0015] References to "one embodiment" or "an embodiment" in this specification are not necessarily to the same embodiment. The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0016] Terminology. The following paragraphs provide definitions and / or context for terms found in this disclosure (including the appended claims):

[0017] "Area" or "portion" describes a discrete area, volume, portion, or location of an object or material that has definable characteristics but not necessarily fixed boundaries.

[0018] “Comprising” is an open term and does not exclude other structures or steps.

[0019] "Configured to" refers to a structure by indicating a device, such as a unit or component, including a structure that performs one or more tasks during operation, and such structure is configured to perform the task even if the device is not currently operating (e.g., not turned on / activated). A device "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f), paragraph 6.

[0020] The terms "first", "second", etc. are used as labels for the nouns that follow them, and do not imply any type of order (e.g., spatial, temporal, logical, etc.). For example, reference to a "first" semiconductor layer does not necessarily mean that the semiconductor layer is the first semiconductor layer in a sequence; rather, the term "first" is used to distinguish the semiconductor layer from another semiconductor layer (e.g., a "second" semiconductor layer). As used herein, a semiconductor layer may be a polysilicon layer, for example, a polysilicon layer doped with a P-type or N-type dopant. In one example, the first semiconductor layer may be a first polysilicon layer, in which multiple polysilicon layers may be formed (e.g., a second polysilicon layer may be formed).

[0021] "Based on". As used herein, the term is used to describe one or more factors that affect the determination. The term does not exclude additional factors that may affect the determination. That is, the determination may be based only on those factors or at least in part on those factors. Consider the phrase "A is determined based on B". Although B may be a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other examples, A may be determined based only on B.

[0022] “Coupled” means that unless expressly stated otherwise, an element, feature, structure, or node is or can be connected or communicated with another element / node / feature, either directly or indirectly, and not necessarily directly mechanically connected together.

[0023] "Prevent" means to reduce, diminish, minimize, or effectively or physically eliminate something, such as completely avoiding an outcome, consequence, or future state.

[0024] "Thin dielectric layer", "tunnel dielectric layer", "dielectric layer", "thin dielectric material" or intermediate layer / material refers to a material located on a semiconductor region, between a substrate and another semiconductor layer, between doped regions or semiconductor regions on or in a substrate. In one embodiment, the thin dielectric layer can be a tunnel oxide layer or nitride layer having a thickness of about 2 nanometers or less. A thin dielectric layer can be referred to as a very thin dielectric layer through which electrical conduction can be achieved. The conduction can be due to quantum tunneling and / or the presence of small areas that are directly physically connected through thin points in the dielectric layer. Exemplary materials include silicon oxide, silicon dioxide, silicon nitride, and other dielectric materials. In one embodiment, multiple dielectric layers can be formed. "About" or "approximately". As used herein, with respect to recited values, including, for example, integers, fractions, and / or percentages, the terms "about" or "approximately" generally indicate that the recited value encompasses a range of values ​​(e.g., + / - 5% to 10% of the recited value) that a person of ordinary skill in the art would consider equivalent to the recited value (e.g., performing substantially the same function, acting in substantially the same manner and / or having substantially the same results).

[0025] In addition, certain terms may be used in the following description for reference purposes only, and therefore, these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings for which reference is provided. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation and / or position of certain portions of a component within a consistent but arbitrary reference system, which can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0026] Methods for manufacturing solar cell emitter regions and the resulting solar cells are described herein. In the following description, many specific details, such as specific process flow operations, are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known manufacturing techniques, such as lithography and patterning techniques, are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be understood that the various embodiments shown in the figures are exemplary displays and are not necessarily drawn to scale.

[0027] To provide background information, in a hybrid structure, two semiconductor layers (such as polysilicon layers) are deposited separately. The overlap between the semiconductor layers is separated by a dielectric layer or structure. The contact can largely coincide with the emitter on the wafer. In contrast, the embodiments described herein can be implemented so that the contact can be offset from the emitter region on the wafer.

[0028] According to one or more embodiments described herein, a biased contact structure is implemented to separate the semiconductor layer from contact with the metal and contact with the substrate or wafer. If the contacts are made by laser ablation, laser damage on one type of emitter may be reduced or eliminated because the dielectric and lower polycrystalline layers prevent the damage from being transferred to the substrate. In contrast, damage to the emitter region may occur in the case where the laser scribing overlaps or at least partially overlaps the emitter region. Another potential benefit is the elimination of the risk of aluminum "spikes" for hybrid emitters. For example, spikes can be formed to make contact without causing shunting. Another potential benefit is that the docking area can be formed independently of the emitter region. If the emitter and the contact overlap to a large extent, it may be difficult to reduce the emitter to a point-like structure and maintain alignment tolerances. If alignment tolerances do not need to be maintained, the emitter can have a variety of shapes, such as a line to minimize the docking area, or many small dots to maximize the docking area.

[0029] As an exemplary structure with bias contacts, Figure 1A cross-sectional view of a portion of a solar cell 100 according to some embodiments is shown. In a certain embodiment, the solar cell 100 may include a substrate 106 having a front side 102 and a back side 104 (the front side 102 is opposite the back side 104). In some embodiments, the front side 102 may be referred to as a front surface, and the back side 104 may be referred to as a back surface. In a certain embodiment, the front side may have a textured surface. The textured surface 130 may be a surface having a regular or irregular shape, which is used to scatter incident light, reduce the amount of light reflected from the light receiving surface and / or exposed surface of the solar cell 100.

[0030] Reference again Figure 1 In some embodiments, the solar cell 100 may include a first dielectric layer 120 disposed on the back side 104 of the substrate 106. In some embodiments, the first dielectric layer 120 may be referred to as a first thin dielectric layer. In some examples, the first dielectric layer 120 may be a thin oxide layer, such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In some embodiments, the first dielectric layer 120 may have a thickness of about 2 nanometers or less.

[0031] Still refer to it again Figure 1 In an embodiment, the solar cell 100 may include a first semiconductor layer 112 disposed on the back side of the solar cell 100. In an embodiment, the first semiconductor layer 112 may be disposed on the first dielectric layer 120. In an embodiment, the first semiconductor layer 112 may be a first polysilicon layer. In an embodiment, the first semiconductor layer 112 may include a first conductivity type. In an example, the first semiconductor layer 112 may be a first polysilicon layer of the first conductivity type. In a specific embodiment, the first conductivity type is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In some embodiments, the first semiconductor layer is a pre-doped polysilicon layer. In one such embodiment, a first semiconductor layer having a specific conductivity type (e.g., N-type or P-type) is formed.

[0032] Reference again Figure 1 In one embodiment, the solar cell 100 may include a second dielectric layer 114 disposed on the back side 104 of the substrate 106. In some embodiments, the second dielectric layer 114 may be referred to as a second thin dielectric layer. In a certain example, the second dielectric layer 114 may be a thin oxide layer, such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In a certain embodiment, the second dielectric layer 114 may have a thickness of about 2 nanometers or less.

[0033] Reference again Figure 1In a certain embodiment, the solar cell 100 may include a second semiconductor layer 108 disposed on the second dielectric layer 114. In an embodiment, the second semiconductor layer 108 may be a second polysilicon layer. In a certain embodiment, the second semiconductor layer may include a second conductivity type. In a certain example, the second semiconductor layer 108 may be a second polysilicon layer of the second conductivity type. In a specific embodiment, the second conductivity type is P-type (e.g., formed using boron impurity atoms). In some embodiments, the second semiconductor layer is a pre-doped polysilicon layer. In one such embodiment, a second semiconductor layer having a specific conductivity type (e.g., N-type or P-type) is formed. In a certain embodiment, the solar cell 100 may also include a first insulator layer 110 disposed on the second semiconductor layer 108. In an example, the first insulator layer 110 may be silicon dioxide or include silicon dioxide.

[0034] Reference again Figure 1 In some embodiments, the third dielectric layer 116 is between the first semiconductor layer 112 and the second semiconductor layer 108. In some embodiments, the third dielectric layer 116 may be referred to as a third thin dielectric layer. In some examples, the third dielectric layer 116 may be a thin oxide layer, such as a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In some embodiments, the third dielectric layer 116 may have a thickness of about 2 nanometers or less. In some embodiments, the first dielectric layer 120, the second dielectric layer 114, and the third dielectric layer 116 may form a continuous dielectric layer. In some examples, the continuous dielectric layer may include the first dielectric layer 120, the second dielectric layer 114, and the third dielectric layer 11 and does not include any gaps or discontinuities. In some embodiments, any combination of continuous dielectric layers may be formed. For example, the first dielectric layer and the second dielectric layer may alternatively form a continuous dielectric layer. In one example, the first dielectric layer and the third dielectric layer and / or the second dielectric layer and the third dielectric layer may form a continuous dielectric layer.

[0035] Reference again Figure 1 In one embodiment, the second insulator layer 125 may be disposed on the first semiconductor layer 112. In one embodiment, the second insulator layer 125 may be a dopant layer. In one embodiment, the dopant layer may have a first conductivity type. In one embodiment, the dopant layer has the same conductivity type as the first semiconductor layer 112. In one example, the dopant layer is N-type (e.g., formed using phosphorus atoms or arsenic impurity atoms). In another example, the dopant layer is P-type (e.g., formed using boron impurity atoms). In one embodiment, the second insulator layer 125 may be a discontinuous layer (e.g., as Figure 1). In some examples, the second insulator layer 125 can be divided into discrete parts and still be referred to as a single dielectric layer or dopant layer. In one embodiment, the second insulator layer 125 can include silicon oxide or silicon oxynitride. In some embodiments, the second insulator layer 125 can be a dielectric layer.

[0036] Reference again Figure 1 , the first conductive contact 129 can be disposed on the first semiconductor layer 112. In one embodiment, the first conductive contact 129 is disposed in the opening 123 in the second insulator layer 125. In one embodiment, although Figure 1 2, as described below, the solar cell 100 may include a second conductive contact (eg, Figure 2A and Figure 2B 128, as described below). In one embodiment, the second conductive contact may be disposed in an opening in the first insulator layer 110 (eg, Figure 2A and Figure 2B 121, as described below).

[0037] In one embodiment, the first conductive contact 129 and the second conductive contact 128 may include plated metal. In a certain example, the first conductive contact 129 and the second conductive contact 128 may include copper, tin, titanium, tungsten and / or nickel and other metals. In some embodiments, the first conductive contact 129 and the second conductive contact 128 may include deposited metal and / or metal foil. In a certain example, the first conductive contact 129 and the second conductive contact 128 may include aluminum or aluminum foil. In a certain embodiment, the first conductive contact 129 and the second conductive contact 128 may include wire, ribbon or any other applicable conductive material type. In a certain example, the first conductive contact 129 and the second conductive contact 128 may include aluminum wire, aluminum ribbon, etc.

[0038] Again, reference Figure 1 In an embodiment, the solar cell 100 may further include a fourth dielectric layer 132 disposed on the front side 102. In an embodiment, the fourth dielectric layer 132 may be an anti-reflective coating (ARC). In an example, the fourth dielectric layer 132 may include silicon nitride. In an example, the fourth dielectric layer may include a tunnel dielectric layer (e.g., tunnel oxide, silicon oxynitride, silicon oxide). In an embodiment, a polysilicon layer may be formed on the fourth thin dielectric layer 132. In an embodiment, a fifth dielectric layer may be disposed on the polysilicon layer. In an embodiment, the fifth dielectric layer may be an anti-reflective coating (ARC). In an example, the fifth dielectric layer may include silicon nitride.

[0039] Reference again Figure 1, in some embodiments, the second semiconductor layer 108 may be a P-type polysilicon layer. In one embodiment, the first semiconductor layer 112 may be an N-type polysilicon layer. In a certain embodiment, the substrate 106 may be an N-type single crystal silicon substrate. In a certain embodiment, the first dielectric layer 120, the second dielectric layer 114, the third dielectric layer 116, and the second insulator layer 125 may include silicon oxide. In a certain embodiment, the first insulator layer 110 is silicon dioxide or includes silicon dioxide. In a certain embodiment in which the second insulator layer 125 may include a dopant layer, the second insulator layer 125 may include phosphorus, arsenic, or boron. In one embodiment, the second semiconductor layer 108 may be an N-type polysilicon layer. In a certain embodiment, the first semiconductor layer 112 may be a P-type polysilicon layer. In some embodiments, the substrate 106 may be a P-type single crystal silicon substrate.

[0040] Reference again Figure 1 In certain embodiments, the first conductive contact 129 (and / or the second conductive contact mentioned) may include a deposited metal. In certain embodiments, the deposited metal may be aluminum-based. In one such embodiment, the aluminum-based deposited metal may have a thickness approximately in the range of 0.3 microns to 20 microns, and include an aluminum content greater than about 97%, and a silicon content approximately in the range of 0% to 2%. In certain examples, the aluminum-based deposited metal may include copper, titanium, titanium tungsten, nickel and / or aluminum and other metals. In certain embodiments, the aluminum-based deposited metal is formed by a blanket deposition process. In certain embodiments, the aluminum-based deposited metal may be a metal seed layer. In some examples, the deposited metal may be deposited aluminum. In one embodiment, the conductive contacts as described herein may include copper, tin, nickel and / or aluminum and other metals.

[0041] Again, reference Figure 1 In some embodiments, the conductive contacts as described herein include metal foil. In a certain embodiment, the metal foil is aluminum (Al) foil having a thickness in the range of about 5-100 microns. In one embodiment, the Al foil is an aluminum alloy foil comprising aluminum and a second element such as, but not limited to, copper, manganese, silicon, magnesium, zinc, tin, lithium, or a combination thereof. In one embodiment, the Al foil is a tempered grade foil such as, but not limited to, grade F (free state), grade O (fully soft), grade H (strain hardened), or grade T (heat treated). In one embodiment, the aluminum foil is an anodized aluminum foil. In another embodiment, the aluminum foil is not anodized.

[0042] Still refer to it again Figure 1In certain embodiments, the conductive contacts as described herein include conductive wires. In certain embodiments, the conductive wires may include a conductive material (e.g., a metal such as aluminum, copper, or another suitable conductive material, with or without a coating such as tin, silver, nickel, or an organic solderability preservative). In certain examples, the conductive wires may be bonded to the first semiconductor layer and / or the second semiconductor layer by thermocompression bonding, ultrasonic bonding, or thermosonic bonding methods.

[0043] See again Figure 1 According to a certain embodiment of the present disclosure, the solar cell 100 includes a first emitter region 150 on a substrate 106. The first emitter region 150 has a perimeter around a portion of the substrate, i.e., viewed from a plan view (i.e., viewed from a direction perpendicular to the spherical surface of the substrate), wherein the perimeter surrounds an area of ​​the emitter region 150 above the substrate. The first conductive contact 129 is electrically coupled to the first emitter region 150 at a location outside the perimeter 150 of the first emitter region (i.e., at a location not above the first emitter region 150, viewed from a plan view). It should be understood that the term "offset" as used refers to a contact opening outside the perimeter of the emitter region 150, not just a misalignment of the contact opening from the underlying emitter region.

[0044] In a certain embodiment, the solar cell 100 further includes a first semiconductor layer 112 on the substrate 106. In one embodiment, the first emitter region 150 is in a first portion 112A of the first semiconductor layer 112, and a location outside the perimeter 150 of the first emitter region is on a second portion 112B of the first semiconductor layer 112. In one such embodiment, the first portion 112A of the first semiconductor layer 112 is continuous with the second portion 112B of the first semiconductor layer 112.

[0045] In a certain embodiment, the solar cell 100 further includes a first insulator layer 110 over the substrate 106. The first insulator layer 110 has a first opening 111. The first portion 112A of the first semiconductor layer is in the first opening 111 of the first insulator layer 110. The second portion 112B of the first semiconductor layer 112 is over the portion 110A of the first insulator layer 110.

[0046] In a certain embodiment, the solar cell 100 further includes a second insulator layer 125 above the first semiconductor layer 112. The second insulator layer 125 has an opening 123. In one such embodiment, a location outside the perimeter of the first emitter region 150 is below the opening 123 of the second insulator layer 125, and a first portion 129A of the first conductive contact 129 is in the opening 125 of the second insulator layer. In a specific such embodiment, a second portion 129B of the first conductive contact 129 is on the portion 125A of the second insulator layer 125 above the first insulator layer 110. A third portion 129C of the first conductive contact 129 is on the portion 125B of the second insulator 125 layer above the first emitter region 150. In a certain embodiment, the solar cell 100 further includes a second semiconductor layer 108 between the first insulator layer 110 and the substrate 106. In one embodiment, the second semiconductor layer 108 has a conductivity type opposite to that of the first semiconductor layer 112. In one embodiment, the second semiconductor layer 112 is included in the second emitter region (e.g., Figure 2A and Figure 2B 152, as described below). In one embodiment, the first insulator layer 110 has a second opening (eg, Figure 2A and Figure 2B 121, as described below). The second conductive contact (e.g., Figure 2A and Figure 2B 128 , described below) is electrically coupled to the second semiconductor layer 108 at a location below the second opening 121 of the first insulator layer 110 .

[0047] Now go to Figure 2A and Figure 2B , Figure 2A and Figure 2B A plan view and a cross-sectional view respectively show a portion of a solar cell according to some embodiments. It should be understood that the plan view shows a larger portion of the solar cell than the cross-sectional view, because both show a single emitter structure including a conductive contact of type 128, but the cross-sectional view only shows a single emitter structure including a first conductive contact of type 129, while the plan view shows two emitter structures including a first conductive contact of type 129.

[0048] refer to Figure 2A and Figure 2B , the solar cell 200 includes a first insulator layer 110 above the substrate 106. The first insulator layer 110 has a first opening 111 (in this case, Figure 2A and Figure 2B10. The first semiconductor layer 112 is over the substrate 106. The first portion 112 of the first semiconductor layer is in the first opening 111 of the first insulator layer 110. The second portion 112 of the first semiconductor layer is over a portion of the first insulator layer 110. In one embodiment, the first portion of the first semiconductor layer 112 is continuous with the second portion of the first semiconductor layer 112.

[0049] See again Figure 2A and Figure 2B , the second semiconductor layer 108 is above the substrate 106. The second semiconductor layer 108 is between the first insulator layer 110 and the substrate 106. The second semiconductor layer 108 has a conductivity type opposite to the conductivity type of the first semiconductor layer 112. The second insulator layer 125 is above the first semiconductor layer 112. The second insulator layer 125 has an opening 123 above the second portion of the first semiconductor layer 112. In a certain embodiment, the first semiconductor layer 112 includes a first emitter region 150 (for example, a first emitter region 150 based on the first emitter region 150). Figure 2A and Figure 2B A single emitter structure of a first conductive contact 129, two of which are shown), and the second semiconductor layer 108 is included in a second emitter region 152, which may be an emitter region having a conductivity type opposite to the conductivity type of one or more emitter regions 150.

[0050] See again Figure 2A and Figure 2B , a first conductive contact 129 (in this case, two such contacts are shown as bridging between two corresponding emitter regions 150) is in the opening 111 of the second insulator layer 125. The first conductive contact 129 is electrically coupled to the second portion of the first semiconductor layer 112 at a location below the opening 123 of the second insulator layer 125. In a certain embodiment, the first conductive contact 129 is also on a portion of the second insulator layer 125 that is above the first insulator layer 110. In one such embodiment, the first conductive contact 129 is also on a portion of the second insulator layer 125 that is above the first portion of the first semiconductor layer 112 (i.e., the portion of the first semiconductor layer 112 that is in the opening 111 and included in the emitter region 150).

[0051] See again Figure 2A and Figure 2BIn some embodiments, a portion of the insulator layer 110 may be located below the opening 123 and above the substrate 106. In the same embodiment, the portion of the insulator layer 110 may be disposed on the second semiconductor layer 108. In some embodiments, the portion of the first insulator layer 110 may physically and / or electrically isolate the first semiconductor layer 112 from the second semiconductor layer 108. In the same embodiment, the portion of the insulator layer 110 may be located between at least two openings 111 of the second insulator layer 125. In some embodiments, the portion of the insulator layer 110 may be surrounded by the first semiconductor layer 112. In some examples, three sides of the portion of the insulator layer 110 may be surrounded by the first semiconductor layer 112, such as Figure 2B shown.

[0052] See again Figure 2A and Figure 2B In some embodiments, a portion of the second semiconductor layer 108 may be located below the opening 123 and above the substrate 106. In the same embodiment, a portion of the second semiconductor layer 108 may be located below a portion of the insulator layer 110 (e.g., the portion below the opening 123) and above the substrate 106. In the same embodiment, the portion of the second semiconductor layer 108 may be located between two emitter regions 150. In the same embodiment, the portion of the second semiconductor layer 108 may be physically and / or electrically isolated (e.g., disconnected, not in contact with) other portions of the first semiconductor layer 112 and / or the second semiconductor layer 108.

[0053] The second conductive contact 128 is in the second opening 121 of the first insulator layer 110. The second conductive contact 128 is electrically coupled to the second semiconductor layer 108 at a position below the second opening 121 of the first insulator layer 110. In a certain embodiment, the second conductive contact 128 may extend over the first insulator layer 110, for example, the second conductive contact 128 may extend in the opening 121 and over at least one edge of the first insulator layer 110.

[0054] refer to Figure 2A 200, it should be understood that the opening 123 and the emitter regions 150, 152 are shown for clarity and may not be visible in a similar view of the final product. In a certain example, the conductive contact 128 can be disposed over the emitter region 152, and the conductive contact 129 can be disposed over the emitter region 150 and the opening 123, thereby covering the opening 123 and the emitter regions 150, 152 and making them invisible.

[0055] Now go to Figure 3 , Figure 3A cross-sectional view of a portion of a solar cell 300 according to some embodiments is shown. In the example shown, for each emitter structure including a first semiconductor layer of type 112 and a first conductive contact of type 129, two openings 123 may be formed in the second insulator layer 125. In a certain example, although two openings 123 are shown, 1, 2, 3, 4 or more openings may be formed.

[0056] Now go to Figure 4 , Figure 4 A cross-sectional view of a portion of a solar cell 400 according to some embodiments is shown. In the example shown, for each emitter structure including a first semiconductor layer of type 112 and a first conductive contact of type 129, two openings 111 may be formed in the first insulator layer 110. In a certain example, although two openings 111 are shown, 1, 2, 3, 4 or more openings may be formed.

[0057] Now go to Figure 5 , Figure 5 A cross-sectional view of a portion of a solar cell 500 according to some embodiments is shown. In the example shown, for each emitter structure including a first semiconductor layer of type 112 and a first conductive contact of type 129, three openings 111 are formed in the first insulator layer 110, and two openings 123 are formed in the second insulator layer 125. In a certain example, although two openings 123 and three openings 111 are shown, 1, 2, 3, 4 or more openings may be formed.

[0058] Now go to Figure 6 , in one example of an open emitter configuration, Figure 6 A cross-sectional view of a portion of a solar cell 600 is shown in accordance with some embodiments. In the example shown, for each emitter structure including a first semiconductor layer of type 112 and a first conductive contact of type 129, three openings 111 are formed in the first insulator layer 110 and two openings 123 are formed in the second insulator layer 125. However, the first conductive contact 129 is in a center opening of the three openings 111 in the first insulator layer 110. In one embodiment, the first conductive contact 129 is effectively recessed or retracted from the outer portions of the emitter structure. It should be understood that the portion of the second semiconductor layer 112 that extends beyond the first conductive contact 129 should not contact the first semiconductor layer 108 or the conductive contact of type 128 coupled to the first semiconductor layer 108, for example with reference to FIG. Figure 2A and Figure 2B108, 128. In some examples, the portion of the solar cell 600 can include an exposed portion 125, for example, which is not covered and / or is below the conductive contact 129. In some examples, the exposed portion 125 can be located above the opening 111 that is also not covered and / or is below the conductive contact 129.

[0059] It will be appreciated that in each of the above cross-sectional views, the conductive layer 129 is shown as being in continuous, intimate contact with the dielectric layer 125 immediately below the conductive contact 129. However, it will be appreciated that in some embodiments, the conductive contact 129 need only be in physical contact with the second emitter in the opening in the dielectric 123. In all other locations, the conductive contact 129 may be floating. In some cases, it may even be advantageous for the conductive contact 129 not to be in intimate contact with the insulator above the first emitter (e.g., to reduce the risk of shunting). Turning now to Figure 7 , Figure 7 An exemplary plan view showing a portion of a solar cell according to some embodiments.

[0060] refer to Figure 7 In part (a), the solar cell 700 may include any shape suitable for the emitter region 150, such as a square as shown in the figure. Figure 7 In part (b), the solar cell 702 may include a uniform line shape for the emitter region 150. Figure 7 In part (c), the solar cell 704 may include any suitable shape for the opening 123 to provide a bias contact, such as a square as shown in the figure. Figure 7 In part (d), solar cell 706 may include a uniform linear shape for opening 123 to provide a bias contact. In some examples, the shape and / or form of the emitter region and / or opening may be controlled by the method of forming these emitter regions and / or openings. For example, in the case where opening 123 can be formed using a laser contact formation process, opening 123 has an area related to the laser spot size. In addition, although specific shapes are shown, it should be understood that the embodiments herein may have any type of shape and are not limited to the specific shapes and / or forms presented above.

[0061] Now go to Figure 8 , as an exemplary manufacturing method, Figure 8 800 is a flow chart illustrating a method of manufacturing a solar cell according to some embodiments.

[0062] refer to Figure 8In operation 802 of flowchart 800, a method of manufacturing a solar cell includes forming a first insulator layer, a first semiconductor layer, and a second semiconductor layer over a substrate. The first insulator layer may have a first opening, wherein a first portion of the first semiconductor layer may be in the first opening of the first insulator layer, and a second portion of the first semiconductor layer may be over a portion of the first insulator layer. The second semiconductor layer may be between the first insulator layer and the substrate. The second semiconductor layer may have a conductivity type opposite to that of the first semiconductor layer.

[0063] In one embodiment, the first portion of the first semiconductor layer is continuous with the second portion of the first semiconductor layer. In one embodiment, the first semiconductor layer comprises polycrystalline silicon, and the substrate comprises single crystal silicon. In one embodiment, the first dielectric layer is between the first semiconductor layer and the substrate. The second dielectric layer may be between the second semiconductor layer and the substrate.

[0064] In a certain embodiment, before forming the first insulator layer, the first semiconductor layer and the second semiconductor layer above the substrate, a texturing process may be performed on the front side of the substrate. In a certain example, a textured surface may be formed on the front side of the substrate using a hydroxide-based wet etchant. However, it should be understood that the texturing of the front side may be omitted from the process flow. In a certain embodiment, the substrate may be cleaned, polished, flattened and / or thinned before or within the same or single process operation of the texturing process. In a certain example, a wet chemical cleaning process may be performed before and / or after the texturing process. Although the texturing process may be performed at the beginning of the manufacturing process, in another embodiment, the texturing process may be performed in another operation of the manufacturing process. In a certain example, the texturing process may be performed alternatively after the patterning process. In one example, the texturing process may be performed before the thermal process. In one such example, the texturing process may be performed after patterning (e.g., patterning of polysilicon regions) and before the thermal process.

[0065] In a certain embodiment, the second dielectric layer may be formed in an oxidation process and is a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the second dielectric layer may be formed in a deposition process. In a certain embodiment, the second dielectric layer is a thin oxide layer or a silicon oxynitride layer. In a certain embodiment, forming the second dielectric layer may include forming a second dielectric layer having a thickness of about 2 nanometers or less. In a certain example, a thermal process or an oven may be used to grow the second dielectric layer. As used herein, the second dielectric layer may also be referred to as a second thin dielectric layer.

[0066] In one embodiment, forming the second semiconductor layer may include forming a polysilicon layer. In one embodiment, forming the second semiconductor layer may include forming a silicon layer on the second dielectric layer, forming the silicon layer between the first insulator layer, and then patterning the silicon layer, the first insulator layer, and the second dielectric layer to form openings in the first insulator layer and the second semiconductor layer (e.g., to form a polysilicon layer with an insulator layer thereon, wherein openings are formed in the polysilicon layer and the insulator layer). In another example, in contrast to the above, the second semiconductor layer may be formed using screen printing, inkjet printing, or any other process for directly depositing a patterned silicon layer.

[0067] In a certain embodiment, the second dielectric layer is formed on the back side of the substrate (e.g., a silicon substrate). In one embodiment, the second dielectric layer is a thin oxide layer. In a certain embodiment, a second semiconductor layer such as a silicon layer may be deposited on the second dielectric layer. In one example, a low pressure chemical vapor deposition process may be used to deposit the silicon layer on the second dielectric layer. In a certain embodiment, the silicon layer is grown on the second dielectric layer in a thermal process and / or an oven. In one embodiment, the second dielectric layer and the silicon layer may be formed (e.g., grown) in the same or a single oven and / or in the same or a single process operation. In some embodiments, the second dielectric layer and the silicon layer may be formed on the back side, front side, and / or side of the substrate, wherein a subsequent patterning or cleaning process may be performed to remove the second dielectric layer and the second semiconductor layer from the front side and / or side of the substrate.

[0068] In a certain embodiment, forming the second semiconductor layer may include forming a silicon layer having a second conductivity type. In a certain example, forming the silicon layer may include growing a P-type silicon layer on top of a second dielectric layer (e.g., a thin oxide layer). In other embodiments, the silicon layer may be an N-type silicon layer. In a certain embodiment, the silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In a certain embodiment, the silicon layer may be polycrystalline silicon. In a certain embodiment, the silicon layer is grown on the second dielectric layer in a thermal process and / or oven. In one embodiment, the second dielectric layer and the silicon layer may be grown in the same or a single oven and / or in the same or a single process operation.

[0069] In another embodiment, the silicon layer may be formed undoped. In one such embodiment, a dopant layer may be formed on the silicon layer, and a thermal process may be performed to drive dopants from the dopant layer into the silicon layer, thereby producing a silicon layer having a second conductivity type (e.g., P-type or N-type). In a certain embodiment, forming the second semiconductor layer may include forming a first insulator layer on the silicon layer. In a certain embodiment, the first insulator layer may include silicon dioxide. In a certain example, a blanket deposition process may be performed to form the first insulator layer. In a certain embodiment, a first insulator layer having a thickness less than or equal to about 1000 angstroms may be formed.

[0070] In a certain embodiment, the first dielectric layer may be formed in an oxidation process and is a thin oxide layer such as a tunnel dielectric layer (e.g., silicon oxide). In one embodiment, the first dielectric layer may be formed in a deposition process. In a certain embodiment, the first dielectric layer is a thin oxide layer or a silicon oxynitride layer. In a certain embodiment, the first dielectric layer may have a thickness of about 2 nanometers or less. In a certain example, forming the first dielectric layer on a portion of the second semiconductor layer and a portion of the substrate may include forming the first dielectric layer on an exposed portion of the second semiconductor layer and an exposed portion of the substrate. In one example, the exposed area of ​​the second semiconductor layer and the substrate may be formed after performing a patterning process to pattern the first insulator layer, the second semiconductor layer, and the second dielectric layer. As used herein, the first dielectric layer may also be referred to as a first thin dielectric layer.

[0071] With regard to forming the first semiconductor layer, in certain embodiments, a silicon layer may be deposited on top of the first dielectric layer using a low pressure chemical vapor deposition process. In certain embodiments, the silicon layer may be polycrystalline silicon. In certain embodiments, the silicon layer is grown on the first dielectric layer in a thermal process and / or oven. In one embodiment, the first dielectric layer and the silicon layer may be grown in the same or a single oven and / or in the same or a single process operation. In certain embodiments, the silicon layer may be formed without doping. In certain embodiments, the silicon layer is an amorphous silicon layer. In one such embodiment, the amorphous silicon layer is formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0072] In another embodiment, forming the first semiconductor layer may include forming a silicon layer having a different conductivity type than the second semiconductor layer. In one such example, forming the silicon layer may include forming a pre-doped silicon layer. In one example, forming the silicon layer may include forming an N-type silicon layer on top of the first dielectric layer (e.g., a thin oxide layer). In an alternative embodiment, a P-type silicon layer is formed.

[0073] refer to Figure 8 At operation 804 of Flowchart 800 , the method of manufacturing a solar cell further includes forming a second insulator layer over the first semiconductor layer.

[0074] In a certain embodiment, forming a first semiconductor layer over the back side of the substrate includes forming the first semiconductor layer over the first dielectric layer. Forming the first semiconductor layer may include: forming a silicon layer over the first dielectric layer; forming a second insulator layer over the silicon layer; patterning the silicon layer, the second insulator layer, and the first dielectric layer; and possibly, subsequently performing a thermal process to drive dopants from the second insulator layer into the silicon layer to form the first semiconductor layer. For example, in a certain embodiment, as described herein, the second insulator layer may include a dopant layer, wherein patterning the silicon layer, the second insulator layer, and the first dielectric layer may include patterning the first silicon layer, the dopant layer, and the first dielectric layer. In another example, in contrast to the above, the first semiconductor layer may be formed using screen printing, inkjet printing, or any other process for directly depositing a patterned silicon layer.

[0075] In an embodiment in which the second insulator layer may include a dopant layer, forming the first semiconductor layer may include performing a thermal process to drive dopants from the dopant layer into the silicon layer. In an embodiment, the conductivity type of the dopant is N-type, for example, the dopant is a phosphorus and / or arsenic dopant. In an example, the thermal process may include heating to a temperature of approximately greater than or equal to 900 degrees Celsius to drive dopants from the dopant layer into the first silicon layer. In some embodiments, the operation of patterning the first semiconductor layer may be performed after performing the thermal process. In some embodiments, for example, where the silicon layer is pre-doped or formed to include an N-type or P-type conductivity type, in this case, it may not be necessary to perform a thermal process.

[0076] refer to Figure 8 At operation 806 of flowchart 800, the method of manufacturing a solar cell further includes forming an opening in the second insulator layer, the opening being above the second portion of the first semiconductor layer. The second opening is formed in the first insulator layer.

[0077] In a certain embodiment, the first insulator layer, the second semiconductor layer, and the second dielectric layer may be patterned to form openings therein. In a certain embodiment, the first semiconductor layer may have a second insulator layer formed on the second semiconductor layer. In a certain embodiment, an opening may be formed in the second insulator layer during a patterning process for forming the second opening in the first insulator layer. In a certain embodiment, a photolithography or screen printing mask and a subsequent etching process may be used to pattern the first insulator layer and the second insulator layer and possibly pattern the second semiconductor layer. In another embodiment, a laser ablation process (e.g., direct writing) may be used to pattern the first insulator layer and the second insulator layer and possibly pattern the second semiconductor layer.

[0078] In a certain embodiment, a mask and an etching process may be used to form contact openings. In a certain example, a mask may be formed, and a subsequent wet chemical etching process may be performed to form the contact openings. In some embodiments, a wet chemical cleaning process may be performed to remove the mask. In one embodiment, patterning may include performing a laser patterning process (e.g., laser ablation) to form contact openings in the first insulator layer and the second insulator layer. In one embodiment, the patterning process for forming contact openings in the first insulator layer and the second insulator layer may be performed in the same or a single operation (e.g., using a laser in the same or a single laser processing chamber), or may alternatively be performed separately (e.g., a separate laser patterning process may be used to form contact openings in the first insulator layer and the second insulator layer). In a certain embodiment, where the second insulator layer may include a dopant layer, patterning may include performing an operation of patterning the first insulator layer and the dopant layer in a single operation or separately to form contact openings through the first insulator layer and the dopant layer.

[0079] refer to Figure 8 At operation 808 of flowchart 800, the method of manufacturing a solar cell also includes forming a first conductive contact in the opening of the second insulator layer, the first conductive contact electrically coupled to the second portion of the first semiconductor layer at a location below the opening of the second insulator layer. In one embodiment, the first conductive contact is further on a portion of the second insulator layer above the first insulator layer, and the first conductive contact is further on a portion of the second insulator layer above the first portion of the first semiconductor layer.

[0080] refer to Figure 8 At operation 810 of Flowchart 800 , the method of manufacturing a solar cell further includes forming a second conductive contact in the second opening of the first insulator layer, the second conductive contact electrically coupled to the second semiconductor layer at a location below the second opening of the first insulator layer.

[0081] In a certain embodiment, forming a conductive contact structure may include performing a sputtering process, locally depositing a metal, a blanket deposition process, a plating process, bonding a metal foil and / or a bonding wire to a first semiconductor layer and a second semiconductor layer. In a certain example, the conductive contact structure may include locally deposited aluminum, aluminum foil, and / or aluminum wire. In a certain embodiment, the conductive contact structure may include one or more metals and / or metal alloys. In a certain example, the conductive contact structure may include aluminum, titanium tungsten, and / or copper, among other metals. In a certain embodiment, the conductive contact structure may include one, two, or more metal layers. In a certain example, the conductive contact structure may include a metal seed layer. In a certain embodiment, the metal seed layer may include a first layer, a second layer, and a third layer, wherein the first layer includes copper, the second layer includes tungsten, and the third layer includes aluminum.

[0082] In a certain embodiment, the first conductive contact and the second conductive contact may be electrically connected to the first semiconductor layer and the second semiconductor layer (e.g., the first polysilicon layer and the second polysilicon layer) using a hot pressing process. In a certain example, one or more wires may be adhered to the first semiconductor layer and the second semiconductor layer using a hot pressing process. In one embodiment, a metal foil may be bonded (e.g., welded) to the first semiconductor layer and the second semiconductor layer. In a certain embodiment, forming the first conductive contact and the second conductive contact may include performing a blanket deposition process. In a certain example, forming the first conductive contact and the second conductive contact may include performing an electroplating process. In some examples, forming the first conductive contact and the second conductive contact may include performing a blanket deposition process to form a metal seed layer, followed by plating metal and performing a patterning process to form the first conductive contact and the second conductive contact. In a certain example, forming the first conductive contact and the second conductive contact using a plating process may include placing the substrate in a bath to plate the metal to the substrate and forming the first conductive contact and the second conductive contact. In another embodiment, a local metal deposition process may be used to form the first conductive contact and the second conductive contact in one process operation.

[0083] It should be understood that as used throughout the text, similar reference numerals refer to similar elements in all drawings. In certain embodiments, the description of the first semiconductor layer 112, the first conductive contact 129, and / or the first insulator layer 112 of FIG. 2 may also be applicable to or describe Figure 1 The first semiconductor layer 112, the first conductive contact 129 and / or the first insulator layer 112. In one example, the entire Figure 1 , Figure 2A , Figure 2B , Figure 3 and Figure 4-7 middle, Figure 1 , Figure 2A , Figure 2B , Figure 3 and Figure 4-7 Similar reference numerals in the drawings may refer to similar elements. It should also be understood that although certain materials are specifically described with reference to the above-mentioned embodiments, in such embodiments, other materials may be easily replaced with some of the materials, and these embodiments are still within the spirit and scope of the embodiments of the present disclosure. For example, in a certain embodiment, a substrate of a different material, such as a substrate of a III-V material, may be used instead of a silicon substrate. In addition, although the back contact solar cell arrangement is mainly mentioned, it should be understood that the methods described herein can also be applied to front contact electrode solar cells. In addition, it is to be understood that in the case of specific descriptions of N+ type and P+ type doping, other embodiments envisioned include respectively opposite conductivity types, for example, P+ type and N+ type doping.

[0084] Now go to Fig. 9 , Fig. 9 A cross-sectional view of a portion of a solar cell is shown for comparison purposes. Fig. 9 , the solar cell 900 includes a substrate 906, a first semiconductor layer 912, and a second semiconductor layer 908. A first dielectric layer 920 is between the substrate 906 and the first semiconductor layer 912. A second dielectric layer 914 is between the substrate 906 and the second semiconductor layer 908. A third dielectric layer 916 is between the first semiconductor layer 912 and the second semiconductor layer 908. The first dielectric layer 910 has an opening 921 with a conductive contact 928 in the opening 921. The second dielectric layer 925 has an opening 923 with a conductive contact 929 in the opening 923. Unlike the above-described embodiments, the conductive contact 929 is formed in the opening 923 within or inside the emitter region of the solar cell 900. That is, the contact 929 is aligned with the associated emitter structure. This arrangement is susceptible to damage by metal spikes and / or laser contacts (e.g., the latter is used in a laser ablation process to form the contact opening, where the contact opening is within the periphery of the emitter region).

[0085] In contrast, for solar cell 900, the embodiments described herein may be less susceptible to metal spikes and / or laser contact damage, particularly where the laser scribe overlaps or at least partially overlaps the underlying emitter region. Advantages of implementing the embodiments described herein may include, but are not necessarily limited to or constrained by, the following: (1) resistance to metal spike formation; (2) laser contact elimination of one type of emitter structure; (3) the ability to achieve many different emitter coverages, for example, very small floating contact coverage with a larger emitter perimeter; and / or (4) applicability to a variety of types of metallization, such as plating, line metallization, or laser-assisted metallization processes. Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. Unless otherwise stated, the examples of features provided in the present disclosure are intended to be illustrative and not limiting. The above description is intended to cover those alternatives, modifications, and equivalents that will be apparent to those skilled in the art that have the benefits of the present disclosure.

[0086] The scope of the present disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made for any such combination of features during the examination process of the present application (or an application claiming priority thereto). In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims, and features from corresponding independent claims may be combined in any appropriate manner, and not just in the specific forms enumerated in the appended claims.

Claims

1. A solar cell comprising: a first emitter region over a substrate, the first emitter region having a perimeter surrounding a portion of the substrate; a first conductive contact electrically coupled to the first emitter region through an opening in a first insulator layer only at a location outside the perimeter of the first emitter region, the first conductive contact having a portion extending vertically above the first emitter region, wherein the portion of the first emitter region at the location outside the perimeter of the first emitter region is not in direct physical contact with the substrate; as well as A second insulator layer above the substrate, wherein a second portion of the first emitter region is within one or more openings in the second insulator layer and along an upper surface of the second insulator layer, and wherein the second portion of the first emitter region is in contact with sidewalls of the one or more openings of the second insulator layer and in contact with the upper surface of the second insulator layer.

2. The solar cell according to claim 1, further comprising: A first semiconductor layer is provided over the substrate, wherein the first emitter region is in a first portion of the first semiconductor layer and a location outside the perimeter of the first emitter region is on a second portion of the first semiconductor layer.

3. The solar cell according to claim 2, wherein the first portion of the first semiconductor layer is continuous with the second portion of the first semiconductor layer.

4. The solar cell according to claim 2, further comprising: A second semiconductor layer is between the first insulator layer and the substrate, the second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer, and the second semiconductor layer is included in a second emitter region of the solar cell.

5. The solar cell according to claim 4, wherein the first insulator layer has a second opening, the solar cell further comprising: A second conductive contact is electrically coupled to the second semiconductor layer at a location below the second opening of the first insulator layer.

6. The solar cell according to claim 2, wherein the first semiconductor layer comprises polycrystalline silicon, and the substrate comprises single crystal silicon.

7. The solar cell according to claim 6, further comprising: A dielectric layer is between the first semiconductor layer and the substrate.

8. A solar cell comprising: a first insulator layer over the substrate, the first insulator layer having a first opening and a second opening; a first semiconductor layer over the substrate, wherein a first portion of the first semiconductor layer is in the first opening of the first insulator layer and a second portion of the first semiconductor layer is over a portion of the first insulator layer; a second semiconductor layer over the substrate, the second semiconductor layer being between the first insulator layer and the substrate, the second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; a second insulator layer over the first semiconductor layer, the second insulator layer having an opening over a second portion of the first semiconductor layer; a first conductive contact in the opening of the second insulator layer, the first conductive contact electrically coupled to a second portion of the first semiconductor layer at a location below the opening of the second insulator layer; as well as a second conductive contact in the second opening of the first insulator layer, the second conductive contact being electrically coupled to the second semiconductor layer at a location below the second opening of the first insulator layer, The second portion of the first semiconductor layer contacts a sidewall of the opening of the first insulator layer and contacts an upper surface of the first insulator layer.

9. The solar cell according to claim 8, wherein the first portion of the first semiconductor layer is continuous with the second portion of the first semiconductor layer.

10. The solar cell according to claim 8, wherein the first semiconductor layer comprises polycrystalline silicon, and the substrate comprises single crystal silicon.

11. The solar cell according to claim 10, further comprising: A dielectric layer is between the first semiconductor layer and the substrate.

12. The solar cell of claim 8, wherein the first conductive contact is further on a portion of the second insulator layer over the first insulator layer, and the first conductive contact is further on a portion of the second insulator layer over the first portion of the first semiconductor layer.

13. A method for manufacturing a solar cell, the method comprising: forming a first insulator layer, a first semiconductor layer, and a second semiconductor layer over a substrate, the first insulator layer having a first opening, wherein a first portion of the first semiconductor layer is in the first opening of the first insulator layer, and a second portion of the first semiconductor layer is over a portion of the first insulator layer, and wherein the second semiconductor layer is between the first insulator layer and the substrate, and the second semiconductor layer has a conductivity type opposite to that of the first semiconductor layer; forming a second insulator layer over the first semiconductor layer; forming an opening in the second insulator layer, the opening being over a second portion of the first semiconductor layer, and forming a second opening in the first insulator layer; forming a first conductive contact in the opening of the second insulator layer, the first conductive contact being electrically coupled to a second portion of the first semiconductor layer at a position below the opening of the second insulator layer; and wherein the second portion of the first semiconductor layer is in contact with a sidewall of the opening of the first insulator layer and in contact with an upper surface of the first insulator layer; as well as A second conductive contact is formed in the second opening of the first insulator layer, the second conductive contact being electrically coupled to the second semiconductor layer at a location below the second opening of the first insulator layer.

14. The method of claim 13, wherein forming the first semiconductor layer comprises forming a first portion of the first semiconductor layer continuous with a second portion of the first semiconductor layer.

15. The method according to claim 13, wherein forming the first semiconductor layer comprises forming polycrystalline silicon over a single crystal silicon substrate.

16. The method according to claim 15, further comprising: A dielectric layer is formed between the first semiconductor layer and the substrate.

17. The method of claim 13, wherein forming the first conductive contact comprises further forming the first conductive contact on a portion of the second insulator layer over the first insulator layer and on a portion of the second insulator layer over the first portion of the first semiconductor layer.

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