Methods of manufacturing radio frequency devices, radio frequency modules, and wireless devices

Abstract

The present disclosure provides a method of manufacturing a radio frequency device, a method of manufacturing a radio frequency module, and a method of manufacturing a wireless device. The method of manufacturing a radio frequency device includes providing a silicon die including a radio frequency circuit, a first side and a second side, and a plurality of vias each configured to provide an electrical connection between the first side and the second side of the silicon die; and mounting a filter device on the first side of the silicon die, the filter device in communication with the radio frequency circuit, the radio frequency circuit implemented in an active layer of the first side of the silicon die, and at least some of the vias coupled with the radio frequency circuit to support an electrical connection between the radio frequency circuit and a mounting feature on the second side of the silicon die, the radio frequency circuit of the silicon die including a switch circuit.

Description

[0001] This application is a divisional application of the invention patent application filed on June 30, 2016, with application number 201610512396.7 and entitled "Apparatus and Method Related to Radio Frequency Filters on Silicon-on-Insulator Substrate". Technical Field

[0002] Among other things, this disclosure also relates to radio frequency (RF) filters on silicon-on-insulator (SOI) substrates. More specifically, this disclosure relates to methods of manufacturing RF devices, methods of manufacturing RF modules, and methods of manufacturing wireless devices. Background Technology

[0003] In some radio frequency (RF) applications, signals received or transmitted via an antenna can be routed to different amplification paths using band-selective switches and corresponding filters. In such applications, minimizing or reducing signal degradation is desirable. Summary of the Invention

[0004] According to various implementations, this disclosure relates to a radio frequency (RF) device comprising: a silicon die including a first side and a second side and a plurality of through-holes, each through-hole being configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device further includes at least one RF flip chip mounted on the first side of the silicon die.

[0005] In some embodiments, the second side of the silicon die can be configured to be mounted in a flip-chip manner. The second side of the silicon die may include a plurality of bump solders, at least some of which are electrically connected to corresponding vias in a plurality of vias.

[0006] In some embodiments, the silicon die may include a silicon-on-insulator (SOI) substrate. The SOI substrate may include an insulating layer disposed between an active silicon layer and a substrate layer.

[0007] In some embodiments, the silicon die may include RF circuitry communicating with the RF flip chip. The RF circuitry may include switching circuitry. The RF circuitry may also include logic circuitry for the switching circuitry. The RF circuitry may also include passive components. Passive components may include one or more of capacitors, inductors, and resistors.

[0008] In some embodiments, the RF circuit may further include one or more of a low-noise amplifier (LNA) circuit and a power amplifier (PA) circuit.

[0009] In some embodiments, the RF circuitry may include band selection circuitry configured to route received RF signals to a selected low-noise amplifier (LNA). In some embodiments, the received RF signals may be routed through a filter preceding the selected LNA, the filter being implemented in an RF flip chip. In some embodiments, the received RF signals may be routed through a filter following the selected LNA, the filter being implemented in an RF flip chip.

[0010] In some embodiments, the RF circuitry may be part of an LNA module. In some embodiments, the RF circuitry may be part of a diversity reception (RX) module.

[0011] In some embodiments, the RF circuitry may be implemented on or near a first side of the silicon die. At least some vias may be coupled to the RF circuitry to facilitate an electrical connection between the RF circuitry and a mounting feature on a second side of the silicon die.

[0012] In some embodiments, the RF circuitry may be implemented on or near the second side of the silicon die. At least some vias may be coupled to the RF circuitry to allow communication between the RF circuitry and the RF flip chip mounted on the second side of the silicon die.

[0013] In some embodiments, the RF flip chip may include an RF filter. The RF filter may be a surface acoustic wave (SAW) filter or a bulk acoustic wave (BAW) filter. The silicon die may include RF circuitry communicating with the SAW filter. The RF circuitry may include a low-noise amplifier (LNA).

[0014] Based on some teachings, this disclosure relates to a method for manufacturing a radio frequency (RF) device. The method includes forming or providing a silicon wafer including a first side and a second side. The silicon wafer also includes a plurality of through-holes, each configured to provide an electrical connection between the first side and the second side of the silicon wafer. The method further includes mounting a plurality of RF flip chips on the first side of the silicon wafer. The method also includes dicing the silicon wafer into a plurality of bare die units, each bare die unit including at least one RF flip chip mounted on the first side.

[0015] In some implementations, this disclosure relates to a radio frequency (RF) module including a packaging substrate configured to accommodate multiple components and a wafer-level chip-scale package (WLCSP) mounted on the packaging substrate. The WLCSP has a silicon die including a first side and a second side. The silicon die also includes multiple vias, each configured to provide an electrical connection between the first and second sides of the silicon die. The WLCSP also includes at least one RF flip chip mounted on the first side of the silicon die.

[0016] In some embodiments, the silicon die may include RF circuitry communicating with the RF flip chip. The WLCSP may have a lateral dimension smaller than 20% of the lateral area of ​​a package having a silicon die with similar RF circuitry and a similar number of RF flip chips mounted on a packaging substrate instead of the silicon die. The WLCSP may have a height smaller than the height of the package. The height of the WLCSP may be less than 2 / 3 of the height of the package, such that the total volume of the WLCSP is less than approximately 20% of the total volume of the package.

[0017] In some embodiments, the RF flip chip may include filter circuitry. The RF circuitry may include a low-noise amplifier (LNA). The RF module may be, for example, a GPS module, an LNA module, or a diversity receiver (RX) module.

[0018] According to various implementations, this disclosure relates to a wireless device including an antenna configured to receive RF signals and a receiver communicating with the antenna and configured to process the received RF signals. The wireless device also includes an RF module configured to route the received RF from the antenna to the receiver. The RF module includes a wafer-level chip-scale package (WLCSP) having a silicon die including a first side and a second side. The silicon die also includes a plurality of vias, each configured to provide an electrical connection between the first side and the second side of the silicon die. The WLCSP also includes at least one RF flip chip mounted on the first side of the silicon die.

[0019] In some teachings, this disclosure relates to an apparatus including a semiconductor die having a first side and a second side. The semiconductor die also includes a plurality of vias, each configured to provide an electrical connection between the first side and the second side of the semiconductor die. The semiconductor die also includes an active integrated circuit (IC). The apparatus further includes a flip-chip device mounted on the first side of the semiconductor die. The flip-chip device includes signal conditioning circuitry.

[0020] In some embodiments, the signal conditioning circuit may be a passive circuit. In some embodiments, the signal conditioning circuit may be a filter circuit.

[0021] According to various implementations, this disclosure relates to a method of manufacturing a radio frequency (RF) device, comprising: providing a silicon die including RF circuitry, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the silicon die; and mounting a filter device on the first side of the silicon die, the filter device communicating with the RF circuitry, the RF circuitry being implemented in an active layer on the first side of the silicon die, and at least some of the vias being coupled to the RF circuitry to support an electrical connection between the RF circuitry and a mounting feature on the second side of the silicon die, the RF circuitry of the silicon die including a switching circuit.

[0022] According to various implementations, this disclosure relates to a method of manufacturing a radio frequency (RF) module, comprising: providing a packaging substrate configured to accommodate a plurality of components; and mounting a wafer-level chip-scale package on the packaging substrate, the wafer-level chip-scale package having a silicon die including RF circuitry, a first side and a second side, and a plurality of vias, each via being configured to provide an electrical connection between the first side and the second side of the silicon die, the wafer-level chip-scale package further including at least one filter device mounted on the first side of the silicon die, the filter device communicating with the RF circuitry, the RF circuitry being implemented in an active layer on the first side of the silicon die, and at least some of the vias being coupled to the RF circuitry to support an electrical connection between the RF circuitry and mounting features on the second side of the silicon die, the RF circuitry of the silicon die including switching circuitry.

[0023] According to various implementations, this disclosure relates to a method of manufacturing a wireless device, comprising: providing an antenna configured to receive a radio frequency (RF) signal; providing a receiver communicating with the antenna and configured to process the received RF signal; and providing an RF module configured to route the received RF signal from the antenna to the receiver, the RF module comprising a wafer-level chip-scale package having a silicon die including RF circuitry, a first side and a second side, and a plurality of vias, each via being configured to provide an electrical connection between the first side and the second side of the silicon die, the wafer-level chip-scale package further comprising a filter device mounted on the first side of the silicon die, the filter device communicating with the RF circuitry implemented in an active layer on the first side of the silicon die, and at least some of the vias being coupled to the RF circuitry to support an electrical connection between the RF circuitry and a mounting feature on the second side of the silicon die, the RF circuitry of the silicon die including a switching circuit.

[0024] For the purposes of this disclosure, certain aspects, advantages, and novel features of the invention have been described herein. It will be understood that not all of these advantages can necessarily be achieved in any particular embodiment of the invention. Therefore, the invention may be practiced or implemented in a manner that achieves or optimizes one or more advantages taught herein, without necessarily achieving other advantages that may be taught or suggested herein. Attached Figure Description

[0025] Figure 1 A flip-chip device mounted on a semiconductor substrate is shown.

[0026] Figure 2 Examples are shown of a flip-chip device as a filter device such as a radio frequency (RF) filter, and a semiconductor substrate as a silicon-on-insulator (SOI) substrate.

[0027] Figure 3 It shows Figure 2 A more detailed example of a filter-SOI assembly.

[0028] Figure 4 It shows Figure 2 Another example of a more detailed SOI filter assembly.

[0029] Figure 5A and 5B An example process is shown that can be implemented to manufacture an apparatus having one or more of the features described herein.

[0030] Figure 6A and 6B It shows that it can be used as Figure 5A and 5B A more specific example implementation of the process to manufacture a filter device on an SOI substrate.

[0031] Figure 7 A band-selective switching circuit for a low-noise amplifier (LNA) is shown as an example of an RF application, wherein a filter configuration on the SOI as described herein can be implemented for the RF application.

[0032] Figure 8 As shown in some embodiments, having one or more filters on one side of the SOI bare die and a band-selective switching circuit configured to be mounted on the other side can provide several advantageous features.

[0033] Figure 9 An example of a diversity reception (RX) architecture in which one or more features as described herein can be implemented is shown.

[0034] Figure 10 It shows that it can be implemented for Figure 9 A more detailed example of the architecture's diversity RX module.

[0035] Figure 11 In some embodiments, it is shown that Figure 10 The diversity RX module can be implemented with some or all of the filters mounted on one side of a single SOI bare core and the other side configured to be mountable.

[0036] Figure 12 In some embodiments, it is shown that Figure 10 The diversity RX module can be implemented with filters mounted on some or all of multiple SOI bare cores.

[0037] Figure 13 An example of a clock recovery circuit configured to generate a timing signal from an input data signal is shown.

[0038] Figure 14 It shows Figure 11 Some or all of the clock recovery circuitry can be implemented by mounting one or more filters on one side of the semiconductor die and configuring the other side as a mountable configuration.

[0039] Figure 15 An example wireless device having one or more of the beneficial features described herein is illustrated schematically. Detailed Implementation

[0040] The headings provided herein (if any) are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

[0041] This document describes various examples of apparatus and methods relating to one or more flip-chip devices mounted on a semiconductor substrate. Such a configuration (100) in... Figure 1 As described in the text, the flip chip device 102 is shown mounted on a semiconductor substrate 104, for example, with bump solder 106. Figure 2 A more specific example configuration 100 is shown, in which a flip-chip device ( Figure 1 102 in the text can be a filter device 102 such as a radio frequency (RF) filter; and wherein the semiconductor substrate ( Figure 1 104 in the figure can be silicon-on-insulator (SOI) substrate 104.

[0042] Various examples are described herein in the context of filters and SOI substrates. However, it will be understood that one or more features of this disclosure may also be implemented using other types of flip-chip devices and / or semiconductor substrates. In some embodiments, semiconductor substrates such as complementary metal-oxide-semiconductor (CMOS) and silicon-germanium (SiGe) BiCMOS may also be used. In some embodiments, the semiconductor substrate may include gallium arsenide (GaAs) and other compound semiconductor substrates, such as GaAs heterojunction bipolar transistors (HBTs), BiHEMTs (e.g., integration of HBTs and pseudocrystalline high electron mobility transistors (pHEMTs), GaAs BiHEMTs, GaAspHEMTs, and gallium nitride (GaN). In some embodiments, other substrates may be used, including, for example, quartz, polymer materials, silicon carbide, sapphire, diamond, germanium, etc. In some embodiments, active electronic and / or semiconductor devices may be implemented on or in a substrate or a layer formed on such a substrate. In some embodiments (e.g., quartz), passive devices (e.g., capacitors, resistors, inductors, etc.) may be implemented on or in a substrate.

[0043] In the context of filters, flip-chip devices may include, for example, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, and thin-film bulk acoustic resonators (FBARs or TFBARs). For illustrative purposes, it will be understood that filters may include related devices such as duplexers. As described herein, filters such as those exemplified above are used, for example, to modulate RF signals to a desired position relative to related circuitry. Therefore, it will be understood that one or more features of this disclosure may also be implemented using one or more signal conditioning flip-chip devices mounted on a semiconductor substrate such as an SOI substrate, which may or may not include filters.

[0044] Figure 2In some embodiments, one or more filters 102 may be flip-chip mounted (e.g., with bump solder 106) on an SOI substrate 104. Such filters may be mounted on either the front or back side of the SOI substrate. Examples of both configurations will be described in more detail here. For illustrative purposes, the front side may be the side where one or more integrated circuits and / or passive components are formed or provided; and the back side may be the opposite side.

[0045] In some embodiments, the side of the SOI substrate 104 without the filter 102 can be configured to be flip-chip mounted to a circuit board, such as a telephone board. In the example shown, solder bumps 110 can be formed on the non-filter side to allow such flip-chip mounting. Conductive vias 108 can be formed through or partially through the SOI substrate 104 to provide electrical connections between at least some of the solder bumps 110 and one or more circuits that are part of the SOI substrate 104. Examples of such circuits will be described in more detail. Although various flip-chip mounting examples are described herein in the context of solder bumps, it will be understood that other mounting techniques can also be implemented. For example, copper pillars or gold bumps with anisotropic conductive epoxy resin can be used.

[0046] The device configured as described above allows the SOI substrate to include circuitry such as RF switches, low-noise amplifiers (LNAs), power amplifiers (PAs), and / or passive components (e.g., capacitors and inductors); and also has filters with flip-chip mounted thereon. Because the filters are stacked on the SOI substrate, several advantageous features can be achieved. For example, since some or all of the filters can be placed on the SOI substrate rather than next to it on a common surface, the total occupied area of ​​the SOI circuitry and the corresponding filters can be significantly reduced. Furthermore, the flip-chip mounting of the filters on the SOI substrate can significantly reduce the number of electrical connection features (e.g., metal traces), thereby minimizing or reducing signal loss between the SOI circuitry and the filters. In addition to the foregoing, other benefits may include, for example, reduced parasitic effects and improved performance.

[0047] exist Figure 2 In the example, the bump solder 110 and the corresponding conductive via 108 allow SOI circuitry and filters to be collectively configured and packaged as a flip-chip surface-mountable component. In some embodiments, the SOI substrate can be configured to be mounted in other ways, including surface mounting using wire bonding.

[0048] Figure 3 and 4It shows Figure 2 A more detailed example of the filter-SOI assembly 100. Figure 3 In example configuration 150, filter 102 is shown mounted on the front side of SOI substrate 104, where an active silicon layer 160 is provided on the front side, on which an integrated circuit (IC) 158 is formed. An insulating layer 162 is disposed between the active silicon layer 160 and the silicon substrate layer 164 to generally form an SOI structure.

[0049] exist Figure 3 In the example, the bump solder 106 is shown to provide mechanical mounting functionality and electrical connection between contact pads 152 (on filter 102) and 154 (on SOI substrate 104). Contact pad 152 can be electrically connected to the filtering circuitry of filter 102. Similarly, contact pad 154 can be electrically connected to IC 158 to electrically connect the filtering circuitry to IC 158.

[0050] IC 158 can also be electrically connected to conductor 156, which in turn is electrically connected to conductive via 108 through the substrate. On the back side of SOI substrate 104, via 108 is shown as electrically connected to contact pad 166. Bump solder 168 can allow SOI substrate 104 to be mounted to another layer 172, such as a circuit board or package substrate (via contact pad 170). Accordingly, via 108 can provide electrical connections between IC 158 and locations on layer 172, such as circuitry.

[0051] In some embodiments, it may be desirable to configure via 108 (e.g., a conductive through-wafer via (TWV)) to be electrically isolated from conductive portions of the substrate. For example, in the context of the aforementioned SOI substrate, conductive via 108 may pass through silicon substrate layer 164, which is typically a conductive substrate. Therefore, to electrically isolate one via from another, an insulator (e.g., a SiO2 pad) may be provided between via 108 and silicon substrate layer 164. Insulator layer 162 is an insulator, and active silicon layer 160 typically includes processing structures capable of isolating various structures; accordingly, electrical isolation of via 108 may be provided or facilitated by such features. In some embodiments, electrical isolation of via 108 may not be required.

[0052] exist Figure 3 In the example, the flip-chip mounting of filter 102 on the front side of SOI substrate 104 allows filter 102 to be close to IC 158 to produce the beneficial features described herein. In some cases, it may be desirable to place the filter (102) away from IC (158). For example, there may be isolation and / or mechanical design considerations that prefer to have filter (102) on the rear side (e.g., the side opposite the active silicon layer 160).

[0053] Figure 4 An example configuration 150 is shown where a filter 102 is mounted on the rear side of an SOI substrate 104, wherein an active silicon layer 160 is provided on the front side, on which an IC 158 is formed. An insulating layer 162 is disposed between the active silicon layer 160 and the silicon substrate layer 164 to generally form an SOI structure. The front side of the SOI substrate 104 is shown as another layer 172 mounted to, for example, a circuit board or package substrate (via contact pads 186, solder bumps 168, and contact pads 170). The contact pads 186 on the front side can be electrically connected to the IC 158, such that the aforementioned mounting via solder bumps 168 provides electrical connection between the IC 158 and the location on layer 172.

[0054] exist Figure 4 In the example, an example bump solder 106 is shown to provide mechanical mounting functionality and electrical connection between contact pad 152 of filter 102 and contact pad 180 on the rear side of SOI substrate 104. Contact pad 152 can be electrically connected to the filtering circuitry of filter 102. Similarly, contact pad 180 can be electrically connected to IC 158 via conductive via 182 and conductor 184 on the front side of SOI substrate 104, thereby electrically connecting the filtering circuitry to IC 158. In some embodiments, various conductor features such as via 182 can be configured to produce desired properties such as interconnect inductance to provide, for example, modulation of RF signals between various locations of the device.

[0055] Figure 5A and 5B The following are examples of methods to manufacture products with... Figure 1 Examples of the processes 200a and 200b for the device configuration 100. (See reference...) Figure 5A and 5B In both blocks 202a and 202b, a semiconductor substrate may be formed or provided. In both blocks 204a and 204b, integrated circuits (ICs) and / or passive components may be formed on the semiconductor substrate. In both blocks 206a and 206b, a plurality of first contact features may be formed on one side of the semiconductor substrate, wherein at least some of the first contact features are electrically connected to the IC. (Reference) Figure 5A In block 208a, the RF device can be flip-chip mounted on the first contact feature. Similarly, in... Figure 5A In block 210a, a plurality of second contact features may be formed on the other side of the semiconductor substrate, wherein at least some of the second contact features are electrically connected to the IC. (Reference) Figure 5BIn block 208b, a plurality of second contact features may be formed on the other side of the semiconductor substrate, wherein at least some of the second contact features are electrically connected to the IC, and in block 210b, an RF device may be flip-chip mounted on the first contact feature.

[0056] Figure 5A and 5B Each process also illustrates that a device manufactured in the aforementioned manner can be mounted on a circuit board, such as a telephone board. For example, in both blocks 212a and 212b, a semiconductor substrate can be flip-chip mounted on the circuit board.

[0057] Figure 6A and 6B It shows that they can be used as Figure 5A and 5B More specific examples of processes 200a and 200b are implemented to illustrate processes 220a and 220b for fabricating filter devices on multiple SOI substrates. (See references.) Figure 6A and 6B In both blocks 222a and 222b, an SOI wafer can be formed or provided. In both blocks 224a and 224b, multiple wafer-level chip-scale cells can be formed on the SOI wafer, each cell having one or more ICs and / or one or more passive components. In both blocks 226a and 22b6, multiple first contact pads can be formed on one side of the SOI wafer, wherein at least some of the first contact pads are electrically connected to their respective ICs. (Reference) Figure 6A In block 228a, one or more filter devices can be flip-chip mounted on a first contact pad, and in block 230a, a plurality of second contact pads can be formed on the other side of the SOI wafer, wherein at least some of the second contact pads are electrically connected to their respective ICs. Similarly, Figure 6A In box 232a, solder bumps can be formed on the second contact pad. (See reference) Figure 6B In block 228b, a plurality of second contact pads can be formed on the other side of the SOI wafer, wherein at least some of the second contact pads are electrically connected to their respective ICs, and in block 230b, solder bumps can be formed on the second contact pads. Similarly, Figure 5B In block 232b, one or more filter devices can be flip-chip mounted on the first contact pad. Figure 6B In the example, box 232b can also be executed before box 230b. Figure 6A and 6B In each of the blocks 234a and 234b, the SOI wafer can be divided into multiple wafer-level chip-scale package (WLCSP) units.

[0058] Figure 7-12 An example of an RF application that can implement the filter configuration on SOI as described here is shown. Figure 7 An example of a band selection switch circuit 300 for a low-noise amplifier (LNA) is shown. In this example, the pole of the first switch 320 is shown connected to an antenna port (ANT) for receiving RF signals. Four example throws of the first switch 320 are shown to allow the RF signal to be routed to four different paths, each of the first to third paths including its corresponding filter (102a, 102b, or 102c) and LNA (322a, 322b, or 322c), and the fourth path is a bypass path. Although not shown in the diagram... Figure 7 As shown, a filter can also be provided after the LNAs (322a, 322b, 322c). The four throws of the second switch 324 are shown to allow four different paths to be connected to the output port (RFOUT). The bias signals for the LNAs (322a, 322b, 322c) and the logic signals for the first and second switches (320, 324) are shown to be provided by the bias and logic circuitry 326. Control signals, power supply voltage, and ground are shown to be provided to the bias and logic circuitry 326 through various ports (e.g., DGND, VDD, C1, C2). Similarly, RF ground is shown to be facilitated by the RFGND port.

[0059] In some embodiments, a silicon die (e.g., an SOI die) having circuitry for first and second switches 320, 324, LNAs 322a, 322b, 322c, and bias and logic 326 (collective function depicted as dashed box 304) can be mounted on a package substrate in a wire-bonded or flip-chip configuration. Filters 102a, 102b, 102c (collective function depicted as dashed box 302) (and in some embodiments, filters following the LNAs (322a, 322b, 322c)) can also be mounted on the same package substrate. In this configuration, the total area of ​​the device (e.g., a module) having the band-selective switching circuitry 300 will include the area occupied by the circuitry, filters, and associated connectivity features.

[0060] As described here, and as Figure 8 As shown, a band-selective switching circuit 300 having one or more filters 102 on one side of the SOI bare die 104 and configured on the other side to be mountable (e.g., flip-chip mounting using bump solder 306) can provide many advantageous features, including a significant reduction in the total area of ​​the circuit 300. For example, if referenced Figure 7The aforementioned example configuration (where the filter is positioned next to the bare silicon die on the packaging substrate) occupies or requires a volume of approximately 3 mm (length) × 4 mm (width) × 0.9 mm (height), estimated to be... Figure 8 The same circuit implemented in this configuration can occupy or require a reduced volume of approximately 1.3 mm (length) × 1.5 mm (width) multiplied by a height of less than 0.6 mm. In terms of lateral area, the reduced area is approximately 16% of the 3 mm × 4 mm example. In some embodiments, this reduction in lateral area can be, for example, 20% or less, 16% or less, or 13% or less, compared to the lateral area associated with a configuration where the filter is positioned next to the silicon die on the package substrate. In terms of volume, the reduced volume is less than 11% of the 3 mm × 4 mm × 0.9 mm example. In some embodiments, this reduction in volume can be, for example, 20% or less, 15% or less, 13% or less, or 11% or less, compared to the volume associated with a configuration where the filter is positioned next to the silicon die on the package substrate.

[0061] exist Figure 7 In the example band selection switch circuit 300, the circuitry for first and second switches 320, 324, LNAs 322a, 322b, 322c, and bias and logic circuitry 326, implemented on a silicon die, is collectively depicted by block 304. Figure 8 In the example, some or all of such circuits with the same functionality (described as box 304) can be implemented on and / or in the SOI bare die 104. Figure 7 The functions of filters 102a, 102b, and 102c in the example are described by box 302. Figure 8 In the example, the same functionality can be achieved in one or more filters 102 mounted on the SOI bare core 104 (described as box 302).

[0062] Filters 102a, 102b, and 102c are installed in conjunction with... Figure 7 In the context of the same packaging substrate as the bare silicon die in the image, this packaging substrate can be represented by substrate 310. Filters 102a, 102b, and 102c are mounted on... Figure 8 In the context of the SOI bare die 104, the SOI bare die 104 itself can be used as a packaging substrate suitable for mounting onto a circuit board; and correspondingly, it can be provided by Figure 7 The substrate 310 represents the SOI bare core 104. Furthermore, in Figure 8 In the examples, such as reference Figure 7As described, the bump solder 306 can be electrically connected to various ports (e.g., ANT, RFOUT, RFGND, DGND, VDD, C1, C2) associated with the band selection switch circuit 300.

[0063] Figure 9 -12 shows another example in which one or more features of this disclosure can be implemented. Figure 9 An example receive (RX) architecture 350 associated with diversity antenna 352 is shown. This receive antenna is typically positioned relatively far from the main antenna; and both the main antenna and the diversity antenna can be active simultaneously to, for example, increase data throughput. Due to the relatively distant location of the diversity antenna, its signal is typically subjected to a lossy signal path (e.g., Figure 9 372) decay.

[0064] Therefore, and as Figure 9 As shown, diversity RX circuitry 360 (e.g., in a module) can be implemented close to diversity antenna 352 to add gain. Therefore, the RF signal received by diversity antenna 352 can be provided as input (via path 354) to diversity RX module 360. Diversity RX module 360 ​​can process the RF signal and provide a gained processed RF signal before the RF signal is routed to the transceiver via a lossy signal path 372. The transceiver may or may not include an LNA to further amplify the RF signal received from diversity RX module 360.

[0065] exist Figure 9 In the example, the LNA associated with the transceiver (if any) may be configured to include one or more features as described herein, or may not be configured to include them.

[0066] exist Figure 9 In the example, the diversity RX module 360 ​​may include an input switch 362 and an output switch 368 configured to provide band selection functionality for one or more LNAs 366. A filter 364 for various frequency bands associated with the diversity RX module 360 ​​may be provided between the input switch 362 and the LNA 366.

[0067] exist Figure 9 In the example diversity RX module 360, the circuitry associated with input switch 362, output switch 368, and LNA 366 is collectively depicted via block 370. As described herein, some or all of such circuitry can be implemented on and / or in one or more SOI bare dies. Also as described herein, some or all of filter 364 can be mounted on one or more such SOI bare dies.

[0068] Figure 10 It shows that it can be Figure 9A more specific example of the diversity RX module 360. Figure 10 In the example, the diversity RX module 360 ​​is depicted as being configured to process two sets of frequency bands, band 1 and band 2. For example, band 1 may include a high-frequency band (HB) and band 2 may include a mid-frequency band (MB). The filtering and / or duplexing functions associated with such frequency bands are shown as being provided by filters / duplexers 102a-102h, collectively indicated as 364. Tables 1 and 2 list examples of HB and MB frequency bands that can be implemented in the diversity RX module 360.

[0069] Table 1

[0070] Figure 10 Filters / duplexers in frequency band 102a B7 102b B40 102c B41 102d B30

[0071] Table 2

[0072] Figure 10 Filters / duplexers in frequency band 102e B1 102f B25 102g B3 102g B4

[0073] It will be understood that the diversity RX module 360 ​​can be configured to process other frequency bands. It will also be understood that the diversity RX module 360 ​​can also have more or fewer frequency bands (e.g., more than two or fewer).

[0074] exist Figure 10 In the example, the routing of signals associated with filters / duplexers 102a-102d for band 1 can be facilitated by switches 380 and 382, ​​respectively, before and after filters / duplexers 102a-102d, and by switch 384, after the first LNA 388. Switch 380 can be configured to provide, for example, a single-pole four-throw (SP4T) function, which receives RF signals from the band 1 antenna. The four-throw can allow the RF signal to be routed to one of the filters / duplexers 102a-102d. Similarly, switch 382 can be configured to provide, for example, a single-pole four-throw (SP4T) function, which is coupled to the first LNA 388 via a corresponding matching network 386. The four-throw of switch 382 can operate together with switch 380 to receive RF signals from one of the filters / duplexers 102a-102d in order to route the filtered signal to the first LNA 388. The output of the first LNA 388 can be routed to one or more output paths. The example shows three output paths, one of which can be selected by, for example, configuring switch 384 as an SP3T switch.

[0075] Similarly, the routing of signals associated with the filters / duplexers 102e-102h for band 2 can be facilitated by switches 381 and 383 before and after the filters / duplexers 102e-102h, and switch 385 after the second LNA 389, respectively. Switch 381 can be configured to provide, for example, a single-pole 5-throw (SP5T) function, which receives RF signals from the band 2 antenna. The fourth throw of the five throws can allow RF signals to be routed to one of the filters / duplexers 102e-102h, and the fifth throw can be used to provide a bypass path 390. Switch 383 can be configured to provide, for example, an SP4T function, which is coupled to the second LNA 389 via a corresponding matching network 387. The fourth throw of switch 383 can operate together with switch 381 to receive RF signals from one of the filters / duplexers 102e-102h, so as to route the filtered signal to the second LNA 389. The output of the second LNA 389 can be routed to one or more output paths. In the example, three output paths are shown, and selection of one of these paths can be facilitated, for example, by configuring switch 385 as an SP3T switch.

[0076] exist Figure 10 In the examples, each of the example switches 382 and 384 associated with band 1 is depicted as having a single pole and multiple throws. Similarly, each of the example switches 383 and 385 associated with band 2 is depicted as having a single pole and multiple throws. It will be understood that some or all of such circuitry may include more than one pole. For example, switches 382 and 383, individually or in any combination, may include multiple poles coupled to the inputs of different LNAs. In another example, switches 384 and 385, individually or in any combination, may include multiple poles that allow the LNA output to be routed to the outputs of one or more modules.

[0077] The aforementioned switching configuration provides flexibility to the RX architecture. For example, instead of implementing one LNA for multiple frequency bands, multiple LNAs can be implemented using the aforementioned switching configuration. Using such LNAs can reduce the frequency coverage of each LNA, thereby improving performance.

[0078] Figure 10 The diversity RX module 360 ​​is an example of how one or more features of this disclosure can be implemented in various modules. It will be understood that one or more features of this disclosure can also be implemented in other types of modules. For example, a power amplifier (PA) module can benefit from one or more features described herein. Such a PA module can have... Figure 10The example uses a similar architecture, but with the scaled-up direction reversed, thus replacing the LNA function with a PA function. In another example, any module utilizing, for example, SOI switches, passive components, and resonators (e.g., SAW resonators) can benefit from one or more features of this disclosure. In such a module, configurations in which any type of filter or resonator is stacked relative to SOI switches, LNAs, PAs, or any circuit blocks (e.g., on top of them) can be implemented.

[0079] exist Figure 10 In the example, the circuitry associated with switches 380, 381, 382, ​​383, 384, 385, LNAs 388, 389, and matching networks 386, 387 collectively communicates with... Figure 9 Box 370 and similar boxes 370 are used to depict this. As described herein, some or all of such circuitry can be implemented on and / or in one or more SOI dies. For example, some or all of such circuitry can be implemented on a single SOI die 104, such as... Figure 11 As in the example. In another example, some or all of the circuitry before the filter / duplexer 364 can be implemented on the first SOI bare die 104a, and some or all of the circuitry after the filter / duplexer 364 can be implemented on the second SOI bare die 104b, as shown. Figure 12 As in the example.

[0080] As also described herein, some or all of the filters / duplexers 364 can be mounted on one or more such SOI bare dies. For example, if substantially all the circuitry associated with block 370 is implemented on and / or in a single SOI bare die, then all eight filters / duplexers 102a-102h can be mounted on such a single SOI bare die. In another example, if the circuitry associated with block 370 is implemented on and / or in first and second SOI bare dies, then the eight filters / duplexers 102a-102h can be mounted on the first SOI bare die, the second SOI bare die, or both.

[0081] Figure 11 It shows Figure 10 An example of the diversity RX module 360, where it is related to box 370 ( Figure 10 The associated circuitry can be implemented on and / or within a single silicon die, such as a single SOI die 104. Figure 11 In this diagram, such circuits are also collectively depicted through box 370. Figure 10 The functionality of the filters / duplexers 102a-102h in the examples is depicted via box 364. Figure 11 In the example, the same functionality (described as box 364) can be implemented in multiple filters / duplexers 102 mounted on a single SOI bare core 104.

[0082] Figure 12 It shows Figure 10 An example of the diversity RX module 360, where it is related to box 370 ( Figure 10 The associated circuitry can be implemented on and / or within multiple silicon dies, such as multiple SOI dies 104a, 104b. Figure 12 In the diagram, such circuits are also collectively depicted through boxes 370a and 370b. Figure 10 The functionality of the filters / duplexers 102a-102h in the examples is depicted via box 364. Figure 12 In the example, the same functionality (described as boxes 364a, 364b) can be implemented in multiple filters / duplexers 102 mounted on the corresponding SOI bare core 104.

[0083] Figure 13 and 14 Another example is shown in which one or more features of this disclosure can be implemented. Figure 13 A diagram shows an example clock recovery circuit 500 configured to generate a timing signal (at node 520) from a data signal input (at node 510). To achieve this functionality, an integrated circuit (IC) 504, including an edge detector 512, a mixer 514, and a voltage-controlled oscillator (VCO) 518, can be configured together with a filter circuit 502, including a low-pass filter (LPF) 516, as shown.

[0084] Figure 14 This is illustrated in a configuration where one or more filters 102 are mounted on one side of a semiconductor die 104 (e.g., a BiCMOS die) and the other side is configured to be mountable (e.g., flip-chip mounting using solder bumps). Figure 13 Some or all of the clock recovery circuitry 500. As described here, Figure 14 This configuration can provide many advantageous features, including a significant reduction in the total area of ​​the circuit 500.

[0085] exist Figure 14 In the example clock recovery circuit 500, some or all of IC 504 can be implemented on semiconductor die 104. Some or all of filter circuit 502 can be implemented in one or more of the filters 102 mounted on semiconductor die 104.

[0086] In the various examples described herein, passive components may include, for example, resistive elements of a resistor, capacitive elements of a capacitor, inductive elements of an inductor, or any combination thereof.

[0087] It will be understood that one or more features of this disclosure may also be implemented in other types of RF circuits.

[0088] In some implementation methods, see here for reference. Figure 7-14 The various examples described can be viewed as compact assemblies of signal conditioning components and circuitry that are impractical and / or undesirable for complete integration on a single process technology platform. As described herein, such compact assemblies can provide benefits associated with placing one or more signal conditioning components (e.g., filters) in close proximity to one or more circuits (e.g., active circuitry). These benefits can include, for example, minimizing signal loss between said circuitry and the one or more signal conditioning components.

[0089] In some implementations, means and / or circuitry having one or more of the features described herein may be included in an RF device, such as a wireless device. Such means and / or circuitry may be implemented directly in the wireless device, in a modular form as described herein, or in some combination thereof. In some embodiments, such a wireless device may include, for example, a base station configured to provide wireless services, a cellular phone, a smartphone, a handheld wireless device with or without telephone functionality, a wireless tablet, etc.

[0090] Figure 15 An example wireless device 400 having one or more of the advantageous features described herein is schematically depicted. In the context of the various configurations described herein, a front-end module having the functions depicted as 300 may be part of the wireless device. In some embodiments, such a front-end module may or may not include power amplifier (PA) circuitry 418, LNA 322, and / or bias / logic circuitry 326. Figure 7 and 8 In the context of example configuration 300, components such as switching circuitry associated with band selection switch 320 and filters associated with duplexer circuitry 420 can be implemented in the front-end module. In some embodiments, wireless device 400 may include a diversity RX module having one or more features as described herein.

[0091] In the example wireless device 400, a PA circuit 418 having multiple PAs can provide an amplified RF signal to a switch 320 (via a duplexer 420), and the switch 320 can route the amplified RF signal to an antenna 424. The PA circuit 418 can receive unamplified RF signals from a transceiver 414, which can be configured and operated in a known manner.

[0092] Transceiver 414 can also be configured to process received signals. Such received signals can be routed from antenna 424 to LNA 322 via duplexer 420. Various operations of LNA 322 can be facilitated by bias / logic circuitry 326.

[0093] Transceiver 414 is shown interacting with baseband subsystem 410, which is configured to provide conversion between data and / or voice signals suitable for a user and RF signals suitable for transceiver 414. Transceiver 414 is also shown connected to power management component 406, which is configured to manage power for the operation of wireless device 400. Such power management component can also control the operation of baseband subsystem 410 and front-end modules.

[0094] The baseband subsystem 410 is shown connected to the user interface 402 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. The baseband subsystem 410 may also be connected to a memory 404 configured to store data and / or instructions to facilitate the operation of the wireless device and / or to provide information storage for the user.

[0095] Several other wireless device configurations may utilize one or more of the features described herein. For example, the wireless device does not need to be a multi-band device. In another example, the wireless device may include additional antennas such as diversity antennas, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS.

[0096] One or more features of this disclosure can be implemented using various cellular frequency bands as described herein. Examples of such frequency bands are listed in Table 3. It will be understood that at least some of these frequency bands can be divided into sub-bands. It will also be understood that one or more features of this disclosure can be implemented in frequency ranges that do not have the markings shown in the examples in Table 3.

[0097] Table 3

[0098]

[0099]

[0100] Unless the context clearly requires otherwise, throughout the specification and claims, the terms “comprising” and “including” should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of “including, but not limited to”. As is commonly used herein, the term “coupled” refers to two or more elements that can be directly connected or connected via one or more intermediate elements. Furthermore, when used in this application, the terms “here,” “above,” “below,” and similar terms should refer to the entire application, not any particular part of it. When the context permits, the use of singular or plural terms in the above detailed description may also include both singular and plural terms, respectively. The term “or” when referring to a list of two or more items covers all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0101] The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed above. As those skilled in the art will understand, while specific embodiments and examples of the invention have been described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention. For example, although processes or blocks are presented in a given order, alternative embodiments may execute routines with steps in a different order, or employ systems with blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks can be implemented in a variety of different ways. Furthermore, although processes or blocks are sometimes shown as being executed serially, alternatively, these processes or blocks may be executed in parallel, or may be executed at different times.

[0102] The teachings of the present invention provided herein can be applied to other systems, not just those described above. Elements and actions of the various embodiments described above can be combined to provide further embodiments.

[0103] While certain embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel methods and systems described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes in form of the methods and systems described herein can be made without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A method for manufacturing a radio frequency device, comprising: A silicon die is provided, the silicon die including radio frequency circuitry, a first side and a second side, and a plurality of vias, each via being configured to provide an electrical connection between the first side and the second side of the silicon die, the silicon die including a silicon-on-insulator substrate, the silicon-on-insulator substrate including an insulating layer disposed between an active silicon layer and a silicon substrate layer; as well as A filter device is mounted on a first side of the silicon die, the filter device communicating with the radio frequency (RF) circuit implemented in the active silicon layer on the first side of the silicon die, and at least some of the vias are coupled to the RF circuit to support an electrical connection between the RF circuit and a mounting feature on a second side of the silicon die, the RF circuit of the silicon die including a switching circuit.

2. The method as described in claim 1, wherein, The second side of the bare silicon die is configured to be mounted in a flip-chip manner.

3. The method as described in claim 2, wherein, The second side of the silicon bare die includes a plurality of bump solders, at least some of which are electrically connected to corresponding vias in the plurality of vias.

4. The method of claim 1, wherein, The radio frequency circuit also includes logic circuitry for the switching circuit.

5. The method of claim 4, wherein, The radio frequency circuit also includes one or more of a low-noise amplifier circuit and a power amplifier circuit.

6. The method of claim 4, wherein, The radio frequency circuit includes a band selection circuit configured to route received radio frequency signals to a selected low-noise amplifier.

7. The method of claim 6, wherein, The received radio frequency signal is routed through the filter device preceding the selected low-noise amplifier.

8. The method of claim 6, wherein, The received radio frequency signal is routed through the filter device following the selected low-noise amplifier.

9. The method of claim 6, wherein, The radio frequency circuit is part of the diversity receiver module.

10. The method of claim 1, wherein, The filter device is an acoustic filter.

11. A method for manufacturing an RF module, comprising: A packaging substrate is provided, the packaging substrate being configured to accommodate a plurality of components; as well as A wafer-level chip-scale package is mounted on the packaging substrate. The wafer-level chip-scale package has a silicon die including radio frequency (RF) circuitry, a first side and a second side, and a plurality of vias. Each via is configured to provide an electrical connection between the first side and the second side of the silicon die. The silicon die includes a silicon-on-insulator (SiI) substrate, which includes an insulating layer disposed between an active silicon layer and a silicon substrate layer. The wafer-level chip-scale package further includes at least one filter device mounted on the first side of the silicon die. The filter device communicates with the RF circuitry, which is implemented in the active layer of the first side of the silicon die. At least some of the vias are coupled to the RF circuitry to support an electrical connection between the RF circuitry and a mounting feature on the second side of the silicon die. The RF circuitry of the silicon die includes a switching circuit.

12. The method of claim 11, wherein, The wafer-level chip-scale package has a side dimension that is less than 20% of the side area of ​​a package having a silicon die with similar RF circuitry and a similar number of filter devices mounted on a package substrate instead of the silicon die.

13. The method of claim 12, wherein, The wafer-level chip-scale package has a height smaller than the height of the package.

14. The method of claim 11, wherein, The filter device is an acoustic filter.

15. The method of claim 11, wherein, The radio frequency module is a diversity receiver module.

16. A method of manufacturing a wireless device, comprising: An antenna is provided, which is configured to receive radio frequency signals; A receiver is provided, which communicates with the antenna and is configured to process the received radio frequency signals; as well as A radio frequency (RF) module is provided, configured to route received RF signals from an antenna to a receiver. The RF module includes a wafer-level chip-scale package having a silicon die comprising RF circuitry, a first side, a second side, and a plurality of vias. Each via is configured to provide an electrical connection between the first and second sides of the silicon die. The silicon die includes a silicon-on-insulator (SiI) substrate, which includes an insulating layer disposed between an active silicon layer and a silicon substrate layer. The wafer-level chip-scale package further includes a filter device mounted on the first side of the silicon die, the filter device communicating with the RF circuitry implemented in the active layer of the first side of the silicon die. At least some of the vias are coupled to the RF circuitry to support an electrical connection between the RF circuitry and a mounting feature on the second side of the silicon die. The RF circuitry of the silicon die includes switching circuitry.

17. The method of claim 16, wherein, The wafer-level chip-scale package has a side dimension that is less than 20% of the side area of ​​a package having a silicon die with similar RF circuitry and a similar number of filter devices mounted on a package substrate instead of the silicon die.

18. The method of claim 16, wherein, The filter device is an acoustic filter.

19. The method of claim 16, wherein, The radio frequency module is a diversity receiver module.

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