Field effect transistor with polycrystalline body in shallow trench isolation region

Abstract

The present invention relates to a field effect transistor having a polycrystalline body in a shallow trench isolation region, and discloses a structure of the field effect transistor and a method for forming the structure of the field effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is composed of a polycrystalline semiconductor material.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to a structure of a field effect transistor and a method for forming the structure of a field effect transistor. Background Art

[0002] Device structures, such as switching transistors for radio frequency integrated circuits, are susceptible to high capacitance and body-to-body leakage when formed using bulk semiconductor wafers. One measure that can be taken to reduce sensitivity is to provide the bulk semiconductor substrate with triple well isolation, which surrounds the active device region containing the device structure. Another measure that can be taken to reduce sensitivity is to replace the bulk semiconductor substrate with a silicon-on-insulator substrate, wherein a top silicon layer provides the active device region, and a buried insulator or buried oxide (BOX) layer is provided between the active device region and the silicon located below the buried insulator layer.

[0003] While these measures have proven suitable for their intended purpose, there is a need for improved structures of field effect transistors and methods of forming structures of field effect transistors. Summary of the invention

[0004] In one embodiment of the present invention, a structure includes a semiconductor substrate and a shallow trench isolation region located in the semiconductor substrate. The shallow trench isolation region includes a trench. The structure also includes a body region located in the trench of the shallow trench isolation region. The body region is composed of a polycrystalline semiconductor material.

[0005] In one embodiment of the present invention, a method includes forming a shallow trench isolation region in a semiconductor substrate, forming a trench in the shallow trench isolation region, and forming a body region composed of a polycrystalline semiconductor material in the trench of the shallow trench isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0007] Figure 1-3 Cross-sectional views of structures at successive stages of fabrication in a process recipe according to an embodiment of the present invention are shown.

[0008] Figure 4 Display in Figure 3 A cross-sectional view of the structure at a later stage of fabrication.

[0009] Figure 4A Displays a top view, where Figure 4 It is generally made along line 4-4.

[0010] Figure 5 Display in Figure 4 A cross-sectional view of the structure at a later stage of fabrication. DETAILED DESCRIPTION

[0011] Please refer to Figure 1 According to an embodiment of the present invention, a semiconductor substrate 10 including a single crystal semiconductor material, such as single crystal silicon, is provided. The semiconductor substrate 10 may be a bulk substrate including a single crystal semiconductor material (e.g., single crystal silicon). The semiconductor substrate 10 may be a high resistivity bulk substrate including silicon having a resistivity greater than or equal to 100 ohm-cm. In one embodiment, the high resistivity bulk substrate may have a resistivity greater than or equal to 1000 ohm-cm. Alternatively, the semiconductor substrate 10 may be a low resistivity bulk substrate including silicon having a resistivity less than 100 ohm-cm.

[0012] A shallow trench isolation region 12 is formed in a semiconductor substrate 10. The semiconductor substrate 10 is patterned using a photolithography and etching process to form an isolation trench 30. To this end, a patterned hard mask may be formed on the top surface 11 of the semiconductor substrate 10, and an etching process (e.g., a reactive ion etching process) may be used to form the isolation trench 30. Subsequently, the isolation trench 30 may be filled with a deposited dielectric material, such as silicon dioxide, and planarized by using, for example, chemical mechanical polishing to form the shallow trench isolation region 12. The shallow trench isolation region 12 may have a flat or substantially flat top surface 13. The shallow trench isolation region 12 may extend from the top surface 13 through the semiconductor substrate 10 to a lower boundary 14 at an interface of the semiconductor substrate 10. The interface is located at a depth d1 relative to the top surface 11 of the semiconductor substrate 10. When the semiconductor substrate 10 is patterned to form the isolation trench 30, the location of the interface of the semiconductor substrate 10 is established.

[0013] A region 16 comprising a highly disordered (e.g., amorphous) semiconductor material is formed in the semiconductor substrate 10 by ion implantation. The ion implantation process performed to form the region 16 introduces energetic ions, as indicated schematically by a single arrow, whose ion trajectories pass through the semiconductor substrate 10 and the shallow trench isolation region 12 along a path into the semiconductor substrate 10. The energetic ions lose energy along their paths through random scattering events with nuclei and electrons in the materials they pass through. The energy loss in the nuclear collisions (which are dominant at low energies) causes the target atoms of the semiconductor substrate 10 to shift from their original lattice positions. As a result, the lattice structure of the semiconductor substrate 10 is damaged within the region 16 compared to the initial single crystalline state. The ions may eventually stop near the lower boundary 18 of the region 16 after their kinetic energy is completely dissipated due to the energy loss. The region 16 of the semiconductor substrate 10 may be changed from a crystalline semiconductor material (e.g., single crystal silicon) to a highly disordered semiconductor material (e.g., amorphous silicon) due to the use of a high ion dose during implantation.

[0014] The ions may be generated from a suitable source gas using an ion implantation tool and implanted into the semiconductor substrate 10 under given implantation conditions. The implantation conditions (e.g., ion species, dose, energy) may be selected to adjust the characteristics of the region 16. In one embodiment, the ions may be generated from an inert atomic gas (e.g., argon). The ion dose is selected to be less than a threshold ion dose, beyond which it is not possible to recrystallize the damaged semiconductor material in the region 16 by subsequent annealing. For example, the ion dose may be between 1×10 14 ions / cm 2 ) to 1.5x10 15 ions / cm2. The ion energy may be selected so that a lower boundary 18 of region 16 is located below a lower boundary 14 of shallow trench isolation region 12 relative to top surface 11 of semiconductor substrate 10.

[0015] The portion of the semiconductor substrate 10 disposed below the lower boundary 18 of the region 16 may not be affected by the ion implantation because it is outside the range of the implanted ions and may maintain its single crystal state. After the ion implantation, the portion of the semiconductor substrate 10 disposed between the top surface 11 and the region 16 may also include single crystal semiconductor material.

[0016] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 and in the next manufacturing stage of the process method, the semiconductor substrate 10 is subjected to a heat treatment (i.e., an annealing process), which causes the region 16 ( Figure 1) undergoes the heat treatment. In one embodiment, the heat treatment for heat treating the region 16 of the semiconductor substrate 10 may be a rapid thermal anneal. In one embodiment, the rapid thermal anneal may be performed by using, for example, a bank of flash lamps to heat the semiconductor substrate 10 to a peak temperature in the range of 900° C. to 1125° C. and having a dwell time of 30 milliseconds to 60 seconds at the peak temperature.

[0017] The thermal treatment recrystallizes a portion of the highly disordered semiconductor material near the lower boundary 18 of the region 16 into a polycrystalline layer 20 comprising polycrystalline semiconductor material (e.g., polysilicon). The polycrystalline layer 20 may be substantially located at or near a previous location of peak ion dose and / or peak damage in the semiconductor material of the semiconductor substrate 10. In addition to grains of the polycrystalline semiconductor material, the polycrystalline semiconductor material of the polycrystalline layer 20 may also include defects as residual damage. The defects may also include atoms of the noble gas species (e.g., argon) that was ion implanted to form the region 16.

[0018] The thermal treatment also recrystallizes the highly disordered semiconductor material in region 16 between the top surface 11 of the semiconductor substrate 10 and the polycrystalline layer 20 into a single crystal semiconductor material (e.g., single crystal silicon). The single crystal semiconductor material of the semiconductor substrate 10 located below and above the region 16 provides a crystallization template for recrystallization during the thermal treatment. Compared to the polycrystalline layer 20, the recrystallized single crystal semiconductor material is free of grains and defects.

[0019] The polycrystalline layer 20 (which may include only a single layer of polycrystalline semiconductor material) may be considered a trap-rich material that can effectively capture charge carriers. In this regard, the resistivity of the polycrystalline layer 20 may be greater than or equal to the resistivity of the rest of the semiconductor substrate 10. In one embodiment, the polycrystalline layer 20 may have a resistivity greater than or equal to 1000 ohm-cm. In one embodiment, the resistivity of the polycrystalline layer 20 may be in the range of 1,000 ohm-cm to 10,000 ohm-cm.

[0020] The polycrystalline layer 20 may extend laterally in the semiconductor substrate 10 below the lower boundary 14 of the shallow trench isolation region 12. More specifically, the polycrystalline layer 20 includes a portion located below the lower boundary 14 of the shallow trench isolation region 12 and an adjacent portion located in the semiconductor substrate 10. The polycrystalline layer 20 includes a lower boundary 19 and an upper boundary 21 that define a depth profile of the polycrystalline semiconductor material. The single crystalline semiconductor material of the semiconductor substrate 10 is disposed below the lower boundary 19 of the polycrystalline layer 20 and above the upper boundary 21 of the polycrystalline layer 20. In the representative embodiment, the polycrystalline layer 20 is completely disposed below the shallow trench isolation region 12 and the isolation trench 30. More specifically, the lower boundary 14 of the shallow trench isolation region 12 may be disposed in a vertical direction between the upper boundary 21 of the polycrystalline layer 20 and the top surface 13 of the shallow trench isolation region 12. The polycrystalline layer 20 may have a substantially uniform thickness as shown, or, alternatively, may have a thickness that varies with position, such as having a greater thickness where it overlaps the shallow trench isolation region 12. In an embodiment, the polycrystalline layer 20 may be in direct contact with the shallow trench isolation region 12 at a lower boundary 14. In an alternative embodiment, the polycrystalline layer 20 may overlap the shallow trench isolation region 12, with the lower boundary 14 of the shallow trench isolation region 12 being disposed in a vertical direction between a lower boundary 19 and an upper boundary 21 of the polycrystalline layer 20.

[0021] Please refer to Figure 3 , wherein similar reference numerals denote Figure 2 In the next manufacturing stage of the process method, a trench 22 is patterned in the shallow trench isolation region 12 using a photolithography and etching process. To this end, an etching mask 24 is formed by a photolithography process over the shallow trench isolation region 12. The etching mask 24 includes an opening at a predetermined position of the trench 22. An etching process (e.g., reactive ion etching) is used to etch and remove the dielectric material of the shallow trench isolation region 12 located above the area of ​​the opening in the etching mask 24.

[0022] The trench 22 partially penetrates the shallow trench isolation region 12 to set the portion of the dielectric material of the shallow trench isolation region 12 to a lower edge between the bottom of the trench 22 and the lower boundary 14 of the shallow trench isolation region 12. In this aspect, the trench 22 has a lower boundary 23 located at a depth d2 between the lower boundary 14 of the shallow trench isolation region 12 and the top surface 11 of the semiconductor substrate 10. In this aspect, the depth d2 is less than the depth d1 ( Figure 1 ). The etching process to form the trench 22 can be controlled (e.g., timed) to avoid completely penetrating the shallow trench isolation region 12 and thereby provide a lower edge. Portions of the shallow trench isolation region 12 also laterally surround or encircle the trench 22 to provide a lateral edge of dielectric material between the side edges of the trench 22 and the semiconductor substrate 10.

[0023] Please refer to Figure 4 , 4A , wherein similar reference numerals denote Figure 3 1 , and in the next manufacturing stage of the process method, a body region 26 is formed in the trench 22 and embedded in the shallow trench isolation region 12. The body region 26 includes a polycrystalline semiconductor material, such as polycrystalline silicon. In one embodiment, to form the body region 26, a layer of polycrystalline semiconductor material can be deposited by chemical vapor deposition, and the deposited layer can be polished by chemical mechanical polishing. The body region 26 has a top surface 25 that can be coplanar or substantially coplanar with the top surface 13 of the shallow trench isolation region 12. The top surface 25 of the body region 26 can also be coplanar or substantially coplanar with the top surface 11 of the semiconductor substrate 10.

[0024] The body region 26 is completely separated from the polycrystalline layer 20 by a portion of the shallow trench isolation region 12. The polycrystalline layer 20 is located below the shallow trench isolation region 12 and the body region 26, and the dielectric material of this portion of the shallow trench isolation region 12 is located between the polycrystalline layer 20 and the body region 26. The body region 26 has a lower boundary that is adjacent to the lower boundary 23 ( Figure 3 ) overlap and are spaced apart from a lower boundary 14 of the shallow trench isolation region 12 in a vertical direction toward the top surface 11 of the semiconductor substrate 10. Portions of the shallow trench isolation region 12 laterally surround the body region 26. These surrounding portions of the shallow trench isolation region 12 extend through the semiconductor substrate 10 to portions of the shallow trench isolation region 12 that are located between the polycrystalline layer 20 and the body region 26. Thus, the body region 26 is disposed in a bucket of dielectric material provided by different portions of the shallow trench isolation region 12 that surround the body region 26. A top surface 25 of the body region 26 is exposed for additional processing.

[0025] Please refer to Figure 5 , wherein similar reference numerals denote Figure 4 , and in the next manufacturing stage of the process method, the switch field effect transistor 40 can be manufactured as a device structure in the body region 26 by the front-end process. The switch field effect transistor 40 may include a gate 44 located above the top surface 25 of the body region 26 and a source / drain region 46 formed in the body region 26. The gate 44 may include, for example, a plurality of fingers that may be formed by patterning a deposited layer of heavily doped polysilicon, and the source / drain region 46 may be formed by ion implantation or diffusion of, for example, n-type dopants. The switch field effect transistor 40 may include other elements, such as a gate dielectric, a halo region, and an extension region located between the fingers of the gate 44 and the body region 26. In one embodiment, the switch field effect transistor 40 may be deployed in a radio frequency integrated circuit.

[0026] Then, a mid-level process and a back-end process are performed, which include forming contacts, vias, and lines of an interconnect structure coupled to the switch field effect transistor 40 .

[0027] The semiconductor substrate 10 may act as a back gate to which a bias may be applied to provide a partially depleted body region 26 or a fully depleted body region 26. Instead of a switch field effect transistor 40, the body region 26 may be utilized to form a different type of device structure, such as a stacked n-type field effect transistor / p-type field effect transistor combination.

[0028] The switching field effect transistor 40 is formed using the body region 26 comprising a polycrystalline semiconductor, rather than being formed in the single crystalline semiconductor material of the semiconductor substrate 10 .

[0029] The body region 26 of polycrystalline semiconductor material and the portion of the shallow trench isolation region 12 surrounding the body region 26 may combine to provide low harmonic distortion at small channel lengths for the switching field effect transistor 40. The polycrystalline layer 20 may also help to further reduce harmonic distortion.

[0030] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is provided in a single-chip package (e.g., a plastic carrier having pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0031] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0032] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0033] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intervening feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intervening features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intervening feature.

[0034] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: A semiconductor substrate including a first trench; a shallow trench isolation region including a dielectric material in the first trench in the semiconductor substrate, the shallow trench isolation region including a second trench completely surrounded by the dielectric material of the shallow trench isolation region; a body region located in the second trench of the shallow trench isolation region, the body region comprising a polycrystalline semiconductor material, wherein the body region is completely separated from the semiconductor substrate by the dielectric material of the shallow trench isolation region; as well as The field effect transistor comprises a gate located above the body region and a source / drain region located in the body region.

2. The semiconductor structure according to claim 1, wherein: The polycrystalline semiconductor material is polycrystalline silicon, and the semiconductor substrate is composed of single crystal silicon.

3. The semiconductor structure according to claim 1, wherein: The second trench partially passes through the shallow trench isolation region to a lower boundary, and the shallow trench isolation region includes a first portion as an edge of the dielectric material disposed between the body region at the lower boundary of the second trench and the semiconductor substrate adjacent to the lower boundary of the second trench.

4. The semiconductor structure according to claim 3, wherein: The shallow trench isolation region includes a second portion surrounding the second trench and the body region.

5. The semiconductor structure according to claim 4, wherein: The semiconductor substrate includes a top surface, and the second portion of the shallow trench isolation region extends from the top surface of the semiconductor substrate to the first portion of the shallow trench isolation region.

6. The semiconductor structure of claim 1, wherein: The dielectric material is silicon dioxide.

7. The semiconductor structure of claim 1, wherein: The shallow trench isolation region has a top surface, and the body region has a top surface that is substantially coplanar with the top surface of the shallow trench isolation region.

8. The semiconductor structure of claim 7, wherein: The semiconductor substrate has a top surface, and the top surface of the body region is substantially coplanar with the top surface of the semiconductor substrate.

9. The semiconductor structure according to claim 1, in, The shallow trench isolation region includes an edge of the dielectric material between the second trench and the semiconductor substrate.

10. The semiconductor structure of claim 1, further comprising: The polycrystalline layer is located in the semiconductor substrate and is arranged below the shallow trench isolation region and the body region.

11. The semiconductor structure of claim 10, wherein: The polycrystalline layer includes a portion directly contacting the shallow trench isolation region, and the dielectric material of the shallow trench isolation region separates the body region from the polycrystalline layer.

12. The semiconductor structure of claim 10, wherein: The polycrystalline layer includes a portion overlapping the shallow trench isolation region.

13. The semiconductor structure of claim 10, wherein: The shallow trench isolation region includes a portion completely located between the polycrystalline layer and the body region.

14. The semiconductor structure of claim 1, wherein: The semiconductor substrate is a bulk substrate.

15. A method of forming a semiconductor structure, comprising: forming a first trench in a semiconductor substrate; forming a shallow trench isolation region in the first trench; forming a second trench in the shallow trench isolation region, wherein the second trench is completely surrounded by the dielectric material of the shallow trench isolation region; forming a body region comprising a polycrystalline semiconductor material in the second trench of the shallow trench isolation region, wherein the body region is completely separated from the semiconductor substrate by the dielectric material of the shallow trench isolation region; and A field effect transistor is formed, the field effect transistor including a gate located above the body region and source / drain regions located in the body region.

16. The method of claim 15, further comprising: A polycrystalline layer is formed in the semiconductor substrate below the shallow trench isolation region and the body region.

17. The method of claim 16, wherein: The polycrystalline layer includes a portion directly contacting the shallow trench isolation region.

18. The method of claim 15, wherein: The second trench partially passes through the shallow trench isolation region to a lower boundary, and the shallow trench isolation region includes a first portion as an edge of the dielectric material disposed between the body region at the lower boundary of the second trench and the semiconductor substrate adjacent to the lower boundary of the second trench.

19. The method of claim 18, wherein: The shallow trench isolation region includes a second portion surrounding the body region.

20. The method of claim 19, wherein: The second portion of the shallow trench isolation region extends through the semiconductor substrate to the first portion of the shallow trench isolation region.

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