Electronic packaging and method of manufacturing the same

Abstract

An electronic package and its manufacturing method, by first laying out a coating layer on an electronic component and then bonding the coating layer to a bearing structure, so that the coating layer will not flow to the side of the electronic component due to capillary action, so that when a packaging layer used to cover the electronic component and the coating layer is subsequently ground, the stress inside the electronic component can be dispersed, avoiding the problem of the electronic component being broken due to stress concentration.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a flip chip package type electronic package and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-function and high performance. There are many technologies currently used in the field of chip packaging, such as chip scale package (CSP), direct chip attached package (DCA) or multi-chip module package (MCM) and other flip chip packaging modules, or three-dimensional chip stacking integration into a three-dimensional integrated circuit (3D IC) chip stacking module.

[0003] Figure 1 To provide a cross-sectional view of a 3D IC semiconductor package 1, a through silicon interposer (TSI) 10 having a transfer side 10a and a die side 10b opposite to each other is provided, and the silicon interposer 10 has a plurality of conductive through silicon vias (TSVs) 100 connecting the die side 10b and the transfer side 10a, and a circuit structure 101 is formed on the die side 10b for receiving a plurality of semiconductor elements 11 having a plurality of solder bumps 12, and then the solder bumps 12 are coated with a primer 13, and a packaging layer 14 is formed to cover the semiconductor element 11, and the packaging layer 14 is polished to expose the packaging layer 14 on the upper surface of the semiconductor element 11. Next, the silicon interposer 10 is disposed on a packaging substrate 16 through a plurality of conductive elements 15 at its transfer side 10a, and the packaging substrate 16 is electrically connected to the conductive through silicon vias 100, and the conductive elements 15 are then covered with an underfill 17. Next, a packaging colloid 18 is formed on the packaging substrate 16, so that the packaging colloid 18 covers the packaging layer 14 and the silicon interposer 10. Finally, a plurality of solder balls 160 are formed on the lower side of the packaging substrate 16 for being placed on a circuit board 19.

[0004] However, in the known semiconductor package 1, the semiconductor element 11 is first flip-chip bonded to the circuit structure 101, and then the primer 13 is filled, so that the outer side 130 of the primer 13 is sloped, such as Figure 1As shown in FIG. 1 , the outer side 130 of the bottom glue 13 will flow onto the side surface 11c of each semiconductor element 11 due to the capillary action generated by the gap S between each semiconductor element 11, so that the internal stress of the semiconductor element 11 increases. Therefore, when grinding the packaging layer 14, the external grinding force will be transmitted to the semiconductor element 11, causing the stress concentration of the semiconductor element 11 and causing it to break, resulting in poor reliability of the semiconductor package 1.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can avoid the problem of electronic components being cracked due to stress concentration.

[0007] The electronic package of the present invention comprises: a supporting structure; a plurality of electronic components which are arranged on the supporting structure at intervals so that a gap is formed between any two adjacent electronic components, wherein a plurality of conductive bumps and a coating layer covering the plurality of conductive bumps are formed on each of the electronic components, so that each of the electronic components is adhered to the supporting structure by the coating layer, and the conductive bumps are electrically connected to the supporting structure; and a packaging layer which is formed on the supporting structure to cover the plurality of electronic components and the coating layer.

[0008] The present invention also provides a method for manufacturing an electronic package, comprising: providing a plurality of electronic components, wherein each of the electronic components is formed with a plurality of conductive bumps and a coating layer covering the plurality of conductive bumps; arranging the plurality of electronic components on a supporting structure at intervals so that a gap is formed between any two adjacent electronic components, wherein each of the electronic components is adhered to the supporting structure with the coating layer, and the supporting structure is electrically connected with the conductive bumps; and forming a packaging layer on the supporting structure to cover the plurality of electronic components and the coating layer.

[0009] In the aforementioned electronic package and the manufacturing method thereof, the structures of the plurality of electronic components are different from each other.

[0010] In the aforementioned electronic package and its manufacturing method, the spacing of the gap is at most 300 microns.

[0011] The aforementioned electronic package and its manufacturing method further include grinding the packaging layer to expose a surface of the electronic component on a surface of the packaging layer.

[0012] In the aforementioned electronic package and its manufacturing method, the side surface of the coating layer is flush with the side surface of the electronic component.

[0013] In the aforementioned electronic package and its manufacturing method, the coating layer protrudes from the side of the electronic component and does not contact the side of the electronic component. For example, the coating layer protrudes from the side of the electronic component with its end, and the cross section of the edge of the coating layer is spherical.

[0014] In the aforementioned electronic package and its manufacturing method, the coating layer is a non-conductive film.

[0015] In the aforementioned electronic package and its manufacturing method, the Young's modulus of the packaging layer is at least 20 GPa.

[0016] In the aforementioned electronic package and its manufacturing method, the Young's modulus of the packaging layer is greater than the Young's modulus of the coating layer.

[0017] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, the coating layer is mainly arranged on the electronic component to be adhered to the supporting structure, so that the coating layer will not flow to the side of the electronic component due to capillary action. Therefore, compared with the prior art, when grinding the packaging layer, the interior of the electronic component can still disperse the stress even if the external grinding force is transmitted to the electronic component, so as to avoid the problem of the electronic component being broken due to stress concentration, thereby improving the reliability of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a cross-sectional schematic diagram of a well-known semiconductor package.

[0019] Figure 1 'for Figure 1 A partially enlarged cross-sectional schematic diagram of .

[0020] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0021] Figure 2B 'for Figure 2B A partially enlarged cross-sectional schematic diagram of another embodiment of the present invention.

[0022] Figure 2C 'for Figure 2C A cross-sectional schematic diagram of another embodiment of the present invention.

[0023] Figure 3 for Figure 2C A cross-sectional schematic diagram of another embodiment of the present invention.

[0024] Description of Reference Numerals

[0025] 1: Semiconductor packaging

[0026] 10: Silicon interposer

[0027] 10a: Transfer side

[0028] 10b: Chip placement side

[0029] 100: Conductive silicon via

[0030] 101: Line Structure

[0031] 11: Semiconductor components

[0032] 11c, 21c, 23c, 31c: Side

[0033] 12: Solder Bumps

[0034] 13: Base glue

[0035] 130: Outer side

[0036] 14,24: Encapsulation layer

[0037] 15: Conductive elements

[0038] 16: Package substrate

[0039] 160: Solder ball

[0040] 17: Base glue

[0041] 18: Encapsulation colloid

[0042] 19: Circuit Board

[0043] 2,2',3: Electronic packaging

[0044] 2a: Full-page substrate structure

[0045] 20: Bearing structure

[0046] 200: Line layer

[0047] 21,31: Electronic components

[0048] 21a: Action surface

[0049] 21b: Non-active surface

[0050] 210: Electrode pads

[0051] 22: Conductive bump

[0052] 23: Cladding layer

[0053] 230: Edge

[0054] 24b: Upper surface

[0055] 310: Packaging material

[0056] 311: Control chip

[0057] 312: High-bandwidth memory chip

[0058] X: Horizontal direction

[0059] L: Cutting path

[0060] S: Clearance

[0061] t: spacing. DETAILED DESCRIPTION

[0062] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0063] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention. At the same time, the terms such as "above" and the like cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of the relative relationship, without substantially changing the technical contents, should also be regarded as the scope of the implementation of the present invention.

[0064] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0065] like Figure 2A As shown, a full-page substrate structure 2a is provided, which includes a plurality of electronic components 21 arranged in an array, and each of the electronic components 21 is provided with a plurality of conductive bumps 22 and a coating layer 23 coating the conductive bumps 22 .

[0066] The electronic component 21 can be an active component, a passive component, a packaging structure or a combination thereof, and the active component is a semiconductor chip, and the passive component is a resistor, a capacitor and an inductor. In the present embodiment, the electronic component 21 is a semiconductor chip, and has an active surface 21a and an inactive surface 21b opposite to each other, the active surface 21a has a plurality of electrode pads 210, and a conductive bump 22 is formed on each of the electrode pads 210, and the coating layer 23 is formed on the active surface 21a to cover the conductive bumps 22, and each of the conductive bumps 22 is exposed from the coating layer 23.

[0067] In addition, the conductive bump 22 is a metal column (such as a copper column), a solder material or a combination thereof, and the cladding layer 23 is a non-conductive film (NCF for short).

[0068] like Figure 2B As shown, along Figure 2A The cutting path L shown is used to perform a singulation process on the entire substrate structure 2a to separate each of the electronic components 21, and then at least two electronic components 21 are arranged on a supporting structure 20 along a horizontal direction X at intervals, and a space (gap) S is formed between any two adjacent electronic components 21, and the spacing t of the space (gap) S is at most 300 microns (μm).

[0069] The supporting structure 20 may be a packaging substrate (substrate) having a core layer and a circuit structure or a circuit structure without a core layer (coreless), and its structure forms multiple circuit layers 200 on a dielectric material, such as a circuit redistribution layer (RDL). In this embodiment, the supporting structure 20 is a circuit structure without a core layer (coreless). However, in other embodiments, the supporting structure 20 may also be a semiconductor substrate having multiple conductive through-silicon vias (TSV) to serve as a Through Silicon interposer (TSI). It should be understood that the supporting structure 20 may also be other supporting units that can be used to carry electronic components such as chips, such as a lead frame, but is not limited to the above.

[0070] In addition, when the electronic component 21 is pressed and bonded on the supporting structure 20 by means of its covering layer 23 , the conductive bumps 22 are electrically connected to the circuit layer 200 of the supporting structure 20 by means of a flip chip process.

[0071] In addition, through the singulation process, the side surface 21c of the electronic component 21 is flush with the side surface 23c of the coating layer 23. However, in another embodiment, based on the force of pressing the electronic component 21 onto the supporting structure 20, the side surface 23c of the coating layer 23 can be formed into an edge 230 protruding from the side surface 21c of the electronic component 21, such as Figure 2B Specifically, the cross section of the edge 230 of the coating layer 23 is convex (such as a hemispherical sphere).

[0072] In addition, in this embodiment, although the electronic components 21 are of the same type (ie, active components), their internal structures may be the same or different.

[0073] like Figure 2CAs shown, a packaging layer 24 is formed on the supporting structure 20 to cover the covering layer 23 and the electronic components 21 .

[0074] The packaging layer 24 can be an insulating material, such as polyimide (PI), dry film, epoxy, molding compound or other suitable materials. In this embodiment, the packaging layer 24 is formed on the supporting structure 20 by lamination or molding, so that the packaging layer 24 fills the gap S.

[0075] In addition, the Young's modulus of the packaging layer 24 is greater than that of the cladding layer 23. In this embodiment, the Young's modulus of the packaging layer 24 is greater than 20 GPa.

[0076] In addition, the inactive surface 21b of the electronic component 21 and the upper surface 24b of the packaging layer 24 may be made coplanar by a flattening process or a thinning process. Figure 2C ', so that the inactive surface 21b of the electronic component 21 is exposed to the packaging layer 24. For example, when the packaging layer 24 is formed on the supporting structure 20, the packaging layer 24 covers the inactive surface 21b of the electronic component 21, and then part of the material of the packaging layer 24 is removed by grinding or cutting (part of the material of the inactive surface 21b of the electronic component 21 can also be removed at the same time as required), so that the inactive surface 21b of the electronic component 21 is flush with the upper surface 24b of the packaging layer 24.

[0077] In addition, after forming the packaging layer 24, a plurality of solder balls (not shown) may be formed on the lower side (or the ball implantation side) of the supporting structure 20 so that the electronic package 2 can be connected to an electronic device (not shown) such as a circuit board.

[0078] It should be understood that the electronic components 21 may be electronic components of different types. Figure 3 The two electronic components 21 and 31 shown in the figure, the electronic component 21 (active component) is an application-specific integrated circuit (ASIC) type semiconductor chip, and the other electronic component 31 is a packaging structure, which includes a packaging module of a packaging material 310, a control chip 311 and at least one high bandwidth memory (HBM) type chip 312, and the electrode pads 210 of the control chip 311 are combined with the conductive bumps 22.

[0079] Therefore, the manufacturing method of the present invention mainly forms the coating layer 23 on the electronic component 21, 31 first, and then adheres the coating layer 23 to the supporting structure 20, so that the coating layer 23 will not flow onto the side surfaces 21c, 31c of the electronic component 21, 31 due to capillary action. Therefore, regardless of the size of the spacing t of the gap S (such as less than or equal to 150 microns), the coating layer 23 will not have a capillary phenomenon in the gap S, so that the internal stress of the electronic component 21, 31 can be avoided. Therefore, compared with the prior art, when grinding the packaging layer 24, the internal stress of the electronic component 21, 31 can still be dispersed even if the external grinding force is transmitted to the electronic component 21, 31, so as to avoid the problem of the electronic component 21, 31 being broken due to stress concentration, thereby improving the reliability of the electronic package 2.

[0080] In addition, by filling the gap S with the packaging layer 24 having a larger Young's modulus, the strength of the gap can be enhanced, so that stress concentration inside the electronic components 21 , 31 will not cause the packaging component to rupture.

[0081] The present invention further provides an electronic package 2 , 2 ′, 3 , comprising: a supporting structure 20 , a plurality of electronic components 21 , 31 , and a packaging layer 24 .

[0082] The multiple electronic components 21, 31 are arranged on the supporting structure 20 at intervals so that a gap S is formed between any two adjacent electronic components 21, 31. Each of the electronic components 21, 31 has a plurality of conductive bumps 22 and a coating layer 23 covering the plurality of conductive bumps 22, so that each of the electronic components 21, 31 is adhered to the supporting structure 20 by the coating layer 23, and the conductive bumps 22 are electrically connected to the supporting structure 20.

[0083] The packaging layer 24 is formed on the supporting structure 20 to cover the plurality of electronic components 21 , 31 and the covering layer 23 .

[0084] In one embodiment, the structures of the plurality of electronic components 21 , 31 are different from each other.

[0085] In one embodiment, the spacing t of the gap S is at most 300 microns.

[0086] In one embodiment, the surface (eg, inactive surface) of the electronic component 21 , 31 is exposed on the surface 24 b of the packaging layer 24 .

[0087] In one embodiment, the side surface 23 c of the cladding layer 23 is flush with the side surfaces 21 c , 31 c of the electronic components 21 , 31 .

[0088] In one embodiment, the coating layer 23 protrudes from the side surfaces 21c, 31c of the electronic components 21, 31, and the coating layer 23 does not contact the side surfaces 21c, 31c of the electronic components 21, 31. For example, the coating layer 23 protrudes from the side surface 21c of the electronic component 21 with its edge 230, and the cross-section of the edge 230 of the coating layer 23 is spherical.

[0089] In one embodiment, the coating layer 23 is a non-conductive film.

[0090] In one embodiment, the Young's modulus of the encapsulation layer 24 is at least 20 GPa.

[0091] In one embodiment, the Young's modulus of the packaging layer 24 is greater than the Young's modulus of the cladding layer 23 .

[0092] In summary, the electronic package and its manufacturing method of the present invention, by laying the coating layer on the electronic component to be fixed on the supporting structure, the coating layer will not be squeezed onto the side of the electronic component, so the interior of the electronic component of the present invention can avoid the problem of cracking due to stress concentration, thereby improving the reliability of the electronic package. In addition, the packaging layer 24 fills the gap S, which can strengthen the strength of the gap, so that the stress concentration inside the electronic component will not cause the package to crack.

[0093] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the attached claims.

Claims

1. An electronic package, characterized in that: include: load-bearing structure; A plurality of electronic components are arranged on the supporting structure at intervals so that a gap is formed between any two adjacent electronic components, wherein each of the electronic components is formed with a plurality of conductive bumps and a coating layer of a non-conductive film covering the plurality of conductive bumps, so that after each of the electronic components is adhered to the supporting structure by the coating layer of the non-conductive film, the supporting structure is electrically connected by the conductive bumps, and the coating layer of the non-conductive film will not creep to the sides of the two adjacent electronic components at the gap due to capillary action; as well as The packaging layer is formed on the supporting structure to cover the multiple electronic components and the covering layer of the non-conductive film, and the packaging layer fills the gap to cover the entire side surfaces of two adjacent electronic components at the gap.

2. The electronic package according to claim 1, wherein: The plurality of electronic components are configured differently from one another.

3. The electronic package according to claim 1, wherein: The spacing of the gap is at most 300 microns.

4. The electronic package according to claim 1, wherein: A surface of the electronic component is exposed on a surface of the packaging layer.

5. The electronic package according to claim 1, wherein: The side surface of the covering layer is flush with the side surface of the electronic component.

6. The electronic package according to claim 1, wherein: The covering layer protrudes from the side surface of the electronic component, and the covering layer does not contact the side surface of the electronic component.

7. The electronic package according to claim 6, wherein: The end of the covering layer protrudes from the side surface of the electronic component, and the cross section of the edge of the covering layer is spherical.

8. The electronic package according to claim 1, wherein: The Young's modulus of the encapsulation layer is at least 20 GPa.

9. The electronic package according to claim 1, wherein: The Young's modulus of the packaging layer is greater than the Young's modulus of the coating layer.

10. A method for manufacturing an electronic package, characterized in that: include: A plurality of electronic components are provided, wherein each of the electronic components is formed with a plurality of conductive bumps and a coating layer of a non-conductive film covering the plurality of conductive bumps; A plurality of electronic components are arranged on a supporting structure at intervals so that a gap is formed between any two adjacent electronic components, wherein each electronic component is adhered to the supporting structure by the coating layer of the non-conductive film, and the supporting structure is electrically connected to the supporting structure by the conductive bump, and the coating layer of the non-conductive film will not creep to the sides of the two adjacent electronic components at the gap due to capillary action; and A packaging layer is formed on the supporting structure to cover the plurality of electronic components and the covering layer which is the non-conductive film, and the packaging layer fills the gap to cover the entire side surfaces of two adjacent electronic components at the gap.

11. The method for manufacturing an electronic package as claimed in claim 10, wherein: The plurality of electronic components are configured differently from one another.

12. The method for manufacturing an electronic package as claimed in claim 10, wherein: The spacing of the gap is at most 300 microns.

13. The method for manufacturing an electronic package as claimed in claim 10, wherein: The manufacturing method further comprises grinding the packaging layer to expose a surface of the electronic component on a surface of the packaging layer.

14. The method for manufacturing an electronic package as claimed in claim 10, wherein: The side surface of the covering layer is flush with the side surface of the electronic component.

15. The method for manufacturing an electronic package as claimed in claim 10, wherein: The covering layer protrudes from the side surface of the electronic component, and the covering layer does not contact the side surface of the electronic component.

16. The method for manufacturing an electronic package as claimed in claim 15, wherein: The end of the covering layer protrudes from the side surface of the electronic component, and the cross section of the edge of the covering layer is spherical.

17. The method for manufacturing an electronic package as claimed in claim 10, wherein: The Young's modulus of the encapsulation layer is at least 20 GPa.

18. The method for manufacturing an electronic package as claimed in claim 10, wherein: The Young's modulus of the packaging layer is greater than the Young's modulus of the coating layer.

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