Memory device and method of manufacturing the same

Abstract

In some embodiments, an embodiment of the present application discloses a memory device. The memory device includes a bottom electrode disposed above a substrate and a top electrode disposed above the bottom electrode. The upper surface of the bottom electrode faces away from the substrate. The bottom surface of the top electrode faces the substrate. A data storage layer is disposed between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. In addition, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction. An embodiment of the present application also provides a method for manufacturing a memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and a method for manufacturing the same. Background Art

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data in the absence of electricity. Some promising next-generation non-volatile memories include resistive data storage elements, such as resistive random access memory (RRAM) and phase change memory (PCM). Resistive data storage elements are simple in structure and compatible with complementary metal oxide semiconductor (CMOS) logic manufacturing processes. Compared with current non-volatile memories (e.g., flash memory), resistive data storage elements have fast switching times and / or low power consumption. Summary of the invention

[0003] In some embodiments, a memory device comprises: a bottom electrode disposed above a substrate, wherein an upper surface of the bottom electrode faces away from the substrate; a top electrode above the bottom electrode, wherein the top electrode has a bottom surface facing the substrate; a data storage layer arranged between the bottom electrode and the top electrode, wherein at least a portion of the bottom surface of the top electrode does not overlap with any portion of the upper surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode; and wherein at least a portion of the upper surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

[0004] In some embodiments, no more than 60% of the bottom surface of the top electrode overlaps with a portion of the upper surface of the bottom electrode along the first direction. In some embodiments, the bottom surface of the top electrode does not overlap with the upper surface of the bottom electrode along the first direction. In some embodiments, a data storage layer surrounds the bottom surface and sidewalls of the top electrode. In some embodiments, the bottom surface of the data storage layer includes a protrusion extending along the sidewall of the bottom electrode. In some embodiments, the bottom surface of the top electrode includes a protrusion extending toward the bottom electrode. In some embodiments, the data storage layer includes a dielectric resistive memory layer. In some embodiments, the bottom electrode includes a tapered sidewall that forms an acute angle with the upper surface of the bottom electrode at an edge of the bottom electrode facing the bottom surface of the top electrode; and the top electrode includes a tapered sidewall that forms an obtuse angle with the bottom surface of the top electrode at an edge of the top electrode facing the upper surface of the bottom electrode.

[0005] In some embodiments, a memory device comprises: a transistor comprising a first source / drain (S / D) region and a second S / D region; a first conductive structure in a first dielectric layer, the first conductive structure electrically coupled to the first S / D region of the transistor; a second conductive structure in a second dielectric layer; and a data storage layer disposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure; wherein: the top surface of the first conductive structure extends from a first edge to a second edge along a first direction; the bottom surface of the second conductive structure extends from a third edge to a fourth edge along the first direction; and the fourth edge is offset relative to the second edge in the first direction so that the bottom surface of the second conductive structure spans the second edge.

[0006] In some embodiments, the third edge is offset relative to the first edge in the first direction. In some embodiments, a second MEOL structure in the first dielectric layer, the second MEOL structure electrically coupled to the second S / D region of the transistor; and a first through hole in the second dielectric layer, wherein a center of a bottom surface of the second MEOL structure is substantially aligned with a center of a top surface of the first through hole. In some embodiments, a first direction is parallel to a channel of the transistor extending from the second S / D region to the first S / D region; and the first through hole is offset relative to the second conductive structure in a second direction perpendicular to the first direction. In some embodiments, a gate structure, between the first S / D region and the second S / D region above the transistor; and a second through hole, electrically coupled to the gate structure, wherein the second through hole is arranged between the second conductive structure and the first through hole in the second direction.

[0007] In some embodiments, a method for manufacturing a memory device includes: forming a first conductive structure above a substrate; forming a data storage layer above an exposed portion of an upper surface of the first conductive structure, wherein a center of the data storage layer deviates from a center of the upper surface of the first conductive structure in a first direction parallel to the upper surface of the first conductive structure; and forming a second conductive structure above the data storage layer.

[0008] Embodiments of the present application provide a data storage element and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various aspects of the present disclosure may be better understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. The accompanying drawings show the following schematic diagrams

[0010] Figure 1A : A cross-sectional side view of a data storage element having a data storage layer according to some examples of the present disclosure;

[0011] Figure 1B : In low resistance state Figure 1A A cross-sectional side view of a data storage element;

[0012] Figure 2A-2D : A cross-sectional side view of a data storage element having a dielectric resistive data storage layer according to some examples of the present disclosure;

[0013] Figure 3A : A top view of a memory cell according to some examples of the present disclosure;

[0014] Figure 3B : Figure 3A a cross-sectional side view of a memory cell;

[0015] Figure 4A-4B : A top view of a memory cell with an offset via according to some examples of the present disclosure;

[0016] Figure 5 : A flow chart of a method of manufacturing a data storage element according to some examples of the present disclosure;

[0017] Figure 6A-6F : Figure 5 A cross-sectional side view of a sequence of exemplary manufacturing steps of a method;

[0018] Figure 7 : A flow chart of a method of manufacturing a data storage element according to some examples of the present disclosure;

[0019] Figure 8A-8F : Figure 7 A cross-sectional side view of a sequence of exemplary manufacturing steps of a method;

[0020] Fig. 9 : a cross-sectional side view of a memory cell according to some examples of the present disclosure; and

[0021] Fig.10 : A cross-sectional side view of a memory cell having a first through-hole and a data storage layer with rounded edges according to some examples of the present disclosure. DETAILED DESCRIPTION

[0022] The present disclosure provides a plurality of different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] The resistive data storage element typically includes a bottom electrode, a top electrode, and a resistive memory layer arranged between the bottom electrode and the top electrode. The resistive memory layer has a switchable resistance, such as a low resistance state and a high resistance state, which can be used to encode a data bit (i.e., "1" or "0"). The RRAM data storage element includes a dielectric resistive memory layer, which is insulating in its normal state. However, in some dielectric materials, if a sufficiently large initialization voltage is applied, defects such as oxygen vacancies may be formed. These defects cause the material to carry charge, and the charge moves within the dielectric material, so that the material has a non-zero conductivity. After the defect is initially formed, the memory layer can be switched between a conductive state and a basic insulating state by applying an appropriate voltage to the memory layer.

[0025] However, the resistance in the low resistance state may be different for different data storage elements. In a dielectric resistive memory layer, defects may form conductive filaments extending through the dielectric material. If the electric field applied during initialization is uniform, there is no preferred location for the formation of the conductive filaments, and multiple conductive filaments may be formed at different locations throughout the dielectric material. This may result in differences in resistance in different data storage elements. In addition, due to the varying number of conductive filaments, the switching voltage of the RRAM data storage element may also be different.

[0026] In view of the above, various examples of the present application are directed to data storage elements having bottom electrodes and top electrodes that are offset relative to each other. Due to the spatial offset between the bottom electrode and the top electrode, the data storage element has an asymmetric structure relative to the underlying contact. When a voltage is applied between the electrodes, the asymmetric structure produces an uneven electric field. Therefore, the formation of conductive filaments is promoted in certain areas, while their formation is hindered in other areas. This can allow for better control of the number of filaments, thereby reducing the differences in performance characteristics between different data storage elements. Other examples of the present application relate to a memory cell and a method of manufacturing a data storage element that solves similar problems.

[0027] Figure 1A A cross-sectional side view of a data storage element 100 according to some examples of the present disclosure is depicted; the data storage element 100 includes a data storage layer 102 configured to store data. The data storage layer 102 may, for example, include a resistive memory layer, wherein the data is encoded in the resistance of the resistive memory layer. The data storage layer 102 may, for example, include a phase change memory layer or a dielectric resistive memory layer, as described in more detail below.

[0028] The data storage layer 102 is arranged between the bottom electrode 104 and the top electrode 106. The upper surface of the bottom electrode 104 contacts the bottom surface of the data storage layer 102. The bottom surface of the top electrode 106 contacts the upper surface of the data storage layer 102. The elements can, for example, be in direct physical contact and / or electrical contact. In other examples, the elements can be in operational contact through a thin layer arranged therebetween, such as a thin conductive layer that provides electrical contact between the elements.

[0029] The bottom electrode 104 and / or the top electrode 106 include or consist of a conductive material, such as aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, silver, gold, or a combination thereof. The bottom electrode 104 and / or the top electrode 106 can be electrically coupled to other components, such as transistors, ground lines, bit lines, and / or word lines, for example, as described below with reference to Figure 3A , Figure 3B In some examples, the bottom surface of the top electrode 106 and the top surface of the bottom electrode 104 can be substantially parallel. The bottom surface of the top electrode 106 and / or the top surface of the bottom electrode 104 can be substantially flat surfaces.

[0030] The data storage layer 102, the bottom electrode 104, and / or the top electrode 106 may be surrounded by a dielectric layer 108 or embedded in the dielectric layer 108. The dielectric layer 108 may, for example, include or consist of silicon dioxide, silicon nitride, silicon carbide, a low-k dielectric, or a combination thereof. As used herein, a low-k dielectric may be, for example, a dielectric material having a dielectric constant k less than about 3.9, 3, 2, or 1. In some examples, the dielectric layer 108 may include two or more layers, such as a lower layer surrounding the bottom electrode 104 and an upper layer surrounding the top electrode 106 and / or the data storage layer 102, for example, as described below with reference to Figure 3A , Figure 3B In some examples, the dielectric layer 108 can be selected from an inter-layer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, and / or an etch stop layer of a semiconductor device.

[0031] The bottom surface of the top electrode 106 includes a portion 106A that does not overlap any portion of the upper surface of the bottom electrode 104 along a first direction parallel to the bottom surface of the top electrode 106. In some examples, the bottom surface of the top electrode 106 may also include a portion 106B that overlaps with the portion 104B along the first direction, such as Figure 1A As shown in the example of , that is, portion 106B is opposite to portion 104B in a direction perpendicular to the bottom surface of top electrode 106. In other words, the bottom surface of top electrode 106 may extend beyond first sidewall 104-I of bottom electrode 104 in a first direction, so that first sidewall 106-I of top electrode 106 is offset relative to first sidewall 104-I of bottom electrode 104. Figure 1A , the boundary between portion 106A and portion 106B is represented by a dashed line that continues with respect to first sidewall 104-I of bottom electrode 104. In some instances, portion 106B may account for no more than 60% of the surface area of ​​the bottom surface of top electrode 106, and in one instance no more than 40%. In one specific instance, portion 106B may account for about 50% of the surface area of ​​the bottom surface of top electrode 106. In some instances, portion 106B may account for at least 10% of the surface area of ​​the bottom surface of top electrode 106, and in one instance at least 20%. In other instances, the bottom surface of top electrode 106 may not have any overlap with the upper surface of bottom electrode 104 along the first direction, for example, as described below with reference to Figure 2A as described.

[0032] The upper surface of the bottom electrode 104 includes a portion 104A that does not overlap any portion of the bottom surface of the top electrode 106 along the first direction. In other words, the upper surface of the bottom electrode 104 may extend beyond the second sidewall 106-II of the top electrode 106 along the first direction, such that the second sidewall 104-II of the bottom electrode 104 is offset relative to the second sidewall 106-II of the top electrode 106. Figure 1A , the boundary between portion 104A and portion 104B is represented by a dashed line corresponding to the continuation of second sidewall 106-II of top electrode 106. In some examples, portion 104B may account for no more than 60% of the surface area of ​​the upper surface of bottom electrode 104, and in some examples no more than 40%. In one specific example, portion 104B may account for approximately 50% of the surface area of ​​the upper surface of bottom electrode 104. In some examples, portion 104B may account for at least 10% of the surface area of ​​the upper surface of bottom electrode 104, and in one example at least 20%.

[0033] The data storage layer 102 may be disposed on the bottom surface of the top electrode 106, for example, such that the data storage layer 102 covers or overlaps at least a portion of the portion 106A and at least a portion of the portion 106B. Thus, the data storage layer 102 may also cover at least a portion of the portion 104B of the upper surface of the bottom electrode 104. In some examples, the data storage layer 102 may cover or overlap at least a portion of the portion 104A of the upper surface of the bottom electrode 104. In some examples, the data storage layer 102 may cover or overlap the entire bottom surface of the top electrode 106 and / or the entire upper surface of the bottom electrode 104.

[0034] In some examples, the data storage layer 102 may include a resistive memory layer. In addition to the resistive memory layer, the data storage layer 102 may include other layers, such as a top metal layer and / or a bottom metal layer, for example, as described below with reference to Figure 2DAs described in detail. The resistive memory layer may include or consist of a material having a switchable resistance. The resistive memory layer may, for example, present a high resistance state and a low resistance state. Therefore, the state of the resistive memory can be used to encode a data bit. In some instances, the resistive memory layer may be a dielectric resistive memory layer. The dielectric resistive memory layer includes or consists of a dielectric material having a high resistance state and a low resistance state, in which the resistive memory layer is substantially insulated in the high resistance state, and in the low resistance state, the resistive memory layer is conductive. The dielectric material may, for example, include or consist of an oxide, such as hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), tantalum oxide (e.g., Ta2O5), niobium oxide (e.g., Nb2O5), vanadium oxide (e.g., Va2O5), titanium oxide (e.g., TiO2), titanium tantalum oxide, aluminum hafnium oxide, hafnium tantalum oxide, tantalum aluminum oxide, or a combination thereof. A change of state of the dielectric resistive memory layer may be induced, for example, by applying a voltage to the resistive memory layer, for example, between the bottom electrode 104 and the top electrode 106 .

[0035] exist Figure 1B , a data storage element 100 is shown in which the dielectric resistive memory layer is in a low resistance state. On the other hand, Figure 1A The illustration may correspond to a data storage element 100 in which the dielectric resistive memory layer is in a high resistance state. In the low resistance state, there may be defects such as vacancies in the dielectric resistive memory layer, such as oxygen vacancies in an oxide. The defect may be located, for example, in a conductive filament 110 that extends across the thickness of the dielectric resistive memory layer, such as from the top electrode 106 to the bottom electrode 104, or from the top metal layer to the bottom metal layer of the data storage layer 102. The filament 110 may be initially formed, for example, by applying an initialization voltage to the dielectric resistive memory layer. The initialization voltage may be, for example, between about 1.5V and about 3V, and after the initial formation, the filament 110 may be, for example, disconnected or reset by a reset voltage, and reformed or set by a set voltage to transfer data to the data storage layer 102. The set voltage may be less than the initialization voltage, and may be, for example, between about 0.5V and about 2V.

[0036] When a voltage is applied between the bottom electrode 104 and the top electrode 106, the electric field in the data storage layer 102 may be non-uniform due to the partial overlap between the bottom electrode 104 and the top electrode 106. In some instances, the electric field near the edge of the connecting portion 104B of the bottom electrode 104 and the sidewall 104-I may be stronger than the electric field in other portions of the data storage layer 102 that are farther from the edge. Thus, the asymmetric arrangement of the top electrode 104 and the bottom electrode 106 in the data storage element 100 may facilitate the formation of a conductive filament near the edge of the bottom electrode 104, or more generally, may facilitate the control of the position of the conductive path passing through the data storage layer 102. In some instances, a single conductive filament may be formed. This may reduce the difference in performance characteristics between different data storage elements. The asymmetric arrangement may, for example, cause the resistance, set voltage, and / or reset voltage in the low resistance state to vary less.

[0037] Figure 2A-2D 1 and 2. The cross-sectional side views of data storage elements 200, 210, 220, and 230 are shown, respectively, according to some examples of the present disclosure. The data storage elements 200, 210, 220, 230 are similar to Figure 1A , Figure 1B The data storage element 100 also includes a data storage layer 102 disposed between a bottom electrode 104 and a top electrode 106. The data storage layer 102 includes a dielectric resistive memory layer. Figure 2A-2D In FIG. 1 , the data storage layer 102 is depicted in a low resistance state with conductive filaments 110 formed therein extending through the dielectric resistive memory layer.

[0038] In some instances, such as Figure 2A As shown, the bottom surface of the top electrode 106 does not overlap with the upper surface of the bottom electrode 104 along a first direction parallel to the bottom surface of the top electrode 106. In other words, the portion 106A that does not overlap with any portion of the upper surface of the bottom electrode 104 may cover the entire bottom surface area of ​​the top electrode. The portion 104A that does not overlap with any portion of the bottom surface of the top electrode 106 may cover the entire upper surface area of ​​the bottom electrode 104. The filaments 110 may extend between opposite edges of the bottom electrode 104 and the top electrode 106, respectively, as shown in FIG. Figure 2A shown.

[0039] In some instances, such as Figure 2A-2DAs shown, the data storage layer 102 may surround the bottom surface of the top electrode 106 and at least a portion of the sidewalls of the top electrode 106. The data storage layer 102 may, for example, surround the bottom surface and at least a portion of the sidewalls 106-I, 106-II, that is, the data storage layer 102 may cover the entire bottom surface and may extend along all or a portion of the sidewalls 106-I, 106-II. The data storage layer 102 may also surround at least a portion of the sidewalls of the top electrode 106 connecting the sidewalls 106-I and 106-II, for example, parallel to the Figure 2A-2D The data storage layer 102 may be formed to conformally surround the top electrode 106, for example.

[0040] refer to Figure 2B In the data storage element 210 of the embodiment of the present invention, the bottom surface of the data storage layer 102 may include a protrusion 102A extending along at least a portion of the sidewall (e.g., the sidewall 104-I) of the bottom electrode 104. Therefore, a portion of the data storage layer 102 may extend into the dielectric layer 108 or a sublayer thereof below the upper surface of the bottom electrode 104. Thus, the data storage layer 102 may surround the edge between the sidewall 104-I and the upper surface of the bottom electrode 104. In some examples, the protrusion 102A may be in direct contact with the sidewall 104-I.

[0041] In some examples, at least one sidewall of the bottom electrode 104 is tapered, such as the sidewall 104-I. The tapered sidewall 104-I can form an acute angle α with the upper surface of the bottom electrode 104 at the edge of the bottom surface of the bottom electrode 104 facing the top electrode 106. The angle α can be, for example, between about 70° and about 85°. In some examples, without being bound by any theory, the acute angle α can cause a stronger electric field to be generated near the edge of the bottom electrode 104, thereby promoting the formation of the filament 110 between the edge of the bottom electrode and the bottom surface of the top electrode 106.

[0042] In some examples, at least one sidewall of the top electrode 106 is tapered, such as sidewall 106-II. The tapered sidewall 106-II may form an obtuse angle α with the bottom surface of the top electrode 106 at the edge of the top electrode 106 facing the upper surface of the bottom electrode 104. The angle α may be, for example, between about 95° and about 110°. In some examples, without being bound by any theory, the obtuse angle α may cause a weaker electric field to be generated near the edge of the top electrode 106, thereby hindering the formation of a conductive filament between the edge of the top electrode 106 and the upper surface of the bottom electrode 104. In some such examples, the absolute value of the slope of the tapered sidewall 106-II is less than the absolute value of the slope of the sidewall 104-I.

[0043] In other examples, at least one sidewall of the bottom electrode 104 is tapered, such as the sidewall 104-I, and at least one sidewall of the top electrode 106 is tapered, such as the sidewall 106-II. Figure 2B As shown. In addition, in one example, all sidewalls of the bottom electrode and the top electrode can be tapered. Additionally or alternatively, one or more edges of the top electrode 106 and / or the data storage layer 102, in particular the edge of the top electrode 106 facing the upper surface of the bottom electrode 104 can be rounded, for example, as described below with reference to Fig.10 as described.

[0044] In some examples, the bottom surface of the top electrode 106 may not be a flat surface. The bottom surface of the top electrode 106 may include, for example, a protrusion 106C extending toward the bottom electrode 104, for example, Figure 2C The data storage element 220 of the embodiment of the present invention. The protrusion 106C may be, for example, aligned with the portion 106A or partially aligned, i.e., may not overlap any portion of the upper surface of the bottom electrode 104. The filament 110 may be, for example, formed between an edge of the protrusion 106C and an opposite edge of the bottom electrode 104, such as Figure 2C In some examples, the protrusion 106C may extend to a depth substantially aligned with the upper surface of the bottom electrode 104, such as Figure 2C In other examples, the center of the protrusion 106C may be substantially aligned with the edge of the bottom electrode 104 in the first direction. The distance between the upper surface of the bottom electrode 104 and the protrusion 106C may be less than the distance between the upper surface of the bottom electrode 104 and any other portion of the bottom surface of the top electrode 106.

[0045] Additionally or alternatively, the bottom surface of top electrode 106 can include a groove, for example, in portion 106B. In some examples, an edge of top electrode 106 facing bottom electrode 104 can be recessed relative to a portion of the edge of the bottom surface of top electrode 106 facing bottom electrode 104. A distance between bottom electrode 104 and an edge of top electrode 106 facing bottom electrode 104 can be less than a distance between top electrode 106 and an edge of bottom electrode 104 facing top electrode 106.

[0046] In some examples, the data storage layer 102 may include other layers in addition to the resistive memory layer, such as in Figure 2D In the data storage element 230 shown. Figure 2DIn an example of the present invention, the data storage layer 102 includes a bottom metal layer 232, a resistive memory layer 234, and a top metal layer 236. The resistive memory layer 234 may be, for example, arranged between the top metal layer 236 and the bottom metal layer 232. The top metal layer 236 may, for example, be in direct contact or operational contact with the bottom surface of the top electrode 106, and the bottom metal layer 232 may, for example, be in direct contact or operational contact with the upper surface of the bottom electrode 104. Each of the top metal layer 232 and the bottom metal layer 236 may, for example, include or consist of platinum, ruthenium, tantalum nitride, titanium nitride, iridium, tungsten, aluminum, copper, silver, gold, or a combination thereof. In some examples, the data storage layer 102 may include a barrier layer (not shown), for example, between the resistive memory layer 234 and one of the top metal layer 232 and the bottom metal layer 236. The barrier layer may include or consist of, for example, aluminum (e.g., Al2O3), hafnium (e.g., HfO2), zirconium (e.g., ZrO2), lanthanum, tantalum, titanium, or a combination thereof. The barrier layer may have a lower oxygen concentration than the resistive memory layer 234, and may have a higher oxygen reactivity than the top metal layer 232 and / or the bottom metal layer 236.

[0047] Although Figure 2D The data storage layer of FIG. 5 is shown as having other layers in addition to the resistive memory layer, but it should be understood that in some embodiments, Figure 1A-1B and Figure 2A-2C The data storage layer of the embodiment may also have other layers in addition to the resistive memory layer (e.g., a resistive memory layer disposed between the bottom metal layer and the top metal layer). In some such embodiments (e.g., corresponding to Figure 1A-1B The bottom metal layer, the resistive memory layer, and the top metal layer may include substantially planar layers such that a bottom of the resistive memory layer is above a top of the bottom metal layer, and a bottom of the top metal layer is above a top of the resistive memory layer. Figure 2A-2C The bottom metal layer and the top metal layer may be arranged along the vertically and horizontally extending surfaces of the resistive memory layer. Figure 2B-2C The bottom metal layer, the resistive memory layer, and the top metal layer may respectively have protrusions extending outward from the lower surface, so that one or more of the bottom metal layer, the resistive memory layer, and the top metal layer extend below the top of the bottom electrode 104 along the sidewall of the bottom electrode 104.

[0048] Figure 3A and Figure 3B A schematic diagram of a memory cell 300 according to some examples of the present disclosure is shown. Figure 3A depicts a top view of a memory cell 300, Figure 3B Depicts the memory cell along Figure 3A Cross-sectional side view of midline AA.

[0049] The memory cell 300 may include a substrate 302, which may be, for example, a bulk substrate, such as a bulk silicon substrate or a silicon-on-insulator substrate. The substrate 302 may include an active region 304 in which a transistor including a first source / drain (S / D) region 304A and a second S / D region 304B is arranged. The active region 304 and / or the substrate 302 may be doped to have a first conductivity type, and the first S / D region 304A and the second S / D region 304B may be doped to have a second conductivity type opposite to the first conductivity type. In some examples, the active region 304 may be a planar structure of a planar field effect transistor, such as, for example, Figure 3A As shown. In other embodiments (not shown), the active area 304 may include a fin structure of a field effect transistor (finFET). The active area 304 may be surrounded by a shallow trench isolation (STI) region 306, which may, for example, include or consist of a dielectric material arranged in a trench in the substrate 302. The dielectric material may, for example, include or consist of silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof. Above the active area 304, one or more layers may be provided, such as a lower etch stop layer or contact etch stop layer (CESL) 308 and a first dielectric layer 310. The lower etch stop layer 308 may, for example, include or consist of silicon carbide, silicon nitride, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, silicon dioxide, a low-k dielectric, or a combination thereof. The dielectric layer 310 may, for example, include or consist of silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof.

[0050] The gate structure 312 is arranged on top of the channel region of the transistor between the first S / D region 304A and the second S / D region 304B in the active region 304. The gate structure 312 may be, for example, a gate stack including a gate dielectric and a gate electrode. The gate dielectric may, for example, include or consist of silicon dioxide, a high-k dielectric material (e.g., hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, or strontium titanate), aluminum oxide (e.g., Al2O3), or a combination thereof. The gate electrode may, for example, include or consist of doped polysilicon or a metal such as aluminum, copper, tungsten, or a combination thereof. The gate structure 312 may be surrounded by a dielectric spacer 314, which may, for example, include or consist of silicon oxide, silicon nitride, silicon carbide, or a combination thereof. An intermediate etch stop layer (MESL) 316 may be disposed over the gate structure 312 , wherein the MESL 316 may include or consist of silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, silicon oxide, low-k dielectric, or a combination thereof.

[0051] The memory cell 300 also includes a first middle-of-line (MEOL) structure 318 in the first dielectric layer 310. The first MEOL structure 318 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. The first MEOL structure 318 is electrically coupled to the first S / D region 304A of the transistor. The first MEOL structure 318 may, for example, extend through the CESL 308, the first dielectric layer 310, and the MESL 316. The memory cell 300 also includes a first via 320 in a second dielectric layer 322 above the first dielectric layer 310. The first via 320 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. The second dielectric layer 322 may, for example, be disposed on top of the MESL 316. The second dielectric layer 322 may, for example, include or consist of silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof.

[0052] The first MEOL structure 318 and the first through hole 320 form the bottom electrode and the top electrode of the data storage element 324, respectively, and the data storage element 324 includes a data storage layer 326, and the data storage layer 326 is disposed between the top surface of the first MEOL structure 318 and the bottom surface of the first through hole 320. By using the first MEOL structure as the bottom electrode, adjacent memory devices can be formed with a relatively small pitch, and a high-density array can be achieved. In some examples, the data storage element 324 can be similar to one or more of the data storage elements 100, 200, 210, 220, and 230 described above. Therefore, the data storage layer 326 can be similar to the data storage layer 102, and can, for example, include a resistive memory layer, such as a dielectric resistive memory layer as described above. In some examples, the data storage layer 102 can extend into the MESL 316, such as similar to the data storage elements 210 and 220. In some examples, the bottom surface of the first through hole 320 can include a protrusion (not shown) extending toward the top surface of the first MEOL structure 318, such as similar to the data storage element 220. Additionally or alternatively, at least one sidewall of the first MEOL structure 318 and / or at least one sidewall of the first through hole 320 may be tapered, for example, as described above with reference to Figure 2B as described.

[0053] The top surface of the first MEOL structure 318 extends from the first edge 318-I to the second edge 318-II along a first direction. In some examples, the first direction can be parallel to a channel of the transistor extending from the second S / D region 304B to the first S / D region 304A, which can be, for example, Figure 3AIn other examples, the first direction may be, for example, perpendicular to the channel of the transistor. The bottom surface of the first through hole 320 extends from the third edge 320-I to the fourth edge 320-II along the first direction. The fourth edge 320-II is offset relative to the second edge 318-II in the first direction. Thus, the data storage element 324 can be asymmetric relative to a plane perpendicular to the first direction. In some examples, at least a portion of the bottom surface of the first through hole 320 can extend beyond the second edge 318-II in the first direction, such as Figure 3A In some examples, the fourth edge 320-II may be offset relative to the second edge 318-II in the first direction so that the bottom surface of the first through hole 320 spans the first edge 318-I or the second edge 318-II.

[0054] In some examples, the third edge 320-I can be offset relative to the first edge 318-I in the first direction. Thus, at least a portion of the top surface of the first MEOL structure 318 can extend beyond the third edge 320-I in a direction opposite to the first direction, such as Figure 3A In some embodiments, the third edge 320 -I may be offset beyond the second edge 318 -II, ie, similar to the data storage element 200 , the bottom surface of the first through hole 320 may not overlap with the top surface of the first MEOL structure 318 .

[0055] In some embodiments, source lines SL including first interconnects are coupled to the second S / D region 304B, word lines WL including second interconnects are coupled to the gate structure 312, and bit lines BL including third interconnects are coupled to the first vias 320. By selectively applying bias voltages to the bit lines BL, source lines SL, and / or word lines WL, data may be read from and / or written to the data storage layer 326. For example, a bias voltage may be applied to the word lines WL to form a conductive channel under the gate structure 312, thereby allowing the voltages applied by the source lines SL and the bit lines BL to form a potential difference on the data storage layer 326.

[0056] In some embodiments, to read data from the data storage layer 326, the source line SL and the bit line BL may apply a first set of bias conditions to the first MEOL structure 318 (e.g., the lower electrode) and the first via 320 (e.g., the upper electrode). The first set of bias conditions causes a current to pass through the data storage layer 326, which indicates the data state stored by the data storage layer 326. To write a low resistance state within the data storage layer 326, the source line SL and the bit line BL may apply a second set of bias conditions to the first MEOL structure 318 (e.g., the lower electrode) and the first via 320 (e.g., the upper electrode). The second set of bias conditions may form an electric field that causes oxygen to flow from the data storage layer 326 to the first via 320 (e.g., the upper electrode), thereby forming a conductive filament of oxygen vacancies in the data storage layer 326. Alternatively, to write a high resistance state within the data storage layer 326, the source line SL and the bit line BL may apply a third set of bias conditions to the first MEOL structure 318 (e.g., the lower electrode) and the first via 320 (e.g., the upper electrode). The third set of bias conditions may form an electric field that breaks the conductive filament by causing oxygen to flow from the first via 320 (eg, upper electrode) to the data storage layer 326 .

[0057] When a voltage is applied between the first MEOL structure 318 and the first through hole 320, the electric field in the data storage layer 326 may be non-uniform due to the spatial offset between the second edge 318-II and the fourth edge 320-II. In some instances, the electric field near the second edge 318-II of the first MEOL structure 318 may be stronger than the electric field in other portions of the data storage layer 326 that are farther from the edge 318-II. Thus, the asymmetric arrangement of the first MEOL structure 318 and the first through hole 320 in the data storage element 324 may facilitate the formation and spatial control of the conductive filament near the second edge 318-II. In some instances, a single conductive filament may be formed. This may reduce the difference in performance characteristics between different memory cells. The asymmetric arrangement may, for example, result in smaller changes in resistance, set voltage, and / or reset voltage in the low resistance state.

[0058] In some examples, the memory cell 300 may further include a second MEOL structure 328 in the first dielectric layer 310. The second MEOL structure 328 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. The second MEOL structure 328 is electrically coupled to the second S / D region 304B. Similar to the first MEOL structure 318, the second MEOL structure 328 may, for example, extend through the CESL 308, the first dielectric layer 310, and the MESL 316.

[0059] In some examples, the memory cell 300 may also include a second via 330 in the second dielectric layer 322, wherein the second via 330 is electrically coupled to the second MEOL structure 328. The second via 330 may, for example, provide an electrical connection between the second S / D region 304B and the bit line BL to read data from the memory cell 300 and / or write data to the memory cell 300. The center of the bottom surface of the second via 330 may be aligned with the center of the top surface of the second MEOL structure 328 along at least the first direction, i.e., the second MEOL structure 328 and the second via 330 may form a symmetrical structure with respect to a plane perpendicular to the first direction, such as Figure 3A and Figure 3B As shown in the example.

[0060] In some examples, the memory cell 300 may further include a third through hole or gate through hole 332 electrically coupled to the gate structure 312. The gate through hole 332 may, for example, extend through the dielectric spacer 314 and / or the second dielectric layer 322. The gate through hole 332 may, for example, provide an electrical connection between the gate structure 312 and the word line WL for addressing the memory cell 300. The gate through hole 332 may, for example, be arranged such that the gate through hole 332 does not overlap with the active area 304, i.e., is located outside the active area 304. Figure 3A In some embodiments, the gate via 332 may have a top surface that is substantially aligned with the top surfaces of the first MEOL structure 318 and the second MEOL structure 328 .

[0061] In some examples, the second through-hole 330 may be offset relative to the first through-hole 320 in a second direction perpendicular to the first direction. Figure 4A and Figure 4B An example of this is depicted in , which shows top views of memory cells 400 and 410, respectively. Memory cells 400, 410 can be similar to memory cell 300 described above. In some examples, the first direction can be parallel to a channel of the transistor, which can be, for example, parallel to the channel of the transistor. Figure 4A , Figure 4B In some examples, the second through hole 330 can be offset so that the second through hole 330 does not overlap with the first through hole 320 along the second direction, such as Figure 4A and Figure 4B This can create space for a cover window between the first through hole 320 and the second through hole 330, as shown in the memory cell 400. In other examples, the gate through hole 332 can be arranged between the first through hole 320 and the second through hole 330, as shown in the memory cell 400. Figure 4B shown.

[0062] Figure 5A flow chart of a method 500 for manufacturing a data storage element according to some examples of the present disclosure is shown. Although this method and other methods shown and / or described in this application are shown as a series of steps or events, it should be understood that the present disclosure is not limited to the order or steps shown. Therefore, in some examples, these steps can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some examples, the steps or events shown can be subdivided into multiple steps or events, which can be performed at different times or simultaneously with other steps or sub-steps. In some examples, some of the steps or events shown can be omitted, and other steps or events not shown can be included.

[0063] In the following, the method 500 is described using the memory cell 300 having the data storage element 324 as an example. Figure 6A-6F A cross-sectional side view of workpiece 300A at various stages of fabrication is shown. However, method 500 is not limited to this example, and it should be understood that method 500 may also be used to fabricate other data storage elements and / or memory cells including data storage elements, such as data storage elements 100, 200, 210, 220, and 230 and / or memory cells 400, 410, 900, and 1000 described herein.

[0064] The method 500 includes, in step 502, providing a substrate having a dielectric layer above a first conductive structure. In this example, the first conductive structure may correspond to the first MEOL structure 318, and thus the first MEOL structure 318 is also referred to as the first conductive structure 318 hereinafter. In this example, the dielectric layer above the first conductive structure 318 may correspond to the second dielectric layer 322, and thus the second dielectric layer 322 is also referred to as the dielectric layer 322 hereinafter. In other examples, the first conductive structure and the dielectric layer may correspond to the bottom electrode 104 and the dielectric layer 108 of one of the data storage elements 100, 200, 210, 220, and 230, respectively. The first conductive structure 318 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. The second dielectric layer 322 may, for example, include or consist of silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof.

[0065] The dielectric layer 322 covers the first conductive structure 318, such as Fig. 6A As shown. The dielectric layer 322 may be used, for example, as a passivation layer to protect the first conductive structure 318. In addition, the workpiece 300A may include Fig. 6AOther elements are shown, such as an active region 304 having a first S / D region 304A and a second S / D region 304B, an STI region 306, one or more of layers 308, 310, 316, a gate structure 312, a dielectric spacer 314, and / or a third conductive structure 328 which may correspond to a second MEOL structure 328. In some examples, Figure 6A-6F in Figure 3B Elements marked with the same reference numerals in FIG. 3 may correspond to corresponding elements of the memory unit 300 . In this regard, reference is made to the above description.

[0066] In some examples, method 500 may include, at step 504, forming an opening 604 in dielectric layer 322, the opening 604 exposing at least a portion of an upper portion or top surface of third conductive structure 328. This may, for example, include depositing and patterning a first mask layer 602 on dielectric layer 322, and performing a first etch using first mask layer 602 as a mask, such as Figure 6B As shown. The first mask layer 602 may, for example, include or consist of a photoresist and / or a hard mask material, such as silicon oxynitride, silicon nitride, or silicon dioxide. The first etch may, for example, be a unidirectional or vertical etch. The first etch may remove the exposed portion of the dielectric layer 322. In some examples, the first etch may stop at the upper surface of the third conductive structure 328 and / or the intermediate etch stop layer 316. The center of the opening 604 may be aligned with the center of the upper surface of the third conductive structure 328, such as Figure 6B shown.

[0067] In some examples, the method 500 may include, at step 506, forming a conductive structure, such as the second via 330, in the opening 604. Figure 6C As shown, this may include, for example, depositing a conductive layer 606 within the opening 604 and on the dielectric layer 322 by atomic layer deposition, chemical vapor deposition, plasma vapor deposition, spin coating, or a combination thereof. The conductive layer 606 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. In some examples, this may also include removing portions of the conductive layer 606 outside of the opening 604, such as Fig.6D The portion of the conductive layer 606 outside the opening 604 may be removed, for example, by planarization, which may include, for example, chemical mechanical polishing.

[0068] In step 508, the method 500 also includes forming an offset opening 610 in the dielectric layer 322, in this example, the offset opening 610 exposes a portion of the upper surface or top surface of the first conductive structure 318. The center of the offset opening 610 is offset from the center of the upper surface of the first conductive structure 318 in a first direction parallel to the upper surface of the first conductive structure 318. In some examples, the exposed portion may account for no more than 65% of the surface area of ​​the upper surface of the first conductive structure 318, and in one example no more than 45%. In some examples, the exposed portion may account for at least 5% of the surface area of ​​the upper surface of the first conductive structure 318, and in one example at least 15%. Forming the offset opening 610 may, for example, include depositing and patterning a second mask layer 608 on the dielectric layer 322, and performing a second etch using the second mask layer 608 as a mask, such as Fig. 6E As shown. The second mask layer may, for example, include or consist of a photoresist and / or a hard mask material, such as silicon oxynitride, silicon nitride, or silicon dioxide. The second etch may, for example, be a unidirectional or vertical etch. The second etch may remove the exposed portion of the dielectric layer 322.

[0069] In some examples, the second etch may stop at the upper surface of the first conductive structure 318. In other embodiments, the second etch may extend below the upper surface of the conductive structure 318. In some embodiments, the second etch may etch the second conductive structure 318 not covered by the dielectric layer 322 to reduce the height of the portion of the second conductive structure 318 that defines the offset opening 610. In such embodiments, the second etch causes the conductive structure 318 to have a stepped structure, the stepped structure including an upper surface that defines the offset opening 610 and is recessed below the top surface of the conductive structure 318 (which is covered by the dielectric layer 322). In some examples, the sidewalls of the offset opening 610 may be tapered. The tapered sidewalls may form an obtuse angle with the bottom wall of the offset opening 610, such as an angle between about 95° and about 110°, for example to form a data storage element, similar to Figure 2B In some examples, for example, by selecting an appropriate etching chemistry and / or the width of the offset opening 610, the bottom edge of the offset opening 610 can be rounded, for example, as described below with reference to Fig.10 as described.

[0070] In some examples, the first conductive structure 318 can be disposed in a dielectric layer or etch stop layer 316 hereinafter. Thus, the offset opening 610 can expose a portion of the upper surface of the etch stop layer 316 adjacent to the first conductive structure 318. In some examples, the second etch can stop at the upper surface of the etch stop layer 316. In other examples, the second etch can include an overetch that at least partially removes the exposed portion of the intermediate etch stop layer 316. Thus, as shown in FIG. Fig. 6EAs shown, the offset opening 610 may extend below the upper surface of the first conductive structure 318 into the etch stop layer 316 , for example, to form a data storage element, similar to the data storage element 210 described above.

[0071] In step 510, a data storage layer 612 is formed in the offset opening 610. The data storage layer 612 may, for example, include a resistive memory layer, such as described above with reference to Figure 1A , Figure 1B The dielectric resistive memory layer described. The resistive memory layer may, for example, include or consist of an oxide, such as hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), tantalum oxide (e.g., Ta2O5), niobium oxide (e.g., Nb2O5), vanadium oxide (e.g., Va2O5), titanium oxide (e.g., TiO2), titanium tantalum oxide, aluminum hafnium oxide, hafnium tantalum oxide, tantalum aluminum oxide, or a combination thereof. The data storage layer 612 may also include other layers, for example, as described above with reference to Figure 2D The bottom metal layer, the top metal layer and / or the barrier layer are described in detail. The data storage layer 612 can be formed, for example, by atomic layer deposition, chemical vapor deposition, plasma vapor deposition, spin coating, or a combination thereof. The data storage layer 612 can be conformally deposited on the bottom wall and the sidewalls of the opening, that is, so that the data storage layer 612 has a substantially uniform thickness. In some examples, the data storage layer 612 can also be deposited over the top surface of the dielectric layer 322, such as Fig. 6F shown.

[0072] The method 500 also includes, in step 512, forming a second conductive structure in the offset opening 610 above the data storage layer 612. The second conductive structure can be, for example, the first through hole 320 of the memory cell 300, and therefore the first through hole 320 is also referred to as the second conductive structure 320 in the following. The second conductive structure 320 can be formed, for example, by depositing a conductive layer 614 on the data storage layer 612, for example, by atomic layer deposition, chemical vapor deposition, plasma vapor deposition, spin coating, or a combination thereof. The conductive layer 614 can, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof. In some examples, the method 500 may also include removing a portion of the data storage layer 612 and / or the conductive layer 614 outside the offset opening 610, for example by planarization, thereby producing Figure 3A , 3B Memory cell 300 is shown.

[0073] In some examples, the second conductive structure 320 may be formed such that the sidewalls of the second conductive structure 320 are offset from the sidewalls of the first conductive structure 318 in the first direction. To this end, the offset of the center of the offset opening 610 relative to the center of the upper surface of the first conductive structure 318 and / or the thickness of the data storage layer 612 may be adjusted accordingly. Thus, the respective edges of the first conductive structure 318 and the second conductive structure 320 may be offset relative to each other, for example, as Figure 3A , 3B At least a portion of the bottom surface of the second conductive structure 320 may not overlap any portion of the upper surface of the first conductive structure 318 along the first direction, for example, similar to the data storage element 100 described above.

[0074] The thickness of the data storage layer 612 can be adjusted based on the desired structure of the data storage element to be formed, for example by adjusting the deposition or growth time accordingly. In some examples, the thickness of the data storage layer 612 can be selected so that the bottom surface of the second conductive structure 320 does not overlap with the upper surface of the first conductive structure 318, similar to Figure 2A In some examples, the offset opening 610 can extend into the etch stop layer 316, and the thickness of the data storage layer 612 can be selected to be large enough so that the data storage layer 612 on the bottom and side walls of the portion of the offset opening 610 in the etch stop layer 316 is combined into a continuous protrusion, similar to Figure 2B The data storage element 210 is formed in the form of a plurality of data storage elements 210. Thus, the upper surface or top surface of the data storage layer 612 in the deviated opening 610 can be substantially flat, and the second conductive structure 320 can then be formed thereon. In other examples, the thickness of the data storage layer 612 can be selected to be sufficiently small so that the top surface of the data storage layer 612 includes a recess for forming a protrusion of the second conductive structure 320, which extends toward the first conductive structure 318, similar to Figure 2C The data storage element 220 is provided.

[0075] Figure 7 A flow chart of a method 700 of manufacturing a data storage element according to some examples of the present disclosure is shown. Fig. 9 The method 700 is described using a memory cell 900 of FIG. 1 (see below) as an example. Figure 8A-8F A cross-sectional side view of workpiece 900A is shown at various stages of fabrication. However, method 700 is not limited to this example, and it should be understood that method 700 may also be used to fabricate other data storage elements and / or memory cells including data storage elements, such as data storage elements 100, 200, 210, 220, and 230 and / or memory cells 300, 400, 410, and 1000 described herein.

[0076] The method 700 includes providing a substrate having a first conductive structure in step 702. In this example, the first conductive structure may correspond to the first MEOL structure 318, and therefore the first MEOL structure 318 is also referred to as the first conductive structure 318 hereinafter. In other examples, the first conductive structure may correspond to the bottom electrode 104 of one of the data storage elements 100, 200, 210, 220, and 230. The first conductive structure 318 may, for example, include or consist of aluminum, copper, tungsten, tantalum nitride, titanium nitride, platinum, iridium, ruthenium, or a combination thereof.

[0077] In some examples, workpiece 900A may include Fig. 8A Other elements are shown, such as an active region 304 having a first S / D region 304A and a second S / D region 304B, an STI region 306, one or more of layers 308, 310, 316, a gate structure 312, a dielectric spacer 314, and / or a third conductive structure 328 which may correspond to a second MEOL structure 328. In some examples, Figure 8A-8F in Figure 3B Elements marked with the same reference numerals in FIG. 3 may correspond to corresponding elements of the memory unit 300. In this regard, reference is made to the above description.

[0078] In step 704, a data storage layer 612 and a conductive layer 614 are deposited on the substrate. The data storage layer 612 can be formed on the upper surface of the first conductive structure, for example, similar to that described above with respect to step 510 of method 500. The data storage layer 612 can be deposited with a substantially uniform thickness. In some examples, the data storage layer 612 can be deposited above the intermediate etch stop layer 316, for example, as Figure 8B As shown. In some examples, the first conductive structure 318 provided in step 702 can be covered by a protective layer, such as a passivation layer. Step 704 can include, before forming the data storage layer 612, at least partially removing the protective layer to expose a portion of the upper surface of the first conductive structure 318. After forming the data storage layer 612, a conductive layer 614 is formed over the data storage layer 612, for example similar to that described above with respect to step 512 of method 500. The data storage layer 612 can be deposited with a substantially uniform thickness. The thickness of the conductive layer 614 can be greater than the thickness of the data storage layer 612, for example, between two and ten times the thickness of the data storage layer 612. In some examples, the conductive layer 614 can be deposited over the entire upper surface of the data storage layer 612, for example, as Figure 8B shown.

[0079] Subsequently, in step 706, the data storage layer 612 and the conductive layer 614 are patterned to form an offset structure including the patterned data storage layer 326 and the second conductive structure. The second conductive structure can be, for example, the first through hole 320 of the memory cell 900, so the first through hole 320 is also referred to as the second conductive structure 320 below. Step 706 can, for example, include depositing and patterning a mask layer 802 on the conductive layer 614, and performing a first etch using the mask layer 802 as a mask, such as Figure 8B and Figure 8C As shown. Mask layer 802 may, for example, include or consist of a photoresist and / or a hard mask material, such as silicon oxynitride, silicon nitride, or silicon dioxide. The first etch may, for example, be a unidirectional or vertical etch. The first etch may remove exposed portions of layers 612, 614. In some examples, the first etch may stop at the top surface of first conductive structure 318 and / or intermediate etch stop layer 316. The center of data storage layer 326 and the center of second conductive structure 320 are offset from the center of the top surface of first conductive structure 318 in a first direction parallel to the top surface of first conductive structure 318, as shown. Figure 8C In some embodiments, the first etch may cause the patterned data storage layer 326 and the first through hole 320 to have angled sidewalls, which makes the patterned data storage layer 326 and the first through hole 320 narrower as the distance from the substrate 302 increases.

[0080] In some examples, performing the first etch may include performing a lateral overetch on the sidewalls of the second conductive structure 320 and / or the data storage layer 326, for example, to form a Figure 2B In some examples, different etching processes and / or mask layers can be used to pattern the data storage layer 612 and the conductive layer 614, respectively. In one example, an additional etching process is performed after depositing the data storage layer 612 and before depositing the conductive layer 614 to form a recess (not shown) in the data storage layer 612. Subsequently, before performing the first etching as described above, the conductive layer 614 is deposited over the data storage layer 612, for example, so that the data storage layer 326 surrounds the bottom surface and sidewalls of the second conductive structure 320, as shown in FIG. Figure 3B As shown in the example.

[0081] The method 700 may further include, at step 708, forming a dielectric layer over the first conductive structure 318 and / or over the intermediate etch stop layer 316, such as Fig.8DAs shown. The dielectric layer above the first conductive structure 318 may correspond to the second dielectric layer 322 of the memory cell 900, so hereinafter, the dielectric layer above the first conductive structure 318 is also referred to as the dielectric layer 322. The second dielectric layer 322 may, for example, include or consist of silicon dioxide, silicon nitride, a low-k dielectric, or a combination thereof. The dielectric layer 322 may, for example, be formed by atomic layer deposition, chemical vapor deposition, plasma vapor deposition, spin coating, or a combination thereof. Step 708 may also include planarizing the dielectric layer 322, for example, by chemical mechanical polishing, for example, to remove a portion of the dielectric layer 322 above the second conductive structure 320, so that the upper surface of the dielectric layer 322 is substantially flush with the upper surface of the second conductive structure 322, as shown. Fig.8D shown.

[0082] Subsequently, in step 710, in some examples, for example, as described above with respect to step 504 of method 500, an opening 604 can be formed in dielectric layer 322. This can specifically include depositing and patterning a first mask layer 602 on dielectric layer 322, and performing a second etch using the first mask layer 602 as a mask, such as Fig. 8E shown.

[0083] In some examples, the method 700 may further include, at step 712, forming a conductive structure, such as the second via 330, in the opening 604. Figure 8F As shown, this may include depositing a conductive layer 606 on the dielectric layer 322, for example similar to step 506 of method 500. In some examples, this may also include removing a portion of the conductive layer 606 outside of the opening 604, for example by chemical mechanical polishing, to obtain Fig. 9 The memory cell 900 shown in FIG.

[0084] Fig. 9 A schematic diagram of a memory cell 900 according to some examples of the present disclosure is shown in a cross-sectional side view. The memory cell 900 is similar to Figure 3A , 3B Memory cell 300. Therefore, Fig. 9 in Figure 3B Elements marked with the same reference numerals in the memory cell 900 may be similar to or correspond to corresponding elements of the memory cell 300. In this regard, reference is made to the above description. In a top view, the memory cell 900 may also be similar to the memory cell 300, i.e. Fig. 9 The memory cell 900 may correspond to Figure 3A Cross-sectional side view along line AA.

[0085] Memory cell 900 differs from memory cell 300 in the design of data storage element 324. Fig. 9In the example of FIG. 1 , the data storage element 324 of the memory cell 900 is similar to the data storage element 100 of FIG. 1 . The data storage layer 326 is completely covered by the first through hole 320. In some embodiments, the data storage layer 326 can be a substantially flat structure disposed between the top surface of the first conductive structure or the first MEOL structure 318 and the bottom surface of the second conductive structure or the first through hole 320. The sidewalls of the first through hole 320 and the data storage layer 326 are surrounded by the second dielectric layer 322, for example, so that the sidewalls are in direct contact with the second dielectric layer 322. In other embodiments (not shown), the data storage layer 326 may include a stepped structure extending along the sidewalls and the top surface of the first MEOL structure 318. In such embodiments, the data storage layer 306 may have a first upper surface directly above the MESL 316 and a second upper surface directly above the first MEOL structure 318.

[0086] Fig.10 A schematic diagram of a memory cell 1000 according to some examples of the present disclosure is depicted in a cross-sectional side view. The memory cell 1000 is also similar to Figure 3A , 3B The memory cell 300 is similar to the memory cell 300, but the design of the data storage element 324 is different from the memory cell 300. Fig.10 In the example of FIG. 3 , the first through hole 320 and the data storage layer 326 are disposed above the first MEOL structure 318. In some embodiments, the data storage layer 326 extends along the sidewalls of the first MEOL structure 318. In some additional embodiments (not shown), the data storage layer 326 may further extend on the first upper surface of the MEOL structure 318, which is recessed and located below the top surface of the MEOL structure 318. The first through hole 320 and the data storage layer 326 have tapered sidewalls, such as similar to Figure 2B In addition, the edge of the bottom surface of the first through hole 320 and / or the edge of the bottom surface of the data storage layer 326 is rounded or tapered, especially as Fig.10 In some embodiments, without being bound by any theory, making the bottom edge of the first through hole 320 facing the first MEOL structure 318 rounded generates a weaker electric field near the edge, thereby hindering the formation of a conductive filament between the edge of the first through hole 320 and the top surface of the first MEOL structure 318. In some examples, the radius of curvature of the bottom edge of the first through hole 320 can be, for example, between 1 nm and 100 nm, and in one example, between 5 nm and 20 nm.

[0087] Although the present disclosure describes a resistive random access memory (RRAM) device, it should be understood that the present disclosure is not limited to RRAM devices. Instead, the present disclosure may also be applied to other types of memory devices. For example, the present disclosure may be applied to ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), etc.

[0088] Some examples relate to a memory device. The memory device includes: a bottom electrode disposed above a substrate, the upper surface of the bottom electrode facing away from the substrate; a top electrode above the bottom electrode, the top electrode having a bottom surface facing the substrate; a data storage layer arranged between the bottom electrode and the top electrode, at least a portion of the bottom surface of the top electrode does not overlap with any portion of the upper surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode, and at least a portion of the upper surface of the bottom electrode does not overlap with any portion of the lower surface of the top electrode along the first direction. In some embodiments, the area of ​​the bottom surface of the top electrode overlapping with the portion of the upper surface of the bottom electrode along the first direction does not exceed 60%. In some embodiments, the bottom surface of the top electrode does not overlap with the upper surface of the bottom electrode along the first direction. In some embodiments, the data storage layer surrounds the bottom surface and sidewalls of the top electrode. In some embodiments, the bottom surface of the data storage layer includes a protrusion extending along the sidewall of the bottom electrode. In some embodiments, the bottom surface of the top electrode includes a protrusion extending toward the bottom electrode. In some embodiments, the data storage layer includes a dielectric resistive memory layer. In some embodiments, the bottom electrode includes a tapered sidewall, which forms an acute angle with the upper surface of the bottom electrode at the edge of the bottom surface of the bottom electrode facing the top electrode; the top electrode includes a tapered sidewall, which forms an obtuse angle with the bottom surface of the top electrode at the edge of the upper surface of the top electrode facing the bottom electrode.

[0089] Some examples relate to a memory device. The memory device includes: a transistor having a first source / drain (S / D) region and a second S / D region; a first conductive structure in a first dielectric layer, the first conductive structure electrically coupled to the first S / D region of the transistor; a second conductive structure in a second dielectric layer; and a data storage layer disposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure; the top surface of the first conductive structure extends from a first edge to a second edge along a first direction; the bottom surface of the second conductive structure extends from a third edge to a fourth edge along a first direction; the fourth edge is offset relative to the second edge in the first direction so that the bottom surface of the second conductive structure spans the second edge. In some embodiments, the third edge is offset relative to the first edge in the first direction. In some embodiments, the memory device also includes a second MEOL structure in the first dielectric layer, the second MEOL structure electrically coupled to the second S / D region of the transistor; and a first through hole in the second dielectric layer, the center of the bottom surface of the second MEOL structure being substantially aligned with the center of the top surface of the first through hole. In some embodiments, the first direction is parallel to a channel of the transistor, the channel extending from the second S / D region to the first S / D region; the first through hole is offset relative to the second conductive structure in a second direction perpendicular to the first direction. In some embodiments, the memory device further includes a gate structure between the first S / D region and the second S / D region over the transistor; and a second via electrically coupled to the gate structure, the second via being arranged in the second direction between the second conductive structure and the first via.

[0090] Some examples relate to a method for manufacturing a memory device. The method includes forming a first conductive structure above a substrate; forming a data storage layer above an exposed portion of an upper surface of the first conductive structure, the center of the data storage layer deviating from the center of the upper surface of the first conductive structure in a first direction parallel to the upper surface of the first conductive structure; and forming a second conductive structure above the data storage layer. In some embodiments, the method also includes forming a dielectric layer above the first conductive structure; and forming an opening in the dielectric layer, the opening exposing the exposed portion of the upper surface of the first conductive structure, the center of the opening deviating from the center of the upper surface of the first conductive structure in the first direction, and the data storage layer and the second conductive structure are formed in the opening. In some embodiments, the first conductive structure is arranged in an etch stop layer, and the opening exposes the upper surface of the etch stop layer. In some embodiments, the opening extends below the upper surface of the first conductive structure into the etch stop layer. In some embodiments, the data storage layer is conformally deposited on the bottom wall and sidewalls of the opening. In some embodiments, the bottom surface of the second conductive structure does not overlap with the upper surface of the first conductive structure along the first direction. In some embodiments, the sidewalls of the second conductive structure deviate from the sidewalls of the first conductive structure in the first direction.

[0091] It should be understood that in this written description and in the claims that follow, the terms "first," "second," "third," etc., are merely general identifiers used for convenience of description to distinguish different elements of one figure or series of figures. By themselves, these terms do not imply any temporal ordering or structural proximity of these elements, and are not intended to describe corresponding elements in different illustrated and / or unillustrated examples. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an unillustrated example.

[0092] In some embodiments, a memory device includes: a bottom electrode disposed above a substrate, wherein an upper surface of the bottom electrode faces away from the substrate; a top electrode above the bottom electrode, wherein the top electrode has a bottom surface facing the substrate; a data storage layer disposed between the bottom electrode and the top electrode, wherein at least a portion of the bottom surface of the top electrode does not overlap with any portion of the upper surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode; and wherein at least a portion of the upper surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction. In some embodiments, no more than 60% of the bottom surface of the top electrode overlaps with a portion of the upper surface of the bottom electrode along the first direction. In some embodiments, the bottom surface of the top electrode does not overlap with the upper surface of the bottom electrode along the first direction. In some embodiments, the data storage layer surrounds the bottom surface and sidewalls of the top electrode. In some embodiments, the bottom surface of the data storage layer includes a protrusion extending along the sidewalls of the bottom electrode. In some embodiments, the bottom surface of the top electrode includes a protrusion extending toward the bottom electrode. In some embodiments, the data storage layer includes a dielectric resistive memory layer. In some embodiments, the bottom electrode includes a tapered sidewall, which forms an acute angle with the upper surface of the bottom electrode at the edge of the bottom surface of the bottom electrode facing the top electrode; and the top electrode includes a tapered sidewall, which forms an obtuse angle with the bottom surface of the top electrode at the edge of the top surface of the top electrode facing the bottom electrode.

[0093] In some embodiments, a memory device includes: a transistor including a first source / drain (S / D) region and a second S / D region; a first conductive structure in a first dielectric layer, the first conductive structure electrically coupled to the first S / D region of the transistor; a second conductive structure in a second dielectric layer; and a data storage layer disposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure; wherein: the top surface of the first conductive structure extends from a first edge to a second edge along a first direction; the bottom surface of the second conductive structure extends from a third edge to a fourth edge along the first direction; and the fourth edge is offset relative to the second edge in the first direction so that the bottom surface of the second conductive structure spans the second edge. In some embodiments, the third edge is offset relative to the first edge in the first direction. In some embodiments, a second MEOL structure in the first dielectric layer, the second MEOL structure electrically coupled to the second S / D region of the transistor; and a first through hole in the second dielectric layer, wherein a center of a bottom surface of the second MEOL structure is substantially aligned with a center of a top surface of the first through hole. In some embodiments, a first direction is parallel to a channel of the transistor extending from the second S / D region to the first S / D region; and the first via is offset relative to the second conductive structure in a second direction perpendicular to the first direction. In some embodiments, a gate structure is between the first S / D region and the second S / D region over the transistor; and a second via is electrically coupled to the gate structure, wherein the second via is arranged between the second conductive structure and the first via in the second direction.

[0094] In some embodiments, a method for manufacturing a memory device includes: forming a first conductive structure over a substrate; forming a data storage layer over an exposed portion of an upper surface of the first conductive structure, wherein a center of the data storage layer deviates from a center of the upper surface of the first conductive structure in a first direction parallel to the upper surface of the first conductive structure; and forming a second conductive structure over the data storage layer. In some embodiments, it also includes: forming a dielectric layer over the first conductive structure; and forming an opening in the dielectric layer, the opening exposing the exposed portion of the upper surface of the first conductive structure, wherein a center of the opening deviates from the center of the upper surface of the first conductive structure in the first direction, and wherein the data storage layer and the second conductive structure are formed in the opening. In some embodiments, the first conductive structure is arranged in an etch stop layer, and the opening exposes an upper surface of the etch stop layer. In some embodiments, the opening extends into the etch stop layer below the upper surface of the first conductive structure. In some embodiments, the data storage layer is conformally deposited on a bottom wall and side walls of the opening. In some embodiments, the bottom surface of the second conductive structure does not overlap with the upper surface of the first conductive structure along the first direction. In some embodiments, the side walls of the second conductive structure deviate from the side walls of the first conductive structure in the first direction.

[0095] The foregoing summarizes the features of several examples so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the examples introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device, comprising: A bottom electrode is disposed above the substrate, wherein an upper surface of the bottom electrode faces away from the substrate; a top electrode over the bottom electrode, wherein the top electrode has a bottom surface facing the substrate; a data storage layer disposed between the bottom electrode and the top electrode, wherein at least a portion of the bottom surface of the top electrode does not overlap any portion of the upper surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode; and wherein at least a portion of the upper surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction, wherein the data storage layer surrounds the bottom surface and the entire side wall of the top electrode, and the bottommost surface of the data storage layer is higher than the bottom surface of the bottom electrode, The data storage layer includes a bottom metal layer, a resistive memory layer and a top metal layer, wherein the data storage layer also includes a barrier layer, the oxygen concentration of the barrier layer is lower than that of the resistive memory layer, and the oxygen reaction activity of the barrier layer is higher than that of the top metal layer and / or the bottom metal layer.

2. The memory device according to claim 1, wherein: No more than 60% of the bottom surface of the top electrode overlaps with a portion of the upper surface of the bottom electrode along the first direction.

3. The memory device according to claim 2, wherein: The bottom surface of the top electrode does not overlap the upper surface of the bottom electrode along the first direction.

4. The memory device according to claim 1, wherein: Conductive filaments are formed at edges of the bottom electrode.

5. The memory device according to claim 1, wherein: The bottom surface of the data storage layer includes a protrusion extending along a sidewall of the bottom electrode.

6. The memory device according to claim 1, wherein: The bottom surface of the top electrode includes a protrusion extending toward the bottom electrode.

7. The memory device according to claim 1, wherein: The top metal layer and the bottom metal layer include platinum, ruthenium, tantalum nitride, titanium nitride, iridium, tungsten, aluminum, copper, silver, gold, or a combination thereof.

8. The memory device according to claim 1, wherein the bottom electrode comprising a tapered sidewall forming an acute angle with the upper surface of the bottom electrode at an edge of the bottom electrode facing the bottom surface of the top electrode; and The top electrode includes a tapered sidewall that forms an obtuse angle with the bottom surface of the top electrode at an edge of the top electrode facing the upper surface of the bottom electrode.

9. A storage device comprising: a transistor including a first source / drain region and a second source / drain region; a first conductive structure in a first dielectric layer, the first conductive structure electrically coupled to the first source / drain region of the transistor; a second conductive structure in the second dielectric layer; as well as A data storage layer disposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure; in: The top surface of the first conductive structure extends from a first edge to a second edge along a first direction; The bottom surface of the second conductive structure extends from a third edge to a fourth edge along the first direction; and the fourth edge is offset relative to the second edge in the first direction so that the bottom surface of the second conductive structure spans the second edge, wherein the data storage layer surrounds the bottom surface and the entire side wall of the second conductive structure, and the bottommost surface of the data storage layer is higher than the bottom surface of the first conductive structure, The data storage layer includes a bottom metal layer, a resistive memory layer and a top metal layer, wherein the data storage layer also includes a barrier layer, the oxygen concentration of the barrier layer is lower than that of the resistive memory layer, and the oxygen reaction activity of the barrier layer is higher than that of the top metal layer and / or the bottom metal layer.

10. The memory device according to claim 9, wherein: The third edge is offset relative to the first edge in the first direction.

11. The memory device according to claim 9, further comprising: a second MEOL structure in the first dielectric layer, the second MEOL structure electrically coupled to the second source / drain region of the transistor; as well as A first via in the second dielectric layer, wherein a center of a bottom surface of the second MEOL structure is aligned with a center of a top surface of the first via.

12. The memory device according to claim 11, wherein The first direction is parallel to a channel of the transistor extending from the second source / drain region to the first source / drain region; and The first via is offset relative to the second conductive structure in a second direction perpendicular to the first direction.

13. The memory device according to claim 12, further comprising: a gate structure between the first source / drain region and the second source / drain region above the transistor; as well as A second via is electrically coupled to the gate structure, wherein the second via is arranged between the second conductive structure and the first via in the second direction.

14. A method for manufacturing a memory device, the method comprising: forming a first conductive structure over the substrate; forming a data storage layer over the exposed portion of the upper surface of the first conductive structure, wherein a center of the data storage layer is offset from a center of the upper surface of the first conductive structure in a first direction parallel to the upper surface of the first conductive structure; and forming a second conductive structure above the data storage layer, The data storage layer includes a bottom metal layer, a resistive memory layer and a top metal layer, wherein the data storage layer further includes a barrier layer, the oxygen concentration of the barrier layer is lower than that of the resistive memory layer, and the oxygen reaction activity of the barrier layer is higher than that of the top metal layer and / or the bottom metal layer, Wherein a bottom surface of the second conductive structure does not overlap with an upper surface of the first conductive structure along the first direction, and wherein the conductive filament extends from an outermost edge of the first conductive structure to an outermost edge of the second conductive structure.

15. The method according to claim 14, further comprising: forming a dielectric layer over the first conductive structure; as well as An opening is formed in the dielectric layer, the opening exposing the exposed portion of the upper surface of the first conductive structure, wherein the center of the opening deviates from the center of the upper surface of the first conductive structure in the first direction, and wherein the data storage layer and the second conductive structure are formed in the opening.

16. The method according to claim 15, wherein: The first conductive structure is disposed in an etch stop layer, and the opening exposes an upper surface of the etch stop layer.

17. The method according to claim 16, wherein: The opening extends into the etch stop layer below the upper surface of the first conductive structure.

18. The method according to claim 15, wherein: The data storage layer is conformally deposited on the bottom wall and sidewalls of the opening.

19. The method according to claim 14, wherein: The conductive filaments extend through the data storage layer.

20. The method according to claim 14, wherein: The sidewall of the second conductive structure deviates from the sidewall of the first conductive structure in the first direction.

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