Phased array antenna beam control method, system and storage medium

Abstract

The embodiment of the present invention discloses a phased array antenna beam control method, including: a beam control motherboard receives a switching control instruction, searches a pre-stored information table for a target beam control code table corresponding to a beam to be cut with a direction switching requirement on the phased array antenna according to the received switching control instruction, and distributes it to at least one beam control sub-board; after receiving the target beam control code table, the beam control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target beam control code table, so that the phased array antenna can achieve beam direction switching by adjusting the amplitude and phase of each array element included in the beam to be cut. The phased array antenna beam control method provided by the embodiment of the present invention can control multiple beams at the same time and achieve fast and accurate beam direction switching.

Description

Technical Field

[0001] The present invention relates to the field of satellite communication technology, and in particular to a phased array antenna beam control method, system and storage medium. Background Art

[0002] With the rapid development of radio frequency and digital integrated circuit technology, phased array antennas are increasingly used in satellite communication systems, radar systems and electronic countermeasure systems. Phased array antennas switch beam pointing by changing the amplitude and phase of array units to complete beam scanning. Therefore, the beam control system is an important part of the phased array antenna, which directly affects the system's beam switching time and beam pointing accuracy.

[0003] At present, most phased array beam control systems adopt a centralized computational control method, that is, according to the beam pointing requirements, the beam control system calculates the amplitude and phase of each array unit in real time, and completes the amplitude attenuation and phase shift control of each unit.

[0004] Traditional phased array antennas mostly use processors such as DSP and FPGA to solve the beam pointing angle in real time and then control the amplitude and phase of the array units. The solution process is complex, time-consuming and slow to switch. For satellite communication systems, it may cause communication interruption and affect user experience. For radar systems, it may cause the tracked target to be lost or missed, affecting the probability of target detection. Summary of the invention

[0005] The embodiments of the present invention provide a phased array antenna beam control method, system and storage medium, which can control multiple beams at the same time and be applied to beam control in different scenarios to achieve fast and accurate beam pointing switching. It can also realize on-orbit reconstruction of the beam control system and optimize the performance of the phased array antenna.

[0006] In a first aspect, an embodiment of the present invention provides a phased array antenna beam control method, including:

[0007] The beam control motherboard receives the switching control instruction, searches for a target beam control code table corresponding to a beam to be switched with a pointing switching requirement on the phased array antenna from a pre-stored information table according to the received switching control instruction, and distributes the table to at least one beam control daughter board;

[0008] After receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0009] Further, the beam control motherboard receives the switching control instruction, searches for a target beam control code table corresponding to a beam to be switched with a pointing switching requirement on the phased array antenna from a pre-stored information table according to the received switching control instruction, and distributes it to at least one beam control sub-board, including:

[0010] Calculate the starting address of the beam control code table corresponding to the beam to be switched according to the switching control instruction;

[0011] According to the start address of the wave control code table, the target wave control code table corresponding to the to-be-cut beam is searched from the pre-stored information table, and the target wave control code table is distributed to the corresponding wave control sub-board.

[0012] Furthermore, the information table is stored in a set number of storage chips; the information table includes a beam control code table corresponding to each beam formed by the phased array antenna;

[0013] The factors affecting the set number of the storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the total number of array elements of the phased array antenna.

[0014] Further, the calculating, according to the switching control instruction, a starting address of a beam control code table corresponding to the beam to be switched includes:

[0015] Parsing the switching control instruction to obtain a beam center frequency and a beam pointing number contained in the switching control instruction;

[0016] Obtaining the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the beam control code table stored in the at least one storage chip;

[0017] The starting address of the beam control code table corresponding to the beam to be cut is calculated according to the beam center frequency and the beam pointing number, the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the beam control code table stored in the at least one storage chip.

[0018] Further, distributing the target wave control code table to the corresponding wave control sub-board includes:

[0019] The wave control code table is distributed to the corresponding wave control sub-board according to the address information in the wave control code table.

[0020] Further, after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the to-be-cut beam through the target wave control code table, including:

[0021] The amplitude and phase control codes in the target wave control code table are extracted, and the phase shift value of the digital phase shifter and the attenuation value of the digital attenuator are determined according to the amplitude and phase control codes.

[0022] Further, after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the to-be-cut beam through the target wave control code table, and further includes:

[0023] Extracting the digital-to-analog conversion control code from the wave control code table, and establishing two orthogonal voltages according to the digital-to-analog conversion control code;

[0024] The target amplitude and target phase of the corresponding array element of the phased array antenna are determined according to the two orthogonal voltages combined with the vector modulator chip characteristic table.

[0025] Furthermore, before the wave control motherboard receives the switching control instruction, it also includes:

[0026] The beam control motherboard is tested by a host computer to establish the beam control code table; the beam control code table includes the beam center frequency, the beam pointing number, the array element row number, the array element column number and the amplitude and phase control code.

[0027] In a second aspect, an embodiment of the present invention further provides a phased array antenna beam control system, comprising: a beam control motherboard and at least one beam control daughterboard;

[0028] The beam control motherboard is connected to each beam control sub-board and is used to receive a switching control instruction, obtain a target beam control code table corresponding to a beam to be switched with a directional switching requirement on the phased array antenna according to the received switching control instruction, and distribute it to the at least one beam control sub-board;

[0029] The at least one wave control sub-board is used to determine and adjust the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table after receiving the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0030] Optionally, the wave control motherboard includes a control center / host computer interface, a first field programmable logic gate array chip and a wave control daughter board interface;

[0031] The wave control motherboard receives the switching control instruction through the control center / host computer interface;

[0032] The first field programmable logic gate array chip is used to calculate the target beam control code table corresponding to the beam to be switched according to the switching control instruction;

[0033] The wave control motherboard distributes the target wave control code table to the corresponding wave control daughter board through the wave control daughter board interface.

[0034] Optionally, the first field programmable logic gate array chip is specifically used for:

[0035] Parsing the switching control instruction to obtain a beam center frequency and a beam pointing number contained in the switching control instruction;

[0036] Acquire characteristic parameters of the phased array antenna, wherein the characteristic parameters include the total number of beam pointing numbers, the total number of array elements of the phased array antenna, the coordinates and spacing of each array element of the phased array antenna, and the array mode and beamforming of the phased array antenna;

[0037] A target beam control code table corresponding to the beam to be cut is calculated according to the beam center frequency, the beam pointing number and the characteristic parameters of the phased array antenna.

[0038] Optionally, the wave control motherboard further includes: a set number of storage chips;

[0039] The storage chip is used to pre-store the beam control code table corresponding to each beam formed by the phased array antenna;

[0040] Correspondingly, the first field programmable logic gate array chip is connected to each of the storage chips, calculates the starting address of the beam control code table corresponding to the to-be-cut beam according to the switching control instruction, and searches the target beam control code table from the storage chip according to the starting address of the beam control code table;

[0041] The factors affecting the set number of the storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the total number of array elements of the phased array antenna.

[0042] Optionally, the at least one wave control daughter board includes a wave control mother board interface, at least one digital-to-analog conversion chip and at least one vector modulator chip, and each digital-to-analog conversion chip is connected to at least one vector modulator chip;

[0043] The at least one wave control sub-board receives the wave control code table distributed by the wave control motherboard through the wave control motherboard interface;

[0044] The at least one digital-to-analog conversion chip is used to extract the digital-to-analog conversion control code in the wave control code table, and establish two orthogonal voltages according to the digital-to-analog conversion control code;

[0045] The at least one vector modulator chip is used to determine the amplitude and phase of the corresponding array element of the phased array antenna according to the two orthogonal voltages combined with the vector modulator chip characteristic table.

[0046] Optionally, the at least one digital-to-analog conversion chip is further used for:

[0047] The corresponding wave control code table is received according to the address information in the wave control code table.

[0048] Optionally, the wave control daughter board also includes at least one second field programmable logic gate array chip, each second field programmable logic gate array chip is connected to at least one digital-to-analog conversion chip, and the second field programmable logic gate array chip is used to receive the wave control code table distributed by the wave control mother board according to the address information in the wave control code table, and then distribute the wave control code table to the at least one digital-to-analog conversion chip.

[0049] Optionally, the vector modulator chip characteristic table is obtained by testing the vector modulator; the vector modulator characteristic table includes the two orthogonal voltages and the amplitudes and phases of the corresponding array elements.

[0050] In a third aspect, an embodiment of the present invention further provides a phased array antenna beam control storage medium having a computer program stored thereon, which, when executed by a processing device, implements a phased array antenna beam control method as described in any one of the embodiments of the present invention.

[0051] The embodiment of the present invention first receives the switching control instruction through the wave control motherboard, searches the target wave control code table corresponding to the beam to be cut with the direction switching requirement on the phased array antenna from the pre-stored information table according to the received switching control instruction, and distributes it to at least one wave control sub-board; then after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table, so that the phased array antenna can achieve beam direction switching by adjusting the amplitude and phase of each array element included in the beam to be cut. The phased array antenna beam control method provided by the embodiment of the present invention completes the control instruction solution and table lookup through the field programmable logic gate array in the wave control motherboard, so that the wave control sub-board adjusts the amplitude and phase of the array element according to the wave control code table, can control multiple beams at the same time, is applied to beam control in different scenarios, realizes fast and accurate beam direction switching, and can also realize on-orbit reconstruction of the beam control system to optimize the performance of the phased array antenna. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a flow chart of a phased array antenna beam control method in Embodiment 1 of the present invention;

[0053] Figure 2 This is a flow chart of a method for distributing a target wave control code table in Embodiment 2 of the present invention;

[0054] Figure 3 This is a schematic diagram of the structure of a single FLASH chip beam control system in Embodiment 2 of the present invention;

[0055] Figure 4 This is a schematic diagram of the structure of a multi-FLASH chip beam control system in Embodiment 2 of the present invention;

[0056] Figure 5 This is a flow chart of searching and distributing a beam control code table in a beam control system in Embodiment 2 of the present invention;

[0057] Figure 6 It is a schematic diagram of the structure of a phased array antenna beam control system in Embodiment 3 of the present invention;

[0058] Figure 7 This is a schematic diagram of the structure of a wave-controlled motherboard in Embodiment 3 of the present invention;

[0059] Figure 8 This is a schematic diagram of the structure of a wave control sub-board in Embodiment 3 of the present invention;

[0060] Fig. 9 This is a structural diagram of a beam control system including an FPGA chip in a daughter board in the third embodiment of the present invention. DETAILED DESCRIPTION

[0061] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0062] Embodiment 1

[0063] Figure 1 This is a flow chart of a phased array antenna beam control method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where the direction of the beam generated by the phased array antenna is switched and controlled. The method can be executed by a phased array antenna beam control system. Figure 1 As shown, the specific steps include:

[0064] Step 110: The beam control motherboard searches for a target beam control code table corresponding to the beam to be switched from a pre-stored information table according to the received switching control instruction, and distributes the table to at least one beam control daughter board.

[0065] The wave control motherboard may include but is not limited to a control center / host computer interface, a field programmable gate array (FPGA), a memory chip (FLASH) and a wave control daughter board interface, which are used to complete the reception of control instructions, the solution of the wave control code table address, and the reading and distribution of the wave control code table. The control center / host computer interface is connected to the control center / host computer module, the wave control daughter board interface is connected to the wave control daughter board module, the FPGA is used to complete the solution of instruction information, address calculation, wave control code table reading and distribution, and the FLASH is used to complete the storage of the wave control code table.

[0066] Furthermore, the switching control instructions received by the wave control motherboard can be sent by the control center / host computer module, and the control center / host computer module can determine the target beam pointing corresponding to the beam to be switched with the pointing switching requirement on the phased array antenna, and then generate the switching control instructions according to the target beam pointing and send it to the wave control motherboard.

[0067] Specifically, a phased array antenna is an antenna that changes the shape of the radiation pattern by controlling the feeding phase of the array unit in the array antenna. The direction of the beam can be changed by controlling the phase to achieve the purpose of beam scanning. A beam refers to the shape formed on the surface of the earth by the electromagnetic waves emitted by the satellite antenna. A phased array antenna can generate one or more beams. For beams that need to be switched in direction, a control instruction can be generated to switch the beam direction according to the pitch angle and azimuth angle of the target beam direction. The control center / host computer module can obtain the pitch angle and azimuth angle of the target beam direction by calculation, represent the pitch angle and azimuth angle by the beam direction number, and generate a beam switching control instruction containing the beam direction number and send it to the wave control motherboard.

[0068] Optionally, the wave control motherboard receives the switching control instructions sent by the control center / host computer module through the control center / host computer interface, the FPGA parses the switching control instructions, reads the corresponding wave control code table from the FLASH according to the switching control instructions, and finally distributes the wave control code table to the wave control daughter board through the wave control daughter board interface.

[0069] In this embodiment, the wave control motherboard searches for the target wave control code table corresponding to the beam to be cut with the directional switching requirement on the phased array antenna from a pre-stored information table according to the received switching control instruction, and distributes it to at least one wave control sub-board in the following manner: calculating the starting address of the wave control code table corresponding to the beam to be cut according to the switching control instruction; searching for the target wave control code table corresponding to the beam to be cut from the pre-stored information table according to the starting address of the wave control code table, and distributing the target wave control code table to the corresponding wave control sub-board.

[0070] Table 1

[0071]

[0072] Table 1 is a beam control code table in an embodiment of the present invention. As shown in Table 1, assuming that the signal bandwidth is 1 GHz and the frequency interval is 100 MHz, the beam center frequency can be divided into 11 levels. Assuming that the phased array antenna needs to cover the ground range of ±50 degrees, 128 beam pointing numbers can be calculated according to parameters such as the satellite orbit height. Each beam pointing number corresponds to a beam pointing elevation angle (θ) and an azimuth angle ( ) combination, for a 64-element phased array antenna, the coordinates of each element are (1,1), (1,2)…(8,8) respectively. In the wave control code table, each element corresponds to two digital-to-analog conversion control codes (DAC control codes).

[0073] Optionally, the switching control instruction includes the beam center frequency and beam pointing number of the beam to be switched. The FPGA chip can parse the beam center frequency and beam pointing number in the switching control instruction, and then calculate the corresponding starting address of the wave control code table. According to the starting address of the wave control code table, the corresponding target wave control code table can be found from the information table pre-stored in the FLASH, and finally the target wave control code table is distributed to the wave control sub-board according to the address through the wave control sub-board interface.

[0074] Step 120: After receiving the target beam control code table, the beam control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target beam control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0075] The wave control sub-board includes but is not limited to a wave control motherboard interface, a digital-to-analog conversion chip (DAC), a vector modulator chip (VM) and a radio frequency interface, and is used to receive the wave control code table sent by the wave control motherboard, and complete the amplitude and phase modulation according to the DAC control code in the wave control code table. The wave control motherboard interface is connected to the wave control motherboard, the radio frequency interface is connected to the radio frequency module, the DAC chip is used to convert the digital signal into an analog signal and output it to the control end of the VM chip, and the VM chip is used to complete the amplitude and phase modulation according to the analog signal sent by the DAC.

[0076] In this embodiment, after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table by extracting the amplitude and phase control code in the target wave control code table, and determining the phase shift value of the digital phase shifter and the attenuation value of the digital attenuator according to the amplitude and phase control code.

[0077] Optionally, the wave control code table may include an amplitude and phase control code, which corresponds to the target amplitude and target phase of each array element included in the wave control to be switched in the phased array antenna. The wave control sub-board can obtain the amplitude and phase control code from the target wave control code table, and determine the phase shift value of the digital phase shifter and the attenuation value of the digital attenuator according to the amplitude and phase control code, so as to control the amplitude and phase of the corresponding array element.

[0078] In this embodiment, after receiving the target wave control code table, the wave control sub-board can determine the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table by: extracting the digital-to-analog conversion control code in the wave control code table, and establishing two orthogonal voltages according to the digital-to-analog conversion control code; determining the amplitude and phase of the corresponding array element of the phased array antenna according to the two orthogonal voltages in combination with the vector modulator chip characteristic table.

[0079] Optionally, the DAC chip can extract two DAC control codes from the received wave control code table, establish two orthogonal voltages (I / Q two-way voltages) according to the two DAC control codes and send them to the VM chip. The VM chip can be an analog IQ vector modulator, which can determine the amplitude and phase of the array element corresponding to the beam to be cut according to the received I / Q two-way voltage, and the corresponding relationship between the array element amplitude and phase and the I / Q two-way voltage is consistent with the VM chip characteristic table.

[0080] Furthermore, the vector modulator chip characteristic table is obtained by testing the vector modulator; the vector modulator characteristic table includes two orthogonal voltages and amplitudes and phases of corresponding array elements.

[0081] Optionally, the characteristic table of each VM chip is related to itself. To obtain the characteristic table of the VM chip, it can be tested at the factory to form a voltage-controlled amplitude and phase change table, thereby determining the correspondence between the amplitude and phase and the I / Q voltage values ​​generated by the DAC. Furthermore, the VM chip characteristic table can be interpolated according to system requirements to improve the control accuracy of the amplitude and phase, thereby improving the accuracy of beam switching. In theory, the accuracy can be infinitely improved and the error can be reduced through interpolation.

[0082] Furthermore, after the beam control sub-board determines the target amplitude and target phase of each array element included in the beam to be cut, the RF module can send the target amplitude and target phase of each array element to the phased array antenna, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0083] The RF module is responsible for loading and transmitting RF signals. After the beam control sub-board determines the target amplitude and target phase of each array element included in the beam to be cut, the RF module can send it to the phased array antenna. The beam pointing is related to the amplitude and phase of the array element.

[0084] In this embodiment, before the beam control motherboard receives the switching control instruction, the beam control motherboard can also be tested by the host computer to establish a beam control code table; the beam control code table includes the beam center frequency, beam pointing number, array element row number, array element column number and digital-to-analog conversion control code.

[0085] Optionally, assuming that the antenna array is a rectangular grid with rectangular boundaries and arranged in two dimensions with equal spacing, according to the θ and Angle, the beam direction is changed only by changing the phase of the array element, without amplitude attenuation. The calculation formula of the phase shift value of each array element is as follows:

[0086]

[0087] Among them, i, j are the row and column numbers of the array element respectively, C(i,j) is the phase shift value of the array element, θ, are the elevation and azimuth angles of the beam, respectively, X = i × d x ,Y=j×d j are the coordinate values ​​of the array elements, among which d x Array element row spacing, d y is the array element column spacing.

[0088] According to the phase shift value and VM characteristic table obtained by the above calculation, the wave control motherboard is tested through the host computer, and the I / Q two-way input voltage required for a certain phase shift value is found by the VM chip, and converted into the DAC control code required by the DAC chip according to the digital-to-analog conversion relationship of the DAC chip. The beam center frequency, beam pointing number, array element row number, array element column number and DAC control code are stored in the FLASH accordingly, so as to determine what kind of control instruction is needed to switch a certain beam to the set pointing direction.

[0089] The embodiment of the present invention first receives the switching control instruction through the wave control motherboard, searches the target wave control code table corresponding to the beam to be cut with the direction switching requirement on the phased array antenna from the pre-stored information table according to the received switching control instruction, and distributes it to at least one wave control sub-board; then after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table, so that the phased array antenna can achieve beam direction switching by adjusting the amplitude and phase of each array element included in the beam to be cut. The phased array antenna beam control method provided by the embodiment of the present invention completes the control instruction solution and table lookup through the FPGA chip in the wave control motherboard, so that the wave control sub-board adjusts the amplitude and phase of the array element according to the wave control code table, can control multiple beams at the same time, and is applied to beam control in different scenarios to achieve fast and accurate beam direction switching. In addition, when system requirements change, some channels fail, temperature drift factors and other factors affect antenna performance, the beam control system software can be reconstructed on-orbit. Through the satellite communication link, instructions and programs on the onboard computer can be reconstructed to control the beam control system to complete the on-orbit reconstruction of FPAG and beam control code table, thereby optimizing the performance of the phased array antenna.

[0090] Embodiment 2

[0091] Figure 2 This is a flow chart of a method for distributing a target wave control code table in the second embodiment of the present invention. This embodiment is applicable to the case where the wave control motherboard searches for the target wave control code table corresponding to the beam to be cut from the pre-stored information table and distributes it to at least one wave control daughter board. Figure 2 As shown, the specific steps include:

[0092] Step 111: Calculate the starting address of the beam control code table corresponding to the beam to be switched according to the switching control instruction.

[0093] Optionally, the phased array antenna can generate one or more beams, each beam has a corresponding beam control code table, and the beam control motherboard can parse and calculate the received switching control instructions to obtain the starting address of the beam control code table corresponding to the beam to be switched stored in the FLASH, and the corresponding beam control code table can be obtained based on the address.

[0094] In this embodiment, the method for calculating the starting address of the wave control code table corresponding to the beam to be cut according to the switching control instruction can be: parsing the switching control instruction to obtain the beam center frequency and beam pointing number contained in the switching control instruction; obtaining the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in at least one storage chip; calculating the starting address of the wave control code table corresponding to the beam to be cut according to the beam center frequency and beam pointing number, the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in at least one storage chip.

[0095] Optionally, the FPGA chip in the beam control motherboard can parse the beam center frequency and beam pointing number in the beam switching instruction. The total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the beam control code table stored in at least one storage chip are known. The starting address of the beam control code table corresponding to the beam to be switched can be calculated, and the calculation formula is as follows:

[0096]

[0097] Where ADD is the starting address of the beam control code table corresponding to the beam to be cut, ADD_0 is the starting position of all beam control code tables stored in FLASH, num_f0 is the resolved beam center frequency point, N_loc is the total number of beam pointing numbers, N_arr is the total number of array elements, N_bit is the number of storage bits of a digital-to-analog conversion control code, num_loc is the resolved beam pointing number, and 2 represents the I / Q voltage.

[0098] Figure 3This is a schematic diagram of the structure of a single FLASH chip beam control system in this embodiment. As shown in the figure, the system structure includes a beam control motherboard, a beam control daughterboard and a radio frequency module, which can control the beam to quickly switch the beam direction according to the switching control instruction information sent by the control center / host computer. The beam control motherboard includes a FLASH chip, an FPGA chip and a control interface; the beam control daughterboard includes a DAC chip, a VM chip and a control interface. Take a 64-element single-beam satellite communication payload phased array antenna as an example, that is, N_arr=64; assuming that the signal bandwidth is 1GHz and the frequency interval is 100MHz, the beam center frequency is divided into 11 levels, that is, N_f0=11; assuming that the phased array antenna needs to cover the ground range of ±50 degrees, the number of wave positions is calculated to be 128 according to parameters such as the satellite orbit height, that is, N_loc=128; assuming that the beam center frequency number num_f0=3, the beam direction number num_loc=5, and a control code of the DAC is stored in 16 bits, then the calculated starting position of the beam control code table is:

[0099] ADD=ADD_0+(3-1)×128×64×2×16+(5-1)×64×2×16,

[0100] Among them, ADD_0 is the starting position where all wave control code tables are stored in FLASH.

[0101] Step 112: search the target wave control code table corresponding to the to-be-cut beam from the pre-stored information table according to the start address of the wave control code table, and distribute the target wave control code table to the corresponding wave control sub-board.

[0102] Optionally, an information table is pre-stored in the beam control motherboard, and the information table stores the beam control code table of each beam. After the FPGA chip calculates the starting address of the beam control code table, it can find the target beam control code table corresponding to the beam to be cut according to the address, and then distribute it to the beam control daughter board.

[0103] In this embodiment, the information table is stored in a set number of storage chips; the information table includes a beam control code table corresponding to each beam formed by the phased array antenna; the factors affecting the set number of storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the total number of array elements of the phased array antenna.

[0104] Optionally, the information table can be stored in a FLASH chip, and the information table includes the wave control code table corresponding to each beam formed by the phased array antenna. In a beam control system, a wave control motherboard includes at least one FLASH chip, and the number of FLASH chips is related to the chip memory size, the number of beams, the beam switching time index, and the number of array elements of the phased array antenna. For example, for a phased array antenna that needs to control multiple beams, the wave control code table of multiple beams can be stored in a FLASH chip. At this time, the FPGA chip needs to read the multi-beam wave control code table in sequence and control them in sequence; the wave control code table of each beam can also be stored in different FLASH chips. At this time, the FPGA can read multiple wave control code tables at the same time and control the switching of multiple beams.

[0105] Figure 4 This is a schematic diagram of the structure of a multi-FLASH chip beam control system in this embodiment. As shown in the figure, taking a 512-element 16-beam phased array antenna for satellite communication payload as an example, that is, N_arr=512, N_f0=16, 16 FLASH chips can be used to connect to the FPGA, and each FLASH stores a beam control code table. When the beam control system receives the beam switching instruction sent by the control center, the FPGA calculates the starting address of each beam beam control code table, and then reads the beam control code table of each beam in the FLASH in parallel and completes the beam switching control at the same time.

[0106] In this embodiment, the target wave control code table is distributed to the corresponding wave control sub-board in the following manner: the wave control code table is distributed to the corresponding wave control sub-board according to the address information in the wave control code table.

[0107] Optionally, the address information in the wave control code table is the array element coordinates, which can be represented by the array element row number and column number in the wave control code table. Each wave control sub-board controls the corresponding array element. When distributing the wave control code table to the wave control sub-boards, the wave control code table corresponding to the array element of each wave control sub-board can be sent according to the array element row number and column number. Figure 3 As shown in the figure, the DAC chip selected in the beam control daughter board has 32 pins and can control 16 VM chips in a single beam at the same time. A total of 4 DAC chips are required for 64 array elements. Since each DAC chip is connected to 16 fixed VM chips, the RF module that each DAC chip needs to control is also fixed. When distributing the beam control code table, it is only necessary to directly send the beam control code table of the corresponding array element according to the connection pins without recalculating the address.

[0108] Figure 5It is a flow chart of searching and distributing the beam control code table of a beam control system in an embodiment of the present invention. As shown in the figure, after receiving the beam switching control instruction, the FPGA chip parses the control instruction and calculates the starting address of the beam control code table, reads the target beam control code table in the FLASH chip according to the address, and then distributes it to the DAC chip in the beam control sub-board. The DAC chip establishes voltage according to the DAC control code in the beam control code table, so that the VM chip completes amplitude and phase control according to the voltage.

[0109] The embodiment of the present invention first calculates the starting address of the wave control code table corresponding to the beam to be cut according to the switching control instruction; then searches the target wave control code table corresponding to the beam to be cut from the pre-stored information table according to the starting address of the wave control code table, and distributes the target wave control code table to the corresponding wave control sub-board. The distribution method of the target wave control code table provided by the embodiment of the present invention pre-stores the wave control code table in FLASH, searches the wave control code table of the beam to be cut by calculating the starting address of the wave control code table, and then distributes it to the wave control sub-board. It does not need to calculate the DAC control code in real time, and can achieve the purpose of fast search and distribution. The program design is simplified by pre-calculation, burning and searching, and it occupies less resources. At the same time, it has strong versatility and can be applied to beam control in different scenarios. In addition, the FPGA chip can be connected to multiple FLASH chips, and the number of FLASH chips can be reasonably selected according to factors such as the number of beams, the total number of beam pointing numbers, the beam switching time index, and the number of array elements of the phased array antenna. After the FPGA calculates the address, it can read the wave control code tables stored in multiple FLASH chips at the same time, thereby realizing fast beam pointing switching.

[0110] Embodiment 3

[0111] Figure 6 This is a schematic diagram of a phased array antenna beam control system structure provided by Embodiment 3 of the present invention. Figure 6 As shown, the system includes: a wave control mother board 210 and at least one wave control daughter board 220.

[0112] The beam control motherboard 210 is connected to each beam control sub-board and is used to receive a switching control instruction, obtain a target beam control code table corresponding to a beam to be switched with a directional switching requirement on the phased array antenna according to the received switching control instruction, and distribute it to at least one beam control sub-board.

[0113] Optionally, the phased array antenna beam control system may include a control center / host computer module, which can obtain the pitch angle and azimuth angle of the target beam pointing by calculation, represent the pitch angle and azimuth angle by a beam pointing number, and generate a beam switching control instruction containing the beam pointing number and send it to the beam control motherboard 210.

[0114] Optionally, the beam control motherboard 210 includes a control center / host computer interface, a first field programmable logic gate array chip, and a beam control daughter board interface. The beam control motherboard receives a switching control instruction through the control center / host computer interface; the first field programmable logic gate array chip is used to calculate a target beam control code table corresponding to the beam to be switched according to the switching control instruction; and the beam control motherboard distributes the target beam control code table to the corresponding beam control daughter board through the beam control daughter board interface.

[0115] Figure 7 A schematic diagram of the structure of a wave control motherboard provided for an embodiment of the present invention, as shown in the figure, the wave control motherboard 210 may include but is not limited to a control center / host computer interface, a first field programmable gate array (FPGA) and a wave control daughter board interface, which are used to complete the reception of control instructions, the solution of the wave control code table address, and the reading and distribution of the wave control code table. Among them, the control center / host computer interface is connected to the control center / host computer module, and the wave control motherboard 210 can receive the switching control instruction sent by the control center / host computer module through the control center / host computer interface; the first FPGA chip is used to complete the solution of the switching control instruction, the calculation of the wave control code table address, the reading and distribution of the wave control code table; the wave control daughter board interface is connected to the wave control daughter board module, and the wave control motherboard 210 can distribute the wave control code table corresponding to the beam to be cut to the wave control daughter board through the wave control daughter board interface.

[0116] Optionally, the wave control motherboard 210 also includes a set number of storage chips; the storage chip is used to store an information table, the information table including a wave control code table corresponding to each beam formed by the phased array antenna; the first field programmable logic gate array chip is connected to each storage chip; factors affecting the set number of storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the number of array elements of the phased array antenna.

[0117] Specifically, an information table is pre-stored in the beam control motherboard 210, and the information table stores the beam control code table of each beam. The beam control motherboard 210 includes a set number of storage chips (FLASH chips) for storing the information table containing the beam control code table corresponding to each beam. The first FPGA chip is connected to each FLASH chip, and the beam control code table can be read from the FLASH according to the beam switching control instruction.

[0118] Furthermore, in the beam control system, the number of FLASH chips is related to factors such as the chip memory size, the number of beams, the total number of beam pointing numbers, the beam switching time index, and the number of array elements of the phased array antenna. The memory occupied by the beam control code table in the FLASH chip can be calculated using the following formula:

[0119] N_flash=N_f0×N_loc×N_arr×2×N_bit,

[0120] Among them, N_flash is the memory size occupied by the beam control code table in the FLASH chip, N_f0 is the total number of beam frequency levels, N_arr is the total number of beam pointing numbers, N_arr is the total number of phased array antenna elements, and N_bit is the number of storage bits of a digital-to-analog conversion control code.

[0121] The more beams a phased array antenna generates, the more beam control code tables are required for beam control, and the more information in the beam control code tables, the more FLASH chip memory is required. Under the condition of meeting the storage requirements, the number of FLASH chips can be reasonably increased to reduce the beam switching time. For example, for a phased array antenna that needs to control multiple beams, the beam control code tables for multiple beams can be stored in one FLASH chip. At this time, the first FPGA chip needs to read the multi-beam beam control code tables in sequence and control them in sequence; the beam control code tables for each beam can also be stored in different FLASH chips. At this time, the first FPGA can read multiple beam control code tables at the same time and control multiple beams.

[0122] Optionally, the first field programmable logic gate array chip is specifically used to: parse the switching control instruction to obtain the beam center frequency and beam pointing number contained in the switching control instruction; obtain characteristic parameters of the phased array antenna, the characteristic parameters including the total number of beam pointing numbers, the total number of array elements of the phased array antenna, the coordinates and spacing of each element of the phased array antenna, the layout and beam shaping of the phased array antenna; calculate the target beam control code table corresponding to the beam to be cut according to the beam center frequency, beam pointing number and characteristic parameters of the phased array antenna.

[0123] Specifically, the first FPGA chip can parse out the beam center frequency and beam pointing number in the beam switching instruction. Given the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the beam control code table stored in at least one storage chip, the starting address of the target beam control code table corresponding to the beam to be switched can be calculated. The calculation formula is as described in the above embodiment.

[0124] Optionally, the wave control motherboard 210 also includes a host computer interface, a power interface, a clock interface, an RS422-SPI conversion circuit and a power modulation circuit. The host computer interface is connected to the host computer module and is used to receive control instructions when testing the wave control motherboard. The RS422-SPI conversion circuit is used to complete the conversion of instruction information, and the power modulation circuit is used to complete voltage modulation and control.

[0125] At least one wave control sub-board 220 is used to determine and adjust the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table after receiving the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0126] Among them, at least one wave control sub-board 220 includes a wave control motherboard interface, at least one digital-to-analog conversion chip and at least one vector modulator chip, and each digital-to-analog conversion chip is connected to at least one vector modulator chip; at least one wave control sub-board 220 receives the wave control code table distributed by the wave control motherboard 210 through the wave control motherboard interface; at least one digital-to-analog conversion chip is used to extract the digital-to-analog conversion control code in the wave control code table, and establish two orthogonal voltages according to the digital-to-analog conversion control code; at least one vector modulator chip is used to determine the amplitude and phase of the corresponding array element of the phased array antenna according to the two orthogonal voltages combined with the vector modulator chip characteristic table.

[0127] Figure 8 A schematic diagram of the structure of a wave control sub-board provided in an embodiment of the present invention, as shown in the figure, the wave control sub-board 220 includes but is not limited to a wave control motherboard interface, a digital-to-analog conversion chip (DAC), a vector modulator chip (VM) and a radio frequency interface, which is used to receive the wave control code table sent by the wave control motherboard, and complete the amplitude and phase modulation according to the DAC control code in the wave control code table. Among them, the wave control motherboard interface is connected to the wave control motherboard, the radio frequency interface is connected to the radio frequency module, the DAC chip is used to convert the digital signal into an analog signal and output it to the control end of the VM chip, and the VM chip is used to complete the amplitude and phase modulation according to the analog signal sent by the DAC.

[0128] Furthermore, the DAC chip can extract two DAC control codes from the received wave control code table, establish two orthogonal voltages (I / Q two-way voltages) according to the two DAC control codes and send them to the VM chip. The VM chip can be an analog IQ vector modulator, which can determine the amplitude and phase of the array element corresponding to the beam to be cut according to the received I / Q two-way voltage combined with the VM chip characteristic table, and the corresponding relationship between the array element amplitude and phase and the I / Q two-way voltage is consistent with the VM chip characteristic table.

[0129] Optionally, at least one digital-to-analog conversion chip is further used to: receive a corresponding wave control code table according to address information in the wave control code table.

[0130] Specifically, the address information in the wave control code table is the array element coordinates, which can be represented by the array element row number and column number in the wave control code table, and each wave control sub-board controls the corresponding array element. When distributing the wave control code table to the wave control sub-board, the wave control code table corresponding to the array element of each wave control sub-board can be sent according to the array element row number and column number.

[0131] Optionally, the wave control sub-board 220 also includes at least one second field programmable logic gate array chip, each second field programmable logic gate array chip is connected to at least one digital-to-analog conversion chip, and the second field programmable logic gate array chip is used to receive the wave control code table distributed by the wave control motherboard according to the address information in the wave control code table, and then distribute the wave control code table to at least one digital-to-analog conversion chip.

[0132] Fig. 9 This is a structural diagram of a beam control system containing an FPGA chip in a sub-board provided by an embodiment of the present invention. As shown in the figure, the system is a phased array antenna beam control system with 576 array elements, which can form 2 beams at the same time. There are 512 numbered beam directions in the sub-satellite coverage area, and each beam can be quickly switched between 512 beam directions. The system adds a second FPGA chip in the wave control sub-board. The wave control motherboard first sends the wave control code table to the second FPGA chip in the wave control sub-board, and then the second FPGA chip completes the DAC control and the distribution of the DAC control code. The wave control sub-board of the system has a total of 9 second FPGA chips, and the second FPGA chip of each wave control sub-board controls 64 array elements, that is, 9 sub-board FPGAs control 2 beams of 576 array elements. At the same time, the system uses two FLASH chips to connect with the first FPGA chip of the beam control motherboard. Each FLASH chip stores the beam control code table of a beam. When the beam control system receives the beam switching instruction sent by the control center / host computer module, the first FPGA chip calculates the starting address of each beam beam control code table, and then reads the beam control code table of each beam in the FLASH in parallel and completes the beam switching control at the same time.

[0133] Optionally, the vector modulator chip characteristic table is obtained by testing the vector modulator; the vector modulator characteristic table includes two orthogonal voltages and amplitudes and phases of corresponding array elements.

[0134] Specifically, the VM chip characteristic table is obtained by testing the VM chip; the VM chip characteristic table includes I / Q two-way voltages and amplitudes and phases of corresponding array elements.

[0135] Optionally, the characteristic table of each VM chip is related to itself. To obtain the characteristic table of the VM chip, it can be tested at the factory to form a voltage-controlled amplitude and phase change table, thereby determining the correspondence between the amplitude and phase and the I / Q voltage values ​​generated by the DAC. Furthermore, the VM chip characteristic table can be interpolated according to system requirements to improve the control accuracy of the amplitude and phase, thereby improving the accuracy of beam switching. In theory, the accuracy can be infinitely improved and the error can be reduced through interpolation.

[0136] Optionally, the wave control sub-board 220 also includes a power modulation chip to perform voltage modulation and control.

[0137] Optionally, the phased array antenna beam control system may include a radio frequency module, which is a module responsible for loading and transmitting radio frequency signals. After the beam control sub-board 220 determines the target amplitude and target phase of each array element included in the beam to be cut, the radio frequency module can send it to the phased array antenna. The beam pointing is related to the amplitude and phase of the array element, so that the phased array antenna can achieve beam switching by adjusting the amplitude and phase of the array element.

[0138] Optionally, the phased array antenna beam switching control system also includes a host computer module, which is used to test the beam control motherboard and establish a beam control code table; the beam control code table includes the beam center frequency, beam pointing number, array element row number, array element column number and a two-digit digital-to-analog conversion control code.

[0139] Specifically, assuming that the antenna array is a rectangular grid with rectangular boundaries and arranged in two dimensions with equal spacing, according to the θ and Angle, the beam pointing is changed only by changing the array element phase without amplitude attenuation, and the calculation formula of the phase shift value of each array element is as described in the above embodiment.

[0140] According to the phase shift value and VM characteristic table obtained by the above calculation, the wave control motherboard is tested through the host computer, and the I / Q two-way input voltage required for a certain phase shift value is found by the VM chip, and converted into the DAC control code required by the DAC chip according to the digital-to-analog conversion relationship of the DAC chip. The beam center frequency, beam pointing number, array element row number, array element column number and DAC control code are stored in the FLASH accordingly, so as to determine what kind of control instruction is needed to switch a certain beam to the set pointing direction.

[0141] The embodiment of the present invention provides a phased array antenna beam control system, including: a beam control motherboard and at least one beam control subboard; the beam control motherboard is connected to each beam control subboard, and is used to receive a switching control instruction, and obtain a target beam control code table corresponding to the beam to be cut with a direction switching requirement on the phased array antenna according to the received switching control instruction, and distribute it to at least one beam control subboard; at least one beam control subboard is used to determine and adjust the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table after receiving the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut. The phased array antenna beam control system provided by the embodiment of the present invention completes control instruction resolution and table lookup through the field programmable logic gate array in the beam control motherboard, so that the beam control subboard adjusts the amplitude and phase of the array element according to the digital-to-analog conversion control code in the wave control code table, can control multiple beams at the same time, is applied to beam control in different scenarios, realizes fast and accurate beam pointing switching, and can also realize on-orbit reconstruction of the beam control system to optimize the performance of the phased array antenna.

[0142] The above system can execute the methods provided by all the above embodiments of the present disclosure, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not described in detail in this embodiment, please refer to the methods provided by all the above embodiments of the present disclosure.

[0143] Embodiment 4

[0144] The embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processing device, a phased array antenna beam control method as in the embodiment of the present invention is implemented. The above-mentioned computer-readable medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0145] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0146] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0147] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: the control center / host computer module determines the target beam pointing corresponding to the beam to be cut with a pointing switching requirement on the phased array antenna, generates a switching control instruction according to the target beam pointing and sends it to the wave control motherboard; the wave control motherboard receives the switching control instruction, searches for the target wave control code table corresponding to the beam to be cut with a pointing switching requirement on the phased array antenna from a pre-stored information table according to the received switching control instruction, and distributes it to at least one wave control sub-board; after receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table, so that the phased array antenna realizes beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

[0148] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0149] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0150] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0151] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0152] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0153] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A phased array antenna beam control method, characterized in that: include: The wave control motherboard parses the switching control instruction, obtains the beam center frequency and beam pointing number contained in the switching control instruction, obtains the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in the storage chip, calculates the starting address of the wave control code table corresponding to the beam to be cut according to the beam center frequency and the beam pointing number, the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in the storage chip, and searches for the target wave control code table corresponding to the beam to be cut in parallel from the pre-stored information table according to the starting address of the wave control code table, and distributes the target wave control code table to the corresponding wave control sub-board; wherein the information table is stored in a set number of storage chips, and the information table includes the wave control code table corresponding to each beam formed by the phased array antenna, and the wave control code table of each beam to be cut is stored in a different storage chip respectively; After receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the beam to be cut through the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the beam to be cut.

2. The method according to claim 1, characterized in that The factors affecting the set number of the storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the total number of array elements of the phased array antenna.

3. The method according to claim 1, characterized in that Distributing the target wave control code table to the corresponding wave control sub-board includes: The wave control code table is distributed to the corresponding wave control sub-board according to the address information in the wave control code table.

4. The method according to claim 1, characterized in that: After receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the to-be-cut beam through the target wave control code table, including: The amplitude and phase control codes in the target wave control code table are extracted, and the phase shift value of the digital phase shifter and the attenuation value of the digital attenuator are determined according to the amplitude and phase control codes.

5. The method according to claim 1, characterized in that After receiving the target wave control code table, the wave control sub-board determines and adjusts the target amplitude and target phase of each array element included in the to-be-cut beam through the target wave control code table, and further includes: Extracting the digital-to-analog conversion control code from the wave control code table, and establishing two orthogonal voltages according to the digital-to-analog conversion control code; The target amplitude and target phase of the corresponding array element of the phased array antenna are determined according to the two orthogonal voltages combined with the vector modulator chip characteristic table.

6. The method according to claim 1, characterized in that Before the wave control motherboard receives the switching control instruction, the method further includes: The beam control motherboard is tested by a host computer to establish the beam control code table; the beam control code table includes the beam center frequency, the beam pointing number, the array element row number, the array element column number and the amplitude and phase control code.

7. A phased array antenna beam control system, characterized in that: include: A wave control motherboard and at least one wave control daughterboard; The beam control motherboard is connected to each beam control sub-board and is used to receive a switching control instruction, obtain a target beam control code table corresponding to a beam to be switched with a directional switching requirement on the phased array antenna according to the received switching control instruction, and distribute it to the at least one beam control sub-board; The at least one wave control sub-board is used to determine and adjust the target amplitude and target phase of each array element included in the to-be-cut beam through the target wave control code table after receiving the target wave control code table, so that the phased array antenna can achieve beam pointing switching by adjusting the amplitude and phase of each array element included in the to-be-cut beam; The wave control motherboard includes a control center / host computer interface, a first field programmable logic gate array chip and a wave control daughter board interface and a set number of storage chips. The wave control motherboard receives a switching control instruction through the control center / host computer interface. The first field programmable logic gate array chip is used to calculate the target wave control code table corresponding to the beam to be cut according to the switching control instruction. The wave control motherboard distributes the target wave control code table to the corresponding wave control daughter board through the wave control daughter board interface. The storage chip is used to pre-store the wave control code table corresponding to each beam formed by the phased array antenna. The first field programmable logic gate array chip is connected to each of the storage chips to parse the switching control instruction, obtain the beam center frequency and beam pointing number contained in the switching control instruction, and obtain the The total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in the storage chip, calculate the starting address of the wave control code table corresponding to the beam to be cut according to the beam center frequency and the beam pointing number, the total number of beam pointing numbers of the phased array antenna, the total number of array elements of the phased array antenna, the number of storage bits of a digital-to-analog conversion control code, and the starting position of the wave control code table stored in the storage chip, and search the target wave control code table from the storage chip according to the starting address of the wave control code table; wherein, the information table is stored in the storage chip, the information table includes the wave control code tables corresponding to each beam formed by the phased array antenna, and the wave control code tables of each of the beams to be cut are respectively stored in different storage chips.

8. The system according to claim 7, characterized in that The first field programmable logic gate array chip is specifically used for: Parsing the switching control instruction to obtain a beam center frequency and a beam pointing number contained in the switching control instruction; Acquire characteristic parameters of the phased array antenna, wherein the characteristic parameters include the total number of beam pointing numbers, the total number of array elements of the phased array antenna, the coordinates and spacing of each array element of the phased array antenna, and the array mode and beamforming of the phased array antenna; A target beam control code table corresponding to the beam to be cut is calculated according to the beam center frequency, the beam pointing number and the characteristic parameters of the phased array antenna.

9. The system according to claim 7, characterized in that The factors affecting the set number of the storage chips include: the memory size of the storage chip, the number of beams, the total number of beam pointing numbers, the beam switching time index and the total number of array elements of the phased array antenna.

10. The system according to claim 7, characterized in that The at least one wave control daughter board includes a wave control mother board interface, at least one digital-to-analog conversion chip and at least one vector modulator chip, and each digital-to-analog conversion chip is connected to at least one vector modulator chip; The at least one wave control sub-board receives the wave control code table distributed by the wave control motherboard through the wave control motherboard interface; The at least one digital-to-analog conversion chip is used to extract the digital-to-analog conversion control code in the wave control code table, and establish two orthogonal voltages according to the digital-to-analog conversion control code; The at least one vector modulator chip is used to determine the amplitude and phase of the corresponding array element of the phased array antenna according to the two orthogonal voltages combined with the vector modulator chip characteristic table.

11. The system according to claim 10, characterized in that The at least one digital-to-analog conversion chip is also used for: The corresponding wave control code table is received according to the address information in the wave control code table.

12. The system according to claim 10, characterized in that The wave control daughter board also includes at least one second field programmable logic gate array chip, each second field programmable logic gate array chip is connected to at least one digital-to-analog conversion chip, and the second field programmable logic gate array chip is used to receive the wave control code table distributed by the wave control mother board according to the address information in the wave control code table, and then distribute the wave control code table to the at least one digital-to-analog conversion chip.

13. The system according to claim 10, characterized in that The vector modulator chip characteristic table is obtained by testing the vector modulator; the vector modulator characteristic table includes the two orthogonal voltages and the amplitudes and phases of the corresponding array elements.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processing device, the phased array antenna beam control method as described in any one of claims 1-6 is implemented.

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