Atomic layer etching and selective deposition processes for resist improvement in extreme ultraviolet lithography

Abstract

This invention provides a method and system for reducing the roughness of EUV resist and improving etching characteristics. The method involves deslagging the EUV resist, filling depressions in the EUV resist, and protecting the EUV resist with a capping layer. The resulting EUV resist has a smoother characteristic and increased selectivity to the underlying layer, thereby improving the quality of the etching characteristics. The capping layer can be removed after etching of the underlying layer.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] Patterning of thin films is often a key step in the manufacture of micro- and nano-scale devices, such as in semiconductor processing for the manufacture of semiconductor devices. Patterning involves photolithography. In conventional photolithography, such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a photoresist, thereby causing a chemical reaction in the photoresist that removes certain portions of the photoresist after development to form a pattern.

[0004] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and above. For example, in the 16 nm node, the width of a typical via or line in a damascene structure is generally no greater than about 30 nm. The shrinking of features on advanced semiconductor integrated circuits (ICs) and other devices is driving photolithography to improve resolution.

[0005] Extreme ultraviolet (EUV) lithography operates at 30nm scale with different light sources and photoresist materials. EUV lithography can cause roughness in the photoresist due to stochastic effects. EUV lithography may also use photoresist materials that do not have sufficient etch selectivity to the underlying layer being etched. Both properties are undesirable. Summary of the invention

[0006] Disclosed herein are methods and systems for reducing the roughness of extreme ultraviolet (EUV) resists and improving etched features. This can be accomplished by descumming, recess filling, and protecting the EUV resist. The resulting EUV resist has smoother features and increases selectivity to underlying layers, thereby improving the quality of the etched features.

[0007] In one aspect of the embodiments presented herein, a method includes: providing a semiconductor substrate comprising a patterned EUV resist to a processing chamber, the patterned EUV resist exposing a portion of an underlying metal oxide layer; treating the exposed portion of the metal oxide layer with a halogen-containing plasma; selectively depositing a silicon-containing precursor on the carbon-containing features of the patterned EUV resist; and treating the silicon-containing precursor to convert the silicon-containing precursor into a silicon oxide capping layer on the carbon-containing features of the patterned EUV resist. In some embodiments, treating the exposed portion of the metal oxide layer with the halogen-containing plasma is performed using a voltage bias between 0V and 100V, including 0V and 100V. In various embodiments, the halogen-containing plasma includes a hydrogen halide. In some implementations, the halogen-containing plasma includes HBr. In various embodiments, the silicon-containing precursor is selective to the carbon-containing features over the metal oxide layer treated with the halogen-containing plasma, and the ratio is greater than about 10:1.

[0008] In some embodiments, the method further comprises etching the underlying metal oxide layer using the silicon oxide capping layer and the patterned EUV resist as a mask. In some embodiments, the silicon-containing precursor comprises one or more of SiH4, Si2H2, or SiCl4. In various embodiments, processing the silicon-containing precursor uses an oxygen-containing reactant. In some implementations, the oxygen-containing reactant is selected from the group consisting of: H2O, NO, N2O, CO2, O2, or O3.

[0009] In various embodiments, the method further comprises, before treating the metal oxide layer with a halogen-containing plasma, removing undesirable carbon material (scum) from the carbon-containing features of the patterned EUV resist using an atomic layer etch (ALE) process, comprising: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the carbon-containing features; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas to remove the modified scum. In some embodiments, the halogen-containing gas comprises one or more of a halogen gas and a halide gas. In some embodiments, the halogen gas is Cl2 or Br2. In various embodiments, the halide gas is CF4 or HBr. In some embodiments, the inert gas comprises helium, neon, argon, or xenon. In some embodiments, exposing the modified scum on the surface of the patterned EUV resist to a plasma is performed with a voltage bias between 0V and 100V and including 0V and 100V.

[0010] In various embodiments, the method further comprises: after selectively depositing the silicon-containing precursor, modifying a surface layer of the precursor, and exposing the semiconductor substrate to a plasma of an inert gas to remove the modified layer of the precursor by atomic layer etching (ALE). In some implementations, the method further comprises repeating the selective deposition and ALE operations to fill the recesses on the carbon-containing features of the patterned EUV resist. In various embodiments, the method further comprises etching the metal oxide layer using the silicon oxide capping layer and the patterned EUV resist as a mask.

[0011] In another aspect of the embodiments disclosed herein, a method is provided, comprising: providing a semiconductor substrate comprising a patterned EUV resist to a processing chamber, the patterned EUV resist exposing a portion of an underlying metal oxide layer; selectively depositing an amorphous carbon capping layer on the carbon-containing features of the patterned EUV resist by exposing the semiconductor substrate to a gas mixture comprising a hydrocarbon, hydrogen, and an inert gas in the presence of a plasma. In some embodiments, the hydrocarbon is CH4 or C2H2. In some implementations, the inert gas comprises helium, neon, argon, or xenon. In various embodiments, the method further comprises removing undesirable carbon material (scum) from the carbon-containing features of the patterned EUV resist using an atomic layer etch (ALE) process before selectively depositing the amorphous carbon capping layer, comprising: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the carbon-containing features; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas. In some implementations, the halogen-containing gas includes one or more of a halogen gas and a halide gas. In some embodiments, the halogen gas is Cl2 or Br2. In some embodiments, the halide gas is CF4 or HBr. In some embodiments, the inert gas includes helium, neon, argon, or xenon. In various embodiments, exposing the modified scum on the surface of the patterned EUV resist to plasma is performed with a voltage bias between 0V and 100V and including 0V and 100V. In some embodiments, the method also includes etching the amorphous carbon capping layer deposited on the carbon-containing features of the patterned EUV resist. In some implementations, etching the deposited amorphous carbon capping layer includes: exposing the amorphous carbon capping layer to an oxygen-containing reactant to modify the amorphous carbon; and exposing the modified amorphous carbon to a plasma of an inert gas. In various embodiments, the oxygen-containing reactant is O2, O3, H2O, N2O, NO, or CO2. In some embodiments, the method further comprises repeating the selective deposition and etching the deposited amorphous carbon capping layer to fill the recesses on the carbon-containing features of the patterned EUV resist. In various embodiments, the method further comprises etching the underlying metal oxide layer using the amorphous carbon capping layer and the patterned EUV resist as a mask.

[0012] In another aspect of the embodiments disclosed herein, a method is provided, comprising: providing a semiconductor substrate containing a patterned EUV resist that exposes a portion of an underlying layer to a chamber; and removing undesirable carbon material (scum) from carbon-containing features of the patterned EUV resist using an atomic layer etch (ALE) process, comprising: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the carbon-containing features; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas. In some implementations, the underlying layer is a spin-on glass (SOG) layer or a metal oxide. In some embodiments, the method further comprises repeating a cycle of exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the patterned EUV resist; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas. In various embodiments, the halogen-containing gas comprises one or more of a halogen gas and a halide gas. In some embodiments, the halogen gas is Cl2 or Br2. In some implementations, the halide gas is CF4 or HBr. In some embodiments, the inert gas includes helium, neon, argon, neon, or xenon. In some embodiments, exposing the modified scum on the surface of the patterned EUV resist is performed with a voltage bias between 0V and 100V, including 0V and 100V. In various embodiments, the method also includes: selectively depositing a silicon-containing oxide precursor on the patterned EUV resist; repeating the ALE process, which includes: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the patterned EUV resist; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas; and treating the silicon-containing precursor to form a silicon oxide capping layer on the carbon-containing features of the patterned EUV resist.

[0013] In some implementations, the method further includes, before processing the silicon-containing oxide precursor to form a silicon oxide capping layer on the carbon-containing features of the patterned EUV resist, repeating one or more cycles of: selectively depositing a silicon-containing precursor on the patterned EUV resist; and repeating an ALE process comprising: exposing the patterned EUV resist to a halogen-containing gas to modify scum on the surface of the patterned EUV resist; and exposing the modified scum on the surface of the patterned EUV resist to a plasma of an inert gas. In various implementations, the aspect ratio between the patterned EUV resist and the exposed portion of the underlying layer is no greater than 5:1. In various embodiments, the method further includes etching the underlying layer using the silicon oxide capping layer and the patterned EUV resist as a mask.

[0014] In various embodiments, the method further comprises: selectively depositing a carbon-containing material on the patterned EUV resist by exposing the semiconductor substrate to a gas mixture comprising hydrocarbons, hydrogen and an inert gas in the presence of a plasma; modifying a surface layer of the selectively deposited carbon-containing material; and exposing the semiconductor substrate to a plasma of an inert gas by atomic layer etching (ALE) to remove the modified surface layer. In various embodiments, the inert gas comprises helium, neon, argon or xenon. In some embodiments, the method further comprises repeating the selective deposition and ALE operations to fill the recesses on the carbon-containing features of the patterned EUV resist. In various implementations, the method further comprises exposing the substrate comprising the carbon-containing material to a halogen-containing gas to modify the surface of the carbon-containing material; and exposing the modified layer to the inert gas plasma for a duration sufficient to remove the modified surface.

[0015] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A process flow diagram illustrating the operation of an exemplary embodiment is presented.

[0017] Figure 2 A diagram of an exemplary embodiment is presented.

[0018] Figure 3 A process flow diagram for deslagging operations is presented.

[0019] Figure 4A -D presents a diagram of scum and scum removal.

[0020] Figure 5 A process flow diagram illustrating the operation of another exemplary embodiment is presented.

[0021] Figure 6 A diagram of another exemplary embodiment is presented.

[0022] Figure 7 A process flow diagram illustrating the operation of an exemplary embodiment is presented.

[0023] Figure 8 A diagram of another exemplary embodiment is presented.

[0024] Fig.9A -C presents a schematic diagram of recess filling according to an embodiment disclosed herein.

[0025] Fig.10 Schematic diagram of the atomic layer etching (ALE) process.

[0026] Fig.11 and 12is a schematic diagram of an example of a processing chamber for performing a method according to the disclosed embodiments. DETAILED DESCRIPTION

[0027] In the following description, many specific details are set forth to provide a thorough understanding of the embodiments presented. The embodiments disclosed herein may be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. In addition, although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that the specific embodiments are not intended to limit the disclosed embodiments.

[0028] Extreme ultraviolet (EUV) lithography finds use in semiconductor manufacturing at 30nm and below technology nodes. Patterned EUV resists can be used to etch patterns into underlying layers, which requires the patterned EUV resist to have sufficient thickness and / or etch selectivity to maintain the pattern while etching these layers. Increasing the thickness or etch selectivity of the patterned EUV resist can improve the transfer of the pattern to the underlying layers after the etching process.

[0029] A method to increase the thickness and etch selectivity of the patterned EUV resist is to deposit a sacrificial mask or cap layer (cap) on the patterned EUV resist. The cap layer inhibits etching of the resist, thereby protecting it. The selective deposition of the cap layer can be performed to protect the top of the patterned EUV resist and allow etching of exposed features, such as the underlying metal oxide layer.

[0030] Patterned EUV resists may also exhibit roughness, which can be measured by line edge roughness (LER) and line width roughness (LWR) of the resist and the resulting etch. Reducing (e.g., minimizing) the roughness of the resist and the resulting etch can improve process yield and device performance at increasingly smaller critical dimensions. Reducing (e.g., minimizing) both LER and LWR can improve the results of EUV lithography etch processes.

[0031] Incomplete removal of material after extreme ultraviolet lithography of the photoresist during patterning operations can increase roughness due to residues (hereinafter referred to as "scum") left on the patterned EUV resist. Scum can affect etching of the pattern into the underlying layers, which is undesirable. For patterning accuracy, it is desirable to remove the scum (or "de-scum") without damaging other features or structures on the semiconductor substrate. De-scum (or de-scum) refers to the process of removing undesirable carbon materials from between carbon-containing wafer features (e.g., patterned EUV resist). Therefore, removing scum can improve the patterning process and reduce roughness.

[0032] The extreme ultraviolet lithography process of the resist during the patterning operation can also form "divots" on the patterned EUV resist, which are areas that are thinner than the surrounding EUV resist. Divots can cause defects in the underlying layer due to failure to mask the underlying layer during the etching process, resulting in poor etching of the underlying layer. Divot filling refers to the process of adding material to reduce the line thickness variation of wafer features (such as patterned EUV resist). For patterning accuracy, it is desirable to perform divot filling without collapsing or masking features or structures on the semiconductor substrate. Therefore, filling of divots can improve the patterning process and prevent bridging defects.

[0033] In some embodiments, the recess filling may include cyclic selective deposition and selective etching to fill the recess without significantly increasing the aspect ratio or depositing material between features. The selective deposition will only deposit on the carbon-containing features of the patterned EUV resist. The selective etching will etch the inside recess at a lower rate than the non-recessed areas. Therefore, by repeating these two operations, the recess will be filled while maintaining the critical dimensions of the patterned EUV resist. In some embodiments, the recess filling is performed as part of depositing a capping layer.

[0034] Methods of depositing capping layers, removing scum, and filling recesses are provided herein to improve intra-die, intra-wafer, and batch-to-batch patterning accuracy for EUV resists. Such techniques selectively improve the etch selectivity of patterned EUV resists and reduce the roughness of etched features without changing the critical dimensions of the features. The disclosed embodiments may perform one, two, or all three of depositing capping layers, removing scum, and filling recesses.

[0035] In various embodiments disclosed herein, a semiconductor substrate is provided to a processing chamber. The semiconductor substrate can be a silicon or other semiconductor wafer (e.g., a 200-mm wafer, a 300-mm wafer, or a 450-mm wafer), including a wafer on which one or more layers of material (e.g., dielectric, conductive, or semiconductor material) are deposited. In certain embodiments, the semiconductor substrate comprises a blanket layer of silicon (e.g., amorphous silicon), or a blanket layer of germanium. The semiconductor substrate comprises a patterned EUV resist previously deposited and patterned on the semiconductor substrate.

[0036] The processing chamber is a semiconductor processing chamber and can be a processing chamber in a multi-chamber device or a single-chamber device, such as Fig.11 and 12 The semiconductor substrate may be disposed on a susceptor for holding the substrate.

[0037] The patterned EUV resist layer can be made of a variety of materials. In some embodiments, the patterned EUV resist layer can be made of a film containing an organic metal oxide, such as an organic tin oxide (e.g., available from Inpria Corp.), or a conventional chemically amplified resist from Dow / Rohm, Fujifilm, JSR, TOK, and Shin-Etsu Polymer. The patterned EUV resist may also include a chemically amplified resist. The patterned EUV resist layer may be, for example, 10-40 nm thick.

[0038] Figure 1 A process flow diagram is provided for performing operations of a method according to the disclosed embodiments. Figure 1 The method shown may be performed as part of a process to etch a metal oxide layer. In operation 102, a semiconductor substrate (or substrates) having a patterned EUV resist exposing a portion of an underlying metal oxide layer is received in a process chamber. The semiconductor substrate may be in the process chamber due to a previous operation, or may be introduced into the process chamber.

[0039] Operation 104 is an optional operation to descum the patterned EUV resist. In some embodiments, operation 104 is performed to descum the patterned EUV resist, while in other embodiments, operation 104 may not be performed. Whether to perform operation 104 may depend on whether there is any scum on the substrate that affects the critical dimensions of the patterned EUV resist.

[0040] Figure 3 A process flow diagram for descumming a patterned EUV resist, such as will be performed in operation 104, is provided. In operation 302, a substrate having a patterned EUV resist is received in a process chamber. The semiconductor substrate may be in the process chamber due to a previous operation, or may be introduced into the process chamber. The patterned EUV resist exposes portions of an underlying layer. Figure 1 In the context of , the underlying layer is a metal oxide layer. However, Figure 3 The method can also be applied to various layers, including dielectric layers and conductive layers, for example, silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers.

[0041] Operation 306, which includes both operations 308 and 310, removes scum by atomic layer etching (ALE) processing. Background knowledge of ALE helps explain operation 306. In general, ALE can be performed using any suitable technology. Examples of atomic layer etching techniques are described in U.S. Patent No. 8,883,028, issued on November 11, 2014, and U.S. Patent No. 8,808,561, issued on August 19, 2014, which are incorporated herein by reference for the purpose of describing exemplary ALE and etching techniques. An example of ALE technology combined with atomic layer deposition (ALD) technology is described in U.S. Patent No. 9,576,811, issued on February 21, 2017, which is incorporated herein by reference. In various embodiments, ALE can be performed with plasma, or can be performed thermally.

[0042] ALE is performed in cycles. The concept of an "ALE cycle" is relevant to the discussion of various embodiments herein. Typically, an ALE cycle is a minimum set of operations for performing an etching process, such as etching a single layer. The result of one cycle is that at least some of the film layer on the substrate surface is etched. Typically, an ALE cycle includes a modification operation for forming a reaction layer, followed by a removal operation to remove or etch only the modified layer. The cycle may include certain auxiliary operations, such as sweeping one of the reactants or byproducts.

[0043] Typically, an ALE cycle contains one instance of a unique sequence of operations. For example, an ALE cycle may include the following operations: (i) delivering reactant gas, (ii) purging reactant gas from the reaction chamber, (iii) delivering removal gas and optionally plasma, and (iv) purging the chamber. In some embodiments, etching may be performed non-conformally. Fig.10 Two exemplary schematics of ALE cycles are shown. Figures 1071a-1071e show a general ALE cycle. In 1071a, a substrate is provided. In 1071b, the surface of the substrate is modified. In 1071c, the next operation is ready. In 1071d, the modified layer is being etched. In 1071e, the modified layer is removed. Similarly, Figures 1072a-1072e show examples of ALE cycles for etching carbon-containing films. In 1072a, a carbon-containing substrate is provided, which contains many carbon atoms. In 1072b, a reactant gas tetrafluoromethane (CF4) is introduced to the substrate, which modifies the surface of the substrate. For example, the schematic in 1072b shows that some CF4 is adsorbed onto the surface of the substrate. Although Figure 2 CF4 is described in , but any halogen-containing material or suitable reactant may be used. In 1072c, the reactant gas CF4 is purged from the chamber.

[0044] In 1072d, as He+ As shown by the plasma material and arrows, a removal gas helium is introduced with a directional plasma, and ion bombardment is performed to remove the modified surface of the substrate. Figure 2 He is depicted in , but it should be understood that other removal gases may be used, such as helium, nitrogen, argon, and combinations thereof. During removal, a bias may be applied to the substrate to attract ions toward the substrate. For ALE, a bias is typically applied to the substrate to achieve a desired degree of ion directionality toward the substrate. Thus, the ions may be aligned to effectively remove scum from the substrate. However, in some embodiments, no bias is used to reduce sputtering of the substrate and remove less material. In 1072e, the chamber is purged and byproducts are removed.

[0045] A complete ALE cycle may only partially etch material between about 0.1 nm and about 50 nm, or material between about 0.1 nm and about 5 nm, or material between about 0.2 nm and about 50 nm, or material between about 0.2 nm and about 5 nm. The amount of material etched in one cycle may depend on the purpose of the etching; for example, after etching a carbon-containing material to form a pattern, the amount of material etched away depends on the desired critical dimensions of the layer to be etched using the patterned carbon-containing material, for example, less than or in to within the range.

[0046] return Figure 3 In operation 308, the substrate is exposed to a halogen-containing gas (e.g., carbon tetrafluoride (CF4)) with or without igniting a plasma to modify the surface of the carbon-containing material on the substrate (e.g., on the mandrel). The modification operation 308 forms a thin reactive surface layer, for example, less than 1000 mm thick. It is easier to remove than unmodified material in subsequent removal operations. Suitable halogen-containing gases include, but are not limited to: halocarbons, including fluorocarbons (C x F y ) (including CF4), hydrofluorocarbons (C x H y F z ), organic chlorides, organic bromides (C x Br y ) and organic iodide (C x I y); halides, including HBr, HCl, HF, and HI; and halogen gases, including Br2, Cl2, F2, and I2. In some embodiments, the halogen-containing gas is Br2 or Cl2. In some embodiments, the halogen-containing gas is CF4 or HBr. The halogen injection of the substrate produces a saturated monolayer or sub-monolayer on the substrate. The halogen can be adsorbed onto the surface of the substrate without reacting with the carbon-containing material. The halogen-containing gas can be optionally accompanied by a carrier gas, which can be any of helium, nitrogen, argon, neon, xenon, and combinations thereof. Operation 308 can be performed for a duration sufficient to fully saturate the halogen gas on the substrate surface. In some embodiments, the duration can be about 0.1 seconds. In some embodiments, the duration can be between about 0.1 seconds and about 3 seconds, for example, about 0.5 seconds or about 1 second. For example, in some embodiments, the chamber pressure can be about 5 mTorr to 100 mTorr, the chamber temperature is less than 60° C., the plasma power for each substrate station is between about 50 W and about 150 W, and the voltage bias is between 0 V and 60 V. The reactant flow rate can be between 100 sccm and 300 sccm. All process condition ranges are inclusive.

[0047] In operation 310, the substrate containing the saturated monolayer is exposed to an inert gas and a plasma is ignited to remove the modified surface. The plasma applied in operation 310 can be a plasma containing or derived from helium at a frequency of 13.56 MHz or 27 MHz. Plasma derived or generated from N2 can also be used. The selection of plasma can be determined based on the amount of ligands or co-ligands associated with the plasma generated from a given gas. For example, lower amounts of ligands or co-ligands tend to cause the plasma to exhibit relatively directional behavior. However, lower amounts of ligands or co-ligands can result in, for example, relatively excited ions of the plasma, thereby etching more.

[0048] In some embodiments, frequencies of 400 kHz and 60 MHz may be used to control ion energy. Additionally, pulsed plasma activation techniques and dual frequency activation, e.g., low and high frequencies in series, may be used, optionally. The plasma source may include a capacitively coupled reactor (CCP) or an inductively coupled reactor (ICP) delivered from a SHD, or may be thermal, UV, or photon based.

[0049] Inert gas can be selected from including, but not limited to, Ar, He, N2 group, or alternatively the substrate is exposed to vacuum. In order to remove the scum that is modified after being exposed to halogen-containing gas (as shown in operation 308), the surface of the feature and the substrate can be exposed to an energy source in operation 310. Suitable energy sources can include activation or sputtering gas or chemically reactive substances that cause removal, such as helium, to etch (or descum) the substrate by directional sputtering. In some embodiments, the removal operation can be performed by ion bombardment. In some embodiments, operations 302-312 are performed under voltage bias, to adjust the directionality of etching to obtain a desired profile. In some embodiments, operations 302-312 are performed without voltage bias, to isotropically remove scum from the feature surface.

[0050] The amount of sputtering gas can be controlled to etch (or descum) only a targeted amount of material, such as less than or in to In some embodiments, the chamber pressure may be varied between modification and removal operations. The pressure of the gas may depend on the size of the chamber, the flow rate of the gas, the temperature of the reactor, the type of substrate, and the size of the substrate to be etched. In some embodiments, a higher gas pressure may allow for a relatively fast cycle completion time. In some embodiments, the chamber pressure is between 5mTorr and 100mTorr.

[0051] The plasma is ignited at a certain plasma power, which is selected to reduce the sputtering of the material on the substrate surface and control the amount of material etched in each cycle. In some embodiments, the plasma power of a single substrate station can be between about 50W and about 150W, such as 100W. Although the general use of plasma may cause some sputtering, sputtering can usually be controlled by performing the disclosed embodiments or pulsed voltage bias at low plasma power and low voltage bias to obtain fine control of the amount of material etched in each cycle, thereby patterning the carbon-containing material to obtain vertical or clean feature sidewalls. For example, in some embodiments, the chamber pressure can be about 5mTorr to 100mTorr, the plasma power of each substrate station is between about 50W and about 150W, and the voltage bias is between 0V and 100V. In some embodiments, the voltage bias can be pulsed between 0V and about 400V, or between 0V and about 100V. In some embodiments, the plasma can be ignited for a duration of less than about 5 seconds, such as between about 1 second and about 5 seconds. All treatment conditions are inclusive.

[0052] In operation 312, it is determined whether the substrate has been sufficiently etched or cleaned. If not, operations 308-312 may be optionally repeated. Performing operation 306 may constitute one ALE cycle. In various embodiments, etching or descumming may be performed cyclically. The number of cycles depends on the amount of etching required for a particular application. In various embodiments, between about 1 cycle and about 100 cycles may be used. In some embodiments, about 5 cycles to about 100 cycles may be used. In some embodiments, the number of cycles may be about 1 to about 40 cycles, or about 1 to about 20 cycles, or about 30 to about 40 cycles. Any suitable number of ALE cycles may be included to etch the desired amount of film. In some embodiments, ALE is performed cyclically to etch about 10% of the surface of these layers on the substrate. to about In some embodiments, the ALE cycles etch the surface of these layers on the substrate by about to about In some embodiments, the number of cycles can be selected by using optical emission spectroscopy (OES) to identify the amount of etching and set an endpoint at which the etching is stopped. In some embodiments, the cycle time (duration of a single cycle) can be less than 1 second. ALE (such as Figure 3 As shown and discussed) each cycle can be to Many ALE processes more typically remove about to

[0053] Figure 4A-D shows the Figure 3 Perspective and side views of patterned EUV resist being processed for descum. Figure 4A A perspective view of a patterned EUV resist having a feature (e.g., a mandrel 400) is shown with a photoresist (PR) scum 402 on or extending from the mandrel 400. The scum 402 is removed from the mandrel 400 by an atomic layer etch (ALE) process, such as Figure 4B shown. Figure 4C and 4D A cross-sectional side view of an array 404 of mandrels 400 is shown formed on a substrate 406. One of ordinary skill in the art will appreciate that substrate 406 may include a multi-layer stack suitable for semiconductor processing, which may also include other layers such as etch stop layers, capping layers, barrier layers, and other underlying layers.

[0054] Undesirable carbon-based materials that remain on a substrate after photolithography, such as footings, stringers, or other forms of undesirable substrate surface roughness, are collectively referred to herein as "dross," such as dross 402. In some embodiments, dross 402 may include a carbon content that is similar or the same as the carbon content of mandrel 400, also referred to as a carbon-containing feature. Figure 4C As shown in FIG. 4 , several mandrels 400 may be positioned adjacent to each other in an array 404. The scum 402 may present a patterning risk by remaining on the substrate 406 to connect the mandrels 400 after lithography (e.g., when the scum 402 is organized or positioned in the array 404). Such connection of the mandrels 400 through the scum 402 is undesirable, so the scum 402 is removed by the ALE process (e.g., see FIG. 4 ). Figure 3 ) is cleaned so that the array 404 of mandrels 400 is free of scum 402, such as Figure 4D shown.

[0055] In some embodiments, the scum 402 is a residue of the EUV resist development process that is relatively dispersed throughout the mandrel 400, such as Figure 4A As shown, and thus forms a thin layer on the mandrel. Such dross 402 thus has a relatively high surface area to volume ratio, and thus may be easier to remove by an ALE process. Moreover, in some embodiments, the dross 402 may be integrated with or incorporated into the mandrel 400, which is formed of a material that is generally the same as the material of the dross 402. Therefore, the dross 402 may be considered an undesirable protrusion of the mandrel 400.

[0056] return Figure 1, after the patterned EUV resist is optionally descummed in operation 104, the substrate is exposed to a halogen-containing plasma in operation 106 to treat the exposed portion of the metal oxide layer. Suitable halogen-containing plasmas include hydrogen halides (HF, HCl, HBr or HI) and diatomic halogens (Br2, Cl2, F2, I2). The halogen-containing plasma is a "mild" plasma because it uses sufficiently low power and low bias to form a halide layer on the metal oxide layer without etching or very little etching the metal oxide layer. In some embodiments, the mild plasma has a single station power between 10W and 150W (e.g., 100W) and a voltage bias between 0V and 60V (e.g., 0V). In some embodiments, the chamber pressure is between 10mTorr and 100mTorr, and the chamber temperature is less than 60°C, for example, 20°C. In some embodiments, the flow rate of the halogen-containing gas is between 100sccm and 300sccm, for example, 100sccm. In some embodiments, the exposure time or the time the halogen-containing gas flows into the chamber is between 30 seconds and 90 seconds, such as 60 seconds.

[0057] The halide layer can inhibit deposition on the metal oxide layer by increasing the nucleation delay for subsequent deposition operations. When performed at low power and bias, the halide layer will form on exposed portions of the metal oxide layer, including open areas of the exposed portions, or areas with low aspect ratios to features of patterned EUV resist, such as aspect ratios below about 1. The halide layer inhibits deposition of certain reactants, particularly silicon-containing precursors, by increasing the nucleation delay of such reactants.

[0058] In operation 108, a precursor layer containing a silicon oxide precursor is deposited on the patterned EUV resist. The precursor is generally deposited "selectively" relative to the top of the features of the patterned EUV resist, so that there is more precursor deposition on the top of the features than on the sidewalls or exposed portions of the metal oxide layer. For example, in some embodiments, there is no sidewall deposition of the precursor. The halide layer inhibits the deposition of the precursor so that the precursor is not deposited on the metal oxide layer. The inhibition or nucleation delay time can last between 1 second and 6 seconds, or about 3 seconds, after which the silicon-containing precursor can also be deposited on the exposed portions of the halide layer or the metal oxide layer. In some embodiments, the silicon-containing precursor is SiH4, Si2H2, or SiCl4.

[0059] Example processing conditions for depositing the silicon-containing precursor are power between 100 W-500 W (e.g., 300 W), bias voltage between 50 V-200 V (e.g., 120 V), chamber temperature below 60° C., chamber pressure between 5 mTorr and 100 mTorr (e.g., 50 mTorr), and exposure time between 1 s and 5 s. Reactant flow rates are between 10 sccm-50 sccm SiCl4, 0 sccm-200 sccm H2, and 100 sccm-300 sccm He. All processing condition ranges are inclusive.

[0060] Operation 110 is an optional operation for etching back the precursor layer. In some embodiments, the precursor layer is deposited for a sufficient time so that it is formed on the exposed portions of the halide layer or the metal oxide layer. Operation 110 may then be performed to remove such undesirable deposition, such that the net effect of operations 108 and 110 is to have deposition of the precursor layer only on the patterned EUV resist, and no deposition on the halide layer or the metal oxide layer. In some embodiments, operation 110 may also remove the halide layer so that the exposed portions of the metal oxide layer no longer present a nucleation delay time to the deposition of the silicon-containing precursor. In some embodiments, the deposition time of the precursor layer is insufficient to overcome the nucleation delay caused by the halide layer, and the precursor layer is not formed on the halide layer or the metal oxide layer. In such an embodiment, since the precursor layer is not deposited on the halide layer or the metal oxide layer, operation 110 may not be performed. Operation 110 may be performed according to Figure 3 The processing flow chart is executed as described above.

[0061] In some embodiments, operations 106 - 110 are looped to fill the recesses in the patterned EUV resist. Fig.9A -C shows a perspective view and a side view of a patterned EUV resist whose recesses are filled by cyclic deposition and etching operations. Fig.9A A perspective view of a patterned EUV resist having features such as a mandrel 900 with a recess 901 in the mandrel 900 is shown. The recess 901 is filled by cyclic deposition and etching operations, such as Fig. 9B and 9C As shown, to form mandrel 902. Those skilled in the art will appreciate that mandrels 900 and 901 may include a multi-layer stack suitable for semiconductor processing, which may also include other layers such as etch stop layers, capping layers, barrier layers, and other underlying layers.

[0062] Fig. 9BA side view of the mandrel during a single cycle of recess fill is shown. In operation 910, a substrate having a patterned EUV resist 912 having recesses 916 is received in a processing chamber. The substrate may be in the processing chamber due to a previous operation, or may be introduced into the processing chamber. Line 914 is an imaginary line representing an ideal thickness of the EUV resist.

[0063] In operation 920, a deposition layer 922 is selectively deposited on the patterned EUV resist 912. In some embodiments, more material will be deposited in the recess 916 than in the surrounding area of ​​the patterned EUV resist 912. The deposition is selective to the patterned EUV resist as compared to the exposed portion of the layer below the patterned EUV resist. The processing conditions of the deposition process can include any of the deposition processing conditions discussed herein for depositing a precursor or capping layer of a material.

[0064] In operation 930, the substrate is etched to form a filled recess 936 and a covering EUV resist 932. The filled recess 936 is smaller than the recess 916, while the covering EUV resist 932 has a thickness similar to the patterned EUV resist 912. The etching process of operation 930 is selective in that the material inside the recess is etched less than the material outside the recess, thereby achieving a net filling of the recess while maintaining the thickness of the EUV resist. The processing conditions of the etching process depend on the deposited material, and generally, the material inside the recess is etched less or at a lower rate than the material in the surrounding area of ​​the recess. In some embodiments, operation 930 can be performed by etching depending on the aspect ratio or etching depending on the surface area. In some embodiments, operation 930 can be performed according to Figure 3 In other embodiments, operation 930 may be performed according to Figure 5 The operation 508 is performed as described below.

[0065] Fig. 9C 942a-d shows the side view of the patterned EUV resist after four cycles of completing the recess filling. Fig. 9B The resulting EUV profile 942d is substantially similar to line 914 representing the ideal thickness of the EUV resist.

[0066] return Figure 1, operations 106-110 may be cycled to fill the recesses of the patterned EUV resist. Operation 106 may be performed to form a halide layer on the exposed portion of the metal oxide layer. Operation 108 may be performed to deposit a silicon-containing oxide precursor on the patterned EUV resist, including inside the recesses, but not deposited or deposited less on the halide layer or the exposed portion of the metal oxide layer. Operation 110 may then be performed to etch the silicon-containing oxide precursor, and in some embodiments, the halide layer on the exposed portion of the metal oxide layer. Therefore, each cycle of operations 106-110 will result in more deposition inside the recess than in the surrounding area. Operations 106-110 may be cycled until the patterned EUV resist is substantially free of recesses.

[0067] In some embodiments, only operations 108 and 110 are cycled. Since the halide layer reacts with the silicon-containing precursor in operation 110, if it does not react completely with the silicon-containing precursor, it may continue to inhibit the deposition of the silicon-containing precursor in operation 108 by increasing the nucleation delay time. In such embodiments, operation 106 is not required to increase the selectivity of the deposition in operation 108.

[0068] In operation 112, the precursor layer containing silicon oxide precursor is oxidized to form a silicon oxide capping layer. This is accomplished by exposing the substrate to an oxidant (i.e., an oxygen-containing gas) and igniting a plasma, which reacts with the silicon oxide precursor to form a silicon oxide capping layer on the patterned EUV resist. The silicon oxide capping layer is selectively formed on the top of the feature of the patterned EUV resist, rather than on the sidewalls, to maintain the sidewall profile of the feature. Suitable oxidants include, but are not limited to: nitrous oxide (N2O) gas, glycols, water, oxygen, ozone, alcohols, esters, ketones, carboxylic acids, and mixtures thereof. Example processing conditions for oxidizing the silicon oxide precursor are 10W-150W (e.g., 100W), 0V bias, a processing chamber temperature below 60°C, a pressure between 5mTorr and 100mTorr (e.g., 5mTorr), and an exposure time between 5s and 15s (e.g., 5s). The reactant flow rate may be between 100sccm-300sccm O2. All treatment condition ranges are inclusive.

[0069] In operation 114, the metal oxide layer is etched using the patterned EUV resist and the silicon oxide capping layer as a mask. The substrate is exposed to an etching gas and a directional plasma that is selective to the metal oxide layer, i.e., the metal oxide layer is etched at a higher rate than the EUV resist or the silicon oxide capping layer. The silicon oxide capping layer protects the patterned EUV resist from the etchant gas, preventing or inhibiting the etching of the patterned EUV resist until the silicon oxide capping layer has been etched. In some embodiments, the silicon oxide capping layer is completely removed during the etching of the metal oxide layer, while in other embodiments, the silicon oxide capping layer is not removed. Possible etching gases include halogen-containing gases. The etch selectivity of the metal oxide layer to the silicon oxide capping layer can be about 10:1-15:1. Example processing conditions for etching the metal oxide layer are power between 100W-500W (e.g., 300W), bias voltage between 100V-300V, chamber temperature below 60°C, chamber pressure between 10mTorr and 100mTorr (e.g., 20mTorr), exposure time between 10s and 30s. Reactant flow rates may be between 100sccm-300sccm HBr and between 100sccm-300sccm He. All processing condition ranges are inclusive.

[0070] Figure 1 Specific examples of the method are referred to below Figure 2 Have a discussion. Figure 2 An exemplary embodiment of a side view of a semiconductor substrate during deposition of a capping layer on a patterned EUV resist during an etching process is presented. At operation 200, a semiconductor substrate 208 having a metal oxide layer 206, carbonaceous dross 204, and patterned EUV resist features 202 is provided to a processing chamber.

[0071] In operation 210, the substrate is descummed by an ALE process, which uses CF4 to adsorb onto the surface of the substrate and He ions to sputter the adsorbed layer. Operation 210 can be repeated until the scum 204 is sufficiently removed, thereby performing multiple ALE cycles. The result of operation 210 is the removal of scum 204. In some embodiments, operation 210 also etches the features 202 and the metal oxide layer 206, but to a much lesser extent than the scum is etched away.

[0072] In some embodiments, operation 210 is not performed. In some embodiments, scum 204 may be sufficiently minimal that a scum operation is not required. In some embodiments, the EUV lithography process may not produce enough scum to require a descum operation. Generally speaking, if the scum does not affect the critical dimensions of the etch process, a descum operation may not be performed.

[0073] In operation 220, the exposed portions of the metal oxide layer are treated with HBr plasma to form a passivation layer 221. The passivation layer is also formed over the opening regions 222, where the width of the exposed regions has a low aspect ratio to the height of the features 202. The HBr treatment passivates the metal oxide layer, thereby inhibiting the deposition of silicon-containing precursors, such as silicon tetrachloride (SiCl4).

[0074] In operation 230, a silicon-containing precursor (e.g., SiCl4) is selectively deposited on top of the feature 202 to produce a silicon-containing precursor layer 233. Due to the nucleation delay time caused by the passivation layer 221, the SiCl4 is not deposited on the metal oxide layer 206. The SiCl4 is also substantially not deposited on the sidewalls of the feature.

[0075] In some embodiments, the deposition time of SiCl4 is long enough so that the SiCl4 layer is also formed on the passivation layer. Figure 3 By performing an etch-back operation, the undesirable deposition can be removed before oxidizing the deposited SiCl4 to generate silicon oxide. In some embodiments, operations 220, 230 and the etch-back operation can be cycled to fill the recess. In other embodiments, only operation 230 and the etch-back operation are cycled to fill the recess.

[0076] In operation 240, the silicon-containing precursor layer 233 is exposed to an oxygen plasma to produce a silicon oxide (SiO2) capping layer 243. The oxygen reacts with the silicon-containing precursor layer to form an oxide. Depending on the thickness of the silicon-containing precursor layer, the silicon-containing precursor layer is exposed to oxygen for a variable amount of time to ensure that it is fully oxidized.

[0077] Finally, in operation 250, the metal oxide layer is etched using HBr plasma. Unlike the HBr plasma used in operation 220, this plasma is generated with higher energy and higher voltage bias to etch the metal oxide layer instead of depositing the HBr layer thereon. When the exposed portion of the metal oxide layer 206 is etched by the HBr plasma, a patterned metal oxide layer 256 is formed. The patterned metal oxide layer 256 has the same patterning as the feature 202 of the patterned EUV resist. The silicon oxide capping layer 243 is also etched to the thinner capping layer 253, but at a much lower rate than the metal oxide layer. In some embodiments, the silicon oxide capping layer will be removed by etching in operation 250.

[0078] Figure 5 Another process flow diagram is provided for performing operations of a method according to the disclosed embodiments. Figure 5The method may be performed as part of another process of etching a metal oxide layer. In operation 502, a substrate having a patterned EUV resist exposing a portion of an underlying metal oxide layer is received in a process chamber. The semiconductor substrate may be in the process chamber due to a previous operation, or may be introduced into the process chamber.

[0079] Operation 504 is an optional operation to descum the patterned EUV resist. In some embodiments, operation 504 is performed to descum the patterned EUV resist, while in other embodiments, operation 504 is not performed. Whether to perform operation 504 may depend on whether there is any scum on the substrate that affects the critical dimensions of the patterned EUV resist. Figure 3 The process flow diagram is used to perform operation 504, as described above.

[0080] In operation 506, an amorphous carbon capping layer is deposited on the patterned EUV resist. A voltage bias may be applied to improve the conformality of the carbon-based deposition, but in some embodiments, there will be deposition on the sidewalls of the features of the patterned EUV resist. Amorphous carbon deposition may be performed by exposing the substrate to a hydrocarbon (C x H y ) (e.g., methane (CH4)), hydrogen (H2) to deposit on the features of the patterned EUV resist. H ions typically etch metal oxide layers, while carbon-based polymers (e.g., EUV resist) resist H ion etching. In addition, carbon radicals in the plasma will deposit on carbon-based polymers (e.g., EUV resist). Therefore, the hydrocarbon and H2 plasma can be controlled to deposit amorphous carbon on the patterned EUV resist without depositing on or only minimally etching the exposed portions of the underlying metal oxide layer.

[0081] Example processing conditions for some embodiments include: single station power between 10W-200W (e.g., 100W), voltage bias between 0V-100V (e.g., 60V), process chamber temperature below 60°C, pressure between 1mtorr-100mtorr, and exposure time between 1s-10s. In some embodiments, the reactants are CH4 with a flow rate between 10sccm-50sccm (e.g., 20sccm), H2 with a flow rate between 0sccm-200sccm (e.g., 50sccm), and an inert gas, such as helium, with a flow rate between 200sccm-400sccm (e.g., 250sccm), although other inert gases may also be used. All processing condition ranges are inclusive.

[0082] In some embodiments, optional operation 508 is performed to reduce or remove the carbon deposited by operation 506 from the sidewalls of the features of the patterned EUV resist. Operation 508 etches the substrate, removing carbon from the top of the patterned EUV resist as well as the sidewalls. Amorphous carbon deposits more on the top of the features than on the sidewalls, so operation 508 results in a net deposition of amorphous carbon on the top of the features of the patterned EUV resist. This may be done to reduce LER or LWR or to maintain the critical dimensions of the features. In some embodiments, this operation is not performed when any sidewall deposition is insufficient to affect the critical dimensions of the features.

[0083] The etch back operation 508 may be performed in an ALE manner, using the same method as described above with respect to Figure 3 and Fig.10 The same processing conditions as discussed above for the descum operation. In some embodiments, the reactant of the descum operation (e.g., CF4) is used in the etch-back operation. In other embodiments, instead of a halogen-containing gas, an oxidant is adsorbed onto the surface of the carbon-containing features and then removed by a helium plasma. Suitable oxidants include, but are not limited to, oxygen, ozone, water, carbon dioxide (CO2), nitrous oxide (N2O) gas, glycols, alcohols, esters, ketones, and carboxylic acids.

[0084] In some embodiments, operations 506 and 508 are looped to fill recesses in the patterned EUV resist. In some embodiments, operation 506 will selectively deposit in the recess, i.e., more carbon will be deposited in the recess than in the area surrounding the recess. In some embodiments, operation 508 will etch less in the recess than in the surrounding thicker areas. By looping operations 506 and 508, any recess can be gradually filled by the amorphous carbon precursor layer, thereby reducing the variation in EUV resist thickness.

[0085] Finally, in operation 510, the metal oxide layer is etched using the patterned EUV resist and the amorphous carbon capping layer as a mask. The amorphous carbon capping layer protects the patterned EUV resist from the etching gas, preventing or inhibiting the etching of the patterned EUV resist until the amorphous carbon capping layer is removed. In some embodiments, the amorphous carbon capping layer is completely removed during the etching of the metal oxide layer, while in other embodiments, the amorphous carbon capping layer is not removed. The etch selectivity of the metal oxide layer to the amorphous carbon capping layer is about 10:1-15:1. Example processing conditions for operation 510 are the same as above. Figure 1 The operation 114 is the same as in.

[0086] Figure 5 Specific examples of methods are described below. Figure 6 Have a discussion. Figure 6An exemplary embodiment of a side view of a semiconductor substrate during deposition of a capping layer on a patterned EUV resist during an etching process is presented. At operation 600, a semiconductor substrate 608 having a metal oxide layer 606, carbonaceous dross 604, and patterned EUV resist features 602 is provided to a processing chamber.

[0087] At operation 610, the substrate is descummed by an ALE process, which uses CF4 to adsorb onto the surface of the substrate and uses He ions to sputter the adsorbed layer. Operation 610 may be repeated until the scum 604 is sufficiently removed, thereby performing multiple ALE cycles. The result of operation 610 is the removal of scum 604. In some embodiments, operation 610 also etches features 602 and metal oxide layer 606.

[0088] In some embodiments, operation 610 is not performed. In some embodiments, the scum 604 may be sufficiently minimal that a scum operation is not required. In some embodiments, the EUV lithography process may not produce enough scum to require a descum operation. Generally speaking, if the scum does not affect the defect performance or critical dimensions of the etch process, a descum operation may not be performed.

[0089] In operation 620, the substrate is exposed to methane and hydrogen plasmas to selectively deposit amorphous carbon on top of feature 602 to form an amorphous carbon layer 623. As discussed above, the processing conditions are adjusted so that the carbon plasma will deposit on feature 602, while the hydrogen plasma will remove any amorphous carbon deposits on the metal oxide layer and may minimally etch the metal oxide layer. In some embodiments, amorphous carbon may be deposited on the sidewalls of feature 602 to form sidewall carbon 624. The carbon is deposited using a voltage bias to increase the anisotropy of the deposition, but some sidewall deposition may inevitably occur.

[0090] In operation 630, the amorphous carbon precursor layer 623 and the sidewall carbon 624 are etched back by an ALE process, which uses carbon dioxide (CO2) to adsorb onto the carbon-containing surface of the substrate, followed by He ions desorbing the adsorbed layer and forming an amorphous carbon capping layer 633. This operation is used to remove any carbon deposited on the sidewalls, but also removes carbon on the feature 602. Because the carbon is selectively deposited in operation 620, so that more carbon is deposited on the top than on the sidewalls, an amorphous carbon capping layer 633 remains after operation 630.

[0091] In some embodiments, operation 630 is not performed. In some embodiments, sidewall carbon 624 does not affect the critical dimensions of the features to be etched, and this operation can be skipped to increase throughput. In such embodiments, carbon layer 623 is an amorphous carbon capping layer used in operation 640.

[0092] Finally, in operation 640, the metal oxide layer is etched using HBr plasma. HBr plasma is generated at high energy, and a voltage bias is applied to the semiconductor substrate to etch the metal oxide layer without depositing the HBr layer thereon. Since the exposed portion of the metal oxide layer 606 is etched by the HBr plasma, a patterned metal oxide layer 646 is formed. The patterned metal oxide layer 646 has the same patterning as the feature 602 of the patterned EUV resist. The amorphous carbon capping layer 633 (or the amorphous carbon precursor layer 623) is also etched into a thinner capping layer 643, but at a lower rate than the metal oxide layer. In some embodiments, the amorphous carbon capping layer is removed by etching during operation 640.

[0093] Figure 7 A process flow diagram is provided for performing operations of another method according to the disclosed embodiments. Figure 7 The method in may be performed as part of a process of etching an underlying layer (which may or may not be a metal oxide layer). In operation 702, a substrate having a patterned EUV resist exposing a portion of the underlying layer is received in a process chamber. In some embodiments, features of the patterned EUV resist have an aspect ratio of between about 1 to about 5, or between about 1 to about 2 (e.g., about 1.5) relative to the exposed portion of the underlying layer. The semiconductor substrate may be in the process chamber due to a previous operation, or may be directed into the process chamber.

[0094] In operation 704, the EUV resist is patterned according to Figure 3 and Fig.10 In some embodiments, the deslagging is performed according to Figure 3 In some embodiments, the ALE process may be performed in a single ALE cycle. In other embodiments, multiple ALE cycles are performed. In some embodiments, operation 704 does not completely descum the patterned EUV resist. The extent to which operation 704 is performed may depend on whether there is any scum on the substrate that affects the critical dimensions of the patterned EUV resist. In some embodiments, the ALE process will also etch underlying layers.

[0095] In operation 706, a precursor layer of a silicon-containing precursor is deposited on the patterned EUV resist. The precursor is generally deposited "selectively" relative to the top of the features of the patterned EUV resist, so that more precursor is deposited on the top of the features than on the sidewalls or exposed portions of the metal oxide layer. For example, in some embodiments, there is no sidewall deposition of the precursor. In some embodiments, due to the higher aspect ratio, the silicon-containing oxide precursor is not deposited on the underlying layer. In embodiments with lower aspect ratios, the silicon-containing precursor is also deposited on the underlying layer. Example processing conditions for operation 706 are similar to those above. Figure 1The process is the same as operation 108. In some embodiments, the silicon-containing precursor is SiH4, Si2H2, or SiCl4.

[0096] In some embodiments, operation 708 is performed, wherein according to Figure 3 The ALE process etches the patterned EUV resist and precursor layer. The ALE process can remove additional scum that was not removed in the above operation 704, as well as a portion of the underlying layer and a portion of the precursor layer. In some embodiments, multiple ALE cycles are performed to remove scum or other undesirable deposition on the underlying layer, and the precursor layer protects the features of the EUV resist.

[0097] In some embodiments, operations 706 and 708 are cycled to fill recesses in the patterned EUV resist. In some embodiments, in operation 706, more silicon-containing precursor will be deposited in the recesses than in the areas surrounding the recesses, possibly because the recesses have a larger surface area relative to the flatter surrounding field. In some embodiments, operation 708 will etch less in the recesses than in the surrounding thicker areas. By cycling operations 706 and 708, any recesses can be gradually filled with a layer of silicon-containing precursor, thereby reducing variations in EUV resist thickness.

[0098] In operation 710, the precursor layer containing a silicon precursor is oxidized to produce a silicon oxide capping layer. This is accomplished by exposing the substrate to an oxidant (i.e., an oxygen-containing gas) and igniting a plasma, which reacts with the silicon-containing precursor to form a silicon oxide capping layer on the patterned EUV resist. The silicon oxide capping layer is selectively formed on the top of the features of the patterned EUV resist, rather than on the sidewalls, to maintain the sidewall profile of the features. The suitable oxidant and processing conditions for operation 840 are the same as those for operation 112 above.

[0099] In operation 712, the underlying layer is etched using the patterned EUV resist and the silicon oxide capping layer. The silicon oxide capping layer protects the patterned EUV resist from the etchant gas, preventing or inhibiting the etching of the patterned EUV resist until the silicon oxide capping layer has been etched. In some embodiments, the silicon oxide capping layer is completely removed during the etching of the underlying layer, while in other embodiments, the silicon oxide capping layer is not removed. Example processing conditions for operation 712 can be the same as above. Figure 1 The same as operation 114 in . In some embodiments, different etching chemistries can be used as long as there is sufficient etch selectivity between the underlying layer and the combination of the patterned EUV resist and the silicon oxide cap layer and the underlying layer can be etched using the combination as a mask. The specific etching chemistry to be used depends on the material comprising the underlying layer.

[0100] Figure 7 Specific examples of the method are referred to below Figure 8 Have a discussion. Figure 8 An exemplary embodiment of a side view of a semiconductor substrate during an etching process covering a patterned EUV resist is presented. At operation 800, a semiconductor substrate 808 having a metal oxide layer 806, carbonaceous dross 804, and patterned EUV resist features 802 is provided to a processing chamber.

[0101] In operation 810, the substrate is descummed by an ALE process that uses CF4 to adsorb onto the surface of the substrate and He ions to sputter the adsorbed layer. Operation 810 may be repeated until the scum 804 is sufficiently removed, thereby performing multiple ALE cycles. The result of operation 810 is the removal of scum 804. In some embodiments, operation 810 also etches the feature 802 and the underlying layer 806. The above process may be used. Figure 3 Operation 810 is performed using the same processing conditions presented.

[0102] In some embodiments, operation 810 is not performed. In some embodiments, scum 804 may be sufficiently minimal that a scum operation is not required. In some embodiments, the EUV lithography process may not produce sufficient scum to affect the critical dimensions of the patterned EUV resist. Generally speaking, if the scum does not affect the critical dimensions of the etch process, a descum operation may not be performed.

[0103] In operation 820, SiCl4 is selectively deposited on the top of feature 802 to produce a silicon-containing precursor layer 823. Due to the aspect ratio of the patterned EUV resist and the exposed portion of the underlying layer, SiCl4 is not deposited or is deposited less on the underlying layer 806. SiCl4 is also not deposited on the sidewalls of the feature, but is deposited completely or mostly on feature 802.

[0104] In operation 830, the silicon-containing precursor layer is etched using an ALE process that uses CF4 to adsorb onto the surface of the silicon-containing precursor layer and He ions to desorb the adsorbed layer. This can be done to remove a portion of the silicon-containing precursor layer. In some embodiments, this may be beneficial in reducing the aspect ratio of the patterned EUV resist or maintaining the critical dimensions of the features of the patterned EUV resist. In some embodiments, SiCl4 is deposited on the exposed portions of the underlying layer during operation 820, and operation 830 removes this deposition.

[0105] In some embodiments, operation 830 is not performed. In some embodiments, SiCl 4 is not sufficiently deposited on the exposed portions of the underlying layer to require an etching operation.

[0106] In some embodiments, operations 820 and 830 are cycled to fill recesses in the EUV resist. Operation 830 will etch regions with a larger surface area than regions with a smaller surface area, thus etching less in the recess than in the surrounding areas. By cycling operations 820 and 830, any recesses can be gradually filled by the silicon-containing precursor layer 833, thereby reducing variations in EUV resist thickness.

[0107] In operation 840, the silicon-containing precursor layer 823 is oxidized to produce a silicon oxide capping layer 843. This is accomplished by exposing the substrate to an oxidant (i.e., an oxygen-containing gas) and igniting a plasma, which reacts with the silicon-containing precursor to form a silicon oxide capping layer on the patterned EUV resist. The silicon oxide capping layer is selectively formed on the top of the features of the patterned EUV resist, rather than on the sidewalls, to maintain the sidewall profile of the features.

[0108] Finally, in operation 850, the underlying layer is etched using HBr plasma. As the exposed portion of the underlying layer 806 is etched by the HBr plasma, a patterned underlying layer 856 is formed. The patterned underlying layer 856 has the same patterning as the feature 802 of the patterned EUV resist. The silicon oxide capping layer 843 is also etched into a thinner capping layer 853, but at a lower rate than the underlying layer. In some embodiments, the silicon oxide capping layer is completely removed during the etching of the underlying layer, while in other embodiments, the silicon oxide capping layer is not removed.

[0109] Deposition materials

[0110] According to various embodiments, the deposition of the precursor layer or the capping layer may be a plasma deposition, which includes a plasma enhanced chemical vapor deposition (PECVD) process or a high density plasma chemical vapor deposition (HDP-CVD) process. In embodiments where the etching process is performed in a capacitively coupled plasma etching apparatus, the PECVD process may be advantageously performed, while in embodiments where the etching process is performed in an inductively coupled plasma etching apparatus, the HDP-CVD process may be advantageously performed.

[0111] In the process of depositing the silicon-containing oxide precursor, any suitable silicon-containing precursor may be used, including silane (e.g., SiH4), polysilane (H3Si-(SiH2) n-SiH3) (where n ≥ 1), organosilanes, halogenated silanes, and aminosilanes. Organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc. can be used. Halogenated silanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halogenated silanes are iodosilane, bromosilane, chlorosilane, and fluorosilane. Specific chlorosilanes are tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, etc. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilanes (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), and substituted mono-, di-, tri-, and tetra-aminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butylsilylamine, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, etc.

[0112] The deposited films can be amorphous, with the film composition depending on the specific precursors and co-reactants used, with organosilanes producing a-SiC:H films and aminosilanes producing a-SiN:H or a-SiCN:H films.

[0113] In the process of depositing carbon-based films, the chemical formula C x H y wherein X is an integer between 2 and 10, and Y is an integer between 2 and 24. Examples include methane (CH4), acetylene (C2H2), ethylene (C2H4), propylene (C3H6), butane (C4H 10 ), cyclohexane (C6H 12 ), benzene (C6H6), and toluene (C7H8).

[0114] In some embodiments, the cap layer may be doped or include materials such as boron or phosphorus. Additional dopants include arsenic, sulfur, and selenium. In this way, the etch selectivity to the mask layer or cap layer may be improved. For example, for doped dielectrics (particularly silicon dioxide-based dielectrics), the processing gas may include a dopant precursor, such as a boron-containing gas, a phosphorus-containing gas, a carbon-containing gas, or a mixture thereof. In a particular embodiment, the gas includes one or more boron-containing reactants and one or more phosphorus-containing reactants, and the dielectric film includes phosphorus- and boron-doped silica glass (BPSG). Examples of suitable boron and phosphorus precursor gases include borane (BH3), diborane (B2H6), triborane (B3H7), and phosphine (PH3). Examples of arsenic-, sulfur-, and selenium-containing gases include hydrogen selenide (H2Se), arsine (ASH3), and hydrogen sulfide (H2S).

[0115] If the capping layer will contain oxynitride (eg, silicon oxynitride), the deposition gas may include nitrogen-containing reactants such as N2, NH3, NO, N2O, and mixtures thereof. Examples of deposited films include boron-doped silicon, silicon boride, silicon boride carbon, and the like.

[0116] equipment

[0117] According to some embodiments of the present invention, Fig.11 A cross-sectional view of an inductively coupled plasma etching apparatus 1100 is schematically shown. The Kiyo TMReactor is an example of a suitable reactor that can be used to implement the technology described herein. The inductively coupled plasma etching device 1100 includes a total etching chamber that is structurally defined by a chamber wall 1101 and a window 1111. The chamber wall 1101 can be made of stainless steel or aluminum. The window 1111 can be made of quartz or other dielectric materials. The optional internal plasma grid 1150 divides the total etching chamber into an upper sub-chamber 1102 and a lower sub-chamber 1103. In most embodiments, the plasma grid 1150 can be removed, thereby utilizing the chamber space composed of the sub-chambers 1102 and 1103. A chuck 1117 is positioned in the lower sub-chamber 1103 near the bottom inner surface. The chuck 1117 is configured to receive and hold a semiconductor wafer 1119 on which an etching process is performed. The chuck 1117 can be an electrostatic chuck for supporting the wafer 1119 when the wafer 1119 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 1117 and has an upper surface that is approximately in the same plane as the top surface of the wafer 1119 (when the wafer is present above the chuck 1117). The chuck 1117 also includes electrostatic electrodes for clamping and releasing the wafer. Filters and DC clamp power sources (not shown in the figure) can be provided for this purpose. Other control systems can also be provided for lifting the wafer 1119 off the chuck 1117. The chuck 1117 can be charged with an RF power supply 1123. The RF power supply 1123 is connected to the matching circuit 1121 via a connector 1127. The matching circuit 1121 is connected to the chuck 1117 via a connector 1125. In this way, the RF power supply 1123 is connected to the chuck 1117.

[0118] The coil 1133 is located above the window 1111. The coil 1133 is made of a conductive material and includes at least one full turn. Fig.11 The exemplary coil 1133 shown in includes three turns. The cross-section of the coil 1133 is shown with symbols, and the coil with the "X" symbol indicates that the coil extends rotationally into the page, and conversely, the coil with the "●" symbol indicates that the coil extends rotationally out of the page. The RF power supply 1141 is configured to provide RF power to the coil 1133. Generally, the RF power supply 1141 is connected to the matching circuit 1139 through the connector 1145. The matching circuit 1139 is connected to the coil 1133 through the connector 1143. In this way, the RF power supply 1141 is connected to the coil 1133. An optional Faraday shield 1149 is positioned between the coil 1133 and the window 1111. The Faraday shield 1149 is maintained in a spaced relationship relative to the coil 1133. The Faraday shield 1149 is disposed directly above the window 1111. The coil 1133, the Faraday shield 1149 and the window 1111 are each configured to be substantially parallel to each other. The Faraday shield can prevent metal or other substances from being deposited on the dielectric window of the plasma chamber 1101.

[0119] The process gas may be supplied via a main injection port 1160 located in the upper chamber and / or via a side injection port 1170 (sometimes referred to as STG). During an operating plasma process, a vacuum pump (e.g., a primary or secondary mechanical dry pump and / or a turbomolecular pump 1140) may be used to draw the process gas from the process chamber 1124 and maintain the pressure within the process chamber 1100 by using a flow limiting device (e.g., a throttle valve (not shown) or a pendulum valve (not shown)) controlled by a closed loop.

[0120] During operation of the apparatus, one or more reactant gases may be supplied via injection ports 1160 and / or 1170. In some embodiments, gases may be supplied only via the main injection port 1160, or only via the side injection port 1170. In some cases, the injection ports may be replaced by showerheads. The Faraday shield 1149 and / or the optional grid 1150 may include internal channels and holes that allow process gases to be delivered to the chamber. Both or either of the Faraday shield 1149 and the optional grid 1150 may serve as showerheads for process gas delivery.

[0121] RF power is supplied from the RF power supply 1141 to the coil 1133 to cause an RF current to flow through the coil 1133. The RF current flowing through the coil 1133 generates an electromagnetic field around the coil 1133. The electromagnetic field generates an induced current within the upper sub-chamber 1102. During the etching process, the physical and chemical interactions of the generated ions and radicals with the wafer 1119 selectively etch features of the wafer.

[0122] If a plasma grid is used so that both the upper sub-chamber 1102 and the lower sub-chamber 1103 exist, the induced current acts on the gas present in the upper sub-chamber 1102 to produce an electron-ion plasma in the upper sub-chamber 1102. The optional internal plasma grid 1150 limits the amount of hot electrons in the lower sub-chamber 1103. In some embodiments, the device is designed and operated so that the plasma present in the lower sub-chamber 1103 is an ion-ion plasma.

[0123] Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, but the ion-ion plasma will have a greater ratio of anions to cations. Volatile byproducts may be removed from the lower subchamber 1103 through port 1122 .

[0124] The chuck 1117 disclosed herein can be operated at elevated temperatures ranging between about 30° C. to about 250° C. The temperature will depend on the etching process operation and the specific recipe. In some embodiments, the chamber 1101 can also be operated at a pressure ranging between about 1 mTorr to about 95 mTorr. In some embodiments, the pressure can be higher, as disclosed above.

[0125] The chamber 1101 can be coupled to a facility (not shown) when installed in a clean room or manufacturing facility. The facility includes piping that provides process gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to the chamber 1101 when installed in the target manufacturing facility. In addition, the chamber 1101 can be coupled to a transfer chamber so that semiconductor wafers can be transferred into and out of the chamber 1101 by a robot using typical automation.

[0126] In some embodiments, a system controller 1130 (which may include one or more physical or logical controllers) controls some or all operations of the etch chamber. The controller is further described below.

[0127] Fig.12 1 is a schematic diagram of an example of a capacitively coupled plasma etching apparatus according to many embodiments. Plasma etching chamber 1200 includes an upper electrode 1202 and a lower electrode 1204, between which plasma can be generated. A substrate 1299 having a patterned EUV resist thereon as described above can be disposed on lower electrode 1204 and can be held in place by an electrostatic chuck (ESC). Other clamping mechanisms can also be used. Plasma etching chamber 1200 can include plasma confinement rings 1206, which keep the plasma above the substrate and away from the chamber walls. Other plasma confinement structures (e.g., side plates used as inner walls) can be used. In some embodiments, the plasma etching chamber may not include any such plasma confinement structures.

[0128] exist Fig.12 In the example of , the plasma etch chamber 1200 includes two RF sources, wherein the RF source 1210 is connected to the upper electrode 1202 and the RF source 1212 is connected to the lower electrode 1204. Each of the RF sources 1210 and 1212 can include one or more sources of any suitable frequency, including 2 MHz, 13.56 MHz, 27 MHz, and 60 MHz. Gases can be introduced into the chamber from one or more gas sources 1214, 1216, and 1218. For example, the gas source 1214 can include a deposition or etching gas as described above. Gases can be introduced into the chamber via an inlet 1220, and excess gas and reaction byproducts are exhausted by an exhaust pump 1222.

[0129] An example of a plasma etch chamber that may be used is Reactive ion etching tools are commercially available from Lam Research Corp. of Fremont, Calif. Further description of plasma etching chambers can be found in U.S. Patent Nos. 6,841,943 and 8,552,334, the entire disclosures of which are incorporated herein by reference.

[0130] Back to Fig.12 , the controller 1130 may be connected to the RF sources 1210 and 1212 and valves associated with the gas sources 1214, 1216, and 1218, and the exhaust pump 1222. In some embodiments, the controller 1130 controls all activities of the plasma etching chamber 1200.

[0131] The following discussion of controller 1130 may be applied as appropriate. Fig.11 and 12 1130. The controller 1130 may execute control software that is stored in a mass storage device, loaded into a memory device, and executed on a processor. Alternatively, the control logic may be hard-coded in the controller 1130. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays or FPGAs), etc. may be used for these purposes. In the following discussion and Figure 6 In the discussion of controllers in , wherever the term "software" or "code" is used, functionally equivalent hard-coded logic can be used instead.

[0132] The control software may include instructions for controlling the timing and / or amplitude of application of any one or more of the following chamber operating conditions: the mixture and / or composition of gases, chamber pressure, chamber temperature, wafer / wafer support temperature, bias applied to the wafer, frequency and power applied to coils or other plasma generating components, wafer position, wafer movement speed, and other parameters of the specific process performed by the tool. For example, the control software may include instructions for flowing the reactants discussed above (e.g., silicon-containing precursors, halogen-containing gases, oxidants, or inert gases). The control software may be configured in any suitable manner. For example, subroutines or control objects of various process tool components may be written to control the operation of the process tool components required to perform the processes of the various process tools. The control software may be encoded in any suitable computer-readable programming language.

[0133] In some embodiments, the control software may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on a mass storage device and / or memory device associated with the controller 1130 may be employed. Examples of programs or portions of programs for this purpose include process gas control programs, pressure control programs, and RF source control programs.

[0134] The process gas control program may include program code for controlling gas composition (e.g., deposition and process gases described herein) and flow rates and optionally for flowing gases into the chamber prior to deposition to stabilize the pressure in the chamber. The pressure control program may include program code for controlling the pressure in the chamber by adjusting, for example, a throttle valve in the exhaust system of the chamber, gas flow into the chamber, etc. The RF source control program may include program code for setting the RF power level applied to the electrode according to embodiments herein.

[0135] In some embodiments, there may be a user interface associated with the controller 1130. The user interface may include a display screen, graphical software display of the device and / or processing station, and user input devices (e.g., pointing device, keyboard, touch screen, microphone, etc.).

[0136] In some embodiments, the parameters adjusted via the controller 1130 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface. These parameters may be in a form similar to the process conditions provided herein.

[0137] Signals to monitor the process may be provided via analog and / or digital input connections to the system controller 1130 from various process tool sensors. Signals to control the process may be output at analog and digital output connections to the plasma etch chamber. Non-limiting examples of sensors that may be monitored include mass flow controllers, pressure sensors (e.g., manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0138] The controller 1130 may provide program instructions for performing the directional deposition process described above and the subsequent etching process. These program instructions may control various process parameters, such as RF bias power level, pressure, temperature, etc. The instructions may control the parameters to directionally deposit the cap layer growth film according to the various embodiments described herein. For example, the instructions may control the flow rate of the silicon-containing oxide precursor or the power of the halogen-containing plasma.

[0139] The controller 1130 will typically include one or more memory devices and one or more processors configured to execute instructions so that the apparatus performs methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments may be connected to the controller 1130, such as described above.

[0140] In some implementations, the controller 1130 may be or may form part of a system controller that is part of a system that may be part of the above examples. Such a system may include a semiconductor processing device that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronic devices for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronic device may be referred to as a "controller" that may control various components or subcomponents of one or more systems. Depending on the processing conditions and / or system type, the system controller may be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery in and out of tools and other delivery tools and / or load locks connected to or interfaced with a particular system.

[0141] In a broad sense, a system controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions delivered to the system controller in the form of various individual settings (or program files) that define operating parameters for performing specific processing on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0142] In some implementations, the system controller may be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, the system controller may be in the "cloud" or in all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, study trends or performance criteria from multiple manufacturing operations, to change the parameters of the current processing, set the processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (e.g., a server) may provide a processing recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then delivered from the remote computer to the system. In some examples, the system controller receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of processing to be performed and the type of tool that the system controller is configured to interface with or control. Thus, as described above, the system controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., processing and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control processing on the chamber.

[0143] In some embodiments, PECVD deposition can use a remote free radical assisted plasma or microwave plasma. Such deposition can be performed in an etching chamber equipped with a remote or microwave plasma generator, or can be performed in a deposition chamber connected to the etching chamber under vacuum. Similarly, in some embodiments, a remote free radical assisted plasma or microwave plasma can be used to perform the processing operation.

[0144] Exemplary processing parameters are provided below. Exemplary pressures range from 5 mT to 1000 mT, and in some embodiments between 40 mT to 100 mT. In one processing operation, exemplary pressures may range from 5 mT to 300 mT.

[0145] Exemplary plasma powers for inductively coupled plasma sources, such as transformer coupled plasma (TCP) sources available from Lam Research of Fremont, California, are 10 W to 1200 W, 20 W to 500 W, or 50 W to 300 W. Exemplary plasma powers for deposition operations are in the range of 20 W to 200 W. Exemplary plasma powers for treatment operations are in the range of 20 W to 1200 W.

[0146] An exemplary bias voltage is in the range of 0V to -500V, 0V to -80V, such as -50V. The bias voltage may also be expressed in magnitude, such as 0 to 500V, 0 to 80V, or 0 to 50V. An exemplary flow rate during the deposition step is in the range of 1sccm to 2000sccm, 1 to 300sccm, or 100sccm. An exemplary flow rate during the treatment step is in the range of 1sccm to 2000sccm, 1 to 500sccm, or 300sccm. An exemplary substrate temperature is in the range of 40°C to 250°C or 60°C to 120°C. In some embodiments, the deposition and treatment exposure time may be in the range of 0.5s to 20s, or 3s to 10s, or 4s to 6s, with the treatment time of a multi-cycle treatment being taken as an example. In some examples, 10 to 100 cycles are performed.

[0147] in conclusion

[0148] Although the above embodiments have been described in some detail for the purpose of clarity of understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and devices of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and the embodiments are not limited to the details given herein.

Claims

1. A semiconductor processing method, comprising: providing a semiconductor substrate including a patterned EUV resist exposing a portion of an underlying metal oxide layer to a processing chamber; treating the exposed portion of the metal oxide layer with a halogen-containing plasma; selectively depositing a silicon-containing precursor on the carbon-containing features of the patterned EUV resist; as well as The silicon-containing precursor is processed to convert the silicon-containing precursor into a silicon oxide capping layer on the carbon-containing features of the patterned EUV resist.

2. The method of claim 1, wherein treating the exposed portion of the metal oxide layer with a halogen-containing plasma is performed using a voltage bias between 0 V and 100 V, inclusive.

3. The method of claim 1, wherein the halogen-containing plasma comprises hydrogen halide. The method of claim 3 , wherein the halogen-containing plasma comprises HBr.

5. The method of claim 1, wherein the silicon-containing precursor is selective to the carbon-containing feature to the metal oxide layer treated with the halogen-containing plasma in a ratio greater than about 10:

1. 6 . The method of claim 1 , further comprising etching the underlying metal oxide layer using the silicon oxide capping layer and the patterned EUV resist as a mask.

7. The method of claim 1, wherein the silicon-containing precursor comprises one or more of SiH4, Si2H2, or SiCl4.

8. The method of claim 1, wherein processing the silicon-containing precursor uses an oxygen-containing reactant.

9. The method of claim 8, wherein the oxygen-containing reactant is selected from the group consisting of H2O, NO, N2O, CO2, O2, or O3.

10. The method of claim 1 , further comprising removing undesirable carbon material scum from carbon-containing features of the patterned EUV resist using an atomic layer etch (ALE) process prior to treating the metal oxide layer with the halogen-containing plasma, comprising: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the carbon-containing features; as well as The modified scum on the surface of the patterned EUV resist is exposed to a plasma of an inert gas to remove the modified scum. The method of claim 10 , wherein the halogen-containing gas comprises one or more of a halogen gas and a halide gas.

12. The method according to claim 11, wherein the halogen gas is Cl2 or Br2.

13. The method according to claim 11, wherein the halide gas is CF4 or HBr.

14. The method of claim 10, wherein the noble gas comprises helium, neon, argon, or xenon.

15. The method of claim 10, wherein exposing the modified scum on the surface of the patterned EUV resist to plasma is performed with a voltage bias of a continuous mode between 0V and 100V, inclusive, or a pulse mode between 100V and 400V, inclusive.

16. The method of claim 1, further comprising: After selectively depositing a silicon-containing precursor, a surface layer of the precursor is modified, and the semiconductor substrate is exposed to a plasma of an inert gas to remove the modified layer of the precursor by atomic layer etching (ALE). 17 . The method of claim 16 , further comprising repeating the selective deposition and atomic layer etching operations to fill recesses on the carbon-containing features of the patterned EUV resist.

18. The method of claim 10, further comprising etching the metal oxide layer using the silicon oxide capping layer and the patterned EUV resist as a mask.

19. A semiconductor processing method, comprising: providing a semiconductor substrate including a patterned EUV resist exposing a portion of an underlying metal oxide layer to a processing chamber; as well as An amorphous carbon capping layer is selectively deposited on the carbon-containing features of the patterned EUV resist by exposing the semiconductor substrate to a gas mixture comprising a hydrocarbon, hydrogen, and an inert gas in the presence of a plasma, wherein depositing the amorphous carbon capping layer does not occur on the portion of the underlying metal oxide layer.

20. The method of claim 19, wherein the hydrocarbon is CH4 or C2H2.

21. The method of claim 19, wherein the noble gas comprises helium, neon, argon, or xenon.

22. The method of claim 19, further comprising removing undesirable carbon material scum from carbon-containing features of the patterned EUV resist using an atomic layer etch (ALE) process prior to selectively depositing the amorphous carbon capping layer, comprising: exposing the patterned EUV resist to a halogen-containing gas to modify the scum on the surface of the carbon-containing features; as well as The modified scum on the surface of the patterned EUV resist is exposed to a plasma of an inert gas.

23. The method of claim 22, wherein the halogen-containing gas comprises one or more of a halogen gas and a halide gas.

24. The method according to claim 23, wherein the halogen gas is Cl2 or Br2.

25. The method of claim 23, wherein the halide gas is CF4 or HBr.

26. The method of claim 22, wherein the noble gas comprises helium, neon, argon, or xenon.

27. The method of claim 22, wherein exposing the modified scum on the surface of the patterned EUV resist to plasma is performed with a voltage bias of a continuous mode between 0V and 100V, inclusive, or a pulse mode between 100V and 400V, inclusive.

28. The method of claim 19, further comprising etching the amorphous carbon capping layer deposited on the carbon-containing features of the patterned EUV resist.

29. The method of claim 28, wherein etching the deposited amorphous carbon capping layer comprises: exposing the amorphous carbon capping layer to an oxygen-containing reactant to modify the amorphous carbon; as well as The modified amorphous carbon is exposed to a plasma of an inert gas.

30. The method of claim 29, wherein the oxygen-containing reactant is O2, O3, H2O, N2O, NO, or CO2.

31. The method of claim 28, further comprising repeating the selectively depositing and etching the deposited amorphous carbon capping layer to fill recesses on carbon-containing features of the patterned EUV resist.

32. The method of claim 19, further comprising etching the underlying metal oxide layer using the amorphous carbon capping layer and the patterned EUV resist as a mask.

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