Display Substrate, Preparation Method Thereof, and Display Panel

Abstract

A display substrate, a preparation method thereof, and a display panel. The display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels, the first sub-pixels include pixel circuits, and the pixel circuits include a plurality of signal lines; in the light-transmitting area of the first display area, at least part of the signal lines are made of transparent traces; in the area outside the light-transmitting area of the first display area, at least part of the signal lines are made of metal traces. The present disclosure can better achieve high-frequency display.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and particularly relate to a display substrate, a preparation method thereof, and a display panel. Background Art

[0002] With the development of technology, the appearance of mobile terminals has attracted more and more attention. Among them, large-screen terminals with a relatively large screen-to-body ratio have gradually become one of the mainstream designs of mobile terminals. Large-screen terminals can enhance the user's gaming and entertainment experience, are conducive to split-screen display, and have a higher sense of technology for the whole machine, thus bringing a stronger visual impact to users.

[0003] Currently, full-screen display has become the mainstream trend in mobile phone displays. The full screen compresses the design space of components such as cameras, infrared sensors, and earpieces, and places components such as cameras and infrared sensors under the display screen, which has become a relatively potential display device design at present. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display panel, which can better achieve high-frequency display.

[0005] Embodiments of the present disclosure provide a display substrate, including a first display area. The first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels. The first sub-pixel includes a pixel circuit, and the pixel circuit includes a plurality of signal lines. In the light-transmitting area of the first display area, at least part of the signal lines are made of transparent traces, and in the area outside the light-transmitting area of the first display area, at least part of the signal lines are made of metal traces.

[0006] In some exemplary embodiments, the plurality of signal lines include scan signal lines, data signal lines, a first power supply line, initial signal lines, and light-emitting signal lines, where:

[0007] The scan signal lines, data signal lines, first power supply line, and initial signal lines are all metal traces, and the light-emitting signal lines are transparent traces.

[0008] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a plurality of conductive layers located on the substrate;

[0009] In the first display area, the first power supply line and the data signal line are located on different conductive layers, and the orthographic projection of the first power supply line on the substrate overlaps with the orthographic projection of the data signal line on the substrate.

[0010] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a plurality of conductive layers located on the substrate; the scan signal lines include a first scan signal line and a second scan signal line, and the first scan signal line and the second scan signal line are located on different conductive layers;

[0011] The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, and a first reset sub-circuit. The driving sub-circuit is configured to generate a driving current between a second node and a third node under the control of a first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line;

[0012] In the first display area, a positive projection of the first scan signal line on the substrate and a positive projection of the second scan signal line on the substrate have an overlapping area.

[0013] In some exemplary embodiments, in the first display area, the second scan signal line extends along a first direction, the second scan signal line includes bent portions arranged at intervals, and the bent portions extend along a second direction, and the first direction is perpendicular to the second direction.

[0014] In some exemplary embodiments, in the first display area, a positive projection of the first scan signal line on the substrate, a positive projection of the initial signal line on the substrate, and a positive projection of the second scan signal line on the substrate have an overlapping area where all three overlap.

[0015] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a substrate and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer, and a second source-drain metal layer sequentially arranged on the substrate;

[0016] The semiconductor layer includes active layers of a plurality of transistors. At least one of the first gate metal layer and the second gate metal layer includes the second scan signal line. The first source-drain metal layer includes the initial signal line and a first power supply line. The first transparent conductive layer includes the light-emitting signal line. The second source-drain metal layer includes the first scan signal line and a data signal line.

[0017] In some exemplary embodiments, the first display area includes multiple columns of the first sub-pixels, and semiconductor layers in the first sub-pixels of each column are arranged in a staggered manner in the row direction with semiconductor layers in the first sub-pixels of adjacent columns.

[0018] In some exemplary embodiments, in the first display area, the first scanning signal line includes a plurality of branches, the first transparent conductive layer includes a fourteenth connection electrode and a fifteenth connection electrode, the first source-drain metal layer includes a sixth connection electrode and a seventh connection electrode, and the first gate metal layer includes a first connection electrode;

[0019] The sixth connection electrode and the seventh connection electrode are respectively electrically connected to both ends of the first connection electrode through vias, the fourteenth connection electrode is electrically connected to the seventh connection electrode through a via, and the fifteenth connection electrode is electrically connected to the sixth connection electrode through a via;

[0020] Each branch of the first scanning signal line is respectively electrically connected to the fourteenth connection electrode and the fifteenth connection electrode in two adjacent first sub-pixels in the same row through vias.

[0021] In some exemplary embodiments, in the first display area, the initial signal line includes a plurality of branches, and the second gate metal layer includes a third connection electrode;

[0022] Each branch of the initial signal line is respectively electrically connected to the third connection electrode in two adjacent first sub-pixels in the same row through vias.

[0023] In some exemplary embodiments, in the first display area, the first power supply line includes a plurality of branches, the first transparent conductive layer includes an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer includes a seventeenth connection electrode;

[0024] The seventeenth connection electrode is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode through vias, and each branch of the first power supply line is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode in two adjacent first sub-pixels in the same column through vias.

[0025] The embodiments of the present disclosure further provide a display panel, including: the display substrate as described in any one of the above, a polarizer provided on the light-emitting side of the display substrate, a cover plate, and a support layer, a heat dissipation layer, etc. provided on the backlight side of the display substrate.

[0026] The embodiments of the present disclosure further provide a method for manufacturing a display substrate. The display substrate includes a first display area. The first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels. The first sub-pixel includes a pixel circuit, and the pixel circuit includes a plurality of signal lines. The manufacturing method includes:

[0027] Forming a semiconductor layer on a substrate;

[0028] Form a first gate metal layer on the semiconductor layer;

[0029] Form a second gate metal layer on the first gate metal layer;

[0030] Form a first source / drain metal layer on the second gate metal layer; form a first transparent conductive layer on the first source / drain metal layer;

[0031] Form a second source / drain metal layer on the first transparent conductive layer;

[0032] In the light-transmitting area of the first display area, the first transparent conductive layer is used to route at least part of the signal lines; in the area outside the light-transmitting area of the first display area, at least one of the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer is used to route at least part of the signal lines.

[0033] The display substrate, its manufacturing method, and the display panel according to the embodiments of the present disclosure can better achieve high-frequency display by using metal materials for part of the signal routing in the first display area. In addition, by overlapping multiple signal lines for routing, the occupied area of the metal routing in the first display area is effectively reduced, the light transmittance of the first display area is increased, and the camera functions such as self-portrait and face recognition of the front camera are improved. In addition, the manufacturing process of the present disclosure can be well compatible with the existing manufacturing process, the process implementation is simple, easy to implement, has high production efficiency, low production cost, and high yield.

[0034] Other features and advantages of the present disclosure will be described in the subsequent description, and some of them will be obvious from the description, or can be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the accompanying drawings. Description of the Drawings

[0035] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the description. They are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0036] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0037] Figure 2 It is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0038] Figure 3 For Figure 2 It is a schematic diagram of a pixel arrangement structure in the shown display panel;

[0039] Figure 4An equivalent circuit diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0040] Figure 5 is Figure 4 a timing diagram of an operation of the pixel circuit shown;

[0041] Figure 6a A schematic plan view of a display substrate provided by an embodiment of the present disclosure;

[0042] Figure 6b is Figure 6a a cross-sectional view along the A-A position in

[0043] Figure 7 A schematic structural diagram of a semiconductor layer of a display substrate provided by an embodiment of the present disclosure;

[0044] Figure 8 A schematic structural diagram of a first conductive layer of a display substrate provided by an embodiment of the present disclosure;

[0045] Figure 9 A schematic structural diagram of a second conductive layer of a display substrate provided by an embodiment of the present disclosure;

[0046] Figure 10 A schematic structural diagram of a fourth insulating layer of a display substrate provided by an embodiment of the present disclosure;

[0047] Figure 11 A schematic structural diagram of a third conductive layer of a display substrate provided by an embodiment of the present disclosure;

[0048] Figure 12 A schematic structural diagram of a fifth insulating layer of a display substrate provided by an embodiment of the present disclosure;

[0049] Figure 13 A schematic structural diagram of a fourth conductive layer of a display substrate provided by an embodiment of the present disclosure;

[0050] Figure 14 A schematic structural diagram of a first planarization layer of a display substrate provided by an embodiment of the present disclosure;

[0051] Figure 15 A schematic structural diagram of a fifth conductive layer of a display substrate provided by an embodiment of the present disclosure. Detailed implementation manners

[0052] To make the objectives, technical solutions, and advantages of the present disclosure more clearly understood, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the modes and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0053] In the accompanying drawings, for the sake of clarity, the sizes, thicknesses of layers, or areas of the respective components are sometimes exaggerated. Therefore, one mode of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings.

[0054] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of the components, rather than to limit the quantity.

[0055] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components changes appropriately according to the directions describing the respective components. Therefore, it is not limited to the terms described in the specification and can be replaced appropriately according to the circumstances.

[0056] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0057] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0058] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other.

[0059] In this specification, "electrically connected" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0060] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes an angle of 85° or more and 95° or less.

[0061] In this specification, "film" and "layer" can be swapped with each other. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0062] "About" in this disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0063] Figure 1 It is a schematic structural diagram of a display panel. As Figure 1As shown, the OLED display panel may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In some exemplary embodiments, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ……, and Dn. For example, the data signal driver may sample the gray value using a clock signal and apply the data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ……, and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, and m may be a natural number. The light emission signal driver may generate emission signals to be provided to the light emission signal lines E1, E2, E3, ……, and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driver may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission signal driver may be configured in the form of a shift register and may generate emission signals in such a way that the light emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, and each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emission signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and the j-th data signal line.

[0064] Figure 2 Schematic diagram of the planar structure of a display panel according to an exemplary embodiment of the present disclosure. As Figure 2As shown, the display panel provided by the embodiment of the present invention includes a first display area 100 and a second display area 200. The first display area 100 includes a plurality of first sub-pixels and a plurality of light-transmitting areas, and the second display area 200 includes a plurality of second sub-pixels. The first sub-pixels and the first sub-pixels satisfy at least one of the following: the distribution density of the first sub-pixels is less than the distribution density of the second sub-pixels, and the area occupied by the first sub-pixels is less than the area occupied by the second sub-pixels. By reducing the distribution density of the first sub-pixels in the first display area 100 or reducing the area occupied by the first sub-pixels, the area of the light-transmitting areas in the first display area 100 is increased, so that the imaging structure can be arranged in the light-transmitting areas, enabling the first display area 100 to be used for display, improving the screen occupation ratio of the display area, and also being able to perform imaging through the light-transmitting areas to meet various needs of users.

[0065] In some exemplary embodiments, the relative positional relationship between the first display area 100 and the second display area 200 can be such that at least part of the edge of the first display area 100 coincides with at least part of the edge of the second display area 200, and the remaining part of the first display area 100 is surrounded by the second display area 200. In this way, the first display area 100 can be arranged at the edge of the display area of the display panel. In some other exemplary embodiments, the relative positional relationship between the second display area 200 and the first display area 100 can also be such that the second display area 200 surrounds the first display area 100. In this way, the first display area 100 can be arranged inside the display area of the display panel, as Figure 2 shown. For example, the first display area 100 can be arranged at the upper left corner of the second display area 200. For another example, the first display area 100 can be arranged at the upper right corner of the second display area 200. For another example, the first display area 100 can be arranged on the left side of the second display area 200. For another example, the first display area 100 can be arranged on the upper side of the second display area 200. Of course, in actual applications, the specific position of the first display area 100 can be designed and determined according to the actual application environment, and is not limited herein.

[0066] In the actual implementation process, the shape of the first display area 100 can be set to a regular shape, such as a rectangle. The top angles of the rectangle can be right angles, or the top angles of the rectangle can also be arc-shaped angles. For another example, the shape of the first display area 20 can also be set to a trapezoid. The trapezoid can be a regular trapezoid or an inverted trapezoid. In addition, the top angles of the trapezoid can be regular included angles or can also be arc-shaped angles. For another example, the shape of the first display area 100 can also be set to an irregular shape. For example, the shape of the first display area 100 can be set to a water droplet shape. Of course, in actual applications, the shape of the first display area 100 can be designed according to the shape of the components arranged in the first display area 100, and is not limited herein.

[0067] In some exemplary embodiments, the area of the first display region 100 is smaller than the area of the second display region 200. Of course, in practical applications, it can be designed according to the components arranged in the first display region 100, which is not limited herein.

[0068] Figure 3 This is a schematic diagram of the arrangement structure of a pixel array according to an exemplary embodiment of the present disclosure. As Figure 3 shown, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first light-emitting unit P1 that emits first-color light, a second light-emitting unit P2 that emits second-color light, and a third light-emitting unit P3 that emits third-color light. The first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 each include a pixel driving circuit and a light-emitting element. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting elements in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuits of the respective light-emitting units, and the light-emitting elements are configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuits of the respective light-emitting units.

[0069] In an exemplary embodiment, the pixel unit P may include a red (R) light-emitting unit, a green (G) light-emitting unit, and a blue (B) light-emitting unit, or may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit, which is not limited herein. In an exemplary embodiment, the shape of the light-emitting unit in the pixel unit may be rectangular, rhombic, pentagonal, or hexagonal. When the pixel unit includes three light-emitting units, the three light-emitting units may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular pyramid manner. When the pixel unit includes four light-emitting units, the four light-emitting units may be arranged in a horizontal side-by-side, vertical side-by-side, or square (Square) manner, which is not limited herein.

[0070] In some exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 4 This is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As Figure 4As shown, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7), one storage capacitor C, and multiple signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, an initial signal line INIT, a first power supply line VDD, a second power supply line VSS, and a light emission control signal line E).

[0071] In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the first node N1. The gate electrode of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second node N2, and the second pole of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first pole of the fourth transistor T4 is connected to the data signal line D, and the second pole of the fourth transistor T4 is connected to the second node N2. The gate electrode of the fifth transistor T5 is connected to the light emission control signal line E, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the light emission control signal line E, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first pole of the light emitting element). The gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 or the reset control signal line Reset, the first pole of the seventh transistor T7 is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the fourth node N4. The first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the first node N1.

[0072] In some exemplary embodiments, the first transistor T1 to the seventh transistor T7 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0073] In some exemplary embodiments, the second pole of the light-emitting element is connected to the second power supply line VSS, and the signal of the second power supply line VSS continuously provides a low-level signal, while the signal of the first power supply line VDD continuously provides a high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n - 1). The second scan signal line S2 of the current display row and the first scan signal line S1 in the pixel driving circuit of the previous display row can be the same signal line to reduce the signal lines of the display panel and achieve a narrow border of the display panel.

[0074] In some exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light-emitting signal line E, and the initial signal line INIT all extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0075] In some exemplary embodiments, the light-emitting element may be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode).

[0076] Figure 5 For Figure 4 a working timing diagram of the pixel driving circuit shown below. Through Figure 5 the working process of the exemplary pixel driving circuit, the exemplary embodiments of the present disclosure will be described. Figure 4 The pixel driving circuit in [the description] includes seven transistors (the first transistor T1 to the sixth transistor T7), one storage capacitor C1, and seven signal lines (data signal line DATA, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power supply line VDD, second power supply line VSS, and light-emitting signal line EM). All seven transistors are P-type transistors.

[0077] In an exemplary embodiment, the working process of the pixel driving circuit may include:

[0078] The first stage A1, called the reset stage, has the signal of the second scan signal line S2 as a low-level signal, and the signals of the first scan signal line S1 and the light-emitting signal line E as high-level signals. The signal of the second scan signal line S2 being a low-level signal turns on the first transistor T1, and the signal of the initial signal line INIT is supplied to the first node N1 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scan signal line S1 and the light-emitting signal line E being high-level signals turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light in this stage.

[0079] The second stage A2, called the data writing stage or the threshold compensation stage, has the signal of the first scan signal line S1 as a low-level signal, and the signals of the second scan signal line S2 and the light-emitting signal line E as high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal line S1 being a low-level signal turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be supplied to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the sum of the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vdata + Vth, where Vdata is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The conduction of the seventh transistor T7 causes the initial voltage of the initial signal line INIT to be supplied to the first pole of the OLED to initialize (reset) the first pole of the OLED, clear the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scan signal line S2 being a high-level signal turns off the first transistor T1. The signal of the light-emitting signal line E being a high-level signal turns off the fifth transistor T5 and the sixth transistor T6.

[0080] The third stage A3, called the light-emitting stage, has the signal of the light-emitting signal line E as a low-level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 as high-level signals. The signal of the light-emitting signal line E being a low-level signal turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first pole of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the OLED to emit light.

[0081] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the second node N2 is Vdata+Vth, the driving current of the third transistor T3 is as follows:

[0082] I = K*(Vgs-Vth) 2 = K*[(Vdata+Vth-Vdd)-Vth] 2 = K*[(Vdata–Vdd)] 2

[0083] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0084] It can be seen from the above formula that the current I flowing through the light-emitting element is independent of the threshold voltage Vth of the third transistor T3, eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0085] Based on the above working timing, the pixel circuit eliminates the positive charges remaining after the last light emission of the light-emitting element, realizes the compensation of the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

[0086] In the conventional pixel circuit design, the signal lines between the pixel circuits in the first display area are connected by transparent indium tin oxide (ITO) or indium zinc oxide (IZO) traces. However, due to the relatively large resistance value of the transparent ITO or IZO traces themselves, it is very unfavorable for high-frequency display applications.

[0087] Figure 6a FIG. 6b is a schematic structural diagram of the display substrate provided by the embodiment of the present disclosure in the first display area. As Figure 6a shown in the cross-sectional view along the position A-A. As Figure 6a and Figure 6b shown, in the first display area, a plurality of first sub-pixels include pixel circuits (located in the non-light-transmitting area). The pixel circuits include a plurality of signal lines, and adjacent pixel circuits are connected to each other through the signal lines. Each signal line is used to provide different signals for the pixel circuits; in the light-transmitting area of the first display area, at least part of the signal lines adopt transparent traces; in the area outside the light-transmitting area of the first display area, at least part of the signal lines adopt metal traces.

[0088] In some exemplary embodiments, the plurality of signal lines include scan signal lines, data signal lines D, a first power supply line VDD, an initial signal line INIT, and light-emitting signal lines E. Among them, the scan signal lines are used to provide scan signals for the pixel circuits, the data signal lines D are used to provide data signals for the pixel circuits, the first power supply line VDD is used to provide a first power supply signal for the pixel circuits, the initial signal line INIT is used to provide initial signals for the pixel circuits, and the light-emitting signal lines E are used to provide light-emitting control signals for the pixel circuits.

[0089] In some exemplary embodiments, the scan signal lines, the data signal lines D, the first power supply line VDD, and the initial signal line INIT are all metal traces, and the light-emitting signal lines E are transparent traces.

[0090] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a substrate 90 and a plurality of conductive layers located on the substrate 90. The scan signal lines include a first scan signal line S1 and a second scan signal line S2, and the first scan signal line S1 and the second scan signal line S2 are located on different conductive layers.

[0091] In some exemplary embodiments, the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, and a first reset sub-circuit. The driving sub-circuit is configured to generate a driving current between a second node and a third node under the control of a first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line S1; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line S2.

[0092] In some exemplary embodiments, both the first scan signal line S1 and the second scan signal line S2 are metal traces.

[0093] Since the loads of signal traces such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD, and the initial signal line INIT have a greater impact on high frequencies, therefore, in the display substrate of the embodiments of the present disclosure, the ITO traces of the signal traces such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD, and the initial signal line INIT are replaced with conventional metal traces, reducing the resistance of the signal traces, which is thus beneficial for better high-frequency display in the first display area; in addition, since the light-emitting signal lines E have a smaller impact on high-frequency display, they are not changed and still use transparent conductive traces, such as indium tin oxide ITO or indium zinc oxide IZO.

[0094] In some exemplary embodiments, such as Figures 7 to 15As shown, on a plane perpendicular to the display substrate, the display substrate includes a substrate, and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer, and a second source-drain metal layer that are sequentially disposed on the substrate;

[0095] The semiconductor layer includes active layers of multiple transistors. At least one of the first gate metal layer and the second gate metal layer includes a second scan signal line S2. The first source-drain metal layer includes an initial signal line INIT and a first power supply line VDD. The first transparent conductive layer includes a light-emitting signal line E. The second source-drain metal layer includes a first scan signal line S1 and a data signal line D.

[0096] In some exemplary embodiments, as Figure 7 shown, the first display area includes multiple columns of first sub-pixels. The semiconductor layers in the first sub-pixels of each column are staggered in a first direction X with the semiconductor layers in the first sub-pixels of adjacent columns.

[0097] In some exemplary embodiments, as Figure 6a shown, in the first display area, there is an overlapping area between the positive projection of the first scan signal line S1 on the substrate and the positive projection of the second scan signal line S2 on the substrate. In this embodiment, by overlapping the first scan signal line S1 and the second scan signal line S2 for routing, the influence of the metal routing on the transmittance can be minimized to the greatest extent.

[0098] In some exemplary embodiments, as Figure 8 shown, in the first display area, the second scan signal line S2 extends along the first direction X (horizontal direction). The second scan signal line S2 includes bent portions that are spaced apart and extend along the second direction Y (vertical direction). The first direction X and the second direction Y are perpendicular to each other.

[0099] In some exemplary embodiments, as Figures 7 to 15 shown, in the first display area, the first scan signal line includes multiple branches. The first transparent conductive layer includes a fourteenth connection electrode 44 and a fifteenth connection electrode 45. The first source-drain metal layer includes a sixth connection electrode 33 and a seventh connection electrode 34. The first gate metal layer includes a first connection electrode 11;

[0100] The sixth connection electrode 33 and the seventh connection electrode 34 are respectively electrically connected to both ends of the first connection electrode 11 through vias. The fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through a via. The fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through a via;

[0101] Each branch of the first scan signal line S1 is electrically connected to the fourteenth connection electrode 44 and the fifteenth connection electrode 45 in two adjacent first sub-pixels in the same row through vias respectively.

[0102] In some exemplary embodiments, as Figures 7 to 15 shown, in the first display area, there is an overlapping area among the orthographic projections of the first scan signal line S1, the initial signal line INIT, and the second scan signal line S2 on the substrate. In this embodiment, in order to reduce the signal crosstalk caused by the stacked signal traces between the first scan signal line S1 and the second scan signal line S2, in the display substrate of the present disclosure embodiment, the middle layer of the two signal traces is used to route the initial signal line INIT (DC signal), so as to shield the influence of crosstalk to the greatest extent.

[0103] In some exemplary embodiments, in the first display area, the initial signal line INIT includes multiple branches, and the second gate metal layer includes a third connection electrode 21; each branch of the initial signal line INIT is electrically connected to the third connection electrode 21 in two adjacent first sub-pixels in the same row through vias respectively.

[0104] In some exemplary embodiments, as Figure 6a shown, in the first display area, there is an overlapping area between the orthographic projection of the first power supply line VDD on the substrate and the orthographic projection of the data signal line D on the substrate. In this embodiment, by overlapping the routing of the first power supply line VDD and the data signal line D, the influence of the metal traces on the transmittance can be minimized to the greatest extent.

[0105] In some exemplary embodiments, as Figures 11 to 15 shown, in the first display area, the first power supply line VDD includes multiple branches, the first transparent conductive layer includes an eleventh connection electrode 41 and a twelfth connection electrode 42, and the second source-drain metal layer includes a seventeenth connection electrode 51;

[0106] The seventeenth connection electrode 51 is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 through vias respectively, and each branch of the first power supply line VDD is electrically connected to the eleventh connection electrode 41 and the twelfth connection electrode 42 in two adjacent first sub-pixels in the same column through vias respectively.

[0107] The preparation process of the display substrate is described below by way of example to illustrate the structure of the display substrate according to the embodiments of the present disclosure. The "lithography process" as mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be performed using any one or more of spraying and spin coating. Etching can be performed using any one or more of dry etching and wet etching. A "thin film" refers to a thin film made of a certain material on a substrate by using a deposition or coating process. If the "thin film" does not require a lithography process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". When the "thin film" still requires a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process contains at least one "pattern". The statement "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are formed simultaneously through the same lithography process. The statement "the orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0108] In some exemplary embodiments, Figure 6a and Figure 6b the preparation process of the display substrate shown may include the following steps:

[0109] (1) Form a semiconductor layer pattern on the substrate 90. Forming a semiconductor layer pattern on the substrate 90 includes: first depositing an insulating thin film on the substrate 90 to form a first insulating layer 91 pattern covering the entire substrate 90. Subsequently, deposit an active layer thin film, and perform lithography on the active layer thin film through a lithography process to form a semiconductor layer pattern disposed on the first insulating layer 91, as Figure 7 shown. Among them, the semiconductor layer pattern in the first display area may include the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, the active layer 40 of the fourth transistor T4, the active layer 50 of the fifth transistor T5, the active layer 60 of the sixth transistor T6, and the active layer 70 of the seventh transistor T7. In some exemplary embodiments, the first active layer 10, the second active layer 20, the third active layer 30, the fourth active layer 40, the fifth active layer 50, the sixth active layer 60, and the seventh active layer 70 may be an integrally connected structure.

[0110] In some exemplary embodiments, the shape of the first active layer 10 may be in the shape of a door frame, and the shape of the second active layer 20 may be in the shape of The shape of the third active layer 30 can be in a "ji" shape, the shape of the fourth active layer 40 can be in a "1" shape, the shapes of the fifth active layer 50 and the sixth active layer 60 can be in an "L" shape, and the shape of the seventh active layer 70 can be in a dumbbell shape.

[0111] In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In some exemplary embodiments, the second region 102 of the first active layer 10 simultaneously serves as the second region 202 of the second active layer 20, that is, the second region 102 of the first active layer 10 and the second region 202 of the second active layer 20 are interconnected. The first region 301 of the third active layer 30 simultaneously serves as the second region 402 of the fourth active layer 40 and the second region 502 of the fifth active layer 50, that is, the first region 301 of the third active layer 30, the second region 402 of the fourth active layer 40, and the second region 502 of the fifth active layer 50 are interconnected. The second region 302 of the third active layer 30 simultaneously serves as the first region 601 of the sixth active layer 60 and the first region 201 of the second active layer 20, that is, the second region 302 of the third active layer 30, the first region 601 of the sixth active layer 60, and the first region 201 of the second active layer 20 are interconnected. The first region 101 of the first active layer 10 simultaneously serves as the first region 701 of the seventh active layer 70, that is, the first region 101 of the first active layer 10 and the first region 701 of the seventh active layer 70 are interconnected. The first regions 401 of the fourth active layer 40, the first regions 501 of the fifth active layer 50, the second regions 602 of the sixth active layer 60, and the second regions 702 of the seventh active layer 70 are separately provided.

[0112] In some exemplary embodiments, in the first display area 100, a plurality of first sub-pixels include two or more columns, and the semiconductor layers of the first sub-pixels in each column are arranged in a staggered manner in the first direction with respect to the semiconductor layers of the adjacent columns of the first sub-pixels. By arranging the semiconductor layers of the adjacent columns of the first sub-pixels in a staggered manner in the first direction, the spacing (Margin) between the semiconductor layers of the adjacent columns of the first sub-pixels in the first direction is increased, so that the light-transmitting regions for imaging on both sides of the first sub-pixels are larger.

[0113] In some exemplary embodiments, the semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor may all be LTPS thin-film transistors.

[0114] After this process, the display substrate includes a first insulating layer 91 provided on a substrate 90 and a semiconductor layer provided on the first insulating layer 91, and the semiconductor layer may include the active layers of a plurality of transistors.

[0115] (2) Form a first conductive layer pattern. In some exemplary embodiments, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate 90 on which the foregoing pattern is formed, patterning the first metal film through a patterning process to form a second insulating layer 92 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 92. The first conductive layer pattern in the first display area at least includes: a second scan signal line S2, a first connection electrode 11, a second connection electrode 12, and a first plate Ce1 of a storage capacitor, as Figure 8 shown. In some exemplary embodiments, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0116] In the embodiments of the present disclosure, by using a metal wire for the second scan signal line S2 in the first display area, the influence of the wire load on high-frequency display can be reduced, so that the first display area can better achieve high-frequency display.

[0117] In some exemplary embodiments, within each sub-pixel, the second scan signal line S2 is located on a side of the first connection electrode 11 away from the first plate Ce1 of the storage capacitor, and the first plate Ce1 of the storage capacitor is disposed between the first connection electrode 11 and the second connection electrode 12.

[0118] In some exemplary embodiments, a region where the second scan signal line S2 overlaps with the first active layer of the first transistor T1 serves as a gate electrode of a dual-gate structure of the first transistor T1.

[0119] In some exemplary embodiments, in the first display area 100, the second scan signal line S2 has a zigzag structure. Since in the first display area 100, the semiconductor layers of the first sub-pixels in each column are arranged in a staggered manner in the first direction with respect to the semiconductor layers of the first sub-pixels in adjacent columns, and the second scan signal line S2 includes an overlapping region with the first active layer of the first transistor T1 in a row of first sub-pixels, therefore, the second scan signal line S2 has a zigzag structure.

[0120] In some exemplary embodiments, the region where the first connection electrode 11 overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. The first connection electrode 11 is provided with a gate block 11-1 protruding toward the second scan signal line S2. The orthographic projection of the gate block 11-1 on the substrate 90 overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate 90. The region where the first connection electrode 11 and the gate block 11-1 overlap with the second active layer of the second transistor T2 serves as the gate electrode of the dual-gate structure of the second transistor T2. The region where the first connection electrode 11 overlaps with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7. That is, the gate electrodes of the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are interconnected to form an integrated structure.

[0121] In some exemplary embodiments, the region where the second connection electrode 12 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and the region where the second connection electrode 12 overlaps with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. That is, the gate electrodes of the fifth transistor T5 and the sixth transistor T6 are interconnected to form an integrated structure.

[0122] In some exemplary embodiments, the first plate Ce1 may be rectangular, and chamfers may be provided at the corners of the rectangle. The orthographic projection of the first plate Ce1 on the substrate 90 overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate 90. In some exemplary embodiments, the first plate Ce1 simultaneously serves as the gate electrode of the third transistor T3. The region where the third active layer of the third transistor T3 overlaps with the first plate Ce1 serves as the channel region of the third transistor T3. One end of the channel region is connected to the first region of the third active layer, and the other end is connected to the second region of the third active layer.

[0123] In some exemplary embodiments, after forming the first conductive layer pattern, the first conductive layer can be used as a mask to conductivize the semiconductor layer. The semiconductor layer in the region blocked by the first conductive layer forms the channel regions of the respective transistors, and the semiconductor layer in the region not blocked by the first conductive layer is conductivized, that is, the first regions and the second regions of the respective active layers are all conductivized.

[0124] After this process, the display substrate includes a first insulating layer 91 provided on the substrate 90, a semiconductor layer provided on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a first conductive layer provided on the second insulating layer 92. The first conductive layer may include a second scan signal line S2, a first connection electrode 11, a second connection electrode 12, and a first plate Ce1 of a storage capacitor.

[0125] (3) Form a second conductive layer pattern. In some exemplary embodiments, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate 90 on which the aforementioned pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93. The second conductive layer pattern in the first display region at least includes: a second electrode plate Ce2 of the storage capacitor and a third connection electrode 21, as Figure 9 shown. In some exemplary embodiments, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0126] In some exemplary embodiments, within each sub-pixel, the third connection electrode 21 is located on a side of the second scanning signal line S2 away from the first connection electrode 11, and the third connection electrode 21 is used to connect to an initial signal line INIT formed subsequently.

[0127] In some exemplary embodiments, the contour of the second electrode plate Ce2 may be a rectangular shape with a notch H. Chamfers may be provided at the corners of the rectangular shape. There is an overlapping region between the orthographic projection of the second electrode plate Ce2 on the substrate 90 and the orthographic projection of the first electrode plate Ce1 on the substrate 90. The notch H may be located at a corner of the second electrode plate Ce2. The notch H may be a polygon. The notch H exposes the third insulating layer covering the first electrode plate Ce1, and the orthographic projection of the first electrode plate Ce1 on the substrate 90 overlaps with the orthographic projection of the notch H on the substrate 90. In some exemplary embodiments, the notch H is configured to accommodate a third via formed subsequently. The third via is located within the notch H and exposes the first electrode plate Ce1, so that the second pole of the second transistor T2 formed subsequently is connected to the first electrode plate Ce1.

[0128] After this process, the display substrate includes a first insulating layer 91 disposed on the substrate 90, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, a first conductive layer disposed on the second insulating layer 92, a third insulating layer 93 covering the first conductive layer, and a second conductive layer disposed on the third insulating layer 93. The second conductive layer at least includes a second electrode plate Ce2 of the storage capacitor and a third connection electrode 21.

[0129] (4) Pattern the fourth insulating layer 94. Forming the pattern of the fourth insulating layer 94 includes: depositing a fourth insulating thin film on the substrate 90 on which the above structure is formed, patterning the fourth insulating thin film through a patterning process to form a pattern of the fourth insulating layer 94 having a plurality of vias, and the plurality of vias include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, and a fourteenth via V14, as Figure 10 shown.

[0130] In an exemplary embodiment, the fourth insulating layer within the first via V1 is etched away to expose the surface of the second electrode plate Ce2 of the storage capacitor, configured to enable the second branch VDD-B2 of the first power supply line VDD formed subsequently to be electrically connected to the second electrode plate Ce2 of the storage capacitor through this via.

[0131] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose the surface of the first region 501 of the fifth active layer, configured to enable the second branch VDD-B2 of the first power supply line VDD formed subsequently to be connected to the first region 501 of the fifth active layer through this via.

[0132] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the third via V3 are etched away to expose the surface of the first electrode plate Ce1 of the storage capacitor, configured to enable the fourth connection electrode 31 formed subsequently to be electrically connected to the first electrode plate Ce1 of the storage capacitor through this via.

[0133] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away to expose the surface of the second region 102 of the first active layer (which is also the second region 202 of the second active layer), configured to enable the second pole of the first transistor T1 formed subsequently to be connected to the first active layer through this via, and enable the second pole of the second transistor T2 formed subsequently to be connected to the second active layer through this via.

[0134] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away to expose the surface of the second region 702 of the seventh active layer, configured to enable the fifth connection electrode 32 formed subsequently to be electrically connected to the second region 702 of the seventh active layer through this via.

[0135] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region 602 of the sixth active layer, configured to enable the fifth connection electrode 32 formed subsequently to be electrically connected to the second region 602 of the sixth active layer through this via.

[0136] In an exemplary embodiment, the fourth insulating layer within the seventh via V7 is etched away to expose the surface of one end of the third connection electrode 21, configured to enable the first branch INIT-B1 of the initial signal line INIT formed subsequently to be electrically connected to one end of the third connection electrode 21 through this via.

[0137] In an exemplary embodiment, the fourth insulating layer within the eighth via V8 is etched away to expose the surface of the other end of the third connection electrode 21, configured to enable the second branch INIT-B2 of the initial signal line INIT formed subsequently to be electrically connected to the other end of the third connection electrode 21 through this via.

[0138] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the ninth via V9 are etched away to expose the surface of the first region 101 of the first active layer (which is also the first region 701 of the seventh active layer), configured to enable the initial signal line formed subsequently to be electrically connected to the first region 101 of the first active layer (which is also the first region 701 of the seventh active layer) through this via.

[0139] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the tenth via V10 are etched away to expose the surface of one end of the first connection electrode 11, configured to enable the sixth connection electrode 33 formed subsequently to be electrically connected to one end of the first connection electrode 11 through this via.

[0140] In an exemplary embodiment, the fourth insulating layer within the eleventh via V11 is etched away to expose the surface of the other end of the first connection electrode 11, configured to enable the seventh connection electrode 34 formed subsequently to be electrically connected to the other end of the first connection electrode 11 through this via.

[0141] In an exemplary embodiment, the fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away to expose the surface of the first region 401 of the fourth active layer, configured to enable the eighth connection electrode 35 formed subsequently to be electrically connected to the first region 401 of the fourth active layer through this via.

[0142] In an exemplary embodiment, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away to expose the surface of one end of the second connection electrode 12, configured to enable the ninth connection electrode 36 formed subsequently to be electrically connected to one end of the second connection electrode 12 through this via.

[0143] In an exemplary embodiment, the fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the other end of the second connection electrode 12, which is configured to enable the tenth connection electrode 37 formed subsequently to be electrically connected to the other end of the second connection electrode 12 through this via.

[0144] (5) Form a third conductive layer pattern. In some exemplary embodiments, forming the third conductive layer may include: depositing a third metal thin film on the substrate 90 on which the foregoing pattern is formed, and patterning the third metal thin film by a patterning process to form a third conductive layer disposed on the fourth insulating layer 94. As Figure 11 shown, the third conductive layer in the first display region may include a first branch VDD-B1 of the first power supply line VDD, a second branch VDD-B2 of the first power supply line VDD, a first branch INIT-B1 of the initial signal line INIT, a second branch INIT-B2 of the initial signal line INIT, a fourth connection electrode 31, a fifth connection electrode 32, a sixth connection electrode 33, a seventh connection electrode 34, an eighth connection electrode 35, a ninth connection electrode 36, and a tenth connection electrode 37. In some exemplary embodiments, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0145] In the embodiments of the present disclosure, by using metal traces for the first power supply line VDD and the initial signal line INIT in the first display region, the influence of the trace load on high-frequency display can be reduced, so that the first display region can better achieve high-frequency display.

[0146] In some exemplary embodiments, the first branch VDD-B1 of the first power supply line VDD is electrically connected to the second branch VDD-B2 of the first power supply line VDD through a plurality of vias and a plurality of connection electrodes formed subsequently (here, the plurality of vias include: the fifteenth via V15, the sixteenth via V16, the twenty-sixth via, and the twenty-seventh via V27, and the plurality of connection electrodes include: the eleventh connection electrode 41, the twelfth connection electrode 42, and the seventeenth connection electrode 51).

[0147] In some exemplary embodiments, the second branch VDD-B2 of the first power supply line VDD is electrically connected to the second electrode plate Ce2 of the storage capacitor through the first via V1, and is connected to the first region 501 of the fifth active layer through the second via V2, so that the first pole of the fifth transistor T5 has the same potential as the first power supply line VDD.

[0148] In some exemplary embodiments, one side of the first branch VDD-B1 of the first power supply line VDD is electrically connected to the second branch VDD-B2 of the first power supply line VDD within this sub-pixel through a plurality of vias and a plurality of connection electrodes formed subsequently, and on the other hand, it extends to the upper sub-pixel of the column where this sub-pixel is located and serves as the second branch VDD-B2 of the first power supply line VDD in the upper sub-pixel of the column where this sub-pixel is located.

[0149] In some exemplary embodiments, one side of the second branch VDD-B2 of the first power supply line VDD is electrically connected to the first branch VDD-B1 of the first power supply line VDD within this sub-pixel through a plurality of vias and a plurality of connection electrodes formed subsequently, and on the other hand, it extends to the lower sub-pixel of the column where this sub-pixel is located and serves as the first branch VDD-B1 of the first power supply line VDD in the lower sub-pixel of the column where this sub-pixel is located.

[0150] In some exemplary embodiments, the first branch INIT-B1 of the initial signal line INIT is connected to one end of the third connection electrode 21 through the seventh via V7, and the second branch INIT-B2 of the initial signal line INIT is connected to the other end of the third connection electrode 21 through the eighth via V8. In this embodiment, through the third connection electrode 21, the seventh via V7, and the eighth via V8, the electrical connection between the first branch INIT-B1 of the initial signal line INIT and the second branch INIT-B2 of the initial signal line INIT is achieved.

[0151] In some exemplary embodiments, the second branch INIT-B2 of the initial signal line INIT is connected to the first region 101 of the first active layer (which is also the first region 701 of the seventh active layer) through the ninth via V9, so that the first pole of the first transistor T1 (which is also the first pole of the seventh transistor T7) has the same potential as the first initial signal line INIT1.

[0152] In some exemplary embodiments, one side of the first branch INIT-B1 of the initial signal line INIT is electrically connected to the second branch INIT-B2 of the initial signal line INIT within this sub-pixel through the third connection electrode 21, and on the other hand, it extends to the upper sub-pixel of the row where this sub-pixel is located and serves as the second branch INIT-B2 of the initial signal line INIT in the upper sub-pixel of the row where this sub-pixel is located.

[0153] In some exemplary embodiments, on one hand, the second branch INIT-B2 of the initial signal line INIT is electrically connected to the first branch INIT-B1 of the initial signal line INIT within this sub-pixel through the third connection electrode 21, and on the other hand, it extends to the next sub-pixel in the row where this sub-pixel is located and serves as the first branch INIT-B1 of the initial signal line INIT in the next sub-pixel in the row where this sub-pixel is located.

[0154] In some exemplary embodiments, the positive projection of the first branch INIT-B1 of the initial signal line INIT and the positive projection of the second branch INIT-B2 of the initial signal line INIT on the substrate have an overlapping region with the positive projection of the second scan signal line S2 on the substrate.

[0155] In some exemplary embodiments, the fourth connection electrode 31 is electrically connected to the first electrode plate Ce1 of the storage capacitor through the third via V3 and is connected to the second region 102 of the first active layer (which is also the second region 202 of the second active layer) through the fourth via V4. In some exemplary embodiments, the fourth connection electrode 31 can serve as the second pole of the first transistor T1 and the second pole of the second transistor T2.

[0156] In some exemplary embodiments, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5 and is connected to the second region 602 of the sixth active layer through the sixth via V6. In some exemplary embodiments, the fifth connection electrode 32 can serve as the second pole of the seventh transistor T7 and the second pole of the sixth transistor T6.

[0157] In some exemplary embodiments, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via V10.

[0158] In some exemplary embodiments, the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via V11.

[0159] In some exemplary embodiments, the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through the twelfth via V12. In some exemplary embodiments, the eighth connection electrode 35 can serve as the first pole of the fourth transistor T4.

[0160] In some exemplary embodiments, the ninth connection electrode 36 is electrically connected to one end of the second connection electrode 12 through the thirteenth via V13.

[0161] In some exemplary embodiments, the tenth connection electrode 37 is electrically connected to the other end of the second connection electrode 12 through the fourteenth via V14.

[0162] (6) Pattern the fifth insulating layer 95. Forming the pattern of the fifth insulating layer 95 includes: coating a fifth insulating thin film on the substrate 90 on which the foregoing pattern is to be formed, and forming a pattern of the fifth insulating layer 95 covering the third conductive layer through a photolithography process of mask exposure and development. The fifth insulating layer 95 in the first display area is provided with a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, and a twenty-second via V22, as Figure 12 shown.

[0163] In some exemplary embodiments, the fifth insulating layer within the fifteenth via V15 is etched away to expose the surface of the second branch VDD-B2 of the first power supply line VDD, configured to enable the subsequent formed eleventh connection electrode 41 to be electrically connected to the second branch VDD-B2 of the first power supply line VDD through this via.

[0164] In some exemplary embodiments, the fifth insulating layer within the sixteenth via V16 is etched away to expose the surface of the first branch VDD-B1 of the first power supply line VDD, configured to enable the subsequent formed twelfth connection electrode 42 to be electrically connected to the first branch VDD-B1 of the first power supply line VDD through this via.

[0165] In some exemplary embodiments, the fifth insulating layer within the seventeenth via V17 is etched away to expose the surface of the ninth connection electrode 36, configured to enable the first branch E-B1 of the subsequent formed light-emitting signal line E to be electrically connected to the ninth connection electrode 36 through this via.

[0166] In some exemplary embodiments, the fifth insulating layer within the eighteenth via V18 is etched away to expose the surface of the tenth connection electrode 37, configured to enable the second branch E-B2 of the subsequent formed light-emitting signal line E to be electrically connected to the tenth connection electrode 37 through this via.

[0167] In some exemplary embodiments, the fifth insulating layer within the nineteenth via V19 is etched away to expose the surface of the fifth connection electrode 32, configured to enable the subsequent formed thirteenth connection electrode 43 to be electrically connected to the fifth connection electrode 32 through this via.

[0168] In some exemplary embodiments, the fifth insulating layer within the twentieth via V20 is etched away to expose the surface of the seventh connection electrode 34, configured to enable the subsequent formed fourteenth connection electrode 44 to be electrically connected to the seventh connection electrode 34 through this via.

[0169] In some exemplary embodiments, the fifth insulating layer within the twenty-first via V21 is etched away to expose the surface of the sixth connection electrode 33, configured to enable the subsequent formed fifteenth connection electrode 45 to be electrically connected to the sixth connection electrode 33 through this via.

[0170] In some exemplary embodiments, the fifth insulating layer within the twenty-second via V22 is etched away to expose the surface of the eighth connection electrode 35, configured to enable the subsequent formed sixteenth connection electrode 46 to be electrically connected to the eighth connection electrode 35 through this via.

[0171] (7) Form a fourth conductive layer pattern. In some exemplary embodiments, forming the fourth conductive layer may include: depositing a first transparent conductive thin film on the substrate 90 on which the foregoing pattern is formed, and patterning the first transparent conductive thin film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer 95. As Figure 13 shown, the fourth conductive layer in the first display area may include a first branch E-B1 of the light-emitting signal line E, a second branch E-B2 of the light-emitting signal line E, an eleventh connection electrode 41, a twelfth connection electrode 42, a thirteenth connection electrode 43, a fourteenth connection electrode 44, a fifteenth connection electrode 45, and a sixteenth connection electrode 46. In some exemplary embodiments, the fourth conductive layer may be referred to as a first transparent conductive layer.

[0172] In the embodiments of the present disclosure, by making the light-emitting signal line E in the first display area made of a transparent conductive material, the light transmittance in the camera area is increased, improving the imaging effect; at the same time, since the signal load of the light-emitting signal line E has little impact on high-frequency display, therefore, using a transparent conductive material for the light-emitting signal line E does not affect the high-frequency display effect.

[0173] In some exemplary embodiments, one end of the first branch E-B1 of the light-emitting signal line E is electrically connected to one end of the second connection electrode 12 within this sub-pixel through the seventeenth via V17, and on the other hand, extends to the upper sub-pixel in the row where this sub-pixel is located, and is electrically connected to the other end of the second connection electrode 12 in the upper sub-pixel in the row where this sub-pixel is located through the eighteenth via V18 in the upper sub-pixel in the row where this sub-pixel is located.

[0174] In some exemplary embodiments, one end of the second branch E-B2 of the light-emitting signal line E is electrically connected to the other end of the second connection electrode 12 within this sub-pixel through the eighteenth via V18, and on the other hand, extends to the lower sub-pixel in the row where this sub-pixel is located, and is electrically connected to one end of the second connection electrode 12 in the lower sub-pixel in the row where this sub-pixel is located through the seventeenth via V17 in the lower sub-pixel in the row where this sub-pixel is located.

[0175] In this embodiment, the electrical connection between the first branch E-B1 and the second branch E-B2 of the light-emitting signal line E is achieved through the second connection electrode 12, the seventeenth via V17, and the eighteenth via V18.

[0176] In some exemplary embodiments, the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power supply line VDD through the fifteenth via V15.

[0177] In some exemplary embodiments, the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power supply line VDD through the sixteenth via V16.

[0178] In some exemplary embodiments, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through the nineteenth via V19.

[0179] In some exemplary embodiments, the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via V20.

[0180] In some exemplary embodiments, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via V21.

[0181] In some exemplary embodiments, the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through the twenty-second via V22.

[0182] (8) Form a pattern of the first planarization layer 96. Forming the pattern of the first planarization layer 96 includes: depositing a first planarization thin film on the substrate 90 on which the aforementioned pattern is formed, patterning the first planarization thin film using a patterning process to form the first planarization layer 96 disposed on the fourth conductive layer. The first planarization layer 96 is provided with the twenty-third via V23, the twenty-fourth via V24, the twenty-fifth via V25, the twenty-sixth via V26, the twenty-seventh via V27, and the twenty-eighth via V28. The thirteenth via V13 exposes the fourth connection line L4, and the fourteenth via V14 exposes the seventh connection line L7, as Figure 14 shown.

[0183] In some exemplary embodiments, the first planarization layer within the twenty-third via V23 is etched away to expose the surface of the fourteenth connection electrode 44, configured to enable the first branch S1-B1 of the first scan signal line S1 formed subsequently to be electrically connected to the fourteenth connection electrode 44 through this via.

[0184] In some exemplary embodiments, the first planar layer within the twenty-fourth via V24 is etched away to expose the surface of the fifteenth connection electrode 45, configured to enable the second branch S1-B2 of the first scan signal line S1 formed subsequently to be electrically connected to the fifteenth connection electrode 45 through this via.

[0185] In some exemplary embodiments, the first planar layer within the twenty-fifth via V25 is etched away to expose the surface of the sixteenth connection electrode 46, configured to enable the data signal line D formed subsequently to be electrically connected to the sixteenth connection electrode 46 through this via.

[0186] In some exemplary embodiments, the first planar layer within the twenty-sixth via V26 is etched away to expose the surface of the twelfth connection electrode 42, configured to enable the seventeenth connection electrode 51 formed subsequently to be electrically connected to the twelfth connection electrode 42 through this via.

[0187] In some exemplary embodiments, the first planar layer within the twenty-seventh via V27 is etched away to expose the surface of the eleventh connection electrode 41, configured to enable the seventeenth connection electrode 51 formed subsequently to be electrically connected to the eleventh connection electrode 41 through this via.

[0188] In some exemplary embodiments, the first planar layer within the twenty-eighth via V28 is etched away to expose the surface of the thirteenth connection electrode 43, configured to enable the eighteenth connection electrode 52 formed subsequently to be electrically connected to the thirteenth connection electrode 43 through this via.

[0189] (9) Form a fifth conductive layer pattern. Forming the fifth conductive layer may include: depositing a fifth metal thin film on the substrate 90 on which the foregoing pattern is formed, and patterning the fifth metal thin film using a patterning process to form the fifth conductive layer disposed on the first planar layer. As Figure 15 shown, the fifth conductive layer in the first display area may include the first branch S1-B1 of the first scan signal line S1, the second branch S1-B2 of the first scan signal line S1, the data signal line D, the seventeenth connection electrode 51, and the eighteenth connection electrode 52. In some exemplary embodiments, the fifth conductive layer may be referred to as the second source-drain metal (SD2) layer.

[0190] In the embodiments of the present disclosure, by using metal traces for the first scan signal line S1 and the data signal line D in the first display area, the influence of the trace load on high-frequency display can be reduced, so that the first display area can better achieve high-frequency display.

[0191] In some exemplary embodiments, one side of the first branch S1-B1 of the first scan signal line S1 is electrically connected to the fourteenth connection electrode 44 in the present sub-pixel through the twenty-third via V23. On the other hand, it extends to the upper sub-pixel of the row where the present sub-pixel is located and is electrically connected to the fifteenth connection electrode 45 in the upper sub-pixel of the row where the present sub-pixel is located through the twenty-fourth via V24 in the upper sub-pixel of the row where the present sub-pixel is located.

[0192] In some exemplary embodiments, one side of the second branch S1-B2 of the first scan signal line S1 is electrically connected to the fifteenth connection electrode 45 in the present sub-pixel through the twenty-fourth via V24. On the other hand, it extends to the lower sub-pixel of the row where the present sub-pixel is located and is electrically connected to the fourteenth connection electrode 44 in the lower sub-pixel of the row where the present sub-pixel is located through the twenty-third via V23 in the lower sub-pixel of the row where the present sub-pixel is located.

[0193] Since the fourteenth connection electrode 44 is electrically connected to the seventh connection electrode 34 through the twentieth via V20, the fifteenth connection electrode 45 is electrically connected to the sixth connection electrode 33 through the twenty-first via V21, the sixth connection electrode 33 is electrically connected to one end of the first connection electrode 11 through the tenth via V10, and the seventh connection electrode 34 is electrically connected to the other end of the first connection electrode 11 through the eleventh via V11, an electrical connection between the first branch S1-B1 and the second branch S1-B2 of the first scan signal line S1 is achieved.

[0194] In some exemplary embodiments, there is an overlapping area between the orthographic projection of the first branch S1-B1 of the first scan signal line S1 on the substrate 90 and the orthographic projection of the first branch INIT-B1 of the initial signal line INIT on the substrate 90. There is also an overlapping area between the orthographic projection of the second branch S1-B2 of the first scan signal line S1 on the substrate 90 and the orthographic projection of the second branch INIT-B2 of the initial signal line INIT on the substrate 90.

[0195] In some exemplary embodiments, there is an overlapping area between the orthographic projections of the first branch S1-B1 and the second branch S1-B2 of the first scan signal line S1 on the substrate 90 and the orthographic projection of the second scan signal line S2 on the substrate 90.

[0196] In some exemplary embodiments, there is an overlapping region in the orthographic projection on the substrate 90 among the first branch S1-B1 of the first scanning signal line S1, the first branch INIT-B1 of the initial signal line INIT, and the second scanning signal line S2. There is also an overlapping region in the orthographic projection on the substrate 90 among the second branch S1-B2 of the first scanning signal line S1, the second branch INIT-B2 of the initial signal line INIT, and the second scanning signal line S2.

[0197] In the embodiments of the present disclosure, by making there be an overlapping region in the orthographic projection on the substrate 90 between the first scanning signal line S1 and the second scanning signal line S2, the influence of metal traces on the transmittance can be minimized to the greatest extent, the transmittance of the first display area is higher, and the shooting performance is better. And by arranging the initial signal line INIT between the first scanning signal line S1 and the second scanning signal line S2, the signal crosstalk between the first scanning signal line S1 and the second scanning signal line S2 can be reduced, so that the first display area can better achieve high-frequency display, greatly improving the display quality.

[0198] In some exemplary embodiments, the data signal line D is electrically connected to the sixteenth connection electrode 46 through the twenty-fifth via V25. Since the sixteenth connection electrode 46 is electrically connected to the eighth connection electrode 35 through the twenty-second via V22, and the eighth connection electrode 35 is electrically connected to the first region 401 of the fourth active layer through the twelfth via V12, the electrical connection between the data signal line and the first pole of the fourth transistor is realized, so that the data signal transmitted by the data signal line D can be written into the fourth transistor.

[0199] In some exemplary embodiments, there is an overlapping region in the orthographic projection on the substrate 90 among the data signal line D, the first branch VDD-B1 of the first power supply line VDD, and the second branch VDD-B2 of the first power supply line VDD.

[0200] In the embodiments of the present disclosure, by making there be an overlapping region in the orthographic projection on the substrate between the data signal line D and the first power supply line VDD, the influence of metal traces on the transmittance can be minimized to the greatest extent, the transmittance of the first display area is higher, and the shooting performance is better. In addition, the first power supply line VDD can shield the signal crosstalk generated by the metal traces below the third conductive layer on the data signal line D, so that the first display area can better achieve high-frequency display, greatly improving the display quality.

[0201] In some exemplary embodiments, on one hand, the seventeenth connection electrode 51 is electrically connected to the twelfth connection electrode 42 through the twenty-sixth via V26, and on the other hand, it is electrically connected to the eleventh connection electrode 41 through the twenty-seventh via V27. Since the twelfth connection electrode 42 is electrically connected to the first branch VDD-B1 of the first power supply line VDD through the sixteenth via V16, and the eleventh connection electrode 41 is electrically connected to the second branch VDD-B2 of the first power supply line VDD through the fifteenth via V15, the electrical connection between the first branch VDD-B1 and the second branch VDD-B2 of the first power supply line VDD is realized.

[0202] In some exemplary embodiments, the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty-eighth via V28.

[0203] (10) Form a pattern of the second planar layer 97. In some exemplary embodiments, forming a pattern of the second planar layer 97 may include: coating a second planar thin film on the substrate 90 on which the foregoing pattern is formed, patterning the second planar thin film using a patterning process to form the second planar layer 97 covering the fifth conductive layer. At least the twenty-ninth via V29 is provided on the second planar layer 97 in the first display area, as shown in FIG. 6a.

[0204] In some exemplary embodiments, the twenty-ninth via V29 is located in the area where the eighteenth connection electrode 52 is located. The second planar layer in the twenty-ninth via V29 is removed to expose the surface of the eighteenth connection electrode 52. The twenty-ninth via V29 is configured to enable the anode formed subsequently to be electrically connected to the eighteenth connection electrode 52 through this via.

[0205] (11) In some exemplary embodiments, forming an anode pattern may include: depositing a transparent conductive thin film on the substrate 90 on which the foregoing pattern is formed, patterning the transparent conductive thin film using a patterning process to form an anode provided on the second planar layer 97.

[0206] In some exemplary embodiments, in the first display area, the anode is connected to the eighteenth connection electrode 52 through the twenty-ninth via V29. Since the eighteenth connection electrode 52 is electrically connected to the thirteenth connection electrode 43 through the twenty-eighth via V28, the thirteenth connection electrode 43 is electrically connected to the fifth connection electrode 32 through the nineteenth via V19, the fifth connection electrode 32 is electrically connected to the second region 702 of the seventh active layer through the fifth via V5, and is connected to the second region 602 of the sixth active layer through the sixth via V6, the pixel circuit can drive the light-emitting element to emit light.

[0207] In some exemplary embodiments, the subsequent preparation process may include: coating a pixel definition thin film, patterning the pixel definition thin film through a patterning process to form a pixel definition layer (PDL), and a sub-pixel aperture (Subpixel Apertures, SA) is provided in the pixel definition layer of each sub-pixel, and the sub-pixel aperture exposes the anode. An organic light-emitting layer is formed by vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer. A packaging layer is formed, and the packaging layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer. The first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is disposed between the first packaging layer and the third packaging layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0208] In some exemplary embodiments, the substrate 90 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some exemplary embodiments, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be made of amorphous silicon (a-si).

[0209] In some exemplary embodiments, the first conductive layer, the second conductive layer, the third conductive layer, and the fifth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The fourth conductive layer and the anode may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). It may be a single layer, multiple layers, or a composite layer. The first insulating layer is called a buffer (BUF) layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer is called the first gate insulating (GI1) layer, the third insulating layer is called the second gate insulating (GI2) layer, the fourth insulating layer is called the interlayer insulating (ILD) layer, and the fifth insulating layer is called the passivation (PVX) layer. The first planarization (PLN1) layer and the second planarization (PLN2) layer may be made of an organic material. The semiconductor layer may be made of polycrystalline silicon (p-Si) or an oxide.

[0210] In the display substrate according to the embodiments of the present disclosure, by replacing the ITO traces of signal traces such as the first scan signal line S1, the second scan signal line S2, the data signal line D, the first power supply line VDD, and the initial signal line INIT with conventional metal traces, the resistance of the signal traces is reduced, which is beneficial to better high-frequency display in the first display area. In addition, by overlapping multiple signal lines, the occupied area of the metal traces in the first display area is effectively reduced, the light transmittance of the first display area is increased, and the camera functions such as selfies and face recognition of the front camera are improved. In addition, the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield.

[0211] The structure and the preparation process of the display substrate shown in the present disclosure are only an exemplary illustration. In some exemplary embodiments, the corresponding structure may be changed according to actual needs, and the lithography process may be increased or decreased. The present disclosure does not make any limitations here. The structure and the preparation process of the display substrate shown in the present disclosure are described by taking the pixel circuit of 8T1C shown in FIG. 3 as an example. In other exemplary embodiments, the pixel circuit may also be structures such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C. The present disclosure does not make any restrictions on this.

[0212] The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided in the foregoing embodiments. The display substrate includes a first display area, the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels. The first sub-pixel includes a pixel circuit, and the pixel circuit includes a plurality of signal lines. In some exemplary embodiments, the method for manufacturing the display substrate may include the following steps:

[0213] Form a semiconductor layer on a substrate;

[0214] Form a first gate metal layer on the semiconductor layer;

[0215] Form a second gate metal layer on the first gate metal layer;

[0216] Form a first source-drain metal layer on the second gate metal layer;

[0217] Form a first transparent conductive layer on the first source-drain metal layer;

[0218] Form a second source-drain metal layer on the first transparent conductive layer; in the light-transmitting area of the first display area, the first transparent conductive layer is used to route at least part of the signal lines; in the area outside the light-transmitting area of the first display area, at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer is used to route at least part of the signal lines.

[0219] The display substrate manufactured by the method for manufacturing a display substrate provided by the present disclosure has a similar implementation principle and implementation effect to those of the foregoing display substrate, and will not be described in detail herein.

[0220] The present disclosure also provides a display panel. The display panel includes the foregoing display substrate, a polarizer disposed on the light-emitting side of the display substrate, a cover plate, and a support layer, a heat dissipation layer, etc. disposed on the backlight side of the display substrate. The display panel can be used for: mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, and any other products or components with a display function. The embodiments of the present invention are not limited thereto.

[0221] Although the disclosed embodiments are as described above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure and is not intended to limit the present invention. Any person skilled in the art can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, It includes a first display area, and the first display area includes a plurality of first sub-pixels and a light-transmitting area located between the plurality of first sub-pixels; The first sub-pixel includes a pixel circuit, and the pixel circuit includes a plurality of signal lines; In the light-transmitting area of the first display area, at least part of the signal lines are made of transparent traces, and in the area outside the light-transmitting area of the first display area, at least part of the signal lines are made of metal traces; In a plane perpendicular to the display substrate, the display substrate includes a substrate and a plurality of conductive layers located on the substrate; the plurality of signal lines include a first power supply line and a data signal line, the first power supply line and the data signal line are located on different conductive layers, the first power supply line and the data signal line are both metal traces, the first power supply line and the data signal line pass through the light-transmitting area, and in the first display area, there is an overlapping area between the orthographic projection of the first power supply line on the substrate and the orthographic projection of the data signal line on the substrate.

2. The display substrate according to claim 1, wherein The plurality of signal lines further include a scan signal line, an initial signal line, and a light-emitting signal line, wherein: The scan signal line and the initial signal line are both metal traces, and the light-emitting signal line is a transparent trace.

3. The display substrate according to claim 2, wherein The scan signal line includes a first scan signal line and a second scan signal line, and the first scan signal line and the second scan signal line are located on different conductive layers; The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, and a first reset sub-circuit. The driving sub-circuit is configured to generate a driving current between a second node and a third node under the control of a first node; the data writing sub-circuit is configured to write a data signal to the second node under the control of the first scan signal line; the first reset sub-circuit is configured to reset the first node under the control of the second scan signal line; In the first display area, there is an overlapping area between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second scan signal line on the substrate.

4. The display substrate according to claim 3, wherein In the first display area, the second scan signal line extends in a first direction, the second scan signal line includes bent portions arranged at intervals, and the bent portions extend in a second direction, and the first direction is perpendicular to the second direction.

5. The display substrate according to claim 3, wherein In the first display area, there is an area where the orthographic projection of the first scan signal line on the substrate, the orthographic projection of the initial signal line on the substrate, and the orthographic projection of the second scan signal line on the substrate overlap each other.

6. The display substrate according to claim 3, wherein In a plane perpendicular to the display substrate, the display substrate includes a substrate and a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a first transparent conductive layer, and a second source-drain metal layer sequentially arranged on the substrate; The semiconductor layer includes the active layers of a plurality of transistors, at least one of the first gate metal layer and the second gate metal layer includes the second scan signal line, the first source-drain metal layer includes the initial signal line and the first power supply line, the first transparent conductive layer includes the light-emitting signal line, and the second source-drain metal layer includes the first scan signal line and the data signal line.

7. The display substrate according to claim 6, wherein The first display area includes multiple columns of the first sub-pixels, and the semiconductor layers in the first sub-pixels of each column are staggered in the row direction with the semiconductor layers in the first sub-pixels of adjacent columns.

8. The display substrate according to claim 6, wherein In the first display area, the first scanning signal line includes multiple branches, the first transparent conductive layer includes a fourteenth connection electrode and a fifteenth connection electrode, the first source-drain metal layer includes a sixth connection electrode and a seventh connection electrode, and the first gate metal layer includes a first connection electrode; The sixth connection electrode and the seventh connection electrode are respectively electrically connected to both ends of the first connection electrode through vias, the fourteenth connection electrode is electrically connected to the seventh connection electrode through a via, and the fifteenth connection electrode is electrically connected to the sixth connection electrode through a via; Each branch of the first scanning signal line is respectively electrically connected to the fourteenth connection electrode and the fifteenth connection electrode in two adjacent first sub-pixels in the same row through vias.

9. The display substrate according to claim 6, wherein In the first display area, the initial signal line includes multiple branches, and the second gate metal layer includes a third connection electrode; Each branch of the initial signal line is respectively electrically connected to the third connection electrode in two adjacent first sub-pixels in the same row through vias.

10. The display substrate according to claim 6, characterized in that, In the first display area, the first power supply line includes multiple branches, the first transparent conductive layer includes an eleventh connection electrode and a twelfth connection electrode, and the second source-drain metal layer includes a seventeenth connection electrode; The seventeenth connection electrode is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode through vias, and each branch of the first power supply line is respectively electrically connected to the eleventh connection electrode and the twelfth connection electrode in two adjacent first sub-pixels in the same column through vias.

11. A display panel, characterized in that, Comprising: The display substrate according to any one of claims 1 to 10.

12. A method for preparing a display substrate, characterized in that, The display substrate includes a first display area, the first display area includes multiple first sub-pixels and a light-transmitting area located between the multiple first sub-pixels, the first sub-pixels include pixel circuits, the pixel circuits include multiple signal lines, and the manufacturing method includes: Forming a semiconductor layer on a substrate; Forming a first gate metal layer on the semiconductor layer; Forming a second gate metal layer on the first gate metal layer; Forming a first source-drain metal layer on the second gate metal layer; Forming a first transparent conductive layer on the first source-drain metal layer; Forming a second source-drain metal layer on the first transparent conductive layer; in the light-transmitting area of the first display area, the first transparent conductive layer is used for routing at least part of the signal lines; in the area outside the light-transmitting area of the first display area, at least one of the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer is used for routing at least part of the signal lines; the multiple signal lines include a first power supply line and a data signal line, the first power supply line is located on the first source-drain metal layer, the data signal line is located on the second source-drain metal layer, the first power supply line and the data signal line pass through the light-transmitting area, and in the first display area, the orthographic projection of the first power supply line on the substrate overlaps with the orthographic projection of the data signal line on the substrate.

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