semiconductor memory devices

Abstract

A semiconductor memory device (20) includes two types of magnetoresistive memories, namely, a first magnetoresistive memory (21) and a second magnetoresistive memory (22), which are accessed by a target logic unit (41) serving as a logic unit (40). The target logic unit (41), the first magnetoresistive memory (21), and the second magnetoresistive memory (22) are formed on a single semiconductor chip, and the coercive force of the first magnetoresistive memory (21) is greater than the coercive force of the second magnetoresistive memory (22).

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device. Background Art

[0002] As an example of a device using a semiconductor memory device, a memory controller that transmits data to a memory via a signal line, as described in Japanese Patent Application Laid-Open No. 2016-184233 (Patent Document 1), can be cited. In the following description of the background technology, the reference numerals shown in parentheses are the reference numerals of Patent Document 1. Figure 2 As shown, the memory controller (C) includes a memory circuit (15) as a semiconductor memory device. Furthermore, as described in paragraphs 0021 and 0022 of Patent Document 1, the memory controller (C) is configured to use the memory circuit (15) as a working memory for storing working data and to perform various processes such as replacement processing and restoration processing.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-184233 Summary of the Invention

[0006] Furthermore, while volatile memory has been commonly used in semiconductor memory devices (such as the aforementioned working memory) where data is frequently rewritten, magnetoresistive random access memory (MRAM), a type of rewritable nonvolatile memory, is currently under investigation as a replacement for this volatile memory. Thus, when using MRAM in a semiconductor memory device, it is possible to store not only data that is frequently rewritten, such as working data, but also data that is less frequently rewritten, such as setting data (programs and initialization data).

[0007] However, if a magnetoresistive memory is designed to ensure a high number of data rewrite cycles, the data retention period becomes shorter. Therefore, if a magnetoresistive memory is constructed to achieve a rewrite cycle comparable to that of volatile memory, it is easier to shorten the retention period of data that is less frequently rewritten, such as setup data. Consequently, when a device using a semiconductor memory device boots up, setup data must be loaded from another memory device, potentially increasing boot time and power consumption.

[0008] Therefore, when a magnetoresistive memory is used in a semiconductor storage device, it is desired to realize a technology capable of appropriately ensuring both the number of times data can be rewritten and the period during which data is retained.

[0009] The semiconductor storage device of the present invention has two types of magnetoresistive memories, namely a first magnetoresistive memory and a second magnetoresistive memory, which are accessed by an object logic unit as a logic unit. The object logic unit, the first magnetoresistive memory and the second magnetoresistive memory are formed on a semiconductor chip, and the coercive force of the first magnetoresistive memory is greater than the coercive force of the second magnetoresistive memory.

[0010] According to this structure, since the coercive force of the first magnetoresistive memory is greater than that of the second magnetoresistive memory, the coercive force of the second magnetoresistive memory can be reduced to ensure a greater number of data rewrite cycles, while the coercive force of the first magnetoresistive memory can be increased to ensure a longer data retention period. In other words, by using two types of magnetoresistive memory, two memory areas can be formed in the semiconductor memory device: one memory area with a greater number of data rewrite cycles formed by the second magnetoresistive memory, and the other memory area with a longer data retention period formed by the first magnetoresistive memory. Furthermore, this structure can realize a semiconductor chip in which the target logic unit can access both memory areas.

[0011] As described above, according to the above configuration, when a magnetoresistive memory is used in a semiconductor storage device, the number of data rewritable times and the data retention period can be appropriately ensured.

[0012] Further features and advantages of the semiconductor memory device will become apparent from the following description of embodiments illustrated with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a block diagram showing a schematic configuration of an example of a semiconductor chip.

[0014] Figure 2 This is a block diagram showing a schematic configuration of an example of a functional module.

[0015] Figure 3 It is a perspective view showing a schematic structure of an example of a semiconductor memory device.

[0016] Figure 4 This is a diagram showing an example of the arrangement relationship between a semiconductor memory device and an object logic unit. DETAILED DESCRIPTION

[0017] An embodiment of a semiconductor memory device will be described with reference to the accompanying drawings. In this embodiment, a case where the semiconductor memory device is used as a register (register file) will be described as an example.

[0018] The semiconductor memory device 20 is a memory device formed on the semiconductor chip 1. Therefore, the semiconductor memory device 20 (for example, memory cells constituting the semiconductor memory device 20 and a rewrite circuit for rewriting data in the memory cells) is formed using a semiconductor material.

[0019] exist Figure 1 An example of a semiconductor chip 1 having a semiconductor memory device 20 is shown in the figure. The semiconductor chip 1 is, for example, a SoC (System on a Chip). The semiconductor chip 1 has a plurality of circuits (semiconductor integrated circuits) integrated on a single chip. Circuits constituting a logic unit 40 described later and circuits constituting a semiconductor memory device 20 (memory unit) are formed in the semiconductor chip 1. Circuits constituting other functional units (for example, an analog unit) may also be formed in the semiconductor chip 1. The plurality of circuits possessed by the semiconductor chip 1 are formed on a semiconductor substrate (a semiconductor die such as a silicon die) built into the semiconductor chip 1. For example, the semiconductor chip 1 has a single semiconductor substrate, and all the circuits possessed by the semiconductor chip 1 can be configured to be formed on the single semiconductor substrate.

[0020] like Figure 1 As shown, the semiconductor chip 1 has a plurality of functional modules 10 interconnected via an internal bus 12. In addition, the semiconductor chip 1 has a processor 11 such as a CPU (Central Processing Unit), and the processor 11 is connected to each functional module 10 via an internal bus 12. Each functional module 10 functions as, for example, a peripheral logic unit that implements peripheral functions (support functions, etc.) of the processor 11, or functions as an interface unit that exchanges data or signals between the semiconductor chip 1 and an external device 2 (a device provided outside the semiconductor chip 1). The external device 2 is, for example, a storage device, a sensor, etc. provided outside the semiconductor chip 1. In Figure 1 In the illustrated example, some of the plurality of functional modules 10 are functional modules 10 for exchanging data or signals with the external device 2 .

[0021] The functional module 10 and the processor 11 each have a logic unit 40. The logic unit 40 has a logic circuit (logic circuit) and performs processing (calculation processing, conversion processing, etc.) using the logic circuit. Figure 2As shown, in this embodiment, the semiconductor memory device 20 is a semiconductor memory device attached to the functional module 10 and is accessed via the logic unit 40 included in the functional module 10. That is, if a logic unit 40 accessing the semiconductor memory device 20 is referred to as a target logic unit 41, then in this embodiment, the target logic unit 41 is a logic unit 40 included in the functional module 10. In this embodiment, the semiconductor memory device 20 functions as a register of the functional module 10 having the target logic unit 41, and the target logic unit 41 (specifically, the arithmetic circuit 50 described later) operates based on the data stored in the semiconductor memory device 20.

[0022] exist Figure 2 An example of a functional module 10 having an object logic unit 41 is shown in FIG. Figure 2 Functional modules 10 other than the functional modules 10 shown are referred to as other functional modules 10. Figure 2 As shown, the target logic unit 41 includes an arithmetic circuit 50 and a first circuit 51. The arithmetic circuit 50 is configured to perform arithmetic processing according to an operating program. The operating program for operating the arithmetic circuit 50 is stored in the semiconductor memory device 20 (specifically, the first magnetoresistive memory 21 described later).

[0023] The first circuit 51 is connected to the internal bus 12 and the semiconductor memory device 20, and is configured to control data transfer between the semiconductor memory device 20 and other functional modules 10 or the processor 11 via the internal bus 12. In other words, the first circuit 51 functions as an internal bus control unit. An address bus for specifying addresses within the semiconductor memory device 20 and a data bus for exchanging data are formed between the first circuit 51 and the semiconductor memory device 20. The first circuit 51 is configured to read and write data at specified addresses.

[0024] Figure 2 The functional module 10 shown is a functional module for exchanging signals with the external device 2. The object logic unit 41 includes a second circuit 52. The second circuit 52 is connected to the arithmetic circuit 50 and is also connected to the external device 2 via an external bus. The second circuit 52 is a control circuit that functions as an external signal control unit. The second circuit 52 is configured to convert data input from the arithmetic circuit 50 into signals and output them to the external device 2, and to convert signals input from the external device 2 into data and output them to the arithmetic circuit 50. Alternatively, the second circuit 52 may be configured to only output signals from the second circuit 52 to the external device 2 or input signals from the external device 2 to the second circuit 52.

[0025] like Figure 2As shown, the semiconductor memory device 20 has two types of magnetoresistive memories, namely, a first magnetoresistive memory 21 and a second magnetoresistive memory 22, which are accessed by the object logic unit 41. Magnetoresistive random access memory (MRAM) is a non-volatile memory that uses magnetic tunnel junctions as memory cells 30. Figure 3 As schematically shown, a memory cell 30 (magnetic tunnel junction) constituting a magnetoresistive memory has a structure in which a second layer 32, which is an insulating layer, is sandwiched between two ferromagnetic layers, a first layer 31 and a third layer 33. The ferromagnetic layers are formed using, for example, a ferromagnetic semiconductor material.

[0026] One of the first layer 31 and the third layer 33 is a fixed layer with fixed magnetization, while the other is a free layer with variable magnetization. By changing the magnetization direction of the free layer, the resistance of the memory cell 30 (magnetic tunnel junction) is switched, allowing the memory cell 30 to store one bit of information. The memory cells 30 are arranged in an array (a two-dimensional array) on a plane perpendicular to the thickness direction D of the semiconductor chip 1. Although detailed description is omitted, the rewrite circuit for rewriting data in the memory cells 30 is configured to select the memory cell 30 to be rewritten using transistors (cell selection transistors).

[0027] like Figure 3 and Figure 4 As shown schematically, the object logic unit 41, the first magnetoresistive memory 21, and the second magnetoresistive memory 22 are formed in a semiconductor chip 1. That is, the first magnetoresistive memory 21 and the second magnetoresistive memory 22 are embedded MRAM. Among them, the object logic unit 41, the first magnetoresistive memory 21, and the second magnetoresistive memory 22 are mixed in the same semiconductor substrate (semiconductor grain (die)). Specifically, the first magnetoresistive memory 21 and the second magnetoresistive memory 22 are integrally formed on the surface side D1 (surface side) relative to the object logic unit 41. In other words, the object logic unit 41 is formed on the back side D2 (inner side) of the first magnetoresistive memory 21 and the second magnetoresistive memory 22 in the semiconductor chip 1. Among them, the surface side D1 is one side in the thickness direction D (the side on which each element is formed relative to the semiconductor substrate), and the back side D2 is the other side in the thickness direction D (the side opposite to the surface side D1).

[0028] The coercive force of the first magnetoresistive memory 21 is greater than the coercive force of the second magnetoresistive memory 22. Specifically, the coercive force of the memory cell 30 constituting the first magnetoresistive memory 21 (specifically, the coercive force of the free layer) is greater than the coercive force of the memory cell 30 constituting the second magnetoresistive memory 22 (specifically, the coercive force of the free layer). In this embodiment, the volume of the memory cell 30 constituting the first magnetoresistive memory 21 is made larger than the volume of the memory cell 30 constituting the second magnetoresistive memory 22, thereby making the coercive force of the memory cell 30 constituting the first magnetoresistive memory 21 greater than the coercive force of the memory cell 30 constituting the second magnetoresistive memory 22. The volume of the memory cell 30 can be, for example, the total volume of the first layer 31, the second layer 32, and the third layer 33.

[0029] As an example of a structure in which the volume of the memory cells 30 constituting the first magnetoresistive memory 21 is larger than the volume of the memory cells 30 constituting the second magnetoresistive memory 22, the area of ​​the memory cells 30 constituting the first magnetoresistive memory 21 (the area as viewed along the thickness direction D, the same shall apply hereinafter) can be larger than the area of ​​the memory cells 30 constituting the second magnetoresistive memory 22. In this case, since the thickness of the first layer 31, the thickness of the second layer 32, and the thickness of the third layer 33 can be shared by the first magnetoresistive memory 21 and the second magnetoresistive memory 22, it is possible to suppress the complication of the manufacturing process caused by forming two types of magnetoresistive memories on the semiconductor chip 1.

[0030] As described above, since the coercive force of the first magnetoresistive memory 21 is greater than that of the second magnetoresistive memory 22, the coercive force of the second magnetoresistive memory 22 can be reduced to ensure a greater number of data rewrites, while the coercive force of the first magnetoresistive memory 21 can be increased to ensure a longer data retention period. In other words, as memory areas accessible by the target logic unit 41, two types of memory areas can be formed on the semiconductor chip 1: one is a memory area with a greater number of data rewrites formed by the second magnetoresistive memory 22, and the other is a memory area with a longer data retention period formed by the first magnetoresistive memory 21.

[0031] Since the first magnetoresistive memory 21 has a long data retention period, from the perspective of shortening the startup time of the device using the semiconductor chip 1, it is preferable to store data required by the object logic unit 41 when the device is started in the first magnetoresistive memory 21. From this perspective, in this embodiment, setting data is stored in the first magnetoresistive memory 21. The setting data stored in the first magnetoresistive memory 21 includes the operation program of the object logic unit 41 (specifically, the operation circuit 50). The setting data stored in the first magnetoresistive memory 21 may also include other data, for example, initial setting data of the object logic unit 41 (specifically, the operation circuit 50) or data including constants (control constants, etc.) used for operations in the object logic unit 41 (specifically, the operation circuit 50).

[0032] On the other hand, since the second magnetoresistive memory 22 has a large number of data rewritable times, from the perspective of extending the life of the semiconductor memory device 20, it is preferable to store data that is rewritten more frequently in the second magnetoresistive memory 22. From this perspective, in this embodiment, working data is stored in the second magnetoresistive memory 22. The working data stored in the second magnetoresistive memory 22 includes the calculation results of the object logic unit 41 (specifically, the operation circuit 50). The working data stored in the second magnetoresistive memory 22 may also include other data, for example, input data input to the object logic unit 41 (specifically, the operation circuit 50) or output data output from the object logic unit 41 (specifically, the operation circuit 50).

[0033] like Figure 4 As shown schematically, in this embodiment, the second magnetoresistive memory 22 is arranged closer to the arithmetic circuit 50 than the first magnetoresistive memory 21. In this embodiment, as described above, since working data is stored in the second magnetoresistive memory 22, the second magnetoresistive memory 22 exchanges data with the arithmetic circuit 50 more frequently than the first magnetoresistive memory 21. Therefore, by arranging the second magnetoresistive memory 22, which frequently exchanges data with the arithmetic circuit 50, near the arithmetic circuit 50, the length of the wiring path between the arithmetic circuit 50 and the second magnetoresistive memory 22 can be kept short. As a result, the length of the clock tree 60 used to supply clock signals to various components can be kept short, thereby reducing power consumption.

[0034] For example, by configuring at least a portion of the second magnetoresistive memory 22 at a position overlapping with the operation circuit 50 when viewed along the thickness direction D, and configuring at least a portion of the first magnetoresistive memory 21 at a position overlapping with the first circuit 51 or the second circuit 52 when viewed from this direction, a structure in which the second magnetoresistive memory 22 is configured at a position closer to the operation circuit 50 than the first magnetoresistive memory 21 can be achieved.

[0035] (Other embodiments)

[0036] Next, other embodiments of the semiconductor memory device will be described.

[0037] (1) In the above embodiment, the semiconductor memory device 20 is described as an example in which it is used as a register (register file). However, the present invention is not limited to this configuration, and the semiconductor memory device 20 may be used as a storage device other than a register.

[0038] For example, the semiconductor memory device 20 can be configured to be used as a cache for the processor 11. In this case, the target logic unit 41 is the logic unit 40 included in the processor 11. Furthermore, the first magnetoresistive memory 21 stores the tags (addresses) of cached data blocks, and the second magnetoresistive memory 22 stores the contents of the cached data blocks. That is, the first magnetoresistive memory 21 is a tag array (address array), and the second magnetoresistive memory 22 is a data array. Furthermore, the processor 11 may be a GPU (Graphics Processing Unit) or the like in addition to a CPU.

[0039] Furthermore, for example, the semiconductor memory device 20 may be configured to be used as a memory device connected to the processor 11 via the internal bus 12. In this case, the target logic unit 41 is the logic unit 40 included in the processor 11. Furthermore, the memory area formed by the first magnetoresistive memory 21 is used as a program area, and the memory area formed by the second magnetoresistive memory 22 is used as a data area.

[0040] (2) In the above embodiment, the coercive force of the first magnetoresistive memory 21 is made larger than the coercive force of the second magnetoresistive memory 22 by making the volume of the memory cells 30 constituting the first magnetoresistive memory 21 larger than the volume of the memory cells 30 constituting the second magnetoresistive memory 22. However, the present invention is not limited to such a structure. The coercive force of the first magnetoresistive memory 21 may be made larger than the coercive force of the second magnetoresistive memory 22 by making at least one of the structure and material of the memory cells 30 constituting the first magnetoresistive memory 21 and the memory cells 30 constituting the second magnetoresistive memory 22 different. In this case, unlike the above embodiment, the volume of the memory cells 30 constituting the first magnetoresistive memory 21 may be smaller than the volume of the memory cells 30 constituting the second magnetoresistive memory 22.

[0041] (3) In the above embodiment, the second magnetoresistive memory 22 is arranged closer to the arithmetic circuit 50 than the first magnetoresistive memory 21. However, the present invention is not limited to this configuration. For example, a configuration in which the first magnetoresistive memory 21 is arranged closer to the arithmetic circuit 50 than the second magnetoresistive memory 22 may be employed.

[0042] (4) In addition, the structures disclosed in each of the above-mentioned embodiments can also be combined with the structures disclosed in other embodiments (including combinations of the embodiments described as other embodiments) as long as no contradiction arises. With respect to other structures, the embodiments disclosed in this specification are merely illustrative in all respects. Therefore, various changes can be appropriately made within the scope of the present invention.

[0043] (Overview of the above embodiment)

[0044] Hereinafter, an overview of the semiconductor memory device described above will be described.

[0045] A semiconductor memory device (20) includes two types of magnetoresistive memories, namely, a first magnetoresistive memory (21) and a second magnetoresistive memory (22), which are accessed by an object logic unit (41) serving as a logic unit (40). The object logic unit (41), the first magnetoresistive memory (21), and the second magnetoresistive memory (22) are formed on a semiconductor chip (1). The coercive force of the first magnetoresistive memory (21) is greater than the coercive force of the second magnetoresistive memory (22).

[0046] According to this structure, since the coercive force of the first magnetoresistive memory (21) is greater than the coercive force of the second magnetoresistive memory (22), the coercive force of the second magnetoresistive memory (22) can be reduced to ensure a greater number of data rewrites, and the coercive force of the first magnetoresistive memory (21) can be increased to ensure a longer data retention period. That is, by using two types of magnetoresistive memories (21, 22), two types of memory areas can be formed in the semiconductor memory device (20): one is a memory area with a greater number of data rewrites formed by the second magnetoresistive memory (22), and the other is a memory area with a longer data retention period formed by the first magnetoresistive memory (21). Furthermore, according to the above structure, a semiconductor chip (1) can be realized in which the object logic unit (41) can access these two types of memory areas.

[0047] As described above, according to the above configuration, when a magnetoresistive memory is used in a semiconductor storage device (20), both the number of data rewritable times and the data retention period can be appropriately ensured.

[0048] Preferably, the volume of the memory unit (30) constituting the first magnetoresistive memory (21) is larger than the volume of the memory unit (30) constituting the second magnetoresistive memory (22).

[0049] According to this structure, by sharing the structure or material between the first magnetoresistive memory (21) and the second magnetoresistive memory (22) and making the volumes of the memory cells (30) different, the coercive force of the first magnetoresistive memory (21) can be made greater than the coercive force of the second magnetoresistive memory (22). Therefore, compared with a case where the structure or material of the first magnetoresistive memory (21) and the second magnetoresistive memory (22) need to be different, the manufacturing cost of the semiconductor chip (1) can be reduced.

[0050] In addition, preferably, setting data including an action program of the object logic unit (41) is stored in the first magnetoresistive memory (21), and working data including a calculation result of the object logic unit (41) is stored in the second magnetoresistive memory (22).

[0051] According to this structure, by storing setting data in the first magnetoresistive memory (21) having a longer data retention period, the need to write the setting data into the first magnetoresistive memory (21) when starting up a device using the semiconductor chip (1) can be substantially eliminated, thereby shortening the startup time and reducing the power consumption required for such writing. In addition, according to the above structure, by storing working data that is rewritten more frequently in the second magnetoresistive memory (22) having a larger number of data rewrites, the life of the semiconductor memory device (20) can also be appropriately ensured.

[0052] Furthermore, although the data retention period is shorter than that of the first magnetoresistive memory (21), the second magnetoresistive memory (22) can also retain data for a certain period. Therefore, when the device using the semiconductor chip (1) stores working data in the second magnetoresistive memory (22) when starting up, the startup time can be further shortened by using this working data.

[0053] As described above, in a structure in which the setting data is stored in the first magnetoresistive memory (21) and the working data is stored in the second magnetoresistive memory (22), preferably, the object logic unit (41) has an operation circuit (50) for performing operation processing according to the action program, and the second magnetoresistive memory (22) is configured at a position closer to the operation circuit (50) than the first magnetoresistive memory (21).

[0054] When setting data is stored in the first magnetoresistive memory (21) and working data is stored in the second magnetoresistive memory (22), the second magnetoresistive memory (22) exchanges data with the operation circuit (50) more frequently than the first magnetoresistive memory (21). According to the above structure, by arranging the second magnetoresistive memory (22) that frequently exchanges data with the operation circuit (50) near the operation circuit (50), the length of the wiring path between the operation circuit (50) and the second magnetoresistive memory (22) can be kept short, thereby achieving a reduction in power consumption.

[0055] The semiconductor memory device of the present invention only needs to achieve at least one of the above-mentioned effects.

[0056] Description of reference numerals:

[0057] 1. Semiconductor Chip

[0058] 20 Semiconductor storage devices

[0059] 21 First Magnetoresistive Memory

[0060] 22 Second magnetoresistive memory

[0061] 30 memory cells

[0062] 40 Logic Department

[0063] 41 Object Logic

[0064] 50 Operational Circuit

Claims

1. A semiconductor memory device, wherein: There are two types of magnetoresistive memories, namely a first magnetoresistive memory and a second magnetoresistive memory, which are accessed by a target logic unit as one logic unit. The object logic unit, the first magnetoresistive memory, and the second magnetoresistive memory are formed on one semiconductor chip. The coercive force of the first magnetoresistive memory is greater than the coercive force of the second magnetoresistive memory, The first magnetoresistive memory stores setting data including an operating program of the object logic unit. The second magnetoresistive memory stores working data including a calculation result of the object logic unit. The object logic unit includes an arithmetic circuit that performs arithmetic processing according to the operation program. The second magnetoresistive memory is arranged closer to the operation circuit than the first magnetoresistive memory. The first magnetoresistive memory and the second magnetoresistive memory are arranged on one side in the thickness direction of the semiconductor chip, that is, on the surface side, relative to the target logic unit. At least a portion of the second magnetoresistive memory is arranged at a position overlapping with the arithmetic circuit when viewed in the thickness direction.

2. The semiconductor memory device according to claim 1, wherein The volume of the memory cells constituting the first magnetoresistive memory is larger than the volume of the memory cells constituting the second magnetoresistive memory.

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