A synchronous chopper circuit of a current source and a method for improving analog-to-digital conversion accuracy thereof

Abstract

The present invention discloses a current source synchronous chopper circuit and a method for improving analog-to-digital conversion accuracy, and relates to the technical field of synchronous chopping of an excitation current source. The current source synchronous chopper circuit comprises a first current source, a second current source, a first chopping switch Φ1, a second chopping switch Φ2, a clock generator, an oversampling analog-to-digital converter, and a frequency reduction filter. The present invention reduces noise in a resistance temperature detector through synchronous chopping technology, reduces mismatch and drift mismatch in an excitation current source, and improves measurement accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of synchronous chopping of an excitation current source, and in particular to a current source synchronous chopping circuit and a method for improving analog-to-digital conversion accuracy thereof. Background Art

[0002] Resistance temperature detectors (2-wire, 3-wire or 4-wire) are widely used in temperature measurement systems. They generate a voltage signal related to resistance through an excitation current source, which is converted into a digital signal by an analog-to-digital converter for temperature measurement. The performance of the excitation current source plays an important role in the overall accuracy of the temperature measurement value (such as temperature resolution, time drift, and repeatability). Therefore, the measurement system needs to be robust enough to overcome external interference from the environment.

[0003] Figure 1 A block diagram of a known 3-wire resistance temperature detector oversampling analog-to-digital conversion circuit is given, the circuit comprising: an oversampling analog-to-digital converter, a clock generator, a frequency reduction filter, two matched current sources, a 3-wire resistance temperature detector, and a low drift reference resistor. Two matched current sources (IDAC1 and IDAC2) are used to cancel the first lead resistance R lead1 and the second lead resistor R lead2 The first excitation current flows through the reference resistor R REF and the RTD resistor R RTD , the second excitation current passes through the lead resistance R lead2 The voltage generated by the lead resistance R lead1 The resulting voltages cancel and the voltage across the reference resistor can be used as the reference voltage REF(±) for the oversampling ADC.

[0004] V REF =(I IDAC1 +I IDAC2 )xR REF

[0005] V IN1 =I IDAC1 x(R RTD +R lead1 )-I IDAC2 xR lead2

[0006] ADC = V IN1 / V REF =(I IDAC1 xR RTD +I IDAC1 xR lead1 -I IDAC2 xR lead2 ) / ((I IDAC1 +IIDAC2 )xR REF )

[0007] In reality, there is always a mismatch between the two current sources. Due to the mismatch, the error caused by the lead resistance cannot be completely eliminated, and the noise and drift mismatch of the two current sources further affect the accuracy of the final measurement of the analog-to-digital converter.

[0008] In order to solve the above problems, technicians perform a first round of conversion on the input voltage using a pair of matched current sources through an oversampling analog-to-digital converter. After obtaining the first set of analog-to-digital converter conversion data, the polarity of the current source is swapped; another round of conversion is performed on the input voltage using the current source with swapped polarity through the oversampling analog-to-digital converter to obtain the second set of analog-to-digital converter conversion data. The addition of these two conversion results can eliminate the mismatch associated with the current source. Since the polarity swap frequency is equal to the analog-to-digital converter conversion frequency, two complete stable conversion cycles are required, so there is a significant time delay in generating the final result, which is unacceptable for high-precision measurements, especially when using one analog-to-digital converter to measure multiple resistance temperature detectors. In addition, although the analog-to-digital converter is set to a low speed to achieve accurate measurement, the current source accuracy, mismatch and noise will fluctuate significantly during the two polarity swaps. The polarity swap process has no or little effect on reducing low-frequency 1 / f noise, which fundamentally limits the performance of high-precision analog-to-digital converters. Summary of the invention

[0009] In view of the problems existing in the prior art, the present invention provides a current source synchronous chopper circuit and a method for improving analog-to-digital conversion accuracy thereof, which reduces the noise in the resistance temperature detector, reduces the mismatch and drift mismatch in the excitation current source, and improves the measurement accuracy through the synchronous chopping technology.

[0010] To achieve the above object, the present invention adopts the following technical solution: a current source synchronous chopper circuit, comprising:

[0011] (1) a pair of matched current sources consisting of a first current source and a second current source;

[0012] (2) a first chopping switch and a second chopping switch are coupled to the outputs of the first current source and the second current source; the first chopping switch and the second chopping switch cooperate to perform chopping switching between the first connection and the second connection; in the first connection, the first port is coupled to the first current source, and the second port is coupled to the second current source; in the second connection, the first port is coupled to the second current source, and the second port is coupled to the first current source;

[0013] (3) a clock generator coupled to the first chopping switch and the second chopping switch, the clock generator outputting a chopping clock signal to control the chopping switching between the first chopping switch and the second chopping switch;

[0014] (4) an input port of an oversampling analog-to-digital converter is coupled to a first chopping switch and a second chopping switch, converting an input voltage between the first port and the second port into a digital signal, and performing one or more chopping switches in one analog-to-digital converter conversion cycle;

[0015] (5) A frequency reduction filter is coupled to the output of the oversampling analog-to-digital converter. The frequency reduction filter receives a digital signal input and generates a filter output.

[0016] Furthermore, the clock generator outputs a chopping clock signal to control the chopping exchange between the first chopping switch and the second chopping switch; the clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter; the clock generator generates a filter clock signal, and the frequency reduction filter receives the filter clock signal.

[0017] Furthermore, the frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; and the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

[0018] Furthermore, it is characterized in that: the output currents of the two matching current sources are regulated by a reference voltage.

[0019] Furthermore, the present invention also provides a current source synchronous chopper circuit, comprising:

[0020] (1) a pair of matched current sources consisting of a first current source and a second current source;

[0021] (2) A resistance temperature detector includes a resistor that is affected by the ambient temperature;

[0022] (3) a first chopping switch and a second chopping switch are coupled to the outputs of the first current source and the second current source; the first chopping switch and the second chopping switch cooperate to perform chopping switching between the first connection and the second connection; in the first connection, the first port of the resistance temperature detector is coupled to the first current source, and the second port is coupled to the second current source; in the second connection, the first port of the resistance temperature detector is coupled to the second current source, and the second port is coupled to the first current source;

[0023] (4) an input port of an oversampling analog-to-digital converter is coupled to a first chopping switch and a second chopping switch, converting an input voltage between the first port and the second port into a digital signal, and performing one or more chopping switches in one analog-to-digital converter conversion cycle;

[0024] (5) A frequency reduction filter is coupled to the output of the oversampling analog-to-digital converter. The frequency reduction filter receives a digital signal input and generates a corresponding filter output affected by the ambient temperature.

[0025] Furthermore, a reference resistor is coupled to the resistance temperature detector, and two ends of the reference resistor are coupled to an oversampling analog-to-digital converter.

[0026] Further, two ends of the reference resistor are coupled to a first filtering protection circuit, and the first filtering protection circuit is coupled to an oversampling analog-to-digital converter.

[0027] Furthermore, the first port and the second port of the resistance temperature detector are coupled to the oversampling analog-to-digital converter through a second filtering protection circuit, and the first port and the second port of the resistance temperature detector are coupled to the first chopper switch and the second chopper switch through a third filtering protection circuit.

[0028] Furthermore, the clock generator outputs a chopping clock signal to control the chopping exchange between the first chopping switch and the second chopping switch; the clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter; the clock generator generates a filter clock signal, and the frequency reduction filter receives the filter clock signal.

[0029] Furthermore, the frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; and the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

[0030] Furthermore, the two matched current sources are derived from a reference source of an oversampling analog-to-digital converter.

[0031] Furthermore, the present invention also provides a method for improving analog-to-digital conversion accuracy using a current source synchronous chopper circuit, which specifically includes the following steps:

[0032] (1) A clock signal is outputted by a fixed frequency oscillator or by a frequency shaping pseudo-random clock signal generator circuit;

[0033] (2) a matching current source composed of a first current source and a second current source outputs a pair of load currents to a first chopping switch Φ1 and a second chopping switch Φ2, wherein the first chopping switch Φ1 and the second chopping switch Φ2 control the chopping exchange between the first chopping switch Φ1 and the second chopping switch Φ2 through a clock signal;

[0034] (3) converting an input voltage between the first port and the second port into a digital signal by an oversampling analog-to-digital converter, including performing one or more chopping exchanges within one analog-to-digital converter conversion cycle;

[0035] (4) The down-conversion filter generates a filter output based on the digital signal output by the over-sampling analog-to-digital converter.

[0036] Furthermore, the frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; and the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

[0037] Compared with the prior art, the present invention has the following beneficial effects: in the current source synchronous chopper circuit of the present invention, by coupling the first chopper switch Φ1 and the second chopper switch Φ2 to the output ends of the first current source IDAC1 and the second current source IDAC2, any mismatch between the two current sources can be eliminated or minimized: the outputs from the first current source IDAC1 and the second current source IDAC2 are chopped, and equal measurements are performed before and after the chopping, and the measurement results are post-processed, so as to reduce the mismatch between the current sources; and the time delay between the polarity exchange of the first chopper switch Φ1 and the second chopper switch Φ2 is very short, and the influence of environmental variables can be ignored. At the same time, since the chopping clock signal generated by the clock generator is much faster than the data frequency output by the oversampling analog-to-digital converter, it is ensured that the oversampling analog-to-digital converter can perform continuous analog-to-digital conversion operations. The current source synchronous chopper circuit of the present invention is applied to a resistance temperature detector to achieve accurate temperature measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A block diagram of an oversampling analog-to-digital conversion circuit of a known 3-wire resistance temperature detector is provided;

[0039] Figure 2 A block diagram of a current source synchronous chopper circuit provided by the present invention;

[0040] Figure 3 A block diagram of a current source synchronous chopper circuit provided by the present invention and including a resistance temperature detector;

[0041] Figure 4 A block diagram of a current source synchronous chopper circuit provided by the present invention and including a resistance temperature detector and a reference resistor;

[0042] Figure 5 A block diagram of a current source synchronous chopper circuit provided by the present invention and including a resistance temperature detector and a filter protection circuit;

[0043] Figure 6The low frequency 1 / f noise of the known oversampling analog-to-digital converter is shifted to a high frequency position diagram relative to the synchronous chopper according to the present invention;

[0044] Figure 7 A signal diagram for generating an over-sampled clock signal, a chopped clock signal, and a filter clock signal for a clock generator;

[0045] Figure 8 A flow chart of improving the conversion accuracy of an oversampling analog-to-digital converter by a current source synchronous chopper circuit provided by the present invention. DETAILED DESCRIPTION

[0046] The invention will be described below with reference to particular embodiments and drawings but the invention is not limited thereto but only by the claims.The drawings described are at least schematic and non-limiting.

[0047] The present invention is not limited in its application to the details of the construction and arrangement of the components set forth in the following description or illustrated in the accompanying drawings. The present invention may have other embodiments and may be implemented or carried out in a variety of ways. In addition, the words and terms used in the patent are for descriptive purposes and should not be considered as limiting. The use of "including", "comprising", "having", "containing", "involving" and their variations herein means including the items listed below and their equivalents and additional items. In addition, the terms "first", "second", "third", etc. in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a sequential order or a chronological order.

[0048] Figure 2: is a block diagram of a current source synchronous chopper circuit 60 provided by the present invention, the current source synchronous chopper circuit comprises: a matching current source 13 composed of a first current source IDAC1 and a second current source IDAC2, two chopper switches 22 composed of a first chopper switch Φ1 and a second chopper switch Φ2, a clock generator 12, an oversampling analog-to-digital converter 11, and a frequency reduction filter 14, the first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the output ends of the first current source IDAC1 and the second current source IDAC2, specifically, the first port of the first chopper switch Φ1 is coupled to the first current source IDAC1, the second port of the first chopper switch Φ1 is coupled to the second current source IDAC2, and the first port of the second chopper switch Φ2 is coupled to the second current source IDAC1. AC2, the second port of the second chopping switch Φ2 is coupled to the first current source IDAC1, and the first chopping switch Φ1 and the second chopping switch Φ2 work together to minimize the mismatch between the first current source IDAC1 and the second current source IDAC2: chopping is performed on the outputs from the first current source IDAC1 and the second current source IDAC2, and an equal number of measurements are performed before and after the chopping, and the measurement results are post-processed to reduce the mismatch between the current sources; and the time delay between the polarity exchange of the first chopping switch Φ1 and the second chopping switch Φ2 is very short, and the influence of environmental variables can be ignored; at the same time, by increasing the frequency of the first chopping switch Φ1 and the second chopping switch Φ2, the influence of low-frequency 1 / f noise from the two current sources can be reduced. The first chopping switch Φ1 and the second chopping switch Φ2 are coupled to the input port of the oversampling analog-to-digital converter, the clock generator is coupled to the first chopping switch Φ1 and the second chopping switch Φ2, the clock generator is coupled to the oversampling analog-to-digital converter and the frequency reduction filter 14 respectively, and the frequency reduction filter 14 is coupled to the output end of the oversampling analog-to-digital converter. The chopping clock signal output by the clock generator 12 controls the chopping exchange between the first chopping switch Φ1 and the second chopping switch Φ2, and the polarity is exchanged at least once or multiple times within a conversion cycle of the oversampling analog-to-digital converter 11. In the present invention, the clock generator 12 adopts a frequency-shaping pseudo-random clock signal generator using a fixed frequency oscillator or a pseudo-random sequence generator. The clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter 11; the clock generator generates a filter clock signal, and the frequency reduction filter 14 receives the filter clock signal, such as Figure 7The signal diagram of the oversampling clock signal, the chopping clock signal, and the filter clock signal generated by the clock generator. For the oversampling analog-to-digital converter 11, the typical oversampling frequency 71 is usually much higher than the output data rate 73, and is an integer multiple of the output data rate. The frequency of the chopping clock signal 72 is one or more times the frequency of the output data of the frequency reduction filter 14; the frequency of the oversampling clock 71 is an even multiple of the frequency of the chopping clock signal 72, which ensures that the oversampling analog-to-digital converter 11 can perform continuous analog-to-digital conversion operations. The mismatch and low-frequency noise between the first current source IDAC1 and the second current source IDAC2 can be filtered out in the frequency reduction filter 14 through the clock generator 12. The frequency reduction filter 14 in the present invention is coupled to the output end of the oversampling analog-to-digital converter 11. The oversampling analog-to-digital converter 11 converts the input voltage signal into a digital signal. The frequency reduction filter 14 is a low-pass filter 52, which is used to filter the high-frequency noise 61 in the digital signal and output the result of the digital-to-analog conversion.

[0049] like Figure 6 In the existing oversampling analog-to-digital conversion circuit, the low-frequency 1 / f noise 51 in the frequency reduction filter 14 can be completely passed, while in the power supply synchronous chopper circuit of the present invention, the low-frequency 1 / f noise 51 is transferred to the high-frequency position 53 through the first chopper switch Φ1 and the second chopper switch Φ2, and the center frequency is the frequency of the first chopper switch Φ1 and the second chopper switch Φ2, witnessing the suppression of several orders of magnitude of the low-frequency 1 / f noise 51.

[0050] Figure 3The current source synchronous chopper circuit provided by the present invention includes a block diagram of a resistance temperature detector. The current source synchronous chopper circuit includes: a resistance temperature detector 15, a matching current source 13 composed of a first current source IDAC1 and a second current source IDAC2, two chopper switches 22 composed of a first chopper switch Φ1 and a second chopper switch Φ2, a clock generator 12, an oversampling analog-to-digital converter 11, and a frequency reduction filter 14. The resistance temperature detector involved in the present invention is a 2-wire, 3-wire or 4-wire resistance temperature detector. The first port of the resistance temperature detector 15 is respectively coupled to the first port of the first chopper switch Φ1 and the first port of the second chopper switch Φ2, and the second port of the resistance temperature detector 15 is respectively coupled to the second port of the first chopper switch Φ1 and the second port of the second chopper switch Φ2; the first port and the second port of the resistance temperature detector 15 are coupled to the oversampling analog-to-digital converter 11, and the oversampling analog-to-digital converter 11 converts the voltage input from the first port and the second port of the resistance temperature detector 15 into a digital signal. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the output ends of the first current source IDAC1 and the second current source IDAC2. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the input port of the oversampling analog-to-digital converter 11. The clock generator 12 is coupled to the first chopper switch Φ1 and the second chopper switch Φ2. The clock generator 12 is coupled to the oversampling analog-to-digital converter 11 and the down-frequency filter 14 respectively. In the present invention, the clock generator 12 adopts a frequency-shaping pseudo-random clock signal generator using a fixed frequency oscillator or including a pseudo-random sequence generator. The clock generator 12 generates an oversampling clock signal for oversampling the oversampling analog-to-digital converter 11; the clock generator 12 generates a filter clock signal, and the down-frequency filter 14 receives the filter clock signal. The frequency of the chopper clock signal 72 is one or more times the frequency of the output data of the down-frequency filter 14; the frequency of the oversampling clock 71 is an even multiple of the frequency of the chopper clock signal 72, thereby ensuring that the oversampling analog-to-digital converter 11 can perform continuous analog-to-digital conversion operations. The down-conversion filter 14 in the present invention is coupled to the output end of the oversampling analog-to-digital converter 11. The oversampling analog-to-digital converter 11 converts the input voltage signal into a digital signal. The down-conversion filter 14 is a low-pass filter 52, which is used to filter the high-frequency noise 61 in the digital signal and output the result of the digital-to-analog conversion.

[0051] In one analog-to-digital conversion cycle, the first chopper Φ1 chopper and the second chopper Φ2 perform at least one chopping polarity exchange (i.e., Phase 1 and Phase 2), chopping the inputs from the two matching current sources, performing equal measurements before and after chopping, and post-processing the measurement results to reduce the mismatch between the current sources. Specifically, an excitation current passes through the reference resistor R REF and the resistance temperature detector resistance R RTD, another excitation current passes through the lead resistance R lead2 The voltage generated by the lead resistance R lead1 The resulting voltage cancels out.

[0052] Phase 1: V IN1 =I IDAC1 x(R RTD +R lead1 )-I IDAC2 xR lead2；

[0053] Phase 2:V IN2 =I IDAC2 x(R RTD +R lead1 )-I IDAC1 xR lead2；

[0054] ADC=(V IN1 / V REF +V IN2 / V REF ) / 2=(V IN1 +V IN2 ) / (2xV REF )=(R RTD +R lead1 -R lead2 )x(I IDAC1 +I IDAC2 ) / (2xV REF )

[0055] It can be seen from the above formula that the synchronous chopping technology eliminates the error term of the mismatch between the two current sources. At the same time, the frequencies of the first chopping switch Φ1 and the second chopping switch Φ2 can reduce the influence of the low-frequency 1 / f noise on the first current source IDAC1 and the second current source IDAC2, thereby improving the temperature measurement accuracy of the resistance temperature detector.

[0056] like Figure 4The current source synchronous chopper circuit provided by the present invention includes a block diagram of a resistance temperature detector and a reference resistor. The current source synchronous chopper circuit includes: a resistance temperature detector 15, a matching current source 13 composed of a first current source IDAC1 and a second current source IDAC2, two chopper switches 22 composed of a first chopper switch Φ1 and a second chopper switch Φ2, a clock generator 12, an oversampling analog-to-digital converter 11, and a frequency reduction filter 14. The resistance temperature detector involved in the present invention is a 2-wire, 3-wire or 4-wire resistance temperature detector. The first port of the resistance temperature detector 15 is respectively coupled to the first port of the first chopper switch Φ1 and the first port of the second chopper switch Φ2, and the second port of the resistance temperature detector 15 is respectively coupled to the second port of the first chopper switch Φ1 and the second port of the second chopper switch Φ2; the first port and the second port of the resistance temperature detector 15 are coupled to the oversampling analog-to-digital converter 11, and the oversampling analog-to-digital converter 11 converts the voltage input from the first port and the second port of the resistance temperature detector 15 into a digital signal. The resistance temperature detector 15 is coupled to a reference resistor 16, and both ends of the reference resistor 16 are coupled to the oversampling analog-to-digital converter 11. In practical applications, both ends of the reference resistor 16 can be coupled to a first filtering protection circuit 43, and the first filtering protection circuit 43 is coupled to the oversampling analog-to-digital converter 11. The voltage generated on the reference resistor 16 is used as the reference voltage REF(±) of the oversampling analog-to-digital converter. The reference resistor 16 needs to have a low temperature drift, otherwise it will affect the temperature drift of the final conversion result of the oversampling analog-to-digital converter 11. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the output ends of the first current source IDAC1 and the second current source IDAC2. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the input port of the oversampling analog-to-digital converter 11. The clock generator 12 is coupled to the first chopper switch Φ1 and the second chopper switch Φ2. The clock generator 12 is coupled to the oversampling analog-to-digital converter 11 and the down-frequency filter 14 respectively. In the present invention, the clock generator 12 adopts a frequency-shaping pseudo-random clock signal generator using a fixed frequency oscillator or including a pseudo-random sequence generator. The clock generator 12 generates an oversampling clock signal for oversampling the oversampling analog-to-digital converter 11; the clock generator 12 generates a filter clock signal, and the down-frequency filter 14 receives the filter clock signal. The frequency of the chopper clock signal 72 is one or more times the frequency of the output data of the down-frequency filter 14; the frequency of the oversampling clock 71 is an even multiple of the frequency of the chopper clock signal 72, thereby ensuring that the oversampling analog-to-digital converter 11 can perform continuous analog-to-digital conversion operations. The down-conversion filter 14 in the present invention is coupled to the output end of the oversampling analog-to-digital converter 11. The oversampling analog-to-digital converter 11 converts the input voltage signal into a digital signal. The down-conversion filter 14 is a low-pass filter 52, which is used to filter the high-frequency noise 61 in the digital signal and output the result of the digital-to-analog conversion.

[0057] In one analog-to-digital conversion cycle, the first chopper Φ1 chopper and the second chopper Φ2 perform at least one chopping polarity exchange (i.e., Phase 1 and Phase 2), chopping the inputs from the two matching current sources, performing equal measurements before and after chopping, and post-processing the measurement results to reduce the mismatch between the current sources. Specifically, an excitation current passes through the reference resistor R REF and the resistance temperature detector resistance R RTD , another excitation current passes through the lead resistance R lead2 The voltage generated by the lead resistance R lead1 The resulting voltage cancels out.

[0058] Phase 1: V IN1 =I IDAC1 x(R RTD +R lead1 )-I IDAC2 xR lead2； V REF =(I IDAC1 +I IDAC2 )xR REF

[0059] Phase 2:V IN2 =I IDAC2 x(R RTD +R lead1 )-I IDAC1 xR lead2； V REF =(I IDAC1 +I IDAC2 )xR REF

[0060] ADC=(V IN1 / V REF +V IN2 / V REF ) / 2=(V IN1 +V IN2 ) / (2xV REF )=(R RTD +R lead1 -R lead2 ) / (2xR REF )

[0061] It can be seen from the above formula that the synchronous chopping technology eliminates the mismatch error term of the first current source IDAC1 and the second current source IDAC2, thereby improving the temperature measurement accuracy of the resistance temperature detector.

[0062] like Figure 5The invention provides a current source synchronous chopper circuit and a block diagram of a resistance temperature detector and a filter protection circuit. The current source synchronous chopper circuit includes: a resistance temperature detector 15, a matching current source 13 composed of a first current source IDAC1 and a second current source IDAC2, two chopper switches 22 composed of a first chopper switch Φ1 and a second chopper switch Φ2, a clock generator 12, an oversampling analog-to-digital converter 11, and a frequency reduction filter 14. The resistance temperature detector involved in the invention is a 2-wire, 3-wire or 4-wire resistance temperature detector. The first port of the resistance temperature detector 15 is respectively coupled to the first port of the first chopper switch Φ1 and the first port of the second chopper switch Φ2, and the second port of the resistance temperature detector 15 is respectively coupled to the second port of the first chopper switch Φ1 and the second port of the second chopper switch Φ2; the first port and the second port of the resistance temperature detector 15 are coupled to the oversampling analog-to-digital converter 11, and the oversampling analog-to-digital converter 11 converts the voltage input from the first port and the second port of the resistance temperature detector 15 into a digital signal. The first port and the second port of the resistance temperature detector 15 are coupled to the oversampling analog-to-digital converter 11 through the second filtering protection circuit 42, and the first port and the second port of the resistance temperature detector 15 are coupled to the first chopping switch Φ1 and the second chopping switch Φ2 through the third filtering protection circuit 41. The reference resistor 16 is coupled to the resistance temperature detector 15, and both ends of the reference resistor 16 are coupled to the oversampling analog-to-digital converter 11. In practical applications, both ends of the reference resistor 16 can be coupled to the first filtering protection circuit 43, and the first filtering protection circuit 43 is coupled to the oversampling analog-to-digital converter 11. The voltage generated on the reference resistor 16 is used as the reference voltage REF (±) of the oversampling analog-to-digital converter. The reference resistor 16 needs to have a low temperature drift, otherwise it will affect the temperature drift of the final conversion result of the oversampling analog-to-digital converter 11. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the output ends of the first current source IDAC1 and the second current source IDAC2. The first chopper switch Φ1 and the second chopper switch Φ2 are coupled to the input port of the oversampling analog-to-digital converter 11. The clock generator 12 is coupled to the first chopper switch Φ1 and the second chopper switch Φ2. The clock generator 12 is coupled to the oversampling analog-to-digital converter 11 and the down-frequency filter 14 respectively. In the present invention, the clock generator 12 adopts a frequency-shaping pseudo-random clock signal generator using a fixed frequency oscillator or including a pseudo-random sequence generator. The clock generator 12 generates an oversampling clock signal for oversampling the oversampling analog-to-digital converter 11; the clock generator 12 generates a filter clock signal, and the down-frequency filter 14 receives the filter clock signal. The frequency of the chopper clock signal 72 is one or more times the frequency of the output data of the down-frequency filter 14; the frequency of the oversampling clock 71 is an even multiple of the frequency of the chopper clock signal 72, thereby ensuring that the oversampling analog-to-digital converter 11 can perform continuous analog-to-digital conversion operations.The down-conversion filter 14 in the present invention is coupled to the output end of the oversampling analog-to-digital converter 11. The oversampling analog-to-digital converter 11 converts the input voltage signal into a digital signal. The down-conversion filter 14 is a low-pass filter 52, which is used to filter the high-frequency noise 61 in the digital signal and output the result of the digital-to-analog conversion.

[0063] In one analog-to-digital conversion cycle, the first chopper Φ1 chopper and the second chopper Φ2 perform at least one chopping polarity exchange (i.e., Phase 1 and Phase 2), chopping the inputs from the two matching current sources, performing equal measurements before and after chopping, and post-processing the measurement results to reduce the mismatch between the current sources. Specifically, an excitation current passes through the reference resistor R REF and the resistance temperature detector resistance R RTD , another excitation current passes through the lead resistance R lead2 The voltage generated by the lead resistance R lead1 The resulting voltages cancel each other out, thereby improving the temperature measurement accuracy of the RTD.

[0064] like Figure 8 The present invention provides a flow chart of improving the conversion accuracy of an oversampling analog-to-digital converter by using a current source synchronous chopper circuit. The conversion accuracy of the sampling analog-to-digital converter is improved by 80% in the current source synchronous chopper circuit 60 provided by the present invention. The method includes:

[0065] (1) A clock signal is outputted by a fixed frequency oscillator or a frequency shaping pseudo-random clock signal generator circuit; the clock signal includes a chopper clock signal and a down-conversion filter clock signal;

[0066] (2) A matching current source 13 composed of a first current source IDAC1 and a second current source IDAC2 outputs a pair of load currents to a first chopping switch Φ1 and a second chopping switch Φ2. The first chopping switch Φ1 and the second chopping switch Φ2 control the chopping exchange between the first chopping switch Φ1 and the second chopping switch Φ2 through a clock signal; specifically, one or more chopping exchanges are performed within one analog-to-digital converter conversion cycle, and the frequency of the chopping clock signal 72 is one or more times the frequency of the data output by the down-conversion filter 14; the frequency of the oversampling clock 71 is an even multiple of the frequency of the chopping clock signal 72, and the chopping clock is synchronized with the oversampling clock and the clock of the down-conversion filter, so that the mismatch between the current sources and the low-frequency noise can be filtered out in the down-conversion filter 14.

[0067] (3) the input voltage 61 between the first port and the second port is converted into a digital signal by the oversampling analog-to-digital converter 11;

[0068] (4) The down-conversion filter 14 generates a filter output according to the digital signal output by the over-sampling analog-to-digital converter 11.

[0069] Therefore, the present invention provides a system and method for improving the conversion accuracy of an oversampling analog-to-digital converter with a synchronous chopper. For example, the technology of the present invention can reduce the mismatch and drift mismatch in the excitation current source by using synchronous chopping technology. According to some embodiments, these technologies can use a synchronous chopper to move the low-frequency 1 / f noise in the low-frequency noise to the high-frequency region. The technology of the present invention is crucial for certain applications that are interested in faster conversion speeds (and / or shorter conversion times) in the system. The technology of the present invention can be easily implemented in hardware or software. Exemplary embodiments of the present invention are presented for the purpose of illustration and description, and are not intended to be exhaustive or limit the present invention to the precise form disclosed. The present invention is intended to be modified, various changes and replacements. In some cases, the features of the present invention can be adopted without the corresponding use of other features described. Without departing from the scope of the present invention, many modifications and changes can be made according to the above teachings. The scope of the present invention is intended not to be limited by this detailed description, but by the appended claims.

Claims

1. A current source synchronous chopper circuit, characterized in that: include: (1) a pair of matched current sources consisting of a first current source and a second current source; (2) a first chopping switch and a second chopping switch are coupled to the outputs of the first current source and the second current source; the first chopping switch and the second chopping switch cooperate to perform chopping switching between the first connection and the second connection; In a first connection, the first port is coupled to a first current source, and the second port is coupled to a second current source; In the second connection, the first port is coupled to the second current source, and the second port is coupled to the first current source; (3) a clock generator coupled to the first chopping switch and the second chopping switch, the clock generator outputting a chopping clock signal to control the chopping switching between the first chopping switch and the second chopping switch; (4) an input port of an oversampling analog-to-digital converter is coupled to a first chopping switch and a second chopping switch, converting an input voltage between the first port and the second port into a digital signal, and performing one or more chopping switches in one analog-to-digital converter conversion cycle; (5) A frequency reduction filter is coupled to the output of the oversampling analog-to-digital converter. The frequency reduction filter receives a digital signal input and generates a filter output.

2. The current source synchronous chopper circuit according to claim 1, characterized in that: The clock generator outputs a chopping clock signal to control the chopping exchange between the first chopping switch and the second chopping switch; the clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter; the clock generator generates a filter clock signal, and the frequency reduction filter receives the filter clock signal.

3. The current source synchronous chopper circuit according to claim 2, characterized in that: The frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

4. The current source synchronous chopper circuit according to claim 1, characterized in that: Features: The output currents of the two matched current sources are regulated by a reference voltage.

5. A current source synchronous chopper circuit, characterized in that: include: (1) a pair of matched current sources consisting of a first current source and a second current source; (2) A resistance temperature detector includes a resistor that is affected by the ambient temperature; (3) a first chopping switch and a second chopping switch are coupled to the outputs of the first current source and the second current source; the first chopping switch and the second chopping switch cooperate to perform chopping switching between the first connection and the second connection; In a first connection, a first port of the resistance temperature detector is coupled to a first current source, and a second port of the resistance temperature detector is coupled to a second current source; In the second connection, the first port of the resistance temperature detector is coupled to the second current source, and the second port is coupled to the first current source; (4) an input port of an oversampling analog-to-digital converter is coupled to a first chopping switch and a second chopping switch, converting an input voltage between the first port and the second port into a digital signal, and performing one or more chopping switches in one analog-to-digital converter conversion cycle; (5) A frequency reduction filter is coupled to the output of the oversampling analog-to-digital converter. The frequency reduction filter receives a digital signal input and generates a corresponding filter output affected by the ambient temperature.

6. The current source synchronous chopper circuit according to claim 5, characterized in that: A reference resistor is coupled to the resistance temperature detector, and two ends of the reference resistor are coupled to an over-sampling analog-to-digital converter.

7. The current source synchronous chopper circuit according to claim 6, characterized in that: Two ends of the reference resistor are coupled to a first filtering protection circuit, and the first filtering protection circuit is coupled to an oversampling analog-to-digital converter.

8. The current source synchronous chopper circuit according to claim 6, characterized in that: The first port and the second port of the resistance temperature detector are coupled to the oversampling analog-to-digital converter through a second filtering protection circuit, and the first port and the second port of the resistance temperature detector are coupled to the first chopping switch and the second chopping switch through a third filtering protection circuit.

9. The current source synchronous chopper circuit according to claim 5, characterized in that: The clock generator outputs a chopping clock signal to control the chopping exchange between the first chopping switch and the second chopping switch; the clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter; the clock generator generates a filter clock signal, and the frequency reduction filter receives the filter clock signal.

10. The current source synchronous chopper circuit according to claim 9, characterized in that: The frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

11. The current source synchronous chopper circuit according to claim 5, characterized in that: Two matched current sources are derived from the reference source of an oversampled analog-to-digital converter.

12. A method for improving analog-to-digital conversion accuracy using the current source synchronous chopper circuit according to any one of claims 1 to 11, characterized in that: The specific steps include: (1) A clock signal is outputted by a fixed frequency oscillator or by a frequency shaping pseudo-random clock signal generator circuit; (2) a matching current source composed of a first current source and a second current source outputs a pair of load currents to a first chopping switch Φ1 and a second chopping switch Φ2, wherein the first chopping switch Φ1 and the second chopping switch Φ2 control the chopping exchange between the first chopping switch Φ1 and the second chopping switch Φ2 through a clock signal; (3) converting an input voltage between the first port and the second port into a digital signal by an oversampling analog-to-digital converter, including performing one or more chopping exchanges within one analog-to-digital converter conversion cycle; (4) The down-conversion filter generates a filter output based on the digital signal output by the over-sampling analog-to-digital converter.

13. The method for improving analog-to-digital conversion accuracy using a current source synchronous chopper circuit according to claim 12, characterized in that: The frequency of the chopping clock signal is one or more times the frequency of the output data of the frequency reduction filter; the clock generator generates an oversampling clock signal for oversampling of the oversampling analog-to-digital converter, and the frequency of the oversampling clock signal is an even multiple of the frequency of the chopping clock signal.

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