Batch welding of different components in power modules

Abstract

A batch soldering method includes: providing a first passive device; arranging the first passive device on a first metal region of a substrate, wherein an area of ​​a first solder material is between the first passive device and the substrate; providing a semiconductor die; arranging the semiconductor die on a second metal region of the substrate, wherein an area of ​​a second solder material is between the semiconductor die and the substrate; and performing a common soldering step, the common soldering step simultaneously forming a first solder joint from the area of ​​the first solder material and a second solder joint from the area of ​​the second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases are formed within the second solder joint, each of the one or more intermetallic phases having a melting point higher than the second solder material and the soldering temperature.

Description

Background Art

[0001] Semiconductor power modules are common in a wide variety of applications (e.g., automotive, industrial motor drives, AC-DC power supplies, etc.) Semiconductor power modules typically include multiple power semiconductor devices (e.g., power MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), etc.) and other elements (e.g., passive components, bonding wires, etc.) mounted on a common substrate.

[0002] In general, it is desirable to produce semiconductor power modules using batch processing techniques in which various processing steps, such as die attach, wire bonding, contact formation, etc., are performed in parallel. In this way, the time and expense associated with producing the modules are advantageously reduced. However, the welding of the various components of the power module is not very suitable for batch processing. This is because certain welded joints may require high tensile strength and low ductility, while other welded joints may require the opposite properties. Conventional batch welding techniques cannot individually customize welded joints to meet these requirements. Summary of the invention

[0003] According to an embodiment of a method for batch soldering, the method includes: providing a first passive device including a metal bonding surface; arranging the first passive device on a first metal region of a substrate, wherein an area of ​​a first solder material is between the metal bonding surface of the first passive device and the substrate; providing a semiconductor die including a metal bonding surface; arranging the semiconductor die on a second metal region of the substrate, wherein an area of ​​a second solder material is between the metal bonding surface of the semiconductor die and the substrate; and performing a common soldering step, the common soldering step simultaneously forming a first solder joint from the area of ​​the first solder material and a second solder joint from the area of ​​the second solder material. The common soldering step is performed at a soldering temperature so that the area of ​​the second solder material melts and reacts with the metal bonding surface of the semiconductor die and the second metal region of the substrate to form one or more intermetallic phases within the second solder joint. Each of the one or more intermetallic phases has a melting point higher than the second solder material and the soldering temperature.

[0004] Either alone or in combination, the common soldering step is performed without applying mechanical pressure to the first passive device and without applying mechanical pressure to the semiconductor die.

[0005] Either alone or in combination, the minimum thickness of the first weld joint is greater than the maximum thickness of the second weld joint.

[0006] The first solder material alone or in combination comprises a solder paste having a reflow temperature equal to or lower than a soldering temperature, the method further comprises stencil printing the solder paste on the first metal region of the substrate, and the arrangement of the first passive component comprises placing the first passive component on the stencil printed solder paste.

[0007] Alone or in combination, the second solder material comprises a solder preform, and the method further comprises applying the solder preform to the metal bonding surface of the semiconductor die or the second metal region of the substrate before placing the semiconductor die on the second metal region of the substrate.

[0008] Individually or in combination, the minimum thickness of the stencil printed solder paste before the common soldering step is equal to or greater than 30 μm, and the maximum thickness of the solder preform before the common soldering step is equal to or less than 10 μm.

[0009] Alone or in combination, the second solder material comprises liquid solder or solder paste, before the common soldering step, the maximum thickness of the second solder material is greater than the maximum thickness of the second solder joint, and, during the common soldering step, the thickness of the second solder material decreases to reach the maximum thickness of the second solder joint.

[0010] Alone or in combination, the intermetallic phase ratio of the second weld joint is at least 60%.

[0011] Alone or in combination, the intermetallic bridge ratio of the second weld joint is at least 50%.

[0012] Alone or in combination, the first passive component is a mechanical connector.

[0013] Either alone or in combination, the substrate includes a ceramic layer and a metal layer disposed on the ceramic layer, and wherein the first metal region and the second metal region are physically isolated portions of the metal layer.

[0014] Alone or in combination, the first passive device is a discrete electrical component.

[0015] Alternatively or in combination, the semiconductor die includes a second metal bonding surface facing away from the first metal bonding surface, and the method further includes: forming another area of ​​solder material on the second metal bonding surface of the semiconductor die; and forming a third solder joint between the second metal bonding surface and the bonding element from the other area of ​​solder material. The common soldering step simultaneously forms the first solder joint, the second solder joint, and the third solder joint.

[0016] According to an embodiment of the electronic device, the electronic device includes: a substrate, the substrate includes a first metal region and a second metal region; a first passive device, the first passive device includes a metal bonding surface and is arranged on the substrate, wherein the metal bonding surface of the first passive device faces the first metal region; a semiconductor die, the semiconductor die includes a metal bonding surface and is arranged on the substrate, wherein the metal bonding surface of the semiconductor die faces the second metal region; a first welding joint, the first welding joint is between the first metal region and the metal bonding surface of the first passive device; and a second welding joint, the second welding joint is between the second metal region and the metal bonding surface of the semiconductor die. The minimum thickness of the first welding joint is greater than the maximum thickness of the second welding joint.

[0017] Individually or in combination, the minimum thickness of the first weld joint is equal to or greater than 30 μm, and the maximum thickness of the second weld joint is equal to or less than 10 μm.

[0018] Either alone or in combination, the first weld joint has a greater ductility than the second weld joint, and wherein the second weld joint has a greater tensile strength than the first weld joint.

[0019] Either alone or in combination, the intermetallic phase ratio of the second weld joint is at least 60%, and the intermetallic phase ratio of the first weld joint is no greater than 40%.

[0020] Either alone or in combination, the intermetallic bridge ratio of the second weld joint is at least 50%, and the intermetallic bridge ratio of the first weld joint is no more than 20%.

[0021] Either alone or in combination, the substrate includes a ceramic layer and a metal layer disposed on the ceramic layer, the first metal region and the second metal region are physically isolated portions of the metal layer, and the first passive device is a mechanical connector.

[0022] Alternatively or in combination, the electronic device further comprises a passive electrical component and a third solder joint electrically connecting the passive electrical component to the metal layer, and the third solder joint has the same composition and thickness as the first solder joint or the second solder joint.

[0023] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The elements in the drawings are not necessarily drawn to scale relative to each other. Similar reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and described in detail in the following description.

[0025] Figure 1A block diagram of a batch welding method according to an embodiment is shown.

[0026] Figure 2 A to Figure 2 F shows Figure 1 Corresponding cross-sectional views of an embodiment of blocks 102 to 130 of the method.

[0027] Figure 3 A first solder joint between a first passive device and a first metal region and a second solder joint between a semiconductor die and a second metal region are shown in accordance with an embodiment.

[0028] Figure 4 A semiconductor die is shown having two solder joints formed on opposite sides of the die in accordance with an embodiment.

[0029] Figure 5 It is shown that according to the embodiment, there is Figure 1 The intermetallic phase in the weld joint is formed by the diffusion welding process.

[0030] Figure 6 Mechanical connectors and soldering locations of semiconductor dies on a substrate for a power semiconductor module according to an embodiment are shown.

[0031] Figure 7 A power semiconductor module according to an embodiment is shown. DETAILED DESCRIPTION

[0032] Embodiments of a batch soldering process are described herein, in which a plurality of solder joints having different characteristics are simultaneously formed by a common soldering step. According to the technology, a first passive device (e.g., a mechanical connector) is arranged on a first metal region of a substrate, wherein an area of ​​a first solder material (e.g., a solder paste) is disposed between a metal bonding surface of the first passive device and the substrate. In addition, a semiconductor die (e.g., a power transistor) is disposed on a second metal region of the substrate, wherein an area of ​​a second solder material is disposed between a metal bonding surface of the semiconductor die and the substrate. A common soldering step is performed, which simultaneously forms a first solder joint between the first passive device and the substrate and a second solder joint between the semiconductor die and the substrate. The common soldering step forms a first solder joint by standard solder reflow, and forms a second solder joint by diffusion soldering. Thus, the second solder joint includes an intermetallic phase having a melting point higher than the soldering temperature. By using a relatively thin (eg 10 μm or less) layer for the second solder material and a relatively thick (eg 30 μm or more) layer for the first solder material, two different solder reactions can be performed in one common soldering step.

[0033] Figure 1An embodiment of a batch soldering technique is shown. The batch soldering technique includes a front end (FE) processing step (block 100), a stencil printing step (block 102), a passive component pick and place step (block 104), a solder preform cutting and placement step (block 110), a die pick and place step (block 120), a soldering step (block 130), a front side contact formation step (block 140), and a back end (BE) processing step (block 150). Unless inconsistent with the embodiments described herein, Figure 1 Each of the process steps can be performed according to any embodiment of the corresponding identified process steps described in U.S. patent application 16 / 679,408, filed on November 11, 2019, belonging to Heinrich (the contents of which are incorporated herein by reference in their entirety) and U.S. patent application 16 / 679,414, filed on November 11, 2019, belonging to Trunov (the contents of which are incorporated herein by reference in their entirety).

[0034] Figure 2 A shows an area of ​​a first solder material 202 formed on a first metal region 204 of a substrate. In general, the substrate can be any substrate for physically supporting and / or electrically connecting electronic components, wherein the first metal region 204 is a conductive surface of the substrate. For example, in one embodiment, the substrate is a lead frame or a metal clip, as the case may be, and the first metal region 204 is a conductive surface of the lead frame or clip. For example, the lead frame or the metal clip may include Cu, Ni and / or Ag. In another embodiment, the substrate includes an electrically insulating layer (e.g., a ceramic layer) and a metal layer attached to a base layer, wherein the first metal region 204 is part of the metal layer. In one embodiment, the metal layer comprises and / or is plated with Cu, Ni, Ag, Au, Pd, Pt, NiV, NiP, NiNiP, NiP / Pd, Ni / Au, NiP / Pd / Au or NiP / Pd / AuAg. Other types of metals / metal alloys and substrates may also be used.

[0035] In general, the first solder material 202 can be any of a variety of well-known solder materials, including lead-based solder and lead-free solder. In an embodiment, the first solder material 202 is a soft solder paste. For example, the first solder material 202 can include a tin-based lead-free solder paste, which includes, for example, Sn / Ag / Cu solder paste, Sn / Ag solder paste, Sn / Ag / Sb solder paste, Sn / Sb solder paste, Sn / Cu solder paste, etc. In a specific example, the first solder material 202 is a Sn / Sb solder paste, and its Sb concentration is between 2% and 10%, for example, as in SnSb5 and SnSb8.

[0036] The area of ​​the first solder material 202 can be formed using a stencil printing technique. According to this technique, a metal stencil 206 (e.g., stainless steel or nickel) is formed to include openings in the expected geometry of the solder joint. The stencil 206 is placed on the first metal area 204 of the substrate, and the openings are filled with solder paste, for example, using a scraper. The stencil 206 can then be removed. In other embodiments, the area of ​​the first solder material 202 can be formed using a grid, dispense, or any other suitable method for applying solder paste.

[0037] According to an embodiment, the region of the first solder material 202 is formed to have a minimum thickness of 30 μm or more. The minimum thickness is measured in a vertical direction perpendicular to the substrate surface.

[0038] Figure 2 B shows a first passive device 208 arranged on the first metal region 204 of the substrate, wherein the region of the first solder material 202 is between the metal bonding surface 210 of the first passive device 208 and the substrate. In the depicted embodiment, the first passive device 208 is configured as a pin rivet, which is a specific type of mechanical connector with a hollow core, the size of which is determined to be insertably received by the corresponding protrusion. More generally, the first passive device 208 may include any solderable structure that does not include an active circuit. Examples of these passive devices include mechanical connectors such as pins, rivets, metal plates, etc. Other examples of these passive devices include discrete electrical components such as resistors, capacitors, inductors, diodes, etc. The metal bonding surface 210 of the first passive device 208 includes any surface that requires mechanical connection, electrical connection, or both. The first passive device 208 can be arranged to have a metal bonding surface 210 that, for example, uses a pick-and-place machine to interface with the region of the first solder material 202.

[0039] Figure 2C shows a first liquid 212 applied to a second metal region 214 of the substrate. In one embodiment, the first liquid 212 is a volatile, non-reactive liquid that provides surface tension for a subsequently deposited preform solder. The second metal region 214 can be a separate portion of the same metal layer or surface that includes the first metal region 204. For example, the second metal region 214 and the first metal region 204 can be separate surfaces of the same lead frame or metal clip. Alternatively, the second metal region 214 and the first metal region 204 can be portions of the same metal layer attached to an electrically insulating base layer. The first metal region 204 and the second metal region 214 can be physically isolated from each other (completely separated by an air gap), or can be separate portions of a continuous structure.

[0040] Figure 2 D shows an area of ​​second solder material 216 provided on the second metal region 214 of the substrate, wherein the first liquid 212 is disposed between the area of ​​second solder material 216 and the substrate. In the depicted embodiment, the area of ​​second solder material 216 is provided by a solder preform, i.e., a relatively rigid sheet of solder material pre-cut into a desired geometric shape (e.g., square, circular, ring, etc.). As part of the joining technique, the solder preform may be stamped or cut from a roll of preformed solder material, or may be a pre-cut preform, a pre-stamped preform, etc.

[0041] According to an embodiment, an ultra-thin solder preform is used to provide the area of ​​the second solder material 216. In this context, an "ultra-thin" solder preform refers to a solder preform having a maximum thickness of 15 μm. In various embodiments, the ultra-thin solder preform may have a maximum thickness of no more than 12 μm, 10 μm, 8 μm, 7 μm, or even less. The maximum thickness is measured in a vertical direction perpendicular to the substrate surface, wherein the solder preform is flush with the substrate.

[0042] Figure 2 E shows a second liquid 218 applied to the area of ​​the second solder material 216. In one embodiment, the second liquid 218 is a volatile, non-reactive liquid that holds the semiconductor die 222 in place on the solder preform by surface tension. The first liquid 212 and the second liquid 218 can be the same type or different types of liquids.

[0043] In an alternative embodiment, a solder preform is initially provided on the metal bonding surface 220 of the semiconductor die 222. In this case, after singulation, the solder preform is performed on the die locations of the semiconductor wafer or on the individual semiconductor dies 222. Figure 2 A- Figure 2C. Subsequently, semiconductor die 222 is placed on the second metal region 214 of the substrate, with the solder preform facing the substrate. Liquid may be inserted between the solder preform and the substrate to increase surface tension.

[0044] In another alternative embodiment, the area of ​​the second solder material 216 is initially applied as a liquid or paste. This can be done using stencil printing or other techniques. In this case, the initial thickness of the second solder material can be significantly higher, for example, on the order of 30 μm, 20 μm, etc. During the die placement and soldering process described below, the thickness of the liquid or paste is reduced to reach a target value for an effective diffusion soldering process, for example, no greater than 12 μm, 10 μm, 8 μm, 7 μm, or even less.

[0045] Figure 2 F shows a semiconductor die 222 arranged on the second metal region 214 of the substrate, wherein the region of the second solder material 216 is between the metal bonding surface 220 of the semiconductor die 222 and the substrate. According to an embodiment, the semiconductor die 222 is configured as a power transistor die, such as a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), a HEMT (high electron mobility transistor), etc. More generally, the semiconductor die 222 can be configured as a logic die, such as a gate driver, a microcontroller, a memory, etc., or can be configured as a passive die, such as an inductor or capacitor die, etc. The metal bonding surface 220 of the semiconductor die 222 can be a conductive bonding pad, which forms, for example, a load terminal, a control terminal, an I / O terminal, etc. The metal bonding surface 220 of the semiconductor die 222 may include Cu, Ni, Ag, Au, Pd, Pt, NiV, NiP, NiNiP, NiP / Pd, Ni / Au, NiP / Pd / Au, NiP / Pd / AuAg, NiV / Ag, NiV / Au, or NiSi / Ag, among others.

[0046] In general, the second solder material 216 may include any solder material suitable for diffusion soldering techniques, i.e., a soldering technique that produces an intermetallic phase having a melting point higher than the soldering temperature in the solder joint. The second solder material may have a lower melting point than the metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate. In one embodiment, the second solder material 216 includes Sn, Zn, In, Ga, Bi, Cd, or any alloy thereof. For example, the second solder material 216 may include Sn / Ag / Cu, Sn / Ag, Sn / Ag / Sb, Sn / Sb, Sn / Cu, or Au80 / Sn20.

[0047] Once the first passive device 208 and the semiconductor die 222 are arranged on the substrate, wherein the regions of the first solder material 202 and the regions of the second solder material 216, respectively, separate these components from the substrate, a joint soldering step is performed. The joint soldering step simultaneously forms the first solder joint 224 (at Figure 3 and forming a second solder joint 226 from an area of ​​the second solder material 216 (in Figure 3 That is, by a single application of heat to the assembly, the necessary reactions occur in both regions of the solder material 202, 216 to form the first solder joint 224 and the second solder joint 226.

[0048] The common soldering step is performed at a soldering temperature equal to or higher than the reflow temperature of the first solder material 202. As a result, the first solder material 202 melts and forms a metallurgical bond with the metal bonding surface 210 of the first passive component 208 and the first metal region 204 of the substrate in a known manner.

[0049] In addition, the common soldering step is performed at a soldering temperature such that regions of the second solder material 216 melt and react with the metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate to form one or more intermetallic phases within the second solder joint 226, wherein each of the one or more intermetallic phases has a melting point higher than the second solder material 216 and the soldering temperature.

[0050] The metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate may include the same or different metals / metal alloys. If the metal region joined by the second solder joint 226 includes the same metal or metal alloy as the second solder material 216, a single intermetallic phase is formed throughout the second solder joint 226. For example, if both the metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate include Cu or the same Cu-rich alloy, the Cu will be dissolved during the diffusion soldering process via the liquefied second solder material until a certain concentration is reached, at which point the joint solidifies. The resulting Cu-based intermetallic phase will not melt again at the soldering temperature of the diffusion soldering process. The same applies to other types of common die and substrate metallizations, such as Ni-rich alloys and Ag-rich alloys.

[0051] If the metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate include different metals / metal alloys, multiple intermetallic phases are formed throughout the solder joint. In either case, during the common soldering step, the second solder material 216 can react mostly or completely with the metal bonding surface 220 of the semiconductor die 222 and the second metal region 214 of the substrate, so that the second solder joint 226 has a high melting point phase throughout the second solder joint 226.

[0052] The process described above advantageously forms a first weld joint 224 by standard welding and a second weld joint 226 by diffusion welding simultaneously. In a typical diffusion welding process, mechanical pressure is used to achieve welding. For example, a movable press is typically used to apply mechanical pressure to the welding elements. However, the common welding step described herein is performed without applying mechanical pressure to any welding element (e.g., using a movable press). This is made possible by using ultra-thin solder for the second solder material 216. By maintaining the thickness of the second solder material below a certain value, for example, below 10 μm, the welding temperature of the common welding step can be set so that the solder preform melts and reacts, thereby forming the necessary intermetallic phase in the manner described above. In addition, the welding temperature of the common welding step is sufficient to reflow the first solder material, thereby enabling two weld joints to be formed without mechanical pressure.

[0053] In general, the soldering conditions (e.g., time and temperature) of the common soldering step may be selected to induce substantial reflow of the first solder material 202 and induce an intermetallic phase ratio of at least 50% in the second solder material 216. In an embodiment, this intermetallic phase ratio may be obtained by performing the common soldering step at a temperature between about 275° C. and 325° C. for a duration of no greater than about 180 seconds.

[0054] although Figure 2 A to Figure 2 F shows one passive device 208 bonded to the first metal region 204 of the substrate and one semiconductor die 222 bonded to the second metal region 214 of the substrate, but the technique can be a batch process, wherein multiple passive devices and / or multiple semiconductor dies are simultaneously soldered to the same substrate, bonded to separate substrates, or bonded to separate substrates in corresponding groups. In addition, the order of the steps is not limited to Figure 2 A to Figure 2F. More generally, any order of steps for arranging the first passive device 208 and the semiconductor die 222 on the substrate may be performed, wherein the first solder material 202 and the second solder material 216, respectively, separate these components from the substrate prior to a common soldering process. For example, placing the first passive device 208 on an area of ​​the first solder material 202 may occur after placing the semiconductor die 222 on an area of ​​the second solder material 216.

[0055] Figure 3 A particular view of first and second solder joints 224, 226 are shown respectively bonding first passive device 208 to first metal region 204 and semiconductor die 222 to second metal region 214. First and second solder joints 224, 226 have different physical properties.

[0056] The first difference in physical properties between the first weld joint and the second weld joint is the thickness of these weld joints. Specifically, the minimum thickness (T MIN ) is greater than the maximum thickness (T MAX For example, the first weld joint 224 may have a minimum thickness (T ) of about 50 μm, about 40 μm, about 30 μm, etc. MIN ), and the second weld joint 226 may have a maximum thickness (T MAX ). The thickness of the first solder joint 224 and the second solder joint 226 is related to the initial thickness of the first solder material 202 and the second solder material 216 before the common soldering step, but due to the melting of the solder materials and the resulting lateral expansion during the common soldering step, the thickness of the first solder joint 224 and the second solder joint 226 may be less than these initial values.

[0057] The second difference in physical properties between the first weld joint 224 and the second weld joint 226 is the amount of intermetallic phases in these weld joints. An intermetallic phase is a chemical compound composed of two different metals and having a crystal structure different from the elements that compose it. For example, in the case of a Sn-based solder material provided between Cu-based metal surfaces, the first weld joint 224 and the second weld joint 226 may include a CuSn intermetallic phase, which has different crystal properties and a higher melting point than the alloy CuSn or metallic Cu and metallic Sn.

[0058] According to an embodiment, the second weld joint 226 has a higher intermetallic phase ratio than the intermetallic phase ratio of the first weld joint 224. For example, the intermetallic phase ratio of the second weld joint 226 may be at least 50%, at least 60%, at least 70%, etc. The intermetallic phase ratio of the first weld joint 224 may be no greater than 40%, no greater than 20%, no greater than 10%, etc. The intermetallic phase ratio is measured along the cross-sectional thickness of the weld joint extending perpendicular to the joint surface, for example, Figure 3 The intermetallic phase ratio is the ratio between the area of ​​the intermetallic phase present in the weld joint along the cross-sectional thickness and the area of ​​the non-intermetallic phase comprising the solder material along the cross-sectional thickness.

[0059] According to an embodiment, the intermetallic bridge ratio of the second weld joint 226 is higher than the intermetallic bridge ratio of the first weld joint 224. For example, the intermetallic bridge ratio of the second weld joint 226 may be at least 50%, at least 60%, at least 70%, etc. The intermetallic bridge ratio of the first weld joint 224 may be no greater than 40%, no greater than 20%, no greater than 10%, etc. The intermetallic bridge ratio is measured along a single line within the weld joint and perpendicular to the thickness direction of the weld joint (i.e., parallel to the surface of the joined metal). The intermetallic bridge ratio is the ratio between the length of a single line extending through the intermetallic phase and the length of a single line extending through the non-intermetallic phase containing the solder material.

[0060] In general, in the formation of welded joints, there is a trade-off between ductility and tensile strength. That is, a welded joint formed with high ductility will have a low tensile strength, and vice versa. The difference in physical properties between the first welded joint 224 and the second welded joint 226 produces a preferred ductility and tensile strength for each welded joint. Specifically, due to the material composition and low metal-to-metal ratio of the first welded joint 224, the first welded joint 224 has a relatively high ductility and low tensile strength. This high ductility is particularly desirable for welded joints (e.g., pin rivets for press-fit connectors for anchoring power modules) that are subjected to significant mechanical stress. At the same time, due to the material composition and low metal-to-metal ratio of the second welded joint 226, the second welded joint 226 has a relatively low ductility and high tensile strength. This high tensile strength is particularly advantageous for welded joints that experience significant thermal loads during operation of the device. One example of such a solder joint is a load terminal connection (eg, source, drain, etc.) for the power semiconductor die 222 , which experiences significant heating during operation.

[0061] By appropriately tailoring various welding parameters, the ductility and tensile strength of the first weld joint 224 and the second weld joint 226 can be tailored to meet certain application requirements. Examples of these parameters include the thickness of the first solder material 202, the composition of the first solder material 202, the thickness of the second solder material 216, the composition of the second solder material 216, the time of the common welding step, the temperature of the common welding step, etc.

[0062] refer to Figure 4 , which shows an alternative embodiment in which an additional bonding element 228 is soldered to the upper side of the semiconductor die 222 by a common soldering step that forms a first solder joint 224 and a second solder joint 226. The semiconductor die 222 includes a second metal bonding surface 230 facing away from the first metal bonding surface 220. The second metal bonding surface 230 of the semiconductor die 222 can be a conductive bonding pad that forms a terminal of the die, such as a load terminal, a control terminal, an I / O terminal, etc. After the semiconductor die 222 is arranged on the second metal region 214 of the substrate, another solder material is applied to the exposed upper side of the semiconductor die 222 including the second metal bonding surface 230. The other solder material can include a solder paste having the same composition and / or thickness as the first solder material 202 described herein. Alternatively, the other solder material can include a preform solder having the same composition and / or thickness as the second solder material 216 described herein. In yet another embodiment, another solder material is different from the first solder material 202 and the second solder material 216, but has a reflow temperature lower than the soldering temperature of the common soldering step. In any of these examples, the common soldering step forms a third solder joint 232 between the second metal bonding surface 230 and the bonding element 228. As shown, the bonding element 228 is configured as a metal interconnect clip. More generally, the bonding partner can be any conductive structure, for example, a bonding wire, a ribbon, a heat sink, etc.

[0063] refer to Figure 5 , which depicts a cross-sectional view of a second solder joint 226 that can be formed according to the techniques described above, according to an embodiment. As can be seen, the second solder joint 226 includes a high density of intermetallic phases 234 and, therefore, has a high intermetallic phase ratio. As shown, the intermetallic phase ratio is about 60%. In addition, the intermetallic phase 234 is formed substantially over the entire thickness of the second solder joint 226. Therefore, the second solder joint 226 has an advantageous tensile strength and does not melt when the semiconductor die 222 is operated at a high temperature.

[0064] refer to Figure 6, which depicts an example of a batch soldering technique for soldering different components to a DBC substrate 300 of a power semiconductor module according to an embodiment. The DBC substrate 300 includes a ceramic layer 302 formed below a first metallization layer. The first metallization layer is structured to include a plurality of discrete and physically isolated bonding pads 304. Some of these bonding pads 304 provide locations 306 for first passive components. Some of these bonding pads 304 provide locations 310 for semiconductor dies. The group of semiconductor dies includes six power transistor dies and six corresponding gate driver dies. The batch soldering method described herein can be used to form an area of ​​a first solder material 202 in the location 306 for the first passive component and to form an area of ​​a second solder material 216 in the location 310 for the semiconductor die. After forming the solder material and placing the components, a common soldering step can be performed to form a first solder joint 224 for the passive component and a second solder joint 226 for the semiconductor die. Therefore, the technology described herein provides an efficient process with minimal expense compared to the technology of separately forming solder connections for passive components and active components. In addition, the technology can be integrated into a standard assembly line using standard equipment. After forming the solder joint, a bonding wire can be formed on the assembly to complete the necessary electrical connection between the semiconductor die and the keyboard pad 304 including the first passive component.

[0065] Alternatively, the batch welding technique can be used to form a third welding joint between another passive electrical component and the metal layer. For example, the passive electrical component can be a discrete capacitor. The position 312 for another passive electrical component can be located on the same or different bonding pad 304 as the first passive component. The batch welding method described herein is used to apply another solder material in the position 312 for another passive electrical component depicted. Another solder material can be formed according to any of the techniques for forming the first region of the solder material 202 or the second region of the solder material 216. Alternatively, another solder material with different thickness and / or composition can be used, as long as the other solder material is reflowed at the welding temperature of the common welding step. During the common welding step, the third welding joint can be formed simultaneously with the first welding joint 224 and the second welding joint 226. In an embodiment, the third welding joint has the same composition and thickness as the first welding joint 224 or the second welding joint 226. This configuration may be achieved by forming another solder material having the same composition and thickness as the first region of solder material 202 for the first solder joint 224 or the second region of solder material 216 for the second solder joint 226 , as the case may be.

[0066] refer to Figure 7, which shows a completed power semiconductor module 400. The power semiconductor module 400 includes a protective housing having a plurality of press-fit connectors 402 protruding from the housing. The press-fit connectors 402 are mechanically and electrically connected to pin rivets, which in turn are soldered to bonding pads of a DCB substrate. Due to the soldering techniques described herein, the connection can be formed with high ductility, which allows significant stress to be applied on the press-fit connectors 402. At the same time, the soldering techniques described herein provide a high tensile strength solder connection between the semiconductor die and the bonding pads within the power semiconductor module 400, which provides high reliability robustness.

[0067] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0068] As used herein, the terms "having", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0069] It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0070] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternatives and / or equivalent embodiments may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present invention is limited only by the claims and their equivalents.

Claims

1. A batch welding method comprising: providing a first passive device including a metal bonding surface; placing the first passive component on a first metal region of a substrate, wherein a region of a first solder material is between the metal bonding surface of the first passive component and the substrate; providing a semiconductor die including a metal bonding surface; placing the semiconductor die on a second metal region of the substrate, wherein a region of second solder material is between the metal bonding surface of the semiconductor die and the substrate; and performing a common soldering step which simultaneously forms a first solder joint from an area of ​​the first solder material and a second solder joint from an area of ​​the second solder material, wherein the common soldering step is performed at a soldering temperature such that a region of the second solder material melts and reacts with the metal bonding surface of the semiconductor die and the second metal region of the substrate to form one or more intermetallic phases within the second solder joint, each of the one or more intermetallic phases having a melting point higher than the second solder material and the soldering temperature, and wherein the second solder material is formed using a relatively thin layer and the first solder material is formed using a relatively thick layer, and wherein the common soldering step forms the first solder joint by reflow of the first solder material and forms the second solder joint by diffusion soldering.

2. The method according to claim 1, wherein: The common soldering step is performed without applying mechanical pressure to the first passive device and without applying mechanical pressure to the semiconductor die.

3. The method according to claim 1, wherein: The minimum thickness of the first weld joint is greater than the maximum thickness of the second weld joint.

4. The method according to claim 3, wherein: The first solder material comprises a solder paste having a reflow temperature equal to or lower than the soldering temperature, and wherein the method further comprises stencil printing the solder paste on the first metal area of ​​the substrate, and wherein the arrangement of the first passive component comprises placing the first passive component on the stencil printed solder paste.

5. The method according to claim 4, wherein: The second solder material comprises a solder preform, wherein the method further comprises applying the solder preform to the metal bonding surface of the semiconductor die or the second metal region of the substrate before placing the semiconductor die on the second metal region of the substrate.

6. The method according to claim 5, wherein: Before the common soldering step, a minimum thickness of the stencil-printed solder paste is equal to or greater than 30 μm, and wherein, before the common soldering step, a maximum thickness of the solder preform is equal to or less than 10 μm.

7. The method according to claim 4, wherein: The second solder material comprises liquid solder or solder paste, wherein, before the common soldering step, the maximum thickness of the second solder material is greater than the maximum thickness of the second solder joint, and wherein, during the common soldering step, the thickness of the second solder material decreases to reach the maximum thickness of the second solder joint.

8. The method according to claim 1, wherein: The second weld joint has an intermetallic phase ratio of at least 60%.

9. The method according to claim 1, wherein: The second weld joint has an intermetallic bridge ratio of at least 50%.

10. The method according to claim 1, wherein: The first passive component is a mechanical connector.

11. The method according to claim 1, wherein: The substrate includes a ceramic layer and a metal layer disposed on the ceramic layer, and wherein the first metal region and the second metal region are physically isolated portions of the metal layer.

12. The method according to claim 1, wherein: The first passive device is a discrete electrical component.

13. The method according to claim 1, wherein: The semiconductor die includes a second metal bonding surface facing away from the first metal bonding surface, and wherein the method further comprises: forming another region of solder material on the second metal bonding surface of the semiconductor die; and forming a third solder joint between the second metal joining surface and the joining element from another region of the solder material, Wherein, the common welding step simultaneously forms the first weld joint, the second weld joint and the third weld joint.

14. An electronic device comprising: a substrate comprising a first metal region and a second metal region; a first passive component, the first passive component comprising a metal bonding surface and arranged on the substrate, wherein the metal bonding surface of the first passive component faces the first metal region; a semiconductor die comprising a metal bonding surface and disposed on the substrate, wherein the metal bonding surface of the semiconductor die faces the second metal region; a first solder joint between the first metal region and the metal bonding surface of the first passive component; and a second solder joint between the second metal region and the metal bonding surface of the semiconductor die, Wherein a minimum thickness of the first solder joint is greater than a maximum thickness of the second solder joint, and wherein the first solder joint is formed by reflow of a first solder material and the second solder joint is formed by diffusion soldering.

15. The electronic device according to claim 14, wherein: The minimum thickness of the first weld joint is equal to or greater than 30 μm, and wherein the maximum thickness of the second weld joint is equal to or less than 10 μm.

16. The electronic device according to claim 14, wherein: The first weld joint has a greater ductility than the second weld joint, and wherein the second weld joint has a greater tensile strength than the first weld joint.

17. The electronic device according to claim 14, wherein: The second weld joint has an intermetallic phase ratio of at least 60%, and wherein the intermetallic phase ratio of the first weld joint is no greater than 40%.

18. The electronic device according to claim 14, wherein: The second weld joint has an intermetallic bridge ratio of at least 50%, and wherein the intermetallic bridge ratio of the first weld joint is no greater than 20%.

19. The electronic device according to claim 14, wherein: The substrate includes a ceramic layer and a metal layer disposed on the ceramic layer, wherein the first metal region and the second metal region are physically isolated portions of the metal layer, and wherein the first passive device is a mechanical connector.

20. The electronic device of claim 19, further comprising a passive electrical component and a third solder joint electrically connecting the passive electrical component to the metal layer, wherein The third weld joint has the same composition and thickness as the first weld joint or the second weld joint.

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