Apparatus and method for coupling multiple semiconductor devices

Abstract

Apparatus and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a coupling point at a middle semiconductor device of the group, and the signal is propagated away from the coupling point to other semiconductor devices of the group on different (e.g., opposite) signal paths. The load from the coupling point at the middle semiconductor device to the other semiconductor devices of the group may be more balanced than, for example, having a coupling point at a semiconductor device at the end of the group (e.g., the lowest semiconductor device of the stack, the highest semiconductor device of the stack, etc.) and providing the signal from the coupling point. A more balanced topology may reduce timing differences between the times when a signal arrives at each of the semiconductor devices.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and in particular to apparatus and methods for coupling multiple semiconductor devices. Background Art

[0002] In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dies vertically and coupling the dies using through-silicon (or through-substrate) vias (TSVs) and / or wire bonds. Therefore, 3D memory may also be referred to as "stacked memory". 3D memory may provide greater memory capacity and / or higher bandwidth with less area increase than non-3D memory. Example 3D memory devices include hybrid memory cubes (HMCs), high-bandwidth memories (HBMs), and master-slave memories (MSMs), each of which may include multiple dynamic random access memory (DRAM) dies coupled to each other in a stack.

[0003] The memory devices may be coupled to external circuits that provide command, address, and data signals to the stacked die to access the memory.The stacked die are typically coupled to the external circuits at the lowest height die with cascade junctions connecting up to the remaining die in the stack.

[0004] However, as memory speed increases, the delay between signals arriving at the lowest and highest die in the stack becomes non-negligible. Timing differences in arriving signals are typically accommodated by setting the operational timing of the memory device based on the worst case scenario, i.e., the signal arrival time at the highest die in the stack. This approach may result in reduced performance of the memory device. Additionally, as memory speed continues to increase, the timing difference in signal arrival time from the lowest die to the highest die in the stack may no longer be tolerable for desired system performance. Summary of the invention

[0005] According to one aspect of the present disclosure, an apparatus is disclosed. The apparatus includes: a plurality of memory devices, including a first, a second, and a third memory device, the first memory device including a first bonding pad, the second memory device including a second bonding pad, the third memory device including a third bonding pad, the second memory device being disposed between the first and third memory devices; a first conductor coupled to the first and second bonding pads; a second conductor coupled to the second and third bonding pads; and a third conductor coupled to the second bonding pad and configured to provide a signal to the second bonding pad, wherein the first conductor provides the signal from the second bonding pad to the first bonding pad at a first signal timing and the second conductor provides the signal from the second bonding pad to the third bonding pad at a second signal timing equal to the first signal timing.

[0006] According to another aspect of the present disclosure, a multi-die device is provided. The multi-die device includes: a substrate including a conductive signal line; a semiconductor device stack attached to the substrate; and a conductor coupled to the conductive signal line of the substrate and to a bonding pad of an intermediate semiconductor device of the semiconductor device stack.

[0007] According to another aspect of the present disclosure, an apparatus is provided. The apparatus includes: a stack of semiconductor devices, including a lowest semiconductor device, a highest semiconductor device, and at least one intermediate semiconductor device disposed between the lowest and highest semiconductor devices; a plurality of conductors coupled to bonding pads of the semiconductor devices of the stack; and a source conductor coupled to a coupling point at a bonding pad of one of the at least one intermediate semiconductor devices, wherein a first and a second of the plurality of conductors are also coupled to the bonding pad of one of the at least one intermediate semiconductor devices.

[0008] According to another aspect of the present disclosure, a method is provided. The method includes: providing a signal to an intermediate semiconductor device of a semiconductor device stack, the intermediate semiconductor device being disposed between first and second semiconductor devices also included in the semiconductor device stack; propagating the signal away from the intermediate semiconductor device to the first semiconductor device through a first signal path coupled to the intermediate semiconductor device and the first semiconductor device; and propagating the signal away from the intermediate semiconductor device to the second semiconductor device through a second signal path coupled to the intermediate semiconductor device and the second semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram showing a multi-die device.

[0010] Figure 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 3 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 is a diagram showing a multi-die device according to an embodiment of the present disclosure.

[0014] Figure 6 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0015] Figure 7is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0016] Figure 8 is a flow chart for providing a signal to a semiconductor device of a semiconductor device stack according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Apparatus and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a coupling point at a middle semiconductor device of the group, and the signal is propagated away from the coupling point to other semiconductor devices of the group on different (e.g., opposite) signal paths. The load from the coupling point at the middle semiconductor device to the other semiconductor devices of the group may be more balanced than, for example, having a coupling point at a semiconductor device at the end of the group (e.g., the lowest semiconductor device of the stack, the highest semiconductor device of the stack, etc.) and providing the signal from the coupling point. A more balanced topology may reduce timing differences between the times when a signal arrives at each of the semiconductor devices.

[0018] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and embodiments of the present disclosure in an illustrative manner. The detailed description contains sufficient details to enable a person skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0019] Figure 1 is a diagram showing a multi-die device 100. The multi-die device 100 may include a stack 115 of semiconductor devices 120. The stack 115 is shown as including ten semiconductor devices 120(0)-120(9). Each of the semiconductor devices 120(0)-120(9) may be, for example, a memory device, such as a dynamic random access memory (DRAM) device.

[0020] The semiconductor devices 120 of the stack 115 may be attached to each other, and the stack 115 may be attached to a substrate 130. The substrate 130 may include conductive signal lines to route signals to and from the stack 115 of semiconductor devices 120 along the substrate. One or more of the signal lines may be coupled to external terminals 140, such as solder balls, etc. Other circuits may also be attached to the substrate 130 and also coupled to the conductive signal lines. Thus, the circuits attached to the substrate 130 may be coupled to the stack 115 of semiconductor devices 120, for example, through conductive signal lines. Figure 1 1 and 2 are circuits 135 attached to substrate 130 and coupled to stack 115 of semiconductor devices 120. Circuit 135 may be a register clock driver (RCD). The RCD circuit receives and buffers signals provided to multi-die device 100 and may provide the signals to stack 115 of semiconductor devices 120.

[0021] The semiconductor devices 120 may be stacked in a staggered manner, thereby providing a "shingled stack" configuration for the stack 115. That is, the semiconductor devices 120 are offset from one another to allow edge regions of the semiconductor devices 120 to be exposed. The exposed edge regions may include bonding pads to which the conductors 125 are coupled. The conductors 125 may be bonding wires, and the bonding pads of the edge regions may be coupled together by bonding wires.

[0022] Except for the lowest height semiconductor device 120 ( 0 ), the bonding pads of each semiconductor device 120 are coupled to the bonding pads of the immediately preceding semiconductor device 120 in the stack. Figure 1 As shown in FIG. 1 , the bonding pad of semiconductor device 120(9) is coupled to the bonding pad of semiconductor device 120(8) via bonding wire 125(9), the bonding pad of semiconductor device 120(8) is coupled to the bonding pad of semiconductor device 120(7) via bonding wire 125(8), and so on to the bonding pad of semiconductor device 120(0). Semiconductor device 120(0) is coupled to the conductive signal line of substrate 130 via bonding wire 125(0). Thus, a circuit (e.g., circuit 135) attached to substrate 130 can be coupled to semiconductor device 120, for example, via the conductive signal line and bonding wire 125.

[0023] use Figure 1 , the arrival time of a signal provided to the stack 115 (e.g., from the circuit 135) is different for the semiconductor devices 120 due to the inherent propagation delay through the bond wires 125. For example, the signal first arrives at the semiconductor device 120(0) through the bond wire 125(0), then arrives at the semiconductor device 120(1) at a later time after propagating through the bond wire 125(1), then arrives at the semiconductor device 120(2) at an even later time after propagating through the bond wire 125(2), and so on, until the signal finally arrives at the semiconductor device 120(9) after propagating through the bond wire 125(9). As several semiconductor devices 120 are included in the stack, and as memory speeds continue to increase, the time delay between the time a signal arrives at the first one of the semiconductor devices 120 in the stack 115 and the time it arrives at the last one of the semiconductor devices 120 may have a greater impact on the performance of the multi-die device 100.

[0024] Figure 2is a block diagram of a semiconductor device 210 according to an embodiment of the present disclosure. For example, in some embodiments, the semiconductor device 210 may be a memory integrated into a single semiconductor chip (e.g., a semiconductor die). Example memories may include volatile memories (e.g., dynamic random access memory (DRAM) and static random access memory (SRAM)), and non-volatile memories (e.g., flash memory, resistive memory, and ferroelectric memory, or any combination thereof).

[0025] The semiconductor device 210 includes a memory cell array 211. The memory cell array 211 includes a plurality of memory banks, each memory bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder / driver 212 and the selection of the bit lines BL is performed by a column decoder / driver 213. The sense amplifier 218 is coupled to the corresponding bit line BL and is connected to the local I / O line pair LIOT / B. The local IO line pair LIOT / B is connected to the main IO line pair MIOT / B via a transfer gate TG 219 used as a switch.

[0026] The semiconductor device 210 includes a plurality of terminals. In some embodiments of the present disclosure, the terminals may be die pads. The plurality of terminals include a command and address terminal 221, clock terminals 223 and 223', a data terminal 224, a data strobe terminal 224', and power supply terminals 225 and 226. The data terminal 224 may be coupled to an output buffer of the input / output circuit 217 for a read operation. Alternatively, the data terminal 224 may be coupled to an input buffer of the input / output circuit 217 to write access to the memory in response to a data strobe signal DQS provided at the data strobe terminal 224'.

[0027] The command and address terminal 221 is supplied with a command and address signal CA, which includes a command and a memory address. The address provided to the command and address terminal 221 is transferred to the address decoder 232 via the command and address input circuit 231. The address decoder 232 receives the address and supplies the decoded row address to the row decoder / driver 212, and supplies the decoded column address to the column decoder / driver 213. The address decoder 232 also receives a memory bank address and provides the memory bank address to the row decoder / driver 212 and / or the column decoder / driver 213. In the self-refresh mode, the self-refresh circuit 238 can provide the row address to the row decoder / driver 212 for the self-refresh operation.

[0028] The command provided to the command and address terminal 221 is provided to the command decoder 234 via the command and address input circuit 231. The command decoder 234 decodes the command and provides the decoded command to the internal control signal generator 237. The internal control signal generator 237 may generate various internal command signals in response to the decoded command from the command decoder 234. For example, the internal command may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command.

[0029] Therefore, when an activation command is issued and the activation command is supplied to the row address in time, and a read command is supplied to the column address in time, read data is read from the memory cell MC specified by the row address and the column address in the memory cell array 211. The read data DQ is output from the data terminal 224 via the read / write amplifier 215 and the input / output circuit 217. Similarly, when an activation command is issued and the activation command is supplied to the row address in time, and a write command is supplied to the column address in time, the write data DQ supplied to the data terminal 224 is supplied to the memory cell array 211 via the input / output circuit 217 and the read / write amplifier 215 and is written in the memory cell MC specified by the row address and the column address.

[0030] The clock terminal 223 is supplied with clock signals CK_t and CK_c, respectively, and the clock terminal 223' is supplied with data clock signals WCK_t and WCK_c. The clock input circuit 235 receives the clock signals CK_t and CK_c and WCK_t and WCK_c and generates an internal clock signal ICLK. The internal clock signal ICLK may include an internal clock signal based on the clock signals CK_t and CK_c and / or an internal clock signal based on the data clock signals WCK_t and WCK_c. Some or all of the internal clock signals ICLK are supplied to the internal clock and timing generator 236, which generates a phase-controlled internal clock signal LCLK in response. The internal clock and timing generator 236 may include a DLL circuit, but is not limited thereto. The phase-controlled internal clock signal LCLK may be supplied to the input / output circuit 217 and used to time the input and / or output of data. The internal clock and timing generator 236 may further generate various other internal clock signals for various memory operations.

[0031] Power supply terminal 225 is supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to power supply circuit 239. Power supply circuit 239 can generate various internal potentials, such as VPP, VOD, VARY, VPERI, etc. The internal potential VPP is mainly used in row decoder / driver 212, the internal potentials VOD and VARY are mainly used in sense amplifier 218 included in memory cell array 211, and the internal potential VPERI is used in many other circuit blocks. Power supply terminal 226 is supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to input / output circuit 217. The power supply potentials VDDQ and VSSQ can be the same potentials as the power supply potentials VDD and VSS supplied to power supply terminal 225, respectively. However, the power supplier potentials VDDQ and VSSQ are available to the input / output circuit 217 so that the power supplier noise generated by the input / output circuit 217 does not propagate to other circuit blocks.

[0032] Figure 3 is a layout diagram of a semiconductor device 310 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 310 includes Figure 2 A semiconductor device 210 is provided.

[0033] The semiconductor device 310 may have edges 350a, 350b, 350c, and 350d that define ends of the semiconductor device 310. The edges 350b and 350d may extend along a first direction 357a and the edges 350a and 350c may extend along a second direction 357b that may be perpendicular to the first direction 357a. The semiconductor device 310 may include a pad formation region 351, a peripheral circuit region 352, and a memory cell array region 353 that includes memory cells, circuits, and signal lines (e.g., sense amplifier circuits, address decoder circuits, data input / output lines, etc.). The peripheral circuit region 352 may include various circuits and signal lines for performing various operations of the semiconductor device 310. For example, the peripheral circuit region 352 may include command and address input circuits, address and command decoders, clock circuits, power supply circuits, and input / output circuits. The peripheral circuit region 352 may also include terminals coupled to various circuits of the semiconductor device (e.g., as previously described with respect to Figure 1 The terminal may be, for example, a die pad of the semiconductor device.

[0034] The pad forming region 351 may include a plurality of bonding pads 354 disposed along the edge 350a. The plurality of bonding pads 354 may be coupled to terminals of the semiconductor device (e.g., die pads) and represent external terminals of the semiconductor device 310. For example, the plurality of bonding pads 354 may include data terminals, command and address terminals, clock terminals, and / or power supply terminals.

[0035] Circuits included in the memory cell array region 353 and / or circuits of the peripheral circuit region 352 may be coupled to one or more bonding pads 354 included in the pad formation region 351. As previously described, various circuits of the semiconductor device 300 may be coupled to the terminals (e.g., die pads). Conductive structures may be used to couple the terminals to one or more of the bonding pads 354. Thus, the circuits coupled to the terminals are also coupled to the bonding pads 354. The conductive structures may extend from the locations of the terminals included in the memory cell array region 353 and / or the peripheral circuit region 352 to the pad formation region 351. In some embodiments of the present disclosure, the conductive structures may include a conductive redistribution layer (RDL).

[0036] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the conductive structure may be included in Figure 2 A semiconductor device 210, Figure 1 The semiconductor device 120 of the multi-die device 100, Figure 3 In the semiconductor device 310 and / or any semiconductor device according to the embodiments of the present disclosure. For example, in some embodiments of the present disclosure, the conductive structure may be included in Figures 1 to 3 in a conductive redistribution layer (RDL) in one or more of the semiconductor devices.

[0037] Conductive structure 430 may couple terminal 440 of the semiconductor device to bonding pad 420. In some embodiments of the present disclosure, terminal 440 may be a die pad. Terminal 440 may be coupled to one or more circuits 445 of the semiconductor device. Thus, bonding pad 420 may be coupled to circuit 445 through conductive structure 430 and terminal 440. In some embodiments of the present disclosure, circuit 445 may be, for example, included in a memory cell array region (e.g., Figure 3 In some embodiments of the present disclosure, the circuit 445 may be, for example, a circuit included in a peripheral circuit region (eg, Figure 3 The circuit 445 may be used to perform various operations of the semiconductor device. In some embodiments of the present disclosure, the circuit 445 may include a command and address input circuit, an address and command decoder, a clock circuit, a power supply circuit, and an input / output circuit, as well as other circuits.

[0038] The bonding pad 420, the conductive structure 430, the terminal 440 and the circuit 445 of the semiconductor device can be formed by a semiconductor structure. The semiconductor structure can include a conductive layer, a conductive path, an insulating interlayer, etc. The terminal 440 can be coupled to the circuit 445 by, for example, a metal layer and / or a conductive path. The conductive structure 430 can be disposed on one or more insulating interlayers. As previously described, the conductive structure 430 can be further coupled to the bonding pad 420. The conductive structure 430 extends from the terminal 440 to the bonding pad 420, so that the bonding pad 420 and the circuit terminal 440 can be coupled together. Therefore, the circuit 445 coupled to the terminal 440 can be accessed from the outside through the bonding pad 420. The bonding pad 420 can be exposed through the opening 425 in the passivation layer 435. In some embodiments of the present disclosure, the passivation layer 435 can be a polyimide material.

[0039] In some embodiments of the present disclosure, the conductive structure 430 may be coupled to a terminal 440 of a semiconductor device (e.g., a die pad of the semiconductor device) to provide a bonding pad 420 for coupling to the terminal 440 in different locations. For example, the terminal 440 may represent a die pad that is typically located in a peripheral circuit region along a central region of the semiconductor device, and the conductive structure 430 may couple the die pad in the central region to a bonding pad 420 located along an edge of the semiconductor device. The bonding pad 420 along the edge may be more conveniently located and provide coupling to the circuit 445 of the semiconductor device, i.e., through the conductive structure 430 and the terminal 440.

[0040] Figure 5 is a diagram showing a multi-die device 500 according to an embodiment of the present disclosure. The multi-die device 500 may include a stack 515 of semiconductor devices 520. The embodiments of the present disclosure are not limited to Figure 5 5. In some embodiments of the present disclosure, each of the semiconductor devices 520 includes a specific number of semiconductor devices 520 included in the stack 515 shown in FIG. Figure 2 Each of the semiconductor devices 520 may be, for example, a memory device such as a dynamic random access memory (DRAM) device.

[0041] The semiconductor devices 520 of the stack 515 may be attached to each other, and the stack 515 may be attached to the substrate 530. In some embodiments of the present disclosure, the semiconductor devices 520 are attached to each other and / or to the substrate 530 by adhesive epoxy. The substrate 530 may include conductive signal lines to route signals to and from the stack 515 of semiconductor devices 520 along the substrate. One or more of the signal lines may be coupled to external terminals 540. In some embodiments of the present disclosure, the external terminals 540 may include solder balls, etc. Other circuits may also be attached to the substrate 530 and also coupled to the conductive signal lines. Therefore, the circuits attached to the substrate 530 may be coupled to the stack 515 of semiconductor devices 520, for example, by conductive signal lines. Figure 5 5 is shown in FIG. 5 , which is attached to substrate 530 and coupled to stack 515 of semiconductor devices 520. In some embodiments of the present disclosure, circuit 535 may be a register clock driver (RCD). In such embodiments of the present disclosure, the RCD circuit receives and buffers signals provided to multi-die device 500 and may provide the signals to stack 515 of semiconductor devices 520. Additional or alternative circuits may be included in multi-die device 500, and / or circuit 535 may be other circuits as well, without departing from the scope of the present disclosure.

[0042] The semiconductor devices 520 may be stacked in a staggered manner, thereby providing a "shingled stack" configuration for the stack 515. That is, the semiconductor devices 520 are offset from one another to allow edge regions of the semiconductor devices 520 to be exposed. The exposed edge regions may include bonding pads to which the conductors 525 are coupled. In some embodiments of the present disclosure, the conductors 525 may be bonding wires, and the bonding pads of the edge regions may be coupled together by bonding wires.

[0043] Except for the lowest height semiconductor device 520 ( 0 ), the bonding pads of each semiconductor device 520 are coupled to the bonding pads of at least one other semiconductor device 520 in the stack. Figure 5 , the bonding pad of semiconductor device 520(8) is coupled to the bonding pad of semiconductor device 520(9) through conductor 525(9), and the bonding pad is further coupled to the bonding pad of semiconductor device 520(7) through conductor 525(8). Similarly, the bonding pad of semiconductor device 520(1) is coupled to the bonding pad of semiconductor device 520(2) through conductor 525(2), and the bonding pad is further coupled to the bonding pad of semiconductor device 520(0) through conductor 525(1).

[0044] Semiconductor device 520(4) is coupled to a conductive signal line of substrate 530 via source conductor 510. Source conductor 510 may be coupled to, for example, a bonding pad of semiconductor device 520(4). Semiconductor device 520(4) is coupled to semiconductor device 520(3), which is coupled to semiconductor device 520(2), which is coupled to semiconductor device 520(1), which is coupled to semiconductor device 520(0). Semiconductor device 520(4) is also coupled to semiconductor device 520(5), which is coupled to semiconductor device 520(6), which is coupled to semiconductor device 520(7), which is coupled to semiconductor device 520(8), which is coupled to semiconductor device 520(9). Thus, circuits (eg, circuit 535 ) attached to substrate 530 may be coupled to stack 515 of semiconductor devices 520 , such as through conductive signal lines and source conductors 510 and conductors 525 .

[0045] In an embodiment of the present disclosure, coupling to stack 515 at an intermediate semiconductor device of semiconductor devices 520 can reduce timing differences between the time a signal arrives at each of the semiconductor devices. The intermediate semiconductor device can be any semiconductor device between the lowest semiconductor device and the highest semiconductor device (e.g., semiconductor device 520(0) (lowest) and semiconductor device 520(9) (highest)). From a coupling perspective, coupling to the intermediate semiconductor devices of stack 515 can provide a more balanced topology.

[0046] Although Figure 5 The semiconductor devices 520 in the stack 515 are illustrated, but in other embodiments of the present disclosure, the semiconductor devices 520 may be arranged in groups in different ways. For example, the semiconductor devices may be arranged in a row laterally relative to each other. The coupling point may be to an intermediate semiconductor device of the group of laterally arranged semiconductor devices. In such embodiments, the signal provided to the coupling point may propagate laterally in opposite directions from the coupling point to the semiconductor device at the opposite end of the lateral arrangement of the semiconductor devices. In some embodiments of the present disclosure, the semiconductor devices 520 are physically positioned relative to each other in other arrangements. More generally, the scope of the present disclosure is not intended to be limited to only stacked arrangements of semiconductor devices.

[0047] For example, in Figure 5In the embodiment of the present disclosure shown in , the conductive signal line of substrate 530 is coupled to stack 515 at middle semiconductor device 520(4) through source conductor 510. The load from the coupling point at semiconductor device 520(4) to the lowest semiconductor device 520(0) and to the highest semiconductor device 520(9) is more balanced than, for example, having the coupling point at the lowest semiconductor device. Thus, the timing difference of the signal from the coupling point at semiconductor device 520(4) to the lowest semiconductor device 520(0) and to the highest semiconductor device 520(9) of the stack can be reduced.

[0048] It may be advantageous to have a coupling point at a middle semiconductor device near the center of a group (e.g., a stack) of semiconductor devices. A "center" semiconductor device is a middle semiconductor device of a group that may be positioned in the group such that there are an equal number of semiconductor devices in either direction from the center semiconductor device to the opposite end semiconductor devices. For example, in a stack of nine semiconductor devices, the center semiconductor device is the fifth semiconductor device that is positioned in the stack so that there are four semiconductor devices in a first direction to a first end semiconductor device (e.g., the lowest semiconductor device) and in a second direction to a second end semiconductor device (e.g., the highest semiconductor device). Where a group includes an even number of semiconductor devices, the center semiconductor device may be either of two semiconductor devices that are positioned in the group such that there are an almost equal number of semiconductor devices in either direction from the center semiconductor device to the opposite end semiconductor devices (e.g., + / - 1 semiconductor device). For example, in a stack of eight semiconductor devices, the center semiconductor device is the fourth or fifth semiconductor device that is positioned in the stack such that there are four semiconductor devices in a first direction to the first end semiconductor device and three semiconductor devices in a second direction to the second end semiconductor device.

[0049] Figure 6 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 6 The semiconductor device can be represented by Figure 5 In some embodiments of the present disclosure, Figure 6 The semiconductor devices may represent groups of semiconductor devices arranged laterally relative to each other. In some embodiments of the present disclosure, Figure 6 The semiconductor device of FIG. 1 may represent a semiconductor device in other physical arrangements. For ease of description, reference will be made to Figure 5 The semiconductor device 520 is described Figure 6 semiconductor device. However, Figure 6 The semiconductor device is not necessarily limited thereto.

[0050] The bonding pads of semiconductor devices 520(0) to 520(9) are coupled via conductors 525(1) to 525(9). For example, the bonding pad of semiconductor device 520(0) is coupled to the bonding pad of semiconductor device 520(1) via conductor 525(1); the bonding pad of semiconductor device 520(1) is coupled to the bonding pad of semiconductor device 520(2) via conductor 525(2); the bonding pad of semiconductor device 520(2) is coupled to the bonding pad of semiconductor device 520(3) via conductor 525(3); the bonding pad of semiconductor device 520(3) is coupled to the bonding pad of semiconductor device 520(4) via conductor 525(4); and the bonding pad of semiconductor device 520(4) is coupled to the bonding pad of semiconductor device 520(4) via conductor 525(5). 5(5) is coupled to the bonding pad of semiconductor device 520(5); the bonding pad of semiconductor device 520(5) is coupled to the bonding pad of semiconductor device 520(6) through conductor 525(6); the bonding pad of semiconductor device 520(6) is coupled to the bonding pad of semiconductor device 520(7) through conductor 525(7); the bonding pad of semiconductor device 520(7) is coupled to the bonding pad of semiconductor device 520(8) through conductor 525(8); and the bonding pad of semiconductor device 520(8) is coupled to the bonding pad of semiconductor device 520(9) through conductor 525(9).

[0051] Source conductor 510 is coupled to a bonding pad of semiconductor device 520(4). Source conductor 510 may be coupled to another circuit and / or conductive signal line, such as a substrate. Thus, the circuit and / or conductive signal line may be coupled to other semiconductor devices.

[0052] exist Figure 6 In the example of, only one bonding pad is shown for each of the semiconductor devices 520. However, without departing from the scope of the present disclosure, each of the semiconductor devices 520 may include additional bonding pads that may be coupled to other semiconductor devices 520. The bonding pads of the semiconductor devices 520 may also represent one or more physical bonding pads that may be coupled together, and are therefore not limited to only one physical bonding pad to which the multiple conductors are coupled. For example, in some embodiments of the present disclosure, the bonding pads of the semiconductor devices may represent two bonding pads coupled together, one bonding pad coupled to the bonding pad of the first adjacent semiconductor device and another bonding pad coupled to the bonding pad of the second adjacent semiconductor device. In some embodiments of the present disclosure, the bonding pads of the semiconductor devices may represent three bonding pads coupled together, a first bonding pad coupled to the bonding pad of the first adjacent semiconductor device, a second bonding pad coupled to the bonding pad of the second adjacent semiconductor device, and a third bonding pad to which the source conductor 510 may be coupled.

[0053] Conductor 525 includes an inherent propagation delay that can affect the timing of the time when a signal arrives at the corresponding semiconductor device. However, if source conductor 510 is coupled to an intermediate one of semiconductor devices 520(0) to 520(9), a more balanced topology can be provided. The intermediate semiconductor device can be, for example, a semiconductor device between a first end semiconductor device and a second end semiconductor device (e.g., between semiconductor device 520(0) (first end) and semiconductor device 520(9) (second end)). A more balanced topology can reduce the timing differences between the time when a signal arrives at each of semiconductor devices 520. For example, if Figure 6 As shown in the example, utilizing the coupling point at the bonding pad of semiconductor device 520(4), the signal provided on source conductor 510 propagates through four conductors 525(4) to 525(1) to reach semiconductor device 520(0) (e.g., a first end semiconductor device) and propagates through five conductors 525(5) to 525(9) to reach semiconductor device 520(9) (e.g., a second end semiconductor device).

[0054] In embodiments of the present disclosure in which each of conductors 525 provides a similar propagation delay, the difference in arrival time of the signal provided on source conductor 510 to semiconductor device 520(0) and to semiconductor device 520(9) is approximately equal to the propagation delay of one conductor 525 (e.g., conductor 525(9), the fifth conductor), which in some embodiments of the present disclosure may be considered to be approximately equal to the same propagation delay to semiconductor device 520(0) and to semiconductor device 520(9).

[0055] In contrast, the difference in signal timing can be significantly greater than an arrangement in which the signal is first provided to semiconductor device 520(0) (e.g., the first end semiconductor device) and the signal propagates through conductors 525(1) to 525(9) to semiconductor device 520(9). For example, the signal arrives at semiconductor device 520(9) after a propagation delay of nine conductors 525. Thus, the difference in signal timing between semiconductor device 520(0) and semiconductor device 520(9) is the total propagation delay of the nine conductors 525, which can be a significantly longer delay than the timing difference with the propagation delay of one conductor 525, for example, for Figure 6 Instance of .

[0056] An arrangement that couples a source conductor to an intermediate semiconductor device of a semiconductor device group (e.g., a semiconductor device stack) may be advantageous in reducing timing differences in signals reaching the semiconductor devices at both ends. This arrangement may provide improved signal integrity for unidirectional signals with high loads (e.g., command and address signals, chip select signals, clocks, and other signals). An arrangement as disclosed may also require lighter drive and lighter terminal termination (e.g., on die termination) to provide a valid data eye at a receiver circuit.

[0057] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. Figure 7 Five semiconductor devices 720(2)-720(6) are shown, but additional semiconductor devices may be coupled to semiconductor devices 720(2)-720(6) without departing from the scope of the present disclosure. For example, in some embodiments of the present disclosure, the semiconductor devices may be included in a multi-die device (e.g., Figure 2 In a multi-die device 200).

[0058] Bond pads 715-717 may be included in pad forming regions of respective semiconductor devices 720(2)-720(6). The corresponding bond pads of each semiconductor device are coupled together by conductor 725. For example, bond pads 715(2)-715(6) of semiconductor devices 720(2)-720(6) are coupled together by conductors 725(3)A-725(6)A; bond pads 716(2)-716(6) of semiconductor devices 720(2)-720(6) are coupled together by conductors 725(3)B-725(6)B; and bond pads 717(2)-717(6) of semiconductor devices 720(2)-720(6) are coupled together by conductors 725(3)C-725(6)C. Although only three bond pads 715-717 are shown for each semiconductor device 720, additional bond pads may be included without departing from the scope of the present disclosure.

[0059] Respective conductors 710A-710C are coupled to bonding pads 715(4)-717(4) of an intermediate semiconductor device 720(4). Each of conductors 710A-710C may be coupled to circuitry and / or conductive signal lines, such as a substrate. Signals provided on respective conductors 710 may be provided to each of the semiconductor devices via conductors 725 coupled to respective bonding pads 715-717. By having a coupling point at an intermediate semiconductor device and propagating the signal away from the coupling point to the semiconductor device via the conductors on two different (e.g., opposite) signal paths, the signal timing of the signals may be made more balanced. For example, the timing of the signal arriving at semiconductor device 720(2) and the signal arriving at semiconductor device 720(6) can be approximately equal because the propagation delay through conductor 725 should be approximately equal to the propagation delay from the coupling point at bonding pads 715(4) to 717(4) of semiconductor device 720(4) to the corresponding bonding pads 715(2) to 717(2) of semiconductor device 720(2), and approximately equal to the propagation delay from the coupling point at bonding pads 715(4) to 717(4) to the corresponding bonding pads 715(6) to 717(6) of semiconductor device 720(6).

[0060] Figure 8 is a flow chart of providing a signal to a semiconductor device of a semiconductor device stack according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device may be included in Figure 5 Semiconductor device stack and / or Figure 6 In some embodiments of the present disclosure, for Figure 8 The method of stacking a semiconductor device may include as described in reference Figure 7 The semiconductor device is a memory device, for example, a DRAM device in some embodiments of the present disclosure. For ease of description, reference will be made to Figure 5 The stack 515 of semiconductor devices 520 is described Figure 8 Flow chart of method 800. However, Figure 8 The method 800 is not necessarily limited in this regard.

[0061] At step 801, a signal is provided to an intermediate semiconductor device of a semiconductor device stack. The intermediate semiconductor device may be between a first semiconductor device and a second semiconductor device. For example, referring to Figure 5 5. The stack 515 of semiconductor devices 520 of FIG. 5 may include semiconductor device 520(4), which may be an intermediate semiconductor device between semiconductor devices 520(3) and 520(5). The signal may be, for example, a signal provided by a circuit external to the stack, such as circuit 535. As previously described, circuit 535 and stack 515 may be attached to a substrate including a conductive signal line. The signal may be provided to semiconductor device 520(4) through the conductive signal line and through source conductor 510 coupled to the conductive signal line and to a bonding pad of semiconductor device 520(4).

[0062] At step 803, a signal is provided to a first semiconductor device away from the intermediate semiconductor device on a first signal path. Figure 5 In a stack 515 of semiconductor devices 520, semiconductor device 520(3) may be a first semiconductor device and a first signal path may be conductor 525(3). Conductor 525(3) may be coupled to a bonding pad of semiconductor device 520(4) and to a bonding pad of semiconductor device 520(3). A signal provided to semiconductor device 520(4) (e.g., to a bonding pad of semiconductor device 520(4)) may be provided to semiconductor device 520(3) away from semiconductor device 520(4) on conductor 525(3).

[0063] At step 805, the signal is also provided to the second semiconductor device on a second signal path away from the intermediate semiconductor device. Figure 5In the stack 515 of semiconductor devices 520, semiconductor device 520(5) may be a second semiconductor device and the second signal path may be conductor 525(5). Conductor 525(5) may be coupled to a bonding pad of semiconductor device 520(4) and to a bonding pad of semiconductor device 520(5). The signal provided to semiconductor device 520(4) may be provided to semiconductor device 520(5) away from semiconductor device 520(4) on conductor 525(5). In some embodiments of the present disclosure, the second signal path (e.g., conductor 525(5)) and the first signal path (e.g., conductor 525(3)) may be opposite signal paths to provide signals away from an intermediate semiconductor device (e.g., semiconductor device 520(4)).

[0064] Signal paths (e.g., conductors 525(3) and 525(5)) include inherent propagation delays that can affect the timing of when the signal arrives at the respective semiconductor devices. As previously described, providing the signal to an intermediate one of the semiconductor devices (e.g., intermediate semiconductor device 520(4)) and providing the signal away from the intermediate semiconductor device to the first and second semiconductor devices on the respective signal paths (e.g., semiconductor device 520(3) on conductor 525(3) and semiconductor device 520(5) on conductor 525(5)) can provide a more balanced topology. Thus, the timing difference in when the signal arrives at the first and second semiconductor devices can be reduced. For example, in some embodiments of the present disclosure, due to coupling through the intermediate semiconductor device, the propagation delay of the signal through the first signal path to the first semiconductor device can be equal to the propagation delay of the signal through the second signal path to the second semiconductor device.

[0065] Certain details have been described to provide a full understanding of the examples of the present disclosure. However, it will be apparent to those skilled in the art that the examples of the present disclosure can be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be interpreted as limiting the scope of the present disclosure to these specific examples. In other examples, well-known circuits, control signals, timing protocols, and software operations are not shown in detail to avoid unnecessarily obscuring the present disclosure. In addition, terms such as "couples and coupled" indicate that two components can be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0066] From the foregoing it will be apparent that, although specific embodiments of the present disclosure have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to any specific embodiments described herein.

Claims

1. A device comprising: a plurality of memory devices including first, second and third memory devices, the first memory device including a first bonding pad, the second memory device including a second bonding pad, the third memory device including a third bonding pad, the second memory device being disposed between the first and third memory devices; a first conductor coupled to the first bonding pad of the first memory device and the second bonding pad of the second memory device; a second conductor coupled to the second bonding pad of the second memory device and the third bonding pad of the third memory device; and a source conductor coupled to the second bonding pad and to at least one conductive signal line, the source conductor being configured to provide a signal to the second bonding pad, wherein the first memory device is limited to receiving the signal from the second bonding pad at the first bonding pad through the first conductor, and the third memory device is limited to receiving the signal from the second bonding pad at the third bonding pad through the second conductor.

2. The apparatus of claim 1, wherein the second memory device comprises a central memory device among the plurality of memory devices.

3. The apparatus of claim 2, wherein the plurality of memory devices further include a fourth memory device including a fourth bonding pad, the apparatus further comprising a fourth conductor coupled to the third and fourth bonding pads.

4. The apparatus of claim 3 , wherein the plurality of memory devices further include a fifth memory device including a fifth bonding pad, the apparatus further comprising a fifth conductor coupled to the first and fifth bonding pads, wherein the signal provided to the fourth bonding pad through the third and fourth conductors has a third signal timing and the signal provided to the fifth bonding pad through the first and fifth conductors has a fourth signal timing equal to the third signal timing.

5. The apparatus of claim 4, wherein the first, third, fourth, and fifth conductors have the same propagation delay.

6. The apparatus of claim 1, wherein the plurality of memory devices comprises a stack of memory devices.

7. The apparatus of claim 1, wherein the plurality of memory devices comprises an even number of memory devices.

8. The apparatus of claim 1, wherein the plurality of memory devices comprises an odd number of memory devices.

9. The apparatus of claim 1, wherein the first and second conductors comprise bond wires.

10. The apparatus of claim 1, wherein a propagation delay of the signal through the first conductor and a propagation delay of the signal through the second conductor are equal.

11. A multi-die device, comprising: a substrate comprising conductive signal lines; a semiconductor device stack attached to the substrate, the semiconductor device stack comprising a lowermost semiconductor device, an uppermost semiconductor device, and an intermediate semiconductor device disposed between the lowermost semiconductor device and the uppermost semiconductor device; and conductors coupled to a conductive signal line of the substrate and to a bonding pad of the middle semiconductor device, wherein the conductive signal line is configured to provide a signal, and wherein the lowermost semiconductor device and the uppermost semiconductor device are limited to receiving the signal at corresponding bonding pads through corresponding conductors coupled to the bonding pads of the middle semiconductor device.

12. The multi-die device of claim 11, wherein the intermediate semiconductor device comprises a center semiconductor device.

13. The multi-die device of claim 11, wherein the stack of semiconductor devices comprises semiconductor devices in a shingled stack configuration.

14. The multi-die device of claim 11, further comprising circuitry attached to the substrate and coupled to the intermediate semiconductor device through the conductive signal lines and the conductors of the substrate.

15. The multi-die device of claim 14, wherein the circuit comprises a register clock driver.

16. The multi-die device of claim 11, wherein a propagation delay of a signal provided on a bonding wire from the intermediate semiconductor device to the lowest semiconductor device in the stack is approximately the same as a propagation delay of the signal provided on a bonding wire from the intermediate semiconductor device to the highest semiconductor device in the stack.

17. The multi-die device of claim 11, wherein the bonding pad of the middle semiconductor device comprises a first bonding pad and a second bonding pad, the first bonding pad being configured to be coupled to a bonding wire coupled to the bonding pad of another semiconductor device of the stack, and the second bonding pad being coupled to the conductor.

18. An apparatus comprising: a semiconductor device stack comprising a lowest semiconductor device, an uppermost semiconductor device, and at least one intermediate semiconductor device disposed between the lowest and uppermost semiconductor devices; a plurality of conductors coupled to bonding pads of the semiconductor devices of the stack; and A source conductor coupled to a coupling point at a bonding pad of one of the at least one intermediate semiconductor device and to at least one conductive signal line, the at least one conductive signal line being configured to provide a signal to the bonding pad of the one of the at least one intermediate semiconductor device, wherein a first and a second of the plurality of conductors are also coupled to the bonding pad of the one of the at least one intermediate semiconductor device, and wherein the lowest semiconductor device is limited to receiving the signal from the bonding pad of the one of the at least one intermediate semiconductor device through the first of the plurality of conductors at the lowest bonding pad, and the highest semiconductor device is limited to receiving the signal from the bonding pad of the one of the at least one intermediate semiconductor device through the second of the plurality of conductors at the highest bonding pad.

19. The apparatus of claim 18, wherein the source conductor and the first and second of the plurality of conductors are configured to provide a signal to the intermediate semiconductor device and propagate the signal away from the coupling point to a semiconductor device through the first and second of the plurality of conductors on two different signal paths.

20. The apparatus of claim 19, wherein a first additional one of the plurality of conductors is configured to propagate the signal from the coupling point to the uppermost semiconductor device and a second additional one of the plurality of conductors is configured to propagate the signal from the coupling point to the lowermost semiconductor device.

21. The apparatus of claim 18, wherein a first number of dies are between the at least one intermediate semiconductor die to which the source conductor is coupled and the highest semiconductor device and a second number of dies are between the at least one intermediate semiconductor die to which the source conductor is coupled and the lowest semiconductor device, and wherein the first number and the second number are equal or within one.

22. The apparatus of claim 18, further comprising: a substrate to which the semiconductor device stack is attached, the substrate including a conductive signal line to which the source conductor is coupled; and A circuit is coupled to the conductive signal line and attached to the substrate.

23. A method comprising: providing a signal to an intermediate semiconductor device of a semiconductor device stack, the intermediate semiconductor device being disposed between first and second semiconductor devices also included in the semiconductor device stack; propagating the signal away from the intermediate semiconductor device to the first semiconductor device through a first signal path coupled to the intermediate semiconductor device and the first semiconductor device; and The signal is propagated away from the intermediate semiconductor device to the second semiconductor device through a second signal path coupled to the intermediate semiconductor device and the second semiconductor device, wherein the first semiconductor device is limited to receiving the signal via the first signal path coupled to the intermediate semiconductor device and the first semiconductor device, and wherein the second semiconductor device is limited to receiving the signal via the second signal path coupled to the intermediate semiconductor device and the second semiconductor device.

24. The method of claim 23, wherein providing the signal to the intermediate semiconductor device comprises providing the signal to a bond pad of the intermediate semiconductor device, and wherein the first signal path and the second signal path are coupled to the bond pad of the intermediate semiconductor device.

25. The method of claim 23, wherein propagating the signal on the first and second signal paths away from the intermediate semiconductor device comprises propagating the signal on opposite signal paths away from the intermediate semiconductor device.

26. The method of claim 23, wherein providing the signal to the intermediate semiconductor device comprises providing the signal from a circuit coupled to the intermediate semiconductor device through at least a conductive signal line of a substrate and a source conductor coupled to the conductive signal line and the intermediate semiconductor device.

27. The method of claim 23, wherein a propagation delay through the first signal path is approximately equal to a propagation delay through the second signal path.

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