Semiconductor device and method for forming the same

Abstract

The present disclosure relates to a semiconductor device and a method for forming the same. A semiconductor device includes a semiconductor substrate; and a multi-level wiring structure located on the semiconductor substrate, the multi-level wiring structure at least including an intermediate metal layer located above the semiconductor substrate and an uppermost metal layer located above the intermediate metal layer, and the multi-level wiring structure is divided into a main circuit portion and a cut portion surrounding the main circuit portion; wherein the cut portion of the multi-level wiring layer includes at least a metal pad exposed in the intermediate metal layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. Background Art

[0002] For example, in a semiconductor device such as a dynamic random access memory (hereinafter referred to as DRAM), a low-k insulating film with a low dielectric constant is provided between metal interconnects in some cases to reduce the capacitance between the interconnects and achieve high-speed operation of the circuit. For example, SiOC and SiCN are used as films with a low dielectric constant. In the following description, these films with a low dielectric constant are referred to as low-k insulating films. Low-k insulating films have lower adhesion than silicon oxide films and silicon nitride films, and the material is also fragile. For these reasons, when a semiconductor wafer with semiconductor elements such as DRAM formed thereon is cut (dice) to separate the semiconductor elements into individual semiconductor chips, cracks caused by the cut sometimes propagate in the low-k insulating film and the film interface (SiO2 / SiOC, SiOC / SiCN, SiCN / SiO2) and reach the main circuit portion of the semiconductor device, thereby reducing the yield of the semiconductor device. Summary of the invention

[0003] In one aspect, the present disclosure relates to a semiconductor device, comprising: a semiconductor substrate; and a multi-level wiring structure, which is located on the semiconductor substrate, the multi-level wiring structure at least comprising an intermediate metal layer above the semiconductor substrate and an uppermost metal layer above the intermediate metal layer, and the multi-level wiring structure is divided into a main circuit part and a cut-out part surrounding the main circuit part; wherein the cut-out part of the multi-level wiring layer at least comprises a metal pad exposed in the intermediate metal layer.

[0004] In another aspect, the present disclosure relates to a semiconductor device comprising: a semiconductor substrate having a main surface including a first portion and a second portion; a low-k insulating film covering the first portion and the second portion of the main surface of the semiconductor substrate; and a first insulating layer covering the low-k insulating film of the first and second portions of the main surface of the semiconductor substrate; wherein the first insulating layer of the first portion has a first thickness, and the second insulating layer of the second portion has a second thickness.

[0005] In yet another aspect, the present disclosure relates to a method comprising: forming an insulating film over a semiconductor substrate having first, second and third regions; forming a photoresist on the insulating film; and patterning the photoresist using a photomask, the photomask having a first portion with a first transmittance, a second portion with a second transmittance, and a third portion covered with a shielding material so that a remaining thickness of the photoresist becomes different among the first, second and third regions corresponding to the first, second and third portions of the photomask. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a plan view illustrating one example of a schematic configuration of a layout of a semiconductor device according to the embodiment.

[0007] Figure 2 is a plan view illustrating one example of a schematic configuration of a semiconductor device according to the embodiment.

[0008] Figure 3 is a plan view illustrating an example of a schematic configuration of a cutout portion of a semiconductor device according to an embodiment, and is Figure 1 Magnified view of area P in FIG.

[0009] Figure 4A and 4B is a diagram illustrating an example of a schematic configuration of a dicing portion of the semiconductor device according to the first embodiment. Figure 4A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Figure 4B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT in FIG. Figure 4A and 4B is a longitudinal section illustrating a method of forming a semiconductor device according to a first embodiment, and is a diagram illustrating Fig.11A and 11B A diagram of an example of the following steps.

[0010] Figure 5A is a longitudinal cross section illustrating one example of a schematic configuration of a memory cell region of the semiconductor device according to the embodiment. Figure 5B is a longitudinal section illustrating one example of a schematic configuration of a peripheral circuit portion of a semiconductor device according to the embodiment.

[0011] Fig. 6A and 6B is a longitudinal section illustrating an example of an intermediate step of the method of forming the semiconductor device according to the first embodiment. Fig. 6A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Figure 6B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT.

[0012] Fig. 7A and 7B is a longitudinal section illustrating an example of an intermediate step of the method of forming the semiconductor device according to the first embodiment. Fig. 7A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Figure 7B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig. 7A and 7B It is explained in Fig. 6A and 6B A diagram of an example of the steps that follow.

[0013] Figure 8 It is used for Fig. 7A and 7B An enlarged partial plan view of a schematic configuration of a photomask in the steps described. Fig. 8A , 8B 8C and 8D are partial longitudinal sections illustrating schematic configurations of photomasks. Fig. 8E Yes Description Fig.8D 1 is a plan view of a schematic configuration of a portion of a photomask illustrated in FIG.

[0014] Fig. 9A and 9B is a longitudinal section illustrating an example of an intermediate step of the method of forming the semiconductor device according to the first embodiment. Fig. 9A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 9B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig. 9A and 9B It is explained in Fig. 8A and 8B A diagram of an example of the steps that follow.

[0015] Fig. 10A and 10B is a longitudinal section illustrating an example of an intermediate step of the method of forming the semiconductor device according to the first embodiment. Fig. 10A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 10B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig. 10A and 10BIt is explained in Fig. 9A and 9B A diagram of an example of the steps that follow.

[0016] Fig.11A and 11B is a longitudinal section illustrating an example of an intermediate step of the method of forming the semiconductor device according to the first embodiment. Fig.11A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 11B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.11A and 11B It is explained in Fig. 10A and 10B A diagram of an example of the steps that follow.

[0017] Fig. 12A and 12B is a diagram illustrating an example of a schematic configuration of a dicing portion of a semiconductor device according to a second embodiment. Fig. 12A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 12B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT in FIG. Fig. 12A and 12B is a longitudinal section illustrating a method of forming a semiconductor device according to a second embodiment, and is a diagram illustrating Fig.15A and 15B A diagram of an example of the steps that follow.

[0018] Fig.13A and 13B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the second embodiment. Fig.13A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 13B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.13A and 13B It is explained in Fig. 6A and 6B A diagram of an example of the steps that follow.

[0019] Fig.14A and 14B is a diagram illustrating an example of a schematic configuration of a dicing portion of a semiconductor device according to a second embodiment. Fig.14A It is explained along the Figure 3A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 14B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.14A and 14B It is explained in Fig.13A and 13B A diagram of an example of the steps that follow.

[0020] Fig.15A and 15B is a diagram illustrating an example of a schematic configuration of a dicing portion of a semiconductor device according to a second embodiment. Fig.15A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 15B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.15A and 15B It is explained in Fig.14A and 14B A diagram of an example of the steps that follow.

[0021] Fig.16A and 16B is a diagram illustrating an example of a schematic configuration of a dicing portion of a semiconductor device according to a third embodiment. Fig.16A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 16B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT in FIG. Fig.16A and 16B is a longitudinal section illustrating a method of forming a semiconductor device according to a third embodiment, and is a diagram illustrating Fig. 20A and 20B A diagram of an example of the steps that follow.

[0022] Fig.17A and 17B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the third embodiment. Fig.17A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 17B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.17A and 17B It is explained in Fig. 6A and 6B A diagram of an example of the steps that follow. Fig. 17C It is used for Fig.17A and17B An enlarged partial plan view of a schematic configuration of a photomask in the steps described.

[0023] Fig.18A and 18B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the third embodiment. Fig.18A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig.18B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.18A and 18B It is explained in Fig.17A and 17B A diagram of an example of the following steps.

[0024] Fig.19A and 19B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the third embodiment. Fig.19A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig.19B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.19A and 19B It is explained in Fig.18A and 18B A diagram of an example of the following steps.

[0025] Fig. 20A and 20B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the third embodiment. Fig. 20A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 20B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig. 20A and 20B It is explained in Fig.19A and 19B A diagram of an example of the following steps.

[0026] Fig.21A and 21B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the third embodiment. Fig.21A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 21B It is explained along the Figure 3A longitudinal section of a schematic configuration of a portion of line TT. Fig.21A and 21B It is explained in Fig.19A and 19B A diagram of an example of the following steps.

[0027] Fig.22A and 22B is a longitudinal section illustrating an example of an intermediate step of a modification of the method of forming the semiconductor device according to the third embodiment. Fig.22A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 22B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.22A and 22B It is explained in Fig.21A and 21B A diagram of an example of the following steps.

[0028] Fig.23A and 23B is a diagram illustrating an example of a schematic configuration of a dicing portion of a semiconductor device according to a fourth embodiment. Fig.23A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 23B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT in FIG. Fig.23A and 23B is a longitudinal section illustrating a method of forming a semiconductor device according to a fourth embodiment, and is a diagram illustrating Fig.26A and 26B A diagram of an example of the following steps.

[0029] Fig.24A and 24B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the fourth embodiment. Fig.24A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig. 24B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.24A and 24B It is explained in Fig. 6A and 6B A diagram of an example of the following steps.

[0030] Fig.25A and 25Bis a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the fourth embodiment. Fig.25A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig.25B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.25A and 25B It is explained in Fig.24A and 24B A diagram of an example of the steps that follow.

[0031] Fig.26A and 26B is a longitudinal section illustrating an example of an intermediate step of the method of forming a semiconductor device according to the fourth embodiment. Fig.26A It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line SS in FIG. Fig.26B It is explained along the Figure 3 A longitudinal section of a schematic configuration of a portion of line TT. Fig.26A and 26B It is explained in Fig.25A and 25B A diagram of an example of the steps that follow. DETAILED DESCRIPTION

[0032] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that illustrate specific aspects and embodiments of the present invention that can be practiced by means of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that other embodiments may be used and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0033] Hereinafter, several embodiments will be described with reference to the drawings. In the following description, DRAM is given as an example of a semiconductor device. In the following description, elements identical or similar to those previously described will be denoted by the same or similar symbols or will be referred to by the same or similar names, and further description may be omitted.

[0034] (First embodiment)

[0035] Figure 1 1 is a plan view illustrating a schematic configuration of a semiconductor wafer 100. The semiconductor wafer 100 is provided with a main surface on which various elements, insulating films, conductive films, and the like are formed. Figure 1The layout of the plurality of main circuit portions 3 and dicing portions 2 included on the main surface of the semiconductor wafer 100 will be described.

[0036] Figure 1 The semiconductor wafer 100 illustrated in FIG. 1 is schematically illustrated as being in a state before the semiconductor wafer is cut by a dicing step, or in other words, in a state before the semiconductor wafer is separated into individual semiconductor chips. The main surface of the semiconductor wafer 100 includes a plurality of main circuit portions 3 in which circuit elements such as transistors or conductive interconnects forming DRAM are formed. Each main circuit portion 3 has a rectangular shape. The main circuit portions 3 are arranged in a matrix. The dicing portion 2 is disposed around each of the main circuit portions 3. In each main circuit portion 3, components such as a plurality of memory cells, a data-related circuit for reading and writing memory cell data, and a control circuit for controlling the data-related circuit are arranged.

[0037] The dicing portion 2 corresponds to a portion for separating the semiconductor wafer 100 into Figure 2 The dicing area of ​​the individual semiconductor device 1 described in FIG. Figure 3 , the direction across the width of the cut portion 2 is referred to as the width direction E. The cut portion 2 is provided with a predetermined width defining the width direction E. The cut portion 2 extends in a direction orthogonal to the width direction E. In the cut portion 2, the direction at right angles to the width direction E is referred to as the longitudinal direction F.

[0038] exist Figure 3 , the cutout portion 9 is illustrated in the central portion of the cutout portion 2. The cutout portion 9 is formed in a later slitting step. The cutout portion 9 is formed at approximately the center of the cutout portion 2 in the width direction E.

[0039] Figure 3 yes Figure 1 2 is an enlarged view of a region P in FIG. 1 , and is a plan view illustrating an example of a schematic configuration of the cut portion 2 and the main circuit portion 3 adjacent to the cut portion 2 illustrated in the first embodiment.

[0040] like Figure 3 and 4AAs described in the figure, the metal pad 4 is arranged in the cut portion 2. The cut portion 2 includes an undescribed test element group (hereinafter referred to as TEG), which is used to measure the properties of the electrical characteristics of the manufactured semiconductor device 1, for example. The metal pad 4 is electrically connected to the TEG to measure the electrical characteristics of the TEG. During the measurement of the TEG, the electrical characteristics of the TEG are measured by making a measurement probe connected to a measuring instrument abut the metal pad 4. The metal pad 4 contains a conductive material. For example, the metal pad 4 contains a metal such as aluminum (Al). The metal pad 4 may also contain a barrier metal arranged above and below the metal electrode. The metal pad 4 is contained in the intermediate metal layer 39 described later. In an embodiment, the metal pad 4 is contained in the third metal wiring layer 44, and the third metal wiring layer 44 is contained in the uppermost layer of the intermediate metal layer 39.

[0041] Figure 4A A longitudinal section of the cut portion 2 in a portion in which one of the metal pads 4 is disposed is illustrated. Figure 4B The longitudinal section of the cut portion 2 is shown in FIG. 1 , in which one of the metal pads 4 is not disposed. Figure 4A and 4B As described in the figure, the semiconductor device 1 is provided with a semiconductor substrate 14, a low-k insulating film 17 provided on the semiconductor substrate 14, a first metal wiring layer 40 and a second metal wiring layer 42 provided so as to be surrounded by the low-k insulating film 17 at their respective bottoms and sides, and a first connection portion 41 connecting the first metal wiring layer 40 and the second metal wiring layer 42. It should be noted that the semiconductor substrate 14 herein is assumed to include various elements and conductive interconnects forming a DRAM provided on a semiconductor wafer, and an insulating film covering these elements.

[0042] In addition, on the low-k insulating film 17, the semiconductor device 1 is provided with a third metal wiring layer 44, a second connection portion 43 connecting the second metal wiring layer 42 and the third metal wiring layer 44, an uppermost metal layer 46, and a second connection portion 45 connecting the third metal wiring layer 44 and the uppermost metal layer 46. The first metal wiring layer 40, the first connection portion 41, the second metal wiring layer 42, the second connection portion 43, and the third metal wiring layer 44 contain metal.

[0043] Each main circuit portion 3 is provided with a stacked structure 47 formed by stacking a first metal wiring layer 40, a first connection portion 41, a second metal wiring layer 42, a second connection portion 43, a third metal wiring layer 44, a second connection portion 45 and an uppermost metal layer 46. Before slicing, the metal wiring layers 40, 42, 43 and 44, the connection portions 41 and 43, and the low-k insulating film 17 are removed in the slicing area using laser grooving. At this time, the stacked structure 47 is arranged to protect the main circuit portion 3 from heat and vibration. In addition, a function of suppressing cracks generated during slicing from propagating into the main circuit portion 3 is also provided. The stacked structure 47 is arranged in the main circuit portion 3. The stacked structure 47 is arranged on a straight line along the boundary between the slicing portion 2 and each main circuit portion 3.

[0044] The uppermost metal layer 46 is, for example, a redistribution layer, and contains interconnects that are added, for example, to redistribute the terminals in the case of a package configuration with solder bumps and flip-chip connections. The redistribution layer is normally disposed in the uppermost portion of the semiconductor device 1. The redistribution layer requires a low resistance value and is therefore thick. For example, the uppermost metal layer 46 contains a metal such as aluminum (Al).

[0045] On the semiconductor substrate 14 in the cut portion 2, a low-k insulating film 17 and an insulating film 6 are stacked in the above order going upward from the semiconductor substrate 14. Herein, a low-k insulating film means a film having a lower dielectric constant (k) than a silicon oxide film used between a Cu interconnect and a silicon nitride film deposited on the Cu interconnect to prevent Cu diffusion. The insulating film 6 is disposed in the cut portion 2 and has a thickness T1. The insulating film 6 is disposed to include at least a cutout portion 9 disposed in the central portion of the cut portion 2. A portion of the insulating film 6 covers the peripheral portion of the metal pad 4. The area in which the insulating film 6 is disposed is referred to as part C. An opening 8 is formed in the central portion of each metal pad 4. The top surface of the opening 8 is exposed and is not covered by the insulating film 6. The area in which the opening 8 is formed is referred to as part A.

[0046] In each main circuit portion 3, an insulating film 26 covering the low-k insulating film 17 is provided. In addition, a third metal wiring layer 44, an uppermost metal layer 46, and a second connection portion 45 connecting the third metal wiring layer 44 and the uppermost metal layer 46 are provided above the low-k insulating film 17. The uppermost metal layer 46 is provided on the insulating film 26. The top surface of the insulating film 26 is positioned at the bottom surface of the uppermost metal layer 46. The insulating film 26 has a thickness T2. The insulating film 26 covers each main circuit portion 3. The region in which the insulating film 26 is provided is referred to as a portion B. The thickness T1 of the insulating film 6 is smaller than the thickness T2 of the insulating film 26. In each main circuit portion 3, an insulating film 28 covering the upper portion of the uppermost metal layer 46 included in the stacked structure 47 and the insulating film 26, and a polyimide film 30 covering the top surface of the insulating film 28 are provided. For example, the insulating film 28 includes a silicon nitride film.

[0047] Figure 5A 1 is a longitudinal section illustrating an example of a schematic configuration of a DRAM memory cell area in one of the main circuit portions 3. Figure 5B 1 is a longitudinal section illustrating an example of a schematic configuration of a DRAM peripheral circuit area in one of the main circuit portions 3. Figure 5A and 5B As described in FIG. 1 , the main circuit portion 3 is provided with various elements and conductive interconnections forming the DRAM.

[0048] exist Figure 5A Components such as an insulating film 12, a memory element 34, an insulating film 16, a first metal wiring layer 40, a second metal wiring layer 42, low-k insulating films 18, 20, 22, and 24, a third metal wiring layer 44, an insulating film 26, an uppermost metal layer 46, an insulating film 28, and a polyimide film 30 are provided on a silicon substrate 10. The low-k insulating films 18, 20, 22, and 24 are provided between the first metal wiring layer 40 and the second metal wiring layer 42, along the sides of the first metal wiring layer 40 and the second metal wiring layer 42, below the first metal wiring layer 40 and the second metal wiring layer 42, and above the first metal wiring layer 40 and the second metal wiring layer 42. The memory element 34 includes components such as a selection transistor 32 and a capacitor 33.

[0049] exist Figure 5BIn the present invention, components such as the insulating film 12, the peripheral circuit transistor 50, the contact region 50a, the metal film 50b, the metal film 50c, the connection electrode 52, the insulating film 16, the first metal wiring layer 40, the first connection portion 41, the second metal wiring layer 42, the low-k insulating films 18, 20, 22 and 24, the second connection portion 43, the third metal wiring layer 44, the insulating film 26, the uppermost metal layer 46, the insulating film 28 and the polyimide film 30 are provided on the silicon substrate 10. The low-k insulating films 18, 20, 22 and 24 are provided between the first metal wiring layer 40 and the second metal wiring layer 42 and are provided along the sides of the first metal wiring layer 40 and the second metal wiring layer 42. The peripheral circuit transistor 50 is electrically connected to the first metal wiring layer 40 through the contact region 50a, the metal film 50b, the metal film 50c and the connection electrode 52.

[0050] The insulating film 16 is an interlayer insulating film disposed between the memory element 34 and the peripheral circuit transistor 50 and the first metal wiring layer 40. The insulating film 26 is an interlayer insulating film disposed between the third metal wiring layer 44 and the uppermost metal layer 46. Herein, the first metal wiring layer 40, the second metal wiring layer 42, and the third metal wiring layer 44 are referred to as the intermediate metal layer 39 with respect to the uppermost metal layer 46. In the cut portion 2, the metal pad 4 is included in the third metal wiring layer 44. The metal pad 4 is included in the uppermost layer of the intermediate metal layer 39 (i.e., the third metal wiring layer 44).

[0051] In the first embodiment, the low-k insulating film 17 includes, for example, a laminated film of a first low-k insulating film 18, a second low-k insulating film 20, a third low-k insulating film 22, and a fourth low-k insulating film 24. For example, the first low-k insulating film 18 and the third low-k insulating film 22 contain a carbon-doped silicon oxide film (SiOC film). For example, the second low-k insulating film 20 and the fourth low-k insulating film 24 are films capable of preventing Cu diffusion, and contain a nitrogen-doped silicon carbide film (SiCN film). SiOC and SiCN are given as examples, and some other low-k insulating materials with a low dielectric constant can be used as the low-k insulating film 17. Moreover, the low-k insulating film 17 is not necessarily limited to the above configuration, and may also be a laminated film containing even more low-k insulating films. The above configuration is also similar in the second, third, and fourth embodiments described later.

[0052] The semiconductor device 1 includes a semiconductor substrate 14. The semiconductor device 1 includes a multi-level wiring structure on the semiconductor substrate 14. The multi-level wiring structure includes an intermediate metal layer 39 above the semiconductor substrate 14 and an uppermost metal layer 46 above the intermediate metal layer 39. The multi-level wiring structure is divided into a main circuit portion 3 and a cutout portion 2 surrounding the main circuit portion 3. The cutout portion 2 of the multi-level wiring layer includes a metal pad 4 exposed on the surface in the intermediate metal layer 39. The metal pad 4 is included in the third metal layer 44 as the uppermost layer of the intermediate metal layer 39.

[0053] Next, we will refer to Figure 4A and 4B as well as Fig. 6A and 6B arrive Fig.11A and 11B A method for forming a semiconductor device 1 according to a first embodiment is described. The following describes a case where a negative photoresist is used. First, as Fig. 6A and 6B As described above, a first metal wiring layer 40, a first connection portion 41, a second metal wiring layer 42, and a low-k insulating film 17 covering these layers are formed over a semiconductor substrate 14 including a cut portion 2 and a main circuit portion 3. The low-k insulating film 17 is Figure 5A and 5B As described above, the semiconductor substrate 14 includes the various elements and conductive interconnections forming the DRAM provided on the semiconductor wafer, and the insulating film covering these elements.

[0054] In the cut portion 2, a metal pad 4 including a second connection portion 43 and a third metal wiring layer 44 is formed on top of the low-k insulating film 17. In each main circuit portion 3, a second connection portion 43 and a third metal wiring layer 44 included in a stacked structure 47 are formed. Next, after the insulating film 26 is formed, in each main circuit portion 3, a second connection portion 45 is formed to reach the third metal wiring layer 44, and an uppermost metal layer 46 is formed on the second connection portion 45. In addition, an insulating film 28 is formed to cover the cut portion 2 and the top surface of the insulating film 26 on the main circuit portion 3 and the uppermost metal layer 46 of the main circuit portion 3.

[0055] For example, these metal wiring layers and insulating films are formed by chemical vapor deposition. For example, the insulating film 26 contains a silicon oxide (SiO2) film. For example, the first metal wiring layer 40, the first connecting portion 41 and the second metal wiring layer 42 contain copper (Cu). For example, the second connecting portion 45 and the uppermost metal layer 46 contain aluminum (Al). The main circuit portion 3 is placed on either side of the cut portion 2.

[0056] Next, if Fig. 7A and 7B As described in , by applying a photoresist and then performing exposure and development processes, a photoresist pattern 55 in which an opening 55c is patterned is formed. The photoresist pattern 55 also includes a photoresist pattern 55a having a large resist thickness and a photoresist pattern 55b having a small resist thickness.

[0057] The opening 55c is formed to correspond to the opening 8 of the metal pad 4, and the resist in the opening 55c is removed. For example, the photoresist pattern 55 contains a negative photosensitive resin. When the negative photoresist pattern 55 is irradiated with light of a predetermined exposure value or greater in the photolithography step, all or almost all of the applied photoresist is cured, and a photoresist pattern 55a having a thickness S2 is formed. On the other hand, when the negative photoresist pattern 55 is irradiated with light of an exposure value less than the predetermined exposure value in the photolithography step, the thickness of the cured photoresist is reduced, and a photoresist pattern 55b having a thickness S1 is formed. The thickness S2 is greater than the thickness S1.

[0058] By controlling the exposure value in this way, the thickness of the photoresist can be controlled. In the case where the photoresist is a negative type, reducing the exposure value causes the thickness of the photoresist to become less than the applied thickness.

[0059] Figure 8 It is used for Fig. 7A and 7B An enlarged partial plan view of a schematic configuration of a photomask 66 in the photolithography step described in FIG. Fig. 8A , 8B 8C are partial longitudinal cross sections illustrating a schematic configuration of portions A1, B1, and C1 of the photomask 66, and illustrate a corresponding relationship between the semiconductor substrate 14 corresponding to the portions A1, B1, and C1 and the photoresist patterns 55a and 55b formed on the semiconductor substrate 14. Arrow 53 represents light from a light source, and arrows 54a and 54b represent transmitted light having passed through the photomask 66. The transmitted light represented by the arrows 54a and 54b irradiates the resist on the semiconductor substrate 14.

[0060] like Fig. 8AAs illustrated in FIG. 5 , a portion A1 of a photomask 66 is provided with a glass substrate 60, a halftone material 62, and a light shielding member 61. In portion A1, the light designated by the arrow 53 is shielded by the light shielding member 61, and thus the resist on the semiconductor substrate 14 is not irradiated with light. For example, the light shielding member 61 contains a light shielding material, and the light shielding material contains chromium (Cr) or chromium oxide. The light shielding member 61 shields light with a transmittance of substantially 0%. For example, the glass substrate 60 contains a transparent material such as quartz glass. The glass substrate 60 allows light to be transmitted through with no reduction or minimal reduction. The glass substrate 60 allows light to pass through with a transmittance of substantially 100%. The halftone material 62 is a semi-transparent film having a transmittance greater than 0% and less than 100%. For example, the halftone material 62 contains a material such as molybdenum (Mo), chromium (Cr), silicon (Si), and a nitride thereof.

[0061] like Figure 8B , the portion B1 includes the glass substrate 60. In the portion B1, since the halftone material 62 and the light shielding member 61 are not provided, the light indicated by the arrow 53 passes through the portion B1 and becomes the light indicated by the arrow 54a with little or no reduction, and irradiates the photoresist of the semiconductor substrate 14. By irradiating the photoresist on the semiconductor substrate 14 with the light indicated by the arrow 54a, a photoresist pattern 55a having a thickness S2 is formed.

[0062] like Figure 8C As illustrated in FIG. 1 , the portion C1 includes a glass substrate 60 and a halftone material 62. Light passing through the halftone material 62 is reduced. The light transmittance of the halftone material 62 can be controlled by adjusting properties such as the composition ratio of materials contained in the halftone material 62 and the thickness of the halftone material 62. Since the halftone material 62 is provided in the portion C1, the halftone material 62 reduces the light indicated by the arrow 53 to become the light indicated by the arrow 54b, and irradiates the resist on the semiconductor substrate 14 with the light indicated by the arrow 54b. By irradiating the resist on the semiconductor substrate 14 with the light indicated by the arrow 54b, a photoresist pattern 55b having a thickness S1 is formed.

[0063] The transmittance of portion A1 of the photomask 66 is lower than that of portion C1. The transmittance of portion B1 is higher than that of portion C1. The thickness S2 of the photoresist pattern 55a on the semiconductor substrate 14 corresponding to portion B1 is greater than the thickness S1 of the photoresist pattern 55b on the semiconductor substrate 14 corresponding to portion C1.

[0064] Fig.8D and 8E A portion C2 according to a modification of the portion C1 of the photomask 66 will be described. Fig.8DAs shown in FIG. 1 , portion C2 includes a glass substrate 60 and a light-transmitting portion 63. Fig.8D and 8E As described in FIG. 1 , the light transmission portion 63 includes a light shielding portion 64 and an open portion 65. The light shielding portion 64 contains the same material as the light shielding member 61 of the portion A1 and shields light. The open portion 65 is a region where the light shielding portion 64 does not exist and allows light to pass through. By controlling the area ratio of the light shielding portion 64 and the open portion 65, the light transmittance of the light transmission portion 63 can be controlled. Fig. 8E In the embodiment, the light shielding portion 64 has a staggered arrangement but may also have a matrix arrangement. The light indicated by the arrow 53 passes through the portion C2 and is reduced after passing through and becomes the light indicated by the arrow 54d. The resist on the semiconductor substrate 14 is irradiated with the light indicated by the arrow 54d. By irradiating the resist on the semiconductor substrate 14 with the light indicated by the arrow 54d, a photoresist pattern 55b having a thickness S1 is formed. Fig.8D The photomask illustrated in includes a glass substrate 60 and a light shielding member 61. Since the halftone material 62 is not used, the cost of the photomask can be reduced.

[0065] The transmittance of portion A1 of the photomask 66 is lower than the transmittance of portion C2. The transmittance of portion B1 is higher than the transmittance of portion C2. The thickness S2 of the photoresist pattern 55a on the semiconductor substrate 14 corresponding to portion B1 is greater than the thickness S1 of the photoresist pattern 55b on the semiconductor substrate 14 corresponding to portion C2.

[0066] exist Fig. 7A and 7B In the photolithography step described in the above, a photomask 66 provided with the above-mentioned portions A1, B1 and C1 is used. Fig. 7A and 7B As illustrated, portion A1 of the photomask 66 is disposed in a corresponding relationship with portion A, that is, disposed in a region on the semiconductor substrate 14 in which the opening 8 is formed. Since light is shielded by portion A1 of the photomask 66, the photoresist does not remain in portion A, that is, does not remain in the region in which the opening 8 is formed. Thus, the opening 55c is formed.

[0067] The portion B1 of the photomask 66 is disposed in a corresponding relationship with the portion B, that is, disposed in a region on the semiconductor substrate 14 where the insulating film 26 is formed. In the portion B, that is, in the region where the insulating film 26 is formed, the light passing through the portion B1 of the photomask 66 is not reduced, and thus the exposure value is increased and a photoresist pattern 55a having a greater thickness S2 is formed. The portion C1 of the photomask 66 is disposed in a corresponding relationship with the portion C, that is, disposed in a region on the semiconductor substrate 14 where the insulating film 6 is formed. In the portion C, that is, in the region where the insulating film 6 is formed, the exposure value due to the transmitted light is reduced, and thus a photoresist pattern 55b having a thickness S1 less than the thickness S2 is formed. It should be noted that the portion C2 of the photomask 66 is disposed in a corresponding relationship with the portion C, that is, disposed in a region on the semiconductor substrate 14 where the insulating film 6 is formed.

[0068] Next, if Fig. 9A and 9B As described in , anisotropic dry etching is performed on the insulating film 28 and the insulating film 26 using the photoresist pattern 55 as an etching mask. With this arrangement, the insulating film 28 and the insulating film 26 are etched in the portion A, that is, in the region in which the opening 8 is formed. At this time, the etching is controlled so that the insulating film 6b remains on the metal pad 4. Since the photoresist pattern 55b is not as thick as the portion C, that is, the region in which the insulating film 6 is provided, the photoresist pattern 55b is partially eliminated by etching. After the photoresist pattern 55b is eliminated, the insulating film 28 and the insulating film 26 in the portion C are etched, and the insulating film 6a which is thicker than the insulating film 6b but thinner than the insulating film 26 is formed.

[0069] Next, if Fig. 10A and 10B As described in , the photoresist pattern 55 is removed. For example, the photoresist pattern 55 is removed by ashing using oxygen plasma. Next, as Fig.11A and 11B As described in the figure, the polyimide film 30 is formed to cover the portion B. For example, the polyimide film 30 contains a negative photosensitive resin. The polyimide film 30 is patterned as follows. A pre-treated polyimide varnish is dropped onto the semiconductor substrate 14 and applied by spin coating, and a soft bake is performed to evaporate an unnecessary solvent. Next, the polyimide is patterned by performing an exposure and development process.

[0070] Next, if Figure 4A and 4BAs described in , anisotropic etching is performed on the insulating films 6a and 6b using the polyimide film 30 as an etching mask. By this etching, the insulating film 6b on the top of the metal pad 4 is removed, and the surface of the metal pad 4 is exposed. Moreover, in the portion C, the thickness of the insulating film 6a is reduced by etching, and the insulating film 6 having a thickness S2 is formed. The portion C is also disposed in the peripheral portion of the metal pad 4. For this reason, the insulating film 6a is also provided on the peripheral portion of the metal pad 4. Through the above steps, the semiconductor device 1a according to the first embodiment is formed.

[0071] According to the semiconductor device 1 a and the method of forming the same according to the first embodiment, the following effects are exhibited.

[0072] The metal pad 4 provided in the diced portion 2 is included in the third metal wiring layer 44, which is part of the intermediate metal layer 39. The metal pad 4 is not formed by the thick uppermost metal layer 46, but is instead formed by the thin third metal wiring layer 44. By this arrangement, the generation of cracks in the dicing step is suppressed. Moreover, the thickness of the insulating film 6 formed in the portion C of the diced portion 2 is reduced. This also suppresses the generation of cracks in the dicing step.

[0073] In addition, a stacked structure 47 is provided in the main circuit portion 3 along the boundary with the dicing portion 2. The first metal wiring layer 40, the first connection portion 41, and the second metal wiring layer 42 are provided with a low-k insulating film 17 between and on the sides thereof. Before slicing, the metal wiring layers 40, 42, 43, and 44, the connection portions 41 and 43, and the low-k insulating film 17 are removed in the slicing area using laser grooving. At this time, the stacked structure 47 is provided to protect the main circuit portion 3 from heat and vibration. In addition, it is possible to suppress cracks generated during slicing from propagating into the main circuit portion 3.

[0074] In the photoresist pattern 55, a photoresist pattern 55a having a thickness S2 and a photoresist pattern 55b having a thickness S1 less than the thickness S2 are formed. The photoresist pattern 55 acts as an etching mask in the step of etching the insulating film 26. The photoresist pattern 55a having a thickness S2 and the photoresist pattern 55b having a thickness S1 less than the thickness S2 are achieved as follows. The photomask 66 used in the exposure of the resist is provided with portions A1, B1, and C1 having different transmittances. Portion A1 is provided with a glass substrate 60, a halftone material 62, and a light shielding member 61 for shielding light. Portion B1 is provided with a glass substrate 60 to allow light to pass through. Portion C1 is provided with a glass substrate 60 and a halftone material 62 to allow a portion of light to pass through.

[0075] Light transmittance has the following relationship:

[0076] The transmittance of the portion B1 > the transmittance of the portion C1 > the transmittance of the portion A1 .

[0077] Portion A1 of the photomask 66 is disposed on the semiconductor substrate 14 in a corresponding relationship with portion A. Since portion A of the semiconductor substrate 14 is not irradiated with light, no resist pattern is formed. Portion B1 of the photomask 66 is disposed on the semiconductor substrate 14 in a corresponding relationship with portion B. A photoresist pattern 55a having a thickness S2 is formed in portion B of the semiconductor substrate 14. Portion C1 of the photomask 66 is disposed on the semiconductor substrate 14 in a corresponding relationship with portion C. Since portion C of the semiconductor substrate 14 is irradiated with a portion of light passing through portion C1, a photoresist pattern 55b having a thickness S1 that is smaller than thickness S2 is formed.

[0078] Moreover, at this time, the photoresist pattern 55b having a thickness S1 is set to a thickness that allows the photoresist pattern 55b to be partially eliminated by the insulating film etching step. The photoresist pattern 55a having a thickness S2 is set to a thickness that allows the photoresist pattern 55a to not be eliminated and remain after the insulating film etching step. By this arrangement, insulating films 26 and 6 having different residual thicknesses can be formed. In this way, according to the first embodiment, resist patterns having different thicknesses can be formed by a single photolithography step. In addition, by this arrangement, a semiconductor device 1a having insulating films 26 and 6 having different thicknesses can be set by a single photolithography step. Because the number of steps is reduced, it is possible to provide a semiconductor device 1a at a reduced cost.

[0079] (Second embodiment)

[0080] In the following, reference will be made to Fig. 6A and 6B , Figure 8 and 8A to 8C and Fig. 12A and 12B arrive Fig.15A and 15B A semiconductor device 1b and a method for forming the same according to the second embodiment are described. Note that, Figure 1 , 2 The items described in , 3, 5A and 5B also apply to the second embodiment.

[0081] like Fig. 12A and 12BAs described in the figure, in the semiconductor device 1b according to the second embodiment, similarly to the semiconductor device 1a according to the first embodiment, the metal pad 4 provided in the cut portion 2 is included in the third metal wiring layer 44 which is part of the intermediate metal layer 39. The metal pad 4 is not formed by the thick uppermost metal layer 46 but is formed by the thin third metal wiring layer 44 instead.

[0082] Moreover, the thickness of the insulating film 6 formed in the portion C of the scribe portion 2 is reduced. In addition, each main circuit portion 3 is provided with a stacked structure 47 including a first metal wiring layer 40, a first connection portion 41, a second metal wiring layer 42, a second connection portion 43, a third metal wiring layer 44, a second connection portion 45, and an uppermost metal layer 46 at a position close to the scribe portion 2. The first metal wiring layer 40, the first connection portion 41, and the second metal wiring layer 42 are provided with a low-k insulating film 17 therebetween and on the sides thereof. The rest of the configuration is substantially the same as that of the semiconductor device 1a according to the first embodiment.

[0083] Will refer to Fig. 12A and 12B arrive Fig.15A and 15B , Fig. 6A and 6B as well as Figure 8 and 8A 8C describe a method of forming the semiconductor device 1b according to the second embodiment.

[0084] First, similar to the first embodiment, Fig. 6A and 6B Next, Fig.13A and 13B As described in the embodiment, the polyimide film 30 is formed to cover the stacked structure 47 and the main circuit portion 3. For example, the polyimide film 30 contains a negative photosensitive resin. The patterning method of the polyimide film 30 is similar to that of the first embodiment.

[0085] Next, if Fig.14A and 14B As described in FIG. 5 , a photoresist pattern 55 covering portions B and C is formed. The photoresist pattern 55 is provided with a photoresist pattern 55a having a large resist thickness and a photoresist pattern 55b having a small resist thickness. In addition, the photoresist pattern 55 is provided with an opening 55c. For example, the photoresist pattern 55 contains a negative photosensitive resin.

[0086] exist Fig.14A and 14B In the photolithography step described in Figure 8 The photomask 66 provided with the parts A1, B1 and C1 described in FIG. 1 is used as an exposure mask. Fig.14A and 14B , Figure 8 and Figures 8A to 8C , portion A1 of the photomask 66 is disposed in a corresponding relationship with portion A of the semiconductor substrate 14. Since light is shielded by portion A1 of the photomask 66, portion A is not irradiated with light. Therefore, in portion A, the photoresist pattern 55 is not formed, but instead, an opening 55c is formed.

[0087] The portion B1 of the photomask 66 is disposed in a corresponding relationship to the portion B of the semiconductor substrate 14. In the portion B, the light passing through the portion B1 of the photomask 66 is not reduced, and thus the exposure value is increased and the photoresist pattern 55a having a greater thickness S2 is formed. The portion C1 of the photomask 66 is disposed in a corresponding relationship to the portion C of the semiconductor substrate 14. In the portion C, the exposure value becomes smaller due to the reduction of the transmitted light, and thus the photoresist pattern 55b having a thickness S1 less than the thickness S2 is formed.

[0088] Next, if Fig.15A and 15B As described in , anisotropic dry etching is performed on the insulating film 28 and the insulating film 26 using the photoresist pattern 55 as an etching mask. With this arrangement, in the portion A, the insulating film 28 and the insulating film 26 are etched. At this time, the etching is controlled so that the insulating film 6b remains on the metal pad 4. Since the photoresist pattern 55b is not as thick as the portion C, the photoresist pattern 55b is partially eliminated by etching. After the photoresist pattern 55b is eliminated, the insulating film 28 and the insulating film 26 in the portion C are etched, and the insulating film 6a thicker than the insulating film 6b but thinner than the insulating film 26 is formed.

[0089] Next, if Fig. 12A and 12B As described in , the photoresist pattern 55 is removed. For example, the photoresist pattern 55 is removed by a solvent thinned after, for example, plasma treatment with a gas containing oxygen. The polyimide film 30 is not removed. Through the above steps, the semiconductor device 1b according to the second embodiment is formed.

[0090] According to the semiconductor device 1 b and the method of forming the same according to the second embodiment, effects similar to those of the semiconductor device 1 a and the method of forming the same according to the first embodiment can be obtained.

[0091] (Third Embodiment)

[0092] In the following, reference will be made to Fig. 6A and 6B , Figure 8 and 8A to 8C and Fig.16A and 16B arrive Fig.22A and 22B A semiconductor device 1c and a method for forming the same according to the third embodiment are described. Note that, Figure 1 , 2 The items described in , 3, 5A and 5B also apply to the third embodiment.

[0093] In the semiconductor device 1c according to the third embodiment, the portion D is provided between the portion C (i.e., the region in which the insulating film 6 is provided) and the portion B (i.e., the region in which the insulating film 26 is formed). A groove 70 is provided in the portion D. The groove 70 is arranged in the cut portion 2. The groove 70 is arranged between the metal pad 4 and the main circuit portion 3. The groove 70 is arranged in the cut portion 2 along the boundary between the cut portion 2 and the main circuit portion 3. The groove 70 is arranged to extend substantially parallel to the longitudinal direction F of the cut portion 2. The groove 70 provided in the portion D has a rectangular cross section and penetrates the low-k insulating film 17 from the top surface of the insulating film 6. The bottom surface 70a of the groove 70 is positioned below the bottom surface of the low-k insulating film 17. The low-k insulating film 17 is penetrated by the groove 70 and divided along the width direction E. The remaining parts of the configuration are similar to the semiconductor devices 1a and 1b according to the first and second embodiments.

[0094] Next, a method of forming the semiconductor device 1c according to the third embodiment will be described. In the description of the third embodiment, the second opening 55c is denoted by using symbol 55c.

[0095] First, similar to the first embodiment, Fig. 6A and 6B Next, Fig.17A and 17B As described in the figure, a photoresist pattern 55 covering the portions B and C is formed. The photoresist pattern 55 is provided with a photoresist pattern 55a having a large resist thickness and a photoresist pattern 55b having a small resist thickness. The photoresist pattern 55 is provided with a first opening 55d between the photoresist pattern 55a and the photoresist pattern 55b. In addition, the photoresist pattern 55 is provided with a second opening 55c. For example, the photoresist pattern 55 contains a negative photosensitive resin. The first opening 55d corresponds to the groove 70. The second opening 55c corresponds to the opening 8 on the metal pad 4.

[0096] exist Fig.17A and 17B In the photolithography step described in Fig. 17C The photomask 67 of the parts A1, B1 and C1 described in FIG. 1 is used as an exposure mask. Figures 8A to 8C The structures of parts A1, B1 and C1 are described in FIG. Fig.17A , 17B, 17C and 8A to 8C, the portion A1 of the photomask 67 is disposed on the semiconductor substrate 14 in a corresponding relationship with the portion A in which the opening 8 is formed and the portion D in which the groove 70 is formed. Since light is shielded by the portion A1 of the photomask 67, the portion A in which the opening 8 is formed and the portion D in which the groove 70 is formed are not irradiated with light. For this reason, the photoresist pattern 55 is not formed, and the first opening 55d and the second opening 55c are formed.

[0097] The portion B1 of the photomask 67 is disposed in a corresponding relationship to the portion B of the semiconductor substrate 14. In the portion B, the light passing through the portion B1 of the photomask 67 is not reduced, and thus the exposure value is increased and the photoresist pattern 55a having a larger thickness is formed. The portion C1 of the photomask 67 is disposed in a corresponding relationship to the portion C of the semiconductor substrate 14. In the portion C, the exposure value becomes smaller due to the reduction of the transmitted light, and thus the photoresist pattern 55b having a thickness smaller than that of the photoresist pattern 55a is formed.

[0098] Next, if Fig.18A and 18B , anisotropic dry etching is performed on the insulating film 28 and the insulating film 26 using the photoresist pattern 55 as an etching mask. With this arrangement, since the resist serving as an etching mask does not exist in the portion D, that is, does not exist in the region in which the first opening 55d is formed, the insulating film 28, the insulating film 26, and the low-k insulating film 17 are sequentially etched. The etching is performed so as to etch the film material up to the bottom surface of the low-k insulating film 17. In this way, a trench 70c reaching the bottom surface of the low-k insulating film 17 is formed in the portion D.

[0099] Since the resist serving as an etching mask does not exist in the portion A, the insulating film 28 and the insulating film 26 are etched, and the second opening 55c is formed. At this time, etching progresses little or not at all on the metal pad 4. For this reason, etching ends in a state in which the insulating film 26 on the metal pad 4 has been removed, exposing the top surface of the metal pad 4. Since the photoresist pattern 55b is thinner in the portion C, the photoresist pattern 55b is partially eliminated by etching. In the portion C, etching of the insulating film 28 and the insulating film 26 is not performed when the photoresist pattern 55b is present. After eliminating the photoresist pattern 55b, etching of the insulating film 28 and the insulating film 26 in the portion C continues, and an insulating film 6a thinner than the insulating film 26 in the portion B is formed.

[0100] Next, if Fig.19A and 19B As described in , the photoresist pattern 55 is removed. For example, the photoresist pattern 55 is removed by ashing using oxygen plasma. Next, as Fig. 20Aand 20B As described in FIG. 1 , a polyimide film 30 is formed in the portion B. Thereafter, as Fig.16A and 16B As described in the above, if the insulating film is etched using the polyimide film 30 as an etching mask, the thickness of the insulating film 6a is reduced and the insulating film 6 is formed. In addition, a trench 70 having a bottom surface 70a deeper than the bottom surface of the low-k insulating film 17 is formed. Through the above steps, the semiconductor device 1c according to the third embodiment is formed.

[0101] According to the semiconductor device 1c and the method of forming the same according to the third embodiment, effects similar to those of the semiconductor devices 1a and 1b and the method of forming the same according to the first and second embodiments can be obtained.

[0102] In the following, reference will be made to Fig.21A , 21B , 22A and 22B describe variations of the third embodiment. Fig.21A and 21B Description Fig.19A and 19B A modification of the third embodiment extends the formation area of ​​the polyimide film 30 to the groove 70c. Fig.21A and 21B As described in FIG. 1 , the polyimide film 31 is formed to cover the portion B and the portion D. The rest of the configuration is similar to that of FIG. Fig. 20A and 20B .

[0103] Next, if Fig.22A and 22B As described in the above, by etching the insulating film using the polyimide film 31 as an etching mask, the thickness of the insulating film 6a is reduced. Fig.16A and 16B As described in the above, a semiconductor device 1d according to the modification of the third embodiment is formed. According to the semiconductor device 1d and the method for forming the same according to the modification of the third embodiment, effects similar to those of the semiconductor device 1a and the method for forming the same according to the first embodiment are obtained.

[0104] Moreover, an extremely high exposure value is necessary in the polyimide exposure for removing the polyimide film inside the groove 70c. According to the semiconductor device 1d and the method for forming the same according to the modification of the third embodiment, by burying the polyimide film inside the groove 70c, an extremely high exposure value for removing the polyimide inside the groove 70c in the polyimide exposure is not necessary.

[0105] (Fourth embodiment)

[0106] In the following, reference will be made to Fig. 6A and 6B , Figures 8A to 8C , Fig. 17C as well as Fig.23A and 23B arrive Fig.26A and 26B The semiconductor device 1e according to the fourth embodiment and its forming method are described. It should be noted that Figure 1 , 2 The items described in , 3, 5A and 5B also apply to the fourth embodiment.

[0107] like Fig.23A and 23B As described in FIG. 4 , the configuration of the semiconductor device 1 e according to the fourth embodiment is similar to that of the semiconductor device 1 c according to the third embodiment.

[0108] Next, we will refer to Fig.23A and 23B arrive Fig.26A and 26B , Fig. 6A and 6B as well as Figure 8 and 8A 8C describe a method of forming the semiconductor device 1e according to the fourth embodiment. In the description of the fourth embodiment, the symbol 55c is used to refer to the second opening 55c.

[0109] First, similar to the first embodiment, Fig. 6A and 6B Next, Fig.24A and 24B As described in FIG. 1 , the polyimide film 30 is formed to cover the stacked structure 47 and the main circuit portion 3. The method of forming the polyimide film 30 is similar to that of the first embodiment.

[0110] Next, if Fig.25A and 25B As described in the figure, a photoresist pattern 55 covering the portions B and C is formed. The photoresist pattern 55 is provided with a photoresist pattern 55a having a large resist thickness and a photoresist pattern 55b having a small resist thickness. The photoresist pattern 55 is provided with a first opening 55d between the photoresist pattern 55a and the photoresist pattern 55b. In addition, the photoresist pattern 55 is provided with a second opening 55c. For example, the photoresist pattern 55 contains a negative photosensitive resin. The first opening 55d corresponds to the groove 70. The second opening 55c corresponds to the opening 8 on the metal pad 4.

[0111] exist Fig.25A and 25B In the photolithography step described in Fig. 17C The photomask 67 provided with the portions A1, B1, and C1 described in FIG. 1 is used as an exposure mask. The configuration of the photomask 67 is similar to that of the photomask 67 in the third embodiment.

[0112] like Fig.25A and 25B , Fig. 17C as well as Figures 8A to 8C , the portion A1 of the photomask 67 is disposed on the semiconductor substrate 14 in a corresponding relationship with the portion A in which the opening 8 is formed and the portion D in which the groove 70 is formed. Since light is shielded by the portion A1 of the photomask 67, the portion A in which the opening 8 is formed and the portion D in which the groove 70 is formed are not irradiated with light. For this reason, the photoresist pattern 55 is not formed, and the first opening 55d and the second opening 55c are formed.

[0113] The portion B1 of the photomask 67 is disposed in a corresponding relationship to the portion B of the semiconductor substrate 14. In the portion B, the light passing through the portion B1 of the photomask 67 is not reduced, and thus the exposure value is increased and the photoresist pattern 55a having a larger thickness is formed. The portion C1 of the photomask 67 is disposed in a corresponding relationship to the portion C of the semiconductor substrate 14. In the portion C, the exposure value becomes smaller due to the reduction of the transmitted light, and thus the photoresist pattern 55b having a thickness smaller than that of the photoresist pattern 55a is formed.

[0114] Next, if Fig.26A and 26B , anisotropic dry etching is performed on the insulating film 28 and the insulating film 26 using the photoresist pattern 55 as an etching mask. Since the resist serving as an etching mask does not exist in the portion D, the insulating film 28, the insulating film 26, and the low-k insulating film 17 are sequentially etched. The etching is performed so as to etch the film material up to the bottom surface of the low-k insulating film 17. In this way, a trench 70d reaching the bottom surface of the low-k insulating film 17 is formed in the portion D.

[0115] Since the resist serving as an etching mask does not exist in the portion A, the etching of the insulating film 28 and the insulating film 26 continues. At this time, the etching progresses little or not at all on the metal pad 4. For this reason, the etching ends in a state in which the insulating film 26 on the metal pad 4 has been removed, exposing the top surface of the metal pad 4. Since the photoresist pattern 55b is thinner in the portion C, the photoresist pattern 55b is partially eliminated by etching. In the portion C, the etching of the insulating film 28 and the insulating film 26 is not performed when the photoresist pattern 55b is present. After the photoresist pattern 55b is eliminated, the insulating film 28 and the insulating film 26 in the portion C are etched, and the insulating film 6a thinner than the insulating film 26 in the portion B is formed.

[0116] Next, if Fig.26A and 26BAs described above, the photoresist pattern 55 is removed. For example, the photoresist pattern 55 is removed by a solvent that is thinned after plasma treatment with a gas containing oxygen. Thereafter, the insulating film is etched using the polyimide film 30 as an etching mask. Through the above steps, the thickness of the insulating film 6a is reduced and the insulating film 6 is formed. Fig.23A and 23B In addition, a trench 70 having a bottom surface 70a deeper than the bottom surface of the low-k insulating film 17 is formed. Through the above steps, the semiconductor device 1e according to the fourth embodiment is formed.

[0117] According to the semiconductor device 1e and the method of forming the same according to the fourth embodiment, effects similar to those of the semiconductor device 1a and the method of forming the same according to the first embodiment can be obtained.

[0118] In the embodiments described above, the case of using a negative photoresist is given as an example, but a positive photoresist may also be used. In the case of a positive photoresist, the light pattern and the dark pattern of the photomasks 66 and 67 used as exposure masks are reversed.

[0119] As described above, DRAM is described as an example of a semiconductor device according to various embodiments, but the above description is only an example and is not intended to be limited to DRAM. For example, memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory can also be applied as semiconductor devices. In addition, for example, devices other than memory, including logic ICs such as microprocessors and application-specific integrated circuits (ASICs) are also applicable as semiconductor devices according to the aforementioned embodiments.

[0120] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the present invention and its obvious modifications and use of equivalents. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still fall within the scope of the present invention. It should be appreciated that the various features and aspects of the disclosed embodiments can be combined with each other or replace each other to form a variation pattern of the present invention. Therefore, it is desirable that at least some of the scope of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: Semiconductor substrate; and a multi-level wiring structure located on the semiconductor substrate, the multi-level wiring structure comprising at least an intermediate metal layer located above the semiconductor substrate and an uppermost metal layer located above the intermediate metal layer, and the multi-level wiring structure is divided into a main circuit portion and a cut-out portion surrounding the main circuit portion; wherein the cut portion of the multi-level wiring structure at least includes the exposed metal pads in the intermediate metal layer, and The uppermost metal layer is a redistribution layer, and the metal pad is not covered by the redistribution layer. 2 . The semiconductor device according to claim 1 , further comprising a groove between the metal pad and the main circuit portion in the scribed portion.

3. The semiconductor device according to claim 2, wherein The intermediate metal layer comprises a plurality of layers, The semiconductor device further includes a low-k insulating film between at least some of the plurality of layers of the intermediate metal layer; and The trench at least penetrates the low-k insulating film.

4. The semiconductor device according to claim 1, wherein The intermediate metal layer comprises a plurality of layers, and The metal pad is included in an uppermost layer of the plurality of layers of the intermediate metal layer.

5. The semiconductor device according to claim 1, wherein The intermediate metal layer comprises a plurality of layers, and At least one layer of the plurality of layers of the intermediate metal layer includes copper. 6 . The semiconductor device according to claim 1 , further comprising a stack structure arranged in the main circuit portion along a boundary with the scribed portion, the stack structure including the intermediate metal layer and the uppermost metal layer.

7. The semiconductor device according to claim 3, further comprising an insulating film covering the diced portion and the low-k insulating film over the main circuit portion; and The thickness of the insulating film of the cut portion is smaller than the thickness of the insulating film of the main circuit portion. 8 . The semiconductor device according to claim 7 , wherein the uppermost metal layer is above the insulating film of the main circuit portion.

9. A semiconductor device comprising: a semiconductor substrate having a major surface including a first portion and a second portion; a low-k insulating film covering the first portion and the second portion of the main surface of the semiconductor substrate; a first insulating layer covering the low-k insulating film of the first and second portions of the main surface of the semiconductor substrate; a main circuit portion and a diced portion included in said main surface of said semiconductor substrate; a stacked structure including an uppermost metal layer arranged in the main circuit portion; and a metal liner disposed above the scored portion; wherein the first insulating layer above the first portion has a first thickness, and the first insulating layer above the second portion has a second thickness, and The uppermost metal layer is a redistribution layer, and the metal pad is not covered by the redistribution layer.

10. The semiconductor device according to claim 9, wherein the first portion includes at least a portion of the main circuit portion; wherein the second portion includes at least a portion of the cut portion; and The first thickness of the first insulating layer is greater than the second thickness of the first insulating layer. 11 . The semiconductor device according to claim 9 , further comprising a groove in the scribed portion along a boundary with the main circuit portion. 12 . The semiconductor device according to claim 11 , wherein the trench penetrates at least the low-k insulating film. 13 . The semiconductor device according to claim 9 , wherein the stacked structure includes an intermediate metal layer and the uppermost metal layer arranged in the main circuit portion along a boundary with the scribe portion.

14. The semiconductor device according to claim 10, further comprising: an intermediate metal layer disposed below the uppermost metal layer and comprising a plurality of metal layers above the main circuit portion and the scribe portion, a low-k insulating film covering opposite surfaces and side surfaces of the plurality of metal layers included in the intermediate metal layer, and The metal pad is included in an uppermost layer of the plurality of metal layers of the intermediate metal layer.

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