Array substrate and preparation method thereof

Abstract

The present disclosure provides an array substrate and a preparation method thereof, belonging to the field of display technology. The preparation method of the array substrate includes sequentially forming a stacked base substrate, a driving circuit layer and a functional device layer; wherein the formation of the driving circuit layer includes: forming a conductive seed on one side of the base substrate; forming a removable pattern defining layer on the surface of the conductive seed layer, the removable pattern defining layer is provided with a lead opening, and the lead opening exposes part of the conductive seed layer; using an electroplating process to form an electroplated metal layer located on the surface of the conductive seed layer in the lead opening; removing the removable pattern defining layer; removing the portion of the conductive seed layer not covered by the electroplated metal layer to form a first lead layer. The preparation method makes the electroplating process applicable to any metal wiring layer and improves the morphology of the first lead layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof. Background Art

[0002] For medium and large-sized self-luminous panels, such as medium and large-sized Micro LED display panels, medium and large-sized Mini LED backlight sources or display panels, the long distance between metal leads leads to a serious voltage drop on the metal leads, making it difficult to ensure that sufficient driving current is provided for each current-driven light-emitting device. In the prior art, a seed lead can be first formed on a substrate, and then a copper growth layer is generated on the seed lead using a copper electroplating process, thereby preparing a metal lead with a relatively large thickness and reducing the voltage drop on the metal lead. However, this method is only applicable to directly preparing thick copper metal leads on a substrate, has great limitations in applicability, and is difficult to accurately control the morphology of the prepared metal leads and the uniformity of their thickness, which is not conducive to the uniformity of product characteristics.

[0003] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present disclosure is to provide an array substrate and a method for manufacturing the same, so as to increase the thickness of a portion of a metal wiring layer of the array substrate.

[0005] In order to achieve the above-mentioned invention object, the present disclosure adopts the following technical solutions:

[0006] According to a first aspect of the present disclosure, a method for preparing an array substrate is provided, comprising:

[0007] Providing a substrate;

[0008] forming a driving circuit layer on one side of the base substrate;

[0009] forming a functional device layer on a side of the driving circuit layer away from the base substrate;

[0010] Wherein, forming a driving circuit layer on one side of the base substrate includes: forming at least one first lead layer on one side of the base substrate; forming any one first lead layer includes:

[0011] forming a conductive seed layer on one side of the substrate;

[0012] forming a removable pattern defining layer on a surface of the conductive seed layer away from the base substrate, wherein the removable pattern defining layer is provided with a lead opening, and the lead opening exposes a portion of the conductive seed layer;

[0013] Using an electroplating process, forming an electroplated metal layer located on the surface of the conductive seed layer in the lead opening;

[0014] removing the removable pattern defining layer;

[0015] The portion of the conductive seed layer not covered by the electroplated metal layer is removed.

[0016] In an exemplary embodiment of the present disclosure, forming a removable pattern defining layer on a surface of the conductive seed layer away from the base substrate includes:

[0017] forming a removable insulating material layer on a surface of the conductive seed layer away from the substrate;

[0018] The removable insulating material layer is patterned to form the removable pattern defining layer.

[0019] In an exemplary embodiment of the present disclosure, forming a removable insulating material layer on a surface of the conductive seed layer away from the substrate includes:

[0020] Forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate;

[0021] The patterning operation of the removable insulating material layer includes:

[0022] The photoresist material layer is exposed and developed to form the removable pattern defining layer.

[0023] In an exemplary embodiment of the present disclosure, forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate includes:

[0024] Using a degradable photoresist material, forming a photoresist material layer on the surface of the conductive seed layer away from the substrate, wherein the degradable photoresist material is a photoresist material that can be dissolved in a degradation liquid after curing;

[0025] Removing the removable pattern defining layer includes:

[0026] The removable pattern defining layer is dissolved using the degradation liquid.

[0027] In an exemplary embodiment of the present disclosure, forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate includes:

[0028] Using a negative photoresist material, forming a photoresist material layer on the surface of the conductive seed layer away from the substrate;

[0029] Exposing and developing the photoresist material layer includes:

[0030] The photoresist material layer is exposed and developed to form a removable pattern defining layer having a lead opening, so that the width of the lead opening at one end close to the base substrate is greater than the width of the end away from the base substrate.

[0031] In an exemplary embodiment of the present disclosure, forming a removable pattern defining layer on a surface of the conductive seed layer away from the base substrate includes:

[0032] forming a removable pattern defining layer on a surface of the conductive seed layer away from the substrate, wherein the minimum value of the width of the lead opening is a first size value;

[0033] The step of forming an electroplated metal layer on the surface of the conductive seed layer in the lead opening by using an electroplating process comprises:

[0034] An electroplating process is adopted to form an electroplated metal layer on the surface of the conductive seed layer in the lead opening, so that the thickness of the electroplated metal layer is a second dimension value, and the second dimension value is not greater than 5 times the first dimension value.

[0035] In an exemplary embodiment of the present disclosure, forming at least one first lead layer on one side of the base substrate includes:

[0036] forming a first lead layer on one side of the base substrate;

[0037] forming a first planarization layer on a side of the first wiring layer away from the substrate, wherein the first planarization layer exposes at least a portion of the first wiring layer;

[0038] Forming a first transfer metal layer on a side of the first planarization layer away from the base substrate, wherein the first transfer metal layer is connected to the first lead layer;

[0039] A second planarization layer is formed on a side of the first transfer metal layer away from the base substrate, wherein the second planarization layer has a first connection via hole; the first connection via hole exposes a portion of the first transfer metal layer, and an orthographic projection of the first connection via hole on the first lead layer does not overlap with the first lead layer;

[0040] Another layer of the first lead layer is formed on a surface of the second planarization layer away from the base substrate, and the other layer of the first lead layer is connected to the first transfer metal layer through the first connecting via hole.

[0041] According to a second aspect of the present disclosure, there is provided an array substrate, comprising a base substrate, a driving circuit layer and a functional device layer stacked in sequence;

[0042] Wherein, the driving circuit layer includes at least one first lead layer, and any one of the first lead layers includes at least one first lead;

[0043] Any one of the first leads includes a seed lead disposed on one side of the base substrate, and a growth lead disposed on the seed lead away from the surface of the base substrate, and the orthographic projection of the growth lead on the base substrate coincides with the orthographic projection of the seed lead on the base substrate.

[0044] In an exemplary embodiment of the present disclosure, the thickness of the first lead is no greater than 5 times the width of the seed lead.

[0045] In an exemplary embodiment of the present disclosure, a width of the first lead at an end away from the base substrate is smaller than a width of the first lead at an end close to the base substrate.

[0046] In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

[0047] The first lead layer is provided on one side of the base substrate;

[0048] A first planarization layer is provided on a side of the first lead layer away from the base substrate;

[0049] A first transfer metal layer is provided on a side of the first planarization layer away from the base substrate and is connected to the first lead layer;

[0050] A second planarization layer is provided on a side of the first transfer metal layer away from the base substrate and is provided with a first connection via; the first connection via exposes a portion of the first transfer metal layer, and an orthographic projection of the first connection via on the first lead layer does not overlap with the first lead layer;

[0051] Another first lead layer is disposed on a surface of the second planarization layer away from the base substrate and is connected to the first transfer metal layer through the first connecting via.

[0052] In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

[0053] A driving transistor is disposed on one side of the substrate, wherein the driving transistor includes a source-drain metal layer having a source electrode and a drain electrode;

[0054] A third planarization layer is provided on a side of the driving transistor away from the substrate and is provided with a third connection via hole exposing at least a portion of the source-drain metal layer;

[0055] A second transfer metal layer is provided on a side of the third planarization layer away from the base substrate and is connected to the source-drain metal layer through the third connection via;

[0056] a fourth planarization layer, which is disposed on a side of the second transfer metal layer away from the base substrate and has a fourth connection via; the fourth connection via exposes a portion of the second transfer metal layer, and an orthographic projection of the fourth connection via on the base substrate does not overlap with an orthographic projection of the third connection via on the base substrate;

[0057] The first lead layer is disposed on a surface of the fourth planarization layer away from the base substrate and is connected to the second transfer metal layer through the fourth connecting via.

[0058] In an exemplary embodiment of the present disclosure, the driving circuit layer includes:

[0059] A driving transistor is disposed on one side of the substrate, wherein the driving transistor includes a source-drain metal layer having a source electrode and a drain electrode;

[0060] A third planarization layer is provided on a side of the source-drain metal layer away from the base substrate, and is provided with a third connection via hole exposing at least a portion of the source-drain metal layer; an orthographic projection of the third connection via hole on the base substrate does not overlap with an orthographic projection of the second connection via hole on the base substrate;

[0061] The first wiring layer is disposed on a surface of the third planarization layer away from the base substrate and is connected to the source-drain metal layer through the third connection via.

[0062] In an exemplary embodiment of the present disclosure, the driving circuit layer includes a driving transistor, and the driving transistor includes:

[0063] A semiconductor layer is disposed on one side of the substrate; the semiconductor layer includes a source contact region and a drain contact region;

[0064] An interlayer dielectric layer is provided on a side of the semiconductor away from the substrate;

[0065] The first lead layer is arranged on a side of the interlayer dielectric layer away from the base substrate, and is formed with a source and a drain; the source is connected to the source contact area, and the drain is connected to the drain contact area.

[0066] According to the array substrate and its preparation method provided by the present disclosure, a conductive seed layer of the entire surface and a removable pattern defining layer covering the conductive seed layer can be first formed to ensure that the conductive seed layer will not be missing in the lead opening. Then, a metal is grown in the lead opening by an electroplating process to prepare a precursor growth lead located in the lead opening to form an electroplated metal layer; the process of electroplating the entire conductive seed layer can make the electroplating process applicable to any metal wiring layer of the array substrate, which can increase the thickness of any metal wiring layer of the array substrate and improve the thickness uniformity of the first lead layer formed, overcoming the application limitations of the electroplating process in the prior art. During the electroplating process, the removable pattern defining layer enables the precursor growth lead to have a good side morphology; the conductive seed layer can provide a complete electroplating substrate, so that the surface of the precursor growth lead has better uniformity. Then, the removable pattern defining layer is removed and the conductive seed layer is patterned by etching to form a seed lead covered by the precursor growth lead. The precursor growth lead can also be partially etched during the etching process to form a growth lead. By utilizing the etching speed difference at different positions during the etching process, the uniformity of the surface of the growth lead away from the substrate can be further improved. In this way, the first lead layer includes a first lead, and the first lead includes a seed lead and a growth lead stacked on the surface of the seed lead. The surface uniformity of the first lead is better, which can improve the performance of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0068] Figure 1 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0069] Figure 2 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0070] Figure 3 It is a schematic diagram of a process of forming any first lead layer according to an embodiment of the present disclosure.

[0071] Figure 4 It is a schematic structural diagram of providing a substrate according to an embodiment of the present disclosure.

[0072] Figure 5 It is a schematic structural diagram of forming a conductive seed layer on one side of a substrate according to an embodiment of the present disclosure.

[0073] Figure 6 It is a structural schematic diagram of forming a removable pattern defining layer on a surface of a conductive seed layer away from a substrate according to an embodiment of the present disclosure.

[0074] Figure 7 It is a structural schematic diagram of an embodiment of the present disclosure that uses an electroplating process to form an electroplated metal layer located on the surface of a conductive seed layer in a lead opening.

[0075] Figure 8 It is a structural schematic diagram of removing a removable pattern defining layer according to an embodiment of the present disclosure.

[0076] Fig. 9 It is a schematic structural diagram of etching to form a first lead layer according to an embodiment of the present disclosure.

[0077] Fig.10 It is a structural schematic diagram of forming a passivation layer on a surface of a first lead layer away from a base substrate according to an embodiment of the present disclosure.

[0078] Fig.11 It is a schematic diagram of a process of forming a first lead layer group according to an embodiment of the present disclosure.

[0079] Fig.12 It is a structural schematic diagram of forming a first planarization layer on a side of a previous first lead layer away from a base substrate according to an embodiment of the present disclosure.

[0080] Fig.13 It is a structural schematic diagram of forming a first transfer metal layer on a side of a first planarization layer away from a base substrate according to an embodiment of the present disclosure.

[0081] Fig.14 It is a structural schematic diagram of forming a second planarization layer on a side of a first transfer metal layer away from a base substrate according to an embodiment of the present disclosure.

[0082] Fig.15 It is a schematic structural diagram of a first lead layer formed on a surface of a second planarization layer away from a substrate according to an embodiment of the present disclosure.

[0083] Fig.16 It is a structural schematic diagram of forming a pixel definition layer on a side of a driving circuit layer away from a base substrate according to an embodiment of the present disclosure.

[0084] Fig.17 It is a structural schematic diagram of forming a functional device layer on a side of a driving circuit layer away from a base substrate according to an embodiment of the present disclosure.

[0085] Fig.18 It is a schematic structural diagram of a driving circuit layer having a first lead layer stacked in multiple layers in sequence according to an embodiment of the present disclosure.

[0086] Fig.19 It is a schematic diagram of a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

[0087] Fig. 20 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0088] Fig.21 It is a schematic diagram of a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

[0089] Fig. 22 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0090] Fig.23 It is a schematic diagram of a process of forming a first wiring layer electrically connected to a driving transistor according to an embodiment of the present disclosure.

[0091] Fig.24 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0092] Fig.25 It is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

[0093] Fig.26 It is a schematic diagram of a top view structure of an array substrate according to an embodiment of the present disclosure.

[0094] Fig. 27 It is a schematic diagram of a top view structure of an array substrate according to an embodiment of the present disclosure.

[0095] The main components in the figure are described as follows:

[0096] 100, substrate substrate; 110, alignment mark layer; 111, alignment pattern; 120, buffer layer; 200, drive circuit layer; 201, first lead layer; 201a, previous first lead layer; 201b, next first lead layer; 2011, first lead; 202, second lead layer; 210, drive transistor; 220, interlayer dielectric layer; 230, source and drain metal layer; 241, first planarization layer; 242, second planarization layer; 243, third planarization layer; 244, fourth planarization layer; 251, first connection via; 252, second connection via; 253, third connection via; 254, fourth connection via; 261, first transfer metal layer; 262, second transfer Metal layer; 271, pixel definition layer; 272, conductive glue; 300, functional device layer; 310, functional device; 311, LED; 410, conductive seed layer; 411, seed lead; 420, removable pattern defining layer; 421, lead opening; 430, electroplated metal layer; 431, precursor growth lead; 432, growth lead; 440, passivation layer; 510, scan lead; 520, data lead; 530, common voltage lead; 540, binding lead; 610, back side lead layer; 620, insulating layer; 630, binding pad layer; 710, first metal wiring layer; 720, second metal wiring layer; 711, first metal lead; 721, second metal lead. DETAILED DESCRIPTION

[0097] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure.

[0098] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

[0099] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0100] When a structure is “on” another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is “directly” disposed on the other structure, or that the structure is “indirectly” disposed on the other structure via another structure.

[0101] The terms "a", "an", "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0102] In the present disclosure, the width of a lead refers to the dimension of the lead perpendicular to its extension direction on a plane parallel to the substrate. The thickness of a film layer or a lead refers to the dimension of the film layer or the lead perpendicular to the substrate.

[0103] In the related art, a seed lead can be first formed on a substrate, and then a copper growth layer can be generated on the seed lead by a copper electroplating process to form a thick electroplated metal lead. However, when copper is electroplated based on the seed lead, the copper growth layer will grow outward on the surface of the seed lead, and its morphology and width are not easy to control. In some related technologies, a retaining wall structure can also be set between the seed leads, and then the copper electroplating process can be performed to constrain the width of the copper growth layer. However, due to the alignment error when preparing the retaining wall structure, it is difficult to make the retaining wall accurately embedded between the seed leads, which restricts the improvement of the surface uniformity of the copper growth layer.

[0104] The present disclosure provides a method for preparing an array substrate. Figure 1 and Figure 2 As shown, the array substrate includes a base substrate 100, a driving circuit layer 200 and a functional device layer 300 which are stacked in sequence.

[0105] The method for preparing the array substrate comprises:

[0106] Step S110, as Figure 4 As shown, a substrate 100 is provided;

[0107] Step S120, forming a driving circuit layer 200 on one side of the base substrate 100;

[0108] Step S130, forming a functional device layer 300 on a side of the driving circuit layer 200 away from the base substrate 100;

[0109] The step of forming the driving circuit layer 200 on one side of the base substrate 100 includes: forming at least one first lead layer 201 on one side of the base substrate 100; Figure 3 As shown, forming any first lead layer 201 includes:

[0110] Step S210, as Figure 5 As shown, a conductive seed layer 410 is formed on one side of the substrate 100;

[0111] Step S220, as Figure 6 As shown, a removable pattern defining layer 420 is formed on the surface of the conductive seed layer 410 away from the base substrate 100 , and the removable pattern defining layer 420 is provided with a lead opening 421 , and the lead opening 421 exposes a portion of the conductive seed layer 410 ;

[0112] Step S230, as Figure 7 As shown, an electroplating process is used to form an electroplated metal layer 430 located on the surface of the conductive seed layer 410 in the lead opening 421;

[0113] Step S240, as Figure 8 As shown, the removable pattern defining layer 420 is removed;

[0114] Step S250, as Fig. 9 As shown, the portion of the conductive seed layer 410 not covered by the electroplated metal layer 430 is removed to form the first lead layer 201 .

[0115] According to the method for preparing the array substrate provided by the present disclosure, a conductive seed layer 410 covering the entire surface and a removable pattern defining layer 420 covering the conductive seed layer 410 can be formed first. Since the conductive seed layer 410 is not subjected to patterning, it can be ensured that the conductive seed layer 410 is not missing in the lead opening 421, thereby overcoming the problem that a part of the lead opening 421 may lack the electroplating base. Then, a metal is grown in the lead opening 421 by an electroplating process, and a precursor growth lead 431 located in the lead opening 421 is prepared to form an electroplated metal layer 430. During the electroplating process, the removable pattern defining layer 420 can define the side of the precursor growth lead 431, so that the precursor growth lead 431 has a good side morphology; the conductive seed layer 410 in the lead opening 421 can provide a complete electroplating base, so that the surface of the precursor growth lead 431 away from the base substrate 100 has better uniformity. Then, the removable pattern defining layer 420 is removed and the conductive seed layer 410 is patterned by etching to form a seed lead 411 covered by the precursor growth lead 431. The precursor growth lead 431 can also be partially etched during the etching process to form a growth lead 432. By utilizing the difference in etching speed at different positions during the etching process, the uniformity of the surface of the growth lead 432 away from the substrate 100 can be further improved. In this way, the first lead layer 201 includes a first lead 2011, and the first lead 2011 includes a seed lead 411 and a growth lead 432 stacked on the surface of the seed lead 411. The surface uniformity of the first lead 2011 is better, which can improve the performance of the array substrate. In addition, the method for preparing the array substrate provided by the present disclosure overcomes the film layer position limitation of the electroplated metal lead in the existing process, and the first lead layer 201 can be prepared at the desired position according to the performance requirements of the array substrate, thereby ensuring that the functional device 310 of the functional device layer 300 obtains sufficient driving current.

[0116] Below, the steps, principles and effects of the method for preparing the array substrate provided by the present disclosure are further explained and illustrated in conjunction with the accompanying drawings.

[0117] In step S110, a substrate substrate 100 of an array substrate may be provided. The substrate substrate 100 may be a substrate substrate 100 of an inorganic material, or may be a substrate substrate 100 of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate 100 may be a glass material such as soda-lime glass, quartz glass, sapphire glass, or may be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate 100 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In another embodiment of the present disclosure, the substrate 100 may also be a flexible substrate 100, for example, the substrate 100 may be made of polyimide (PI). The substrate 100 may also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the substrate 100 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0118] In step S120, a driving circuit layer 200 may be formed on one side of the base substrate 100, and the driving circuit layer 200 is used to drive each functional device 310 in the functional device layer 300. The driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any metal wiring layer includes at least one metal lead. Among them, at least one metal wiring layer is the first lead layer 201 of the present disclosure.

[0119] It is understandable that if Figure 1 and Figure 2 As shown, each metal wiring layer in the driving circuit layer 200 may be all the first lead layer 201 or may be part of the first lead layer 201. For example, Figure 2As shown, in the driving circuit layer 200, part of the metal wiring layer may be the first lead layer 201, and another part of the metal wiring layer may be the second lead layer 202. The second lead layer 202 may be prepared by forming a metal film layer through a deposition process and patterning the metal film layer; in other words, the second lead layer 202 may not use an electroplating process, and each second lead contained therein may have a lower thickness. In some embodiments, the material of the second lead layer 202 may be the same as or different from the conductive seed layer 410. As an example, one or more of the following metal wiring layers in the driving circuit layer 200 may be the second lead layer 202: a gate lead layer, a source-drain lead layer, a metal transfer layer, a light shielding layer, an electrode layer or a binding layer, etc.; of course, any of the above film layers may also be prepared into the first lead layer 201 by means of an electroplating process. When a metal wiring layer in the driving circuit layer 200 is the first lead layer 201, the first lead layer 201 can be prepared according to the preparation method shown in steps S210 to S250, so that any first lead 2011 can include a seed lead 411 and a growth lead 432 stacked on the seed lead 411 away from the surface of the base substrate 100.

[0120] In some embodiments of the present disclosure, the driving circuit layer 200 may include a passive driving circuit. For example, the driving circuit layer 200 includes a driving circuit composed of at least one metal wiring layer, and any metal wiring layer includes at least one metal lead.

[0121] As an example, the present disclosure provides an array substrate with a passive driving circuit to explain and illustrate the structure and principle of the array substrate of the present disclosure. Fig.26 Only the first metal wiring layer 710, the second metal wiring layer 720 and the functional device layer of the array substrate are shown. In this example, the array substrate includes a base substrate 100, a driving circuit layer 200 and a functional device layer 300 stacked in sequence. Among them, the driving circuit layer 200 includes a first metal wiring layer 710, an insulating layer and a second metal wiring layer 720 stacked on the base substrate 100; the first metal wiring layer 710 includes a plurality of first metal leads 711; the insulating layer is provided with connecting vias exposing part of the first metal lead 711 layer; the second metal lead 721 layer includes a plurality of second metal leads 721, and the second metal leads 721 can be used as an electrode layer of the driving circuit for binding with the functional device 310. Among them, part of the second metal leads 721 is electrically connected to the first metal lead 711 through the connecting vias. The functional device layer 300 includes an array-distributed functional device 310, and the functional device 310 can be an LED 311. One end of the LED 311 is connected to a second metal lead 721 through solder paste, and the other end of the LED 311 is connected to another second metal lead 721 through solder paste.

[0122] In this example, the first metal wiring layer 710 can adopt the first lead layer 201 structure of the embodiment of the present disclosure to ensure that sufficient and sufficient current can be transmitted to the second metal wiring layer 720 and avoid obvious voltage drop during the driving process. The second metal wiring layer 720 can adopt the first lead layer 201 structure of the present disclosure or the second lead layer 202 structure of the present disclosure, which is not limited.

[0123] As a further exemplary introduction, the array substrate may include a plurality of light-emitting areas, and four second metal leads 721 adjacent to each other in sequence may be arranged in any light-emitting area, wherein a group of two second metal leads 721 arranged opposite to each other are respectively connected to two different first metal leads 711 through connecting vias, and the other two second metal leads 721 are not electrically connected to the first metal leads 711. An LED 311 is arranged adjacent to the two second metal leads 721, and the two ends of the LED 311 are respectively connected to the two second metal leads 721. In this way, when a common voltage and a driving voltage are respectively applied to the two first metal leads 711, the four LEDs 311 can be driven to emit light.

[0124] It is understandable that the exemplary array substrate can be used as a backlight source of an LCD display device or as a passively driven display panel, and the present disclosure does not make any special limitation on this. Among them, LED 311 can be an LED lamp bead, or a Micro LED or Mini LED.

[0125] In other embodiments of the present disclosure, the driving circuit layer 200 may include an active driving circuit. For example, the driving circuit layer 200 of the array substrate may also be provided with electronic components such as driving transistors, and each electronic component is electrically connected to the functional device layer 300 through at least one metal wiring layer, and any metal wiring layer includes at least one metal lead. Among them, at least one metal wiring layer is the first lead layer 201 of the present disclosure. Of course, according to the requirements of the array substrate, the driving circuit layer 200 may also be provided with other electronic components, for example, it may also be provided with storage capacitors and other required transistors other than the driving transistors.

[0126] Optionally, the transistor may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS). Taking the thin film transistor as an example, in terms of the film layer structure, the thin film transistor may be a top gate thin film transistor or a bottom gate thin film transistor, which is not limited in the present disclosure. In terms of the thin film transistor material, the thin film transistor may be an amorphous silicon thin film transistor, a low temperature polycrystalline silicon thin film transistor or an oxide thin film transistor, which is not limited in the present disclosure. In terms of the conduction condition of the thin film transistor, the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor, which is not limited in the present disclosure. In the driving circuit layer 200, each thin film transistor and storage capacitor may be formed by film layers such as an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer. Among them, the thin film transistor may include a semiconductor layer located in the active layer, a gate insulating layer, a gate located in the gate layer, an interlayer dielectric layer, and a source-drain electrode layer located in the source-drain metal layer, and the source-drain electrode layer is composed of the source and drain of the thin film transistor. The semiconductor layer includes a channel region and a source contact region and a drain contact region on both sides of the channel region, the source passes through the interlayer dielectric layer to connect to the source contact region, the drain passes through the interlayer dielectric layer to connect to the drain contact region, and the gate and the channel region are isolated by a gate insulating layer. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. For example, the driving circuit layer 200 may include an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a source-drain metal layer stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor. For another example, the driving circuit layer 200 may include a gate layer, a gate insulating layer, an active layer, an interlayer dielectric layer and a source-drain metal layer stacked in sequence, and the thin film transistor formed in this way is a bottom-gate thin film transistor. The driving circuit layer 200 can also adopt a dual-gate structure, that is, the gate layer may include a first gate layer and a second gate layer, and the gate insulating layer may include a first gate insulating layer for isolating the active layer and the first gate layer, and a second gate insulating layer for isolating the first gate layer and the second gate layer. For example, the driving circuit layer 200 may include an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer stacked sequentially on one side of the base substrate 100 .

[0127] As an example, Fig. 27 As shown, the present disclosure provides an array substrate with an active driving circuit to explain and illustrate the structure and principle of the array substrate of the present disclosure. Fig. 27Only the driving transistor, two metal wiring layers and LED as a functional device of the array substrate are shown. In this example, the driving circuit is a semi-active driving circuit, which includes a driving transistor 210, a scanning lead 510, a data lead 520, a common voltage lead 530 and a binding lead 540. The scanning lead 510 is used to control the driving transistor 210 to be turned on or off. The data lead 520 is connected to the source of the driving transistor 210, and the binding lead is connected to the drain of the driving transistor 210. The two ends of the LED as the functional device 310 are respectively connected to the binding lead 540 and the common voltage lead 530. When a valid scanning signal is loaded on the scanning lead 510 to turn on the driving transistor 210, the driving current can flow through the LED through the data lead 520, the driving transistor 210, the binding lead and the common voltage lead 530, so that the LED emits light. In this example, the scanning lead 510 can belong to the second lead layer 202, and each scanning lead 510 does not need to be prepared by an electroplating process. The data lead 520, the common voltage lead 530 and the binding lead 540 belong to the same first lead layer 201. An electroplating process can be used to increase the thickness of each lead and reduce the impedance of each lead to reduce the voltage drop of the driving circuit on the data lead 520 and the common voltage lead 530 and ensure the accuracy of the current flowing through the LED.

[0128] When preparing the driving circuit layer 200 , any first lead layer 201 may be prepared according to the preparation method shown in step S210 to step S250 .

[0129] In step S210, Figure 5 As shown, a metal material may be deposited on one side of the substrate 100 to form a conductive seed layer 410. For example, a magnetron sputtering method may be used to deposit a metal material on one side of the substrate 100 to prepare the conductive seed layer 410 as an electroplating base.

[0130] It is understood that before depositing the metal material, an intermediate substrate can be obtained according to the process steps that have been performed. According to the different process steps that have been performed, the intermediate substrate can have different structures, for example, it can be the base substrate 100 itself, or it can include the base substrate 100 and various film layers that have been formed and are sequentially stacked on the base substrate 100. In step S210, the metal material can be deposited on the surface of the conductive seed layer 410 to be formed of the intermediate substrate. For example, in one embodiment of the present disclosure, if it is necessary to form the first lead layer 201 on the surface of the base substrate 100, the base substrate 100 is used as the intermediate substrate of this step, and the metal material is deposited on the surface of the base substrate 100. For another example, in another embodiment of the present disclosure, if there is a film structure between the first lead layer 201 to be formed and the base substrate 100, when preparing the first lead 2011, the base substrate 100 and the film structure as a whole are used as the intermediate substrate of this step, and the surface of the film structure away from the base substrate 100 is the surface of the conductive seed layer 410 to be formed.

[0131] Optionally, the thickness of the conductive seed layer 410 may be no greater than 1 micron, so as to avoid excessive stress on the intermediate substrate caused by the overly thick conductive seed layer 410, thereby improving the stability and yield of the array substrate. Preferably, the thickness of the conductive seed layer 410 may be no greater than 0.5 microns, so as to shorten the etching time of the conductive seed layer 410 in step S250 and improve the side morphology of the seed lead 411 formed after etching.

[0132] The conductive seed layer 410 can be a metal material, an alloy formed by multiple metal materials, or multiple stacked metal layers. The present disclosure does not impose any special restrictions, as long as it can meet the electroplating requirements and the performance requirements of the array substrate.

[0133] Optionally, the conductive seed layer 410 may include a protective metal layer and a target metal layer located on a surface of the protective metal layer away from the base substrate 100. The target metal layer may serve as an electroplating base to form an electroplated metal layer 430 on a surface thereof away from the base substrate 100. For example, when the electroplating process is a copper plating process, the material of the target metal layer may be copper.

[0134] The protective metal layer is used to protect the target metal layer from corrosion, or to protect the intermediate substrate from corrosion by the metal material of the target metal layer. The material of the protective metal layer can be a metal element or alloy, such as molybdenum, titanium, molybdenum-titanium-nickel alloy, etc.

[0135] In one embodiment of the present disclosure, the conductive seed layer 410 includes a protective metal layer and a target metal layer sequentially stacked on one side of the base substrate 100. The material of the protective metal layer can be MTD alloy (molybdenum-titanium-nickel alloy) with a thickness of 250 to 350 angstroms; the material of the target metal layer is copper with a thickness of 2500 to 3500 angstroms.

[0136] It is understandable that when preparing different first lead layers 201 , the type and thickness of the metal material deposited in step S210 may be the same or different, so that the structures and materials of the seed leads 411 of different first lead layers 201 are the same or different.

[0137] In step S220, Figure 6 As shown, a removable pattern defining layer 420 may be formed on the surface of the conductive seed layer 410 away from the base substrate 100, and the removable pattern defining layer 420 may be provided with a lead opening 421, and the lead opening 421 may include a portion of the conductive seed layer 410. In this way, during the electroplating process, the conductive seed layer 410 exposed by the lead opening 421 may be used as an electroplating base to grow electroplated metal, while the conductive seed layer 410 covered by the removable pattern defining layer 420 may not grow electroplated metal. Therefore, the orthographic projection of the lead opening 421 on the base substrate 100 may coincide with the orthographic projection of the electroplated metal layer 430 formed in step S230.

[0138] Optionally, a removable pattern defining layer 420 may be prepared by steps S221 and S222:

[0139] Step S221 , forming a removable insulating material layer on the surface of the conductive seed layer 410 away from the base substrate 100 ;

[0140] In step S222 , the removable insulating material layer is patterned to form a removable pattern defining layer 420 .

[0141] Preferably, in step S221, the removable insulating material layer may be a photoresist material layer, that is, a photoresist material layer may be formed on the surface of the conductive seed layer 410 away from the base substrate 100. Thus, in step S222, the photoresist material layer may be patterned by exposure and development to form a removable pattern defining layer 420.

[0142] In one embodiment of the present disclosure, in step S221, a degradable photoresist material may be used to form a photoresist material layer on the surface of the conductive seed layer 410 away from the base substrate 100. The degradable photoresist material is a photoresist material that can be dissolved in a degradation liquid after curing.

[0143] Optionally, the degradable photoresist material has a decomposable cross-linking group or forms a decomposable cross-linking group when solidified. After the degradable photoresist material is solidified, when it is necessary to remove the solidified degradable photoresist material, a degradation liquid can be used to treat the solidified degradable photoresist material, and the decomposable cross-linking group in the solidified degradable photoresist material can react with the degradation liquid and break, so that the solidified degradable photoresist material is decomposed into small molecule fragments that can be dissolved in the degradation liquid. In this way, the solidified degradable photoresist material can be gently and thoroughly removed.

[0144] In step S221, a degradable photoresist material is used to prepare a photoresist material layer, and the material of the removable pattern defining layer 420 prepared in step S222 is a solidified degradable photoresist material; in step S240, a degradation liquid can be used to dissolve the removable pattern defining layer 420 to remove the removable pattern defining layer 420, thereby ensuring that the removable pattern defining layer 420 is completely removed and avoiding damage to the electroplated metal layer 430 when removing the removable pattern defining layer 420.

[0145] In another embodiment of the present disclosure, in step S221, a negative photoresist material may be used to form a photoresist material layer on the surface of the conductive seed layer 410 away from the base substrate 100. Thus, in step S222, the photoresist material layer is exposed and developed to form a removable pattern defining layer 420 having a lead opening 421, so that the width of the lead opening 421 at one end close to the base substrate 100 is greater than the width at one end away from the base substrate 100. In other words, the width of the lead opening 421 can be reduced in a direction away from the base substrate 100 by means of the material properties of the negative photoresist material, which not only facilitates the removal of the removable pattern defining layer 420, but also reduces the width of the growth lead 432 formed by electroplating in a direction away from the base substrate 100, thereby improving the strength of the growth lead 432 and reducing the risk of collapse of the growth lead 432. Thus, in the prepared first lead 2011, the width of the first lead 2011 at one end away from the base substrate 100 is smaller than the width of the first lead 2011 at one end close to the base substrate 100. Fig.10 As shown, a passivation material may be deposited on the surface of the first lead 2011 away from the base substrate 100 and the side of the first lead 2011, such as silicon oxide, silicon nitride, silicon oxynitride, etc., to form a passivation layer 440 for protecting the first lead 2011. Since the width of the growth lead 432 formed by electroplating decreases in a direction away from the base substrate 100, the continuity of the passivation layer can be ensured.

[0146] Of course, in other embodiments of the present disclosure, other removable insulating materials may be used to prepare the removable pattern defining layer 420, and the removable pattern defining layer 420 may be removed by a corresponding process in step S240. For example, the removable pattern defining layer 420 may be prepared by using silicon oxide and then removed by an etching process, or the removable pattern defining layer 420 may be prepared by using a photosensitive resin and then removed by a dry stripping process. The present disclosure will not further elaborate on this.

[0147] In step S230, if Figure 7 As shown, an electroplating process can be used to form an electroplated metal layer 430 located on the surface of the conductive seed layer 410 in the lead opening 421. During the electroplating process, the electroplated metal starts to grow from the surface of the conductive seed layer 410 as the electroplating base. Under the constraint of the lead opening 421, the electroplated metal only grows in the lead opening 421, and finally forms a precursor growth lead 431 located in the lead opening 421 after electroplating, and each precursor growth lead 431 forms the electroplated metal layer 430.

[0148] Since the conductive seed layer 410 is a whole surface metal, the electroplating current can be easily loaded to the entire conductive seed layer 410 and the conductive seed layer 410 has a very small voltage drop, so that the uniformity of the electroplating rate at the position of each lead opening 421 can be improved, thereby improving the uniformity of the surface of the precursor growth lead 431 away from the base substrate 100. The preparation method disclosed in the present invention does not need to design additional connecting leads to ensure power supply to the patterned conductive seed layer 410, thereby not only simplifying the design process and preparation process of each first lead layer 201, but also making the method of preparing the first lead layer 201 disclosed in the present invention applicable to any film layer position, overcoming the defect that the prior art can only electroplate copper in the first layer close to the substrate.

[0149] In the prior art, however, the conductive seed layer needs to be patterned before electroplating, which requires the design of additional conductive leads to electrically connect the seed leads to each other to ensure that current can be loaded to each seed lead during the electroplating process. Since the conductive seed layer is patterned into seed leads, it is difficult to maintain uniformity in the electroplating current density on each seed lead, which is not conducive to the uniform growth of the electroplated metal on different seed leads. In addition, during the electroplating process, the electroplated metal may grow on the side of the seed lead, causing the electroplated metal layer to completely cover the seed lead, reducing the pattern-defining effect of the seed lead on the electroplated metal layer. More importantly, since additional conductive leads need to be designed to connect the seed leads, this method is only applicable to the metal wiring layer close to the substrate, and cannot be applied to any metal wiring layer.

[0150] Optionally, the thickness of each precursor growth lead 431, that is, the thickness of the electroplated metal layer 430, can be controlled by controlling the parameters of the electroplating process, such as the electroplating current, the electroplating time, and the like. Optionally, in step S230, the thickness of the electroplated metal layer 430 can be made not greater than five times the width of the lead opening 421. In other words, the minimum value of the width of the lead opening 421 is the first dimension value, that is, the minimum value of the width of the precursor growth lead 431 close to the substrate 100 is the first dimension value; the thickness of the electroplated metal layer 430 is the second dimension value, that is, the thickness of the precursor growth lead 431 is the second dimension value; the second dimension value is not greater than 5 times the first dimension value. In this way, the aspect ratio of the prepared precursor growth lead 431 is not greater than 5, which can improve the bonding strength between the precursor growth lead 431 and the conductive seed layer 410, and avoid the collapse of the precursor growth lead 431, thereby improving the stability of the precursor growth lead 431. Thus, in the first lead 2011 formed after step S250 , the thickness of the first lead 2011 is not greater than 5 times the width of the seed lead 411 .

[0151] Optionally, the thickness of the electroplated metal layer 430 is 1.5 to 20 micrometers, for example, 2 micrometers, 5 micrometers, 10 micrometers, 20 micrometers, etc. Preferably, the thickness of the electroplated metal layer 430 is 5 to 10 micrometers.

[0152] Optionally, the thickness of the electroplated metal layer 430 is greater than the thickness of the conductive seed layer 410 , so as to ensure that the thickness of the first lead 2011 is greater than the thickness of the conductive seed layer 410 , thereby achieving the purpose of increasing the thickness of the first lead 2011 .

[0153] Optionally, the material of the electroplated metal layer 430 can be copper through a copper electroplating process. In this way, the resistance of the growing lead 432 can be reduced, thereby reducing the resistance of the first lead 2011. Further, the conductive seed layer 410 is away from the surface of the base substrate 100 and includes at least one copper metal layer to ensure that the copper electroplated metal layer 430 can be smoothly grown on the surface of the conductive seed layer 410 during the electroplating process.

[0154] In step S250, if Fig. 9 As shown, etching can be performed to remove the portion of the conductive seed layer 410 that is not covered by the electroplated metal layer 430. Optionally, a suitable etching process can be selected according to the thickness and material of the conductive seed layer 410, including selecting a suitable etching solution, etching time, etc., so as to completely etch the exposed portion of the conductive seed layer 410.

[0155] When etching the conductive seed layer 410, it is not necessary to specifically protect the electroplated metal layer 430. In this way, the surface of each precursor growth lead 431 of the electroplated metal layer 430 is partially etched during the etching process, and the remaining portion forms the growth lead 432 of the first lead 2011. In some embodiments, the electroplated metal layer 430 and the conductive seed layer 410 can be etched at a similar speed, so that the thickness of the formed first lead 2011 is close to the thickness of the electroplated metal layer 430. For example, if the thickness of the electroplated metal layer 430 is 1.5 to 20 microns, the thickness of the formed first lead 2011 is 1.5 to 20 microns.

[0156] In some embodiments, the surface of the precursor growth lead 431 away from the base substrate 100 has a slightly rough surface, and the protruding portion of the surface is more easily etched by the etching solution, thereby continuously improving the flatness of the surface of the precursor growth lead 431 away from the base substrate 100 during the etching process. In addition, since there is no need to protect the electroplated metal layer 430, in the formed first lead 2011, the positive projection of the growth lead 432 on the base substrate 100 coincides with the positive projection of the seed lead 411 on the base substrate 100, which ensures the flatness of the side of the first lead 2011 and avoids the problem of the seed lead 411 protruding from the growth lead 432. Therefore, the surface and side of the first lead 2011 have a higher flatness, which can further improve the morphology of the first lead 2011 and improve the performance of the array substrate.

[0157] Thus, using the method for preparing the array substrate provided by the present disclosure, as Figure 1 , Figure 2 and Fig. 9 As shown, the prepared array substrate includes a base substrate 100, a driving circuit layer 200 and a functional device layer 300 which are stacked in sequence; wherein the driving circuit layer 200 includes at least one first lead layer 201, and any first lead layer 201 includes at least one first lead 2011; any first lead 2011 includes a seed lead 411 arranged on one side of the base substrate 100, and a growth lead 432 arranged on the seed lead 411 away from the surface of the base substrate 100, and the orthographic projection of the growth lead 432 on the base substrate 100 coincides with the orthographic projection of the seed lead 411 on the base substrate 100.

[0158] In one embodiment of the present disclosure, Figure 4As shown, the method for preparing the array substrate provided by the present disclosure may further include: forming an alignment mark layer 110 on one side of the base substrate 100, wherein the alignment mark layer 110 has an alignment pattern 111 for alignment. Then, a driving circuit layer 200 is formed on a side of the alignment mark layer 110 away from the base substrate 100. In this way, it is possible to avoid using the pattern of the first lead layer 201 as the alignment pattern 111, so as to avoid the problem that the first lead layer 201 is too thick and the edge is not clear.

[0159] Optionally, the material of the alignment mark layer 110 may be metal, metal oxide, silicon or other materials. For example, the material of the alignment mark layer 110 may be metal such as molybdenum, titanium, copper, aluminum, tungsten, or may be metal oxide such as ITO (indium zinc oxide), or may be amorphous silicon, polycrystalline silicon, etc. In one embodiment of the present disclosure, the material of the alignment mark layer 110 is molybdenum.

[0160] Optionally, a buffer layer 120 may be further disposed between the alignment mark layer 110 and the driving circuit layer 200 . The buffer layer 120 is made of insulating material to isolate the alignment mark layer 110 from the driving circuit layer 200 .

[0161] It is understandable that when other film layers of the array substrate can be used as alignment patterns, there is no need to provide the alignment mark layer 110. For example, if the prepared driving circuit layer 200 includes an active driving circuit, the active layer pattern of the active driving circuit can be used as the alignment pattern 111.

[0162] In some embodiments, Fig.17 As shown, when preparing the driving circuit layer 200, two stacked first lead layers 201 connected by a transfer metal layer can also be prepared. Fig.11 As shown, forming at least one first lead layer 201 on one side of the base substrate 100 may include:

[0163] Step S310, as Fig.12 As shown, a first lead layer 201 is formed on one side of the base substrate 100;

[0164] Step S320, as Fig.12 As shown, a first planarization layer 241 is formed on a side of the first lead layer 201 away from the base substrate 100 , and the first planarization layer 241 exposes at least a portion of the first lead layer 201 ;

[0165] Step S330, as Fig.13 As shown, a first transfer metal layer 261 is formed on a side of the first planarization layer 241 away from the base substrate 100 , and the first transfer metal layer 261 is connected to the first lead layer 201 ;

[0166] Step S340, as Fig.14 As shown, a second planarization layer 242 is formed on a side of the first transfer metal layer 261 away from the base substrate 100, and the second planarization layer 242 has a first connection via 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and the orthographic projection of the first connection via 251 on the first lead layer 201 does not overlap with the first lead layer 201;

[0167] Step S350, as Fig.15 As shown, another first wiring layer 201 is formed on the surface of the second planarization layer 242 away from the base substrate 100 , and the other first wiring layer 201 is connected to the first transfer metal layer 261 through the first connection via 251 .

[0168] So, like Fig.17 As shown, in the array substrate prepared according to the preparation method, the driving circuit layer 200 may include a previous first lead layer 201a, a first planarization layer 241, a first transfer metal layer 261, a second planarization layer 242 and a subsequent first lead layer 201b stacked in sequence, and the previous first lead layer 201a and the subsequent first lead layer 201b form a first lead layer group connected by the first transfer metal layer 261. Among them, the previous first lead layer 201a is arranged on one side of the base substrate 100; the first planarization layer 241 is arranged on the side of the previous first lead layer 201a away from the base substrate 100, and exposes at least part of the previous first lead layer 201a; the first transfer metal layer 261 is arranged on the side of the first planarization layer 241 away from the base substrate 100, and is connected to the previous first lead layer 201a; the second planarization layer 242 is arranged on the side of the first transfer metal layer 261 away from the base substrate 100, and is provided with a first connection via 251; the first connection via 251 exposes part of the first transfer metal layer 261, and the orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201a; the next first lead layer 201b is arranged on the surface of the second planarization layer 242 away from the base substrate 100, and is connected to the first transfer metal layer 261 through the first connection via 251.

[0169] In step S310 , a previous first wiring layer 201 a may be formed on one side of the base substrate 100 through steps S210 to S250 .

[0170] In one embodiment of the present disclosure, before step S320, a first passivation layer may be formed on the surface of the previous first lead layer 201a away from the base substrate 100, and the first passivation layer is used to protect the first lead 2011 from being corroded. The first passivation layer exposes at least a portion of the previous first lead layer 201a, so that the previous first lead layer 201a can be electrically connected to the first transfer metal layer 261.

[0171] In step S320, Fig.12 As shown, a first planarization layer 241 may be formed on a side of the previous first lead layer 201a away from the base substrate 100, and the first planarization layer 241 may fill the gaps between the first leads 2011 to provide a planarized surface for the first transfer metal layer 261. The material of the first planarization layer 241 may be an inorganic material, such as silicon oxide, silicon nitride, etc., or an organic material, such as epoxy resin, polyimide, etc. In one embodiment of the present disclosure, the material of the first planarization layer 241 is a resin material.

[0172] Step S330, as Fig.13 As shown, a first transfer metal layer 261 may be formed on a side of the first planarization layer 241 away from the base substrate 100 , and the first transfer metal layer 261 is used to connect the previous first lead layer 201 a and the next first lead layer 201 b .

[0173] Optionally, a transition metal material layer can be formed by a deposition method such as magnetron sputtering, and then the transition metal material layer is patterned to form a first transition metal. The first transition metal layer can be a layer of conductive material or a stack of multiple conductive materials. In one embodiment of the present disclosure, the first transition metal layer 261 can include a first conductive material layer, a second conductive material layer and a first conductive material layer stacked in sequence, that is, a sandwich structure. Among them, the first conductive material layer can be a corrosion-resistant metal or alloy, such as molybdenum or titanium; the second conductive material layer can be a metal or alloy with high conductivity, such as copper, aluminum, silver, etc. For example, the first transition metal layer 261 can include a titanium metal layer, an aluminum metal layer and a titanium metal layer stacked in sequence, wherein the thickness of the titanium metal layer can be 400 to 600 angstroms, and the thickness of the aluminum metal layer can be 3500 to 5500 angstroms. In another embodiment of the present disclosure, the material of the first transition metal layer 261 can be the same as the material of the conductive seed layer 410. For example, the first transfer metal layer 261 includes an MTD alloy layer and a copper layer stacked in sequence, the thickness of the MTD alloy layer is 250-350 angstroms, and the thickness of the copper layer is 2500-3500 angstroms.

[0174] In one embodiment of the present disclosure, if the surface of the first transfer metal away from the base substrate 100 is a metal material that is easily corroded, such as copper or aluminum, before step S340, a second passivation layer may be formed on the surface of the first transfer metal layer 261 away from the base substrate 100, and the second passivation layer is used to protect the first transfer metal layer 261 from being corroded. The second passivation layer exposes at least a portion of the first transfer metal layer 261, so that the subsequent first lead layer 201b can be electrically connected to the first transfer metal layer 261.

[0175] In step S340, if Fig.14 As shown, a second planarization layer 242 may be formed on the side of the first transfer metal layer 261 away from the base substrate 100. Optionally, the material and preparation method of the second planarization layer 242 may be the same as or different from that of the first planarization layer 241, and the present disclosure does not impose any special limitation on this.

[0176] Among them, the second planarization layer 242 has a first connection via 251; the first connection via 251 exposes part of the first transfer metal layer 261, and the orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201a. In this way, the first transfer metal layer 261 at least includes a first connection area and a second connection area that do not overlap each other, wherein the first connection area is electrically connected to the previous first lead layer 201a, and the second connection area is electrically connected to the next first lead layer 201b. This setting method can avoid the unevenness of the previous first lead layer 201a from being transmitted to the next first lead layer 201b, and can make the next first lead layer 201b have a good morphology without deterioration of the morphology under the influence of the previous first lead layer 201a. In particular, this can also avoid the continuous formation of multiple thicker metal layers at the same position, improve the stability of each first lead 2011 in the first lead layer 201 and improve the stress of the array substrate.

[0177] In step S350, Fig.15 As shown, a subsequent first lead layer 201b can be formed on one side of the base substrate 100 through steps S210 to S250. In one embodiment of the present disclosure, a third passivation layer can also be formed on the surface of the subsequent first lead layer 201b away from the base substrate 100, and the third passivation layer is used to protect the subsequent first lead layer 201b from being corroded. The third passivation layer exposes at least a portion of the subsequent first lead layer 201b so that the subsequent first lead layer 201b can be electrically connected to other structures of the array substrate.

[0178] It is understandable that according to the method for preparing the array substrate provided by the present disclosure, in some embodiments, such as Fig.18As shown, the formed array substrate may have a plurality of first lead layers 201, for example, three, four or five first lead layers 201. A first lead layer group may be formed between two adjacent first lead layers 201, the first lead layer 201 close to the base substrate 100 in the first lead layer group may be the previous first lead layer 201a, the first lead layer 201 far from the base substrate 100 in the first lead layer group may be the next first lead layer 201b, and the previous first lead layer 201a and the next first lead layer 201b may be electrically connected via a first transfer metal layer 261 sandwiched between the two first lead layers 201. In one embodiment of the present disclosure, when a conductive lead layer needs to be very thick according to the performance requirements of the array substrate, in order to avoid the problem that a too thick growth lead 432 is formed by electroplating at one time and the growth lead 432 is easily collapsed, each conductive lead layer can be divided into a plurality of first lead layers 201 stacked in sequence, and two adjacent first lead layers 201 are electrically connected through the first transfer metal layer 261. In this way, the plurality of first lead layers 201 electrically connected to each other can be equivalent to the required thick conductive lead layer in effect, thereby improving the process feasibility and yield of array substrate preparation.

[0179] In one embodiment of the present disclosure, Fig.19 and Fig. 20 As shown, step S120 may include steps S410 to S450 to form a driving circuit layer 200 , and the driving circuit layer 200 includes a driving transistor 210 and a first lead layer 201 connected to the driving transistor 210 .

[0180] Step S410 , forming a driving transistor 210 on one side of the base substrate 100 , wherein the driving transistor 210 includes a source-drain electrode layer consisting of a source electrode and a drain electrode, and the source-drain electrode layer is located at a source-drain metal layer of the driving circuit layer.

[0181] Optionally, the driving transistor 210 may be formed on one side of the base substrate 100 by the following method:

[0182] In step S411, an active layer, a gate insulating layer and a gate layer are formed on one side of the base substrate 100 to form a semiconductor layer and a gate of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located in the active layer and includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; the gate of the driving transistor is located in the gate layer; the channel region and the gate of the semiconductor layer are isolated by a gate insulating layer.

[0183] Step S412, forming an interlayer dielectric layer 220, the active layer, the gate insulating layer and the gate layer are all located between the interlayer dielectric layer 220 and the base substrate 100; the interlayer dielectric layer 220 is provided with a second connection via 252, and the second connection via 252 exposes the source contact area and the drain contact area.

[0184] Step S413, forming a source-drain metal layer 230 on the side of the interlayer dielectric layer 220 away from the base substrate 100, the source-drain metal layer 230 forms the source and drain of the driving transistor, and the source and drain constitute the source-drain metal layer of the driving transistor; wherein the source is connected to the source contact area through the second connecting via 252, and the drain is connected to the drain contact area through the second connecting via 252.

[0185] Optionally, the material and thickness of the source-drain metal layer 230 may be the same as or different from those of the first transfer metal layer 261 .

[0186] Optionally, after forming the source-drain metal layer 230, a passivation layer may be formed on the surface of the source-drain metal layer 230 away from the substrate 100. It is understood that the passivation layer exposes at least a portion of the source-drain metal layer 230 so that the source-drain metal layer 230 can be electrically connected to other conductive structures of the driving circuit layer 200.

[0187] Step S420 , forming a third planarization layer 243 on a side of the driving transistor 210 away from the base substrate 100 , wherein the third planarization layer 243 is provided with a third connection via 253 exposing at least a portion of the source and drain electrode layer.

[0188] Optionally, the material of the third planarization layer 243 may be the same as or different from that of the first planarization layer 241 .

[0189] Optionally, the orthographic projection of the third connection via 253 on the base substrate 100 does not overlap with the orthographic projection of the second connection via 252 on the base substrate 100. In this way, the third connection via 253 can expose the flat surface of the source-drain metal layer 230, which helps to improve the connection strength between the exposed source-drain metal layer 230 and other conductive structures of the driving circuit.

[0190] Step S430 , forming a second transfer metal layer 262 on a side of the third planarization layer 243 away from the base substrate 100 , and the second transfer metal layer 262 is connected to the source-drain metal layer 230 through the third connection via 253 .

[0191] Optionally, the material and thickness of the second transfer metal layer 262 may be the same as or different from those of the first transfer metal layer 261 .

[0192] In step S440, a fourth planarization layer 244 is formed on a side of the second transfer metal layer 262 away from the base substrate 100, and the fourth planarization layer 244 has a fourth connection via 254; the fourth connection via 254 exposes a portion of the second transfer metal layer 262, and the orthographic projection of the fourth connection via 254 on the base substrate 100 does not overlap with the orthographic projection of the third connection via 253 on the base substrate 100.

[0193] Thus, the second transfer metal layer 262 includes at least a third connection region and a fourth connection region which do not overlap each other, wherein the third connection region is electrically connected to the source-drain metal layer 230, and the fourth connection region is electrically connected to the first lead layer 201. This arrangement method can prevent the unevenness of the source-drain metal layer 230 from being transmitted to the first lead layer 201, and can enable the first lead layer 201 to have a good morphology without deterioration of the morphology under the influence of the source-drain metal layer 230.

[0194] Optionally, the material of the fourth planarization layer 244 may be the same as or different from that of the first planarization layer 241 .

[0195] Step S450, forming a first wiring layer 201 on the surface of the fourth planarization layer 244 away from the base substrate 100, the first wiring layer 201 is connected to the second transfer metal layer 262 through the fourth connection via 254. The first wiring layer 201 can be formed according to the method shown in steps S210 to S250.

[0196] Thus, according to the method for preparing the array substrate described in this embodiment, Fig. 20 As shown, the prepared driving circuit layer 200 may include a driving transistor 210, a third planarization layer 243, a second transfer metal layer 262, a fourth planarization layer 244 and a first lead layer 201 which are stacked in sequence.

[0197] in,

[0198] The driving transistor 210 is disposed on one side of the substrate 100, and the driving transistor 210 includes a source-drain electrode layer composed of a source electrode and a drain electrode; the third planarization layer 243 is disposed on the side of the driving transistor 210 away from the substrate 100, and is provided with a third connection via 253 exposing at least part of the source-drain electrode layer; the second transfer metal layer 262 is disposed on the side of the third planarization layer 243 away from the substrate 100, and is connected to the source-drain electrode layer through the third connection via 253; the fourth planarization layer 244 is provided A fourth connecting via 254 is provided on a side of the second transfer metal layer 262 away from the base substrate 100; the fourth connecting via 254 exposes a portion of the second transfer metal layer 262, and the orthographic projection of the fourth connecting via 254 on the base substrate 100 does not overlap with the orthographic projection of the third connecting via 253 on the base substrate 100; the first lead layer 201 is arranged on a surface of the fourth planarization layer 244 away from the base substrate 100, and is connected to the second transfer metal layer 262 through the fourth connecting via 254.

[0199] In another embodiment of the present disclosure, Fig.21 and Fig. 22 As shown, step S120 may include steps S510 to S530 to form a driving circuit layer 200 , and the driving circuit layer 200 includes a driving transistor 210 and a first lead layer 201 connected to the driving transistor 210 .

[0200] Step S510 , forming a driving transistor 210 on one side of the base substrate 100 , wherein the driving transistor 210 includes a source-drain electrode layer consisting of a source electrode and a drain electrode, and the source-drain electrode layer is located at the source-drain metal layer of the driving circuit layer.

[0201] Step S520 , forming a third planarization layer 243 on a side of the driving transistor 210 away from the base substrate 100 , wherein the third planarization layer 243 is provided with a third connection via 253 exposing at least a portion of the source and drain electrode layer.

[0202] Optionally, an orthographic projection of the third connection via 253 on the base substrate 100 does not overlap with an orthographic projection of the second connection via 252 on the base substrate 100 .

[0203] Optionally, steps S510 to S520 may be implemented with reference to the preparation method shown in steps S410 to S420.

[0204] Step S530, forming a first wiring layer 201 on the surface of the third planarization layer 243 away from the base substrate 100, the first wiring layer 201 is connected to the source and drain electrode layer through the third connection via 253. The first wiring layer 201 can be formed according to the method shown in steps S210 to S250.

[0205] Thus, according to the method for preparing the array substrate described in this embodiment, Fig. 22 As shown, the prepared driving circuit layer 200 may include a driving transistor 210, a third planarization layer 243 and a first lead layer 201 stacked in sequence.

[0206] A driving transistor 210 is arranged on one side of the base substrate, and the driving transistor 210 includes a source-drain electrode layer composed of a source and a drain; a third planarization layer 243 is arranged on a side of the source-drain electrode layer away from the base substrate 100, and is provided with a third connection via 253 exposing at least part of the source-drain electrode layer; a first lead layer 201 is arranged on a surface of the third planarization layer 243 away from the base substrate 100, and is connected to the source-drain electrode layer through the third connection via 253.

[0207] According to the array substrate prepared in this embodiment, the source-drain metal layer 230 can be reused as the second transfer metal layer 262, so it is not necessary to prepare the second transfer metal layer 262 and the fourth planarization layer 244, which can reduce two patterning processes and save related materials in terms of process, and can reduce two film layers on the formed array substrate. In this way, the preparation method shown in this embodiment can reduce the preparation cost of the array substrate and improve the preparation efficiency, and can make the array substrate have a smaller thickness.

[0208] In another embodiment of the present disclosure, Fig.23 and Fig.24 As shown, step S120 may include steps S610 to S630 to form a driving circuit layer 200 , and the driving circuit layer 200 includes a driving transistor 210 and a first lead layer 201 connected to the driving transistor 210 .

[0209] Step S610, forming an active layer, a gate insulating layer and a gate layer on one side of the base substrate 100 to form a semiconductor layer and a gate of the driving transistor 210, wherein the semiconductor layer of the driving transistor 210 is located in the active layer and includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; the gate of the driving transistor 210 is located in the gate layer; the channel region and the gate of the semiconductor layer are isolated by the gate insulating layer;

[0210] Step S620, forming an interlayer dielectric layer 220, wherein the active layer, the gate insulating layer and the gate layer are all located between the interlayer dielectric layer 220 and the base substrate 100; the interlayer dielectric layer 220 is provided with a second connecting via 252, and the second connecting via 252 exposes the source contact region and the drain contact region;

[0211] Step S630, forming a first wiring layer 201 on the side of the interlayer dielectric layer 220 away from the base substrate 100, the first wiring layer 201 is formed with a source and a drain, the source is connected to the source contact area through the second connection via 252, and the drain is connected to the drain contact area through the second connection via 252.

[0212] Thus, according to the method for preparing the array substrate described in this embodiment, Fig.24 As shown, the prepared driving circuit layer 200 may include a driving transistor, which includes a semiconductor layer, an interlayer dielectric layer and a first lead layer; the semiconductor layer is arranged on one side of the substrate; the semiconductor layer includes a source contact area and a drain contact area; the interlayer dielectric layer is arranged on a side of the semiconductor layer away from the substrate; the first lead layer is arranged on a side of the interlayer dielectric layer away from the substrate, and is formed with a source and a drain; the source is connected to the source contact area, and the drain is connected to the drain contact area.

[0213] According to the array substrate prepared in this embodiment, the first lead layer 201 can be reused as the source-drain metal layer 230, which can further reduce the patterning process and film layer materials in the array substrate preparation process, reduce the preparation cost of the array substrate, and further reduce the thickness of the array substrate.

[0214] In step S130, a functional device layer 300 may be formed on a side of the driving circuit layer 200 away from the base substrate 100. The functional device layer 300 may include array-distributed functional devices 310, such as light-emitting devices for emitting light, ultrasonic emitting devices for emitting ultrasonic waves, heating devices for generating heat, or other current-driven functional devices 310.

[0215] Optionally, the driving circuit layer 200 may include an electrode layer, and each functional device 310 may be electrically connected to the electrode layer. The electrode layer may be the first lead layer 201 or the second lead layer 202, and the present disclosure does not specifically limit this. Further, the connecting electrode layer may include a first electrode and a second electrode disposed adjacent to each other, and the first end of the functional device 310 may be electrically connected to the first electrode, and the second end of the functional device 310 may be electrically connected to the second electrode. In this way, the driving current may flow through the functional device 310 through the first electrode and the second electrode, so that the functional device 310 works.

[0216] In some embodiments, Fig.16 and Fig.17 As shown, a pixel definition layer 271 can be first formed on the side of the driving circuit layer away from the base substrate, and then a conductive glue 272 is coated in the area defined by the pixel definition layer 271, and the functional device 310 is electrically connected to the electrode layer through the conductive glue 272.

[0217] Exemplarily, the functional device 310 may be an LED, a Mini LED or a Micro LED, and the Mini LED or Micro LED may be connected to the electrode layer via solder paste.

[0218] Optionally, the method for preparing the array substrate of the present disclosure may further include:

[0219] A fan-out lead is prepared on the side of the base substrate 100, and the fan-out lead is electrically connected to the driving circuit layer 200;

[0220] A binding layer is prepared on a side of the base substrate 100 away from the driving circuit layer 200 . The binding layer has a plurality of binding pads. Each binding pad is electrically connected to the driving circuit layer 200 through a fan-out lead.

[0221] In this way, the prepared array substrate may include a base substrate 100, a driving circuit layer 200 and a functional device layer 300 stacked in sequence, a binding layer located on a side of the base substrate 100 away from the driving circuit layer 200, and a fan-out lead located on a side of the base substrate 100. In this way, the array substrate may have a smaller edge, facilitating the formation of a larger substrate by splicing a plurality of different array substrates, and making the larger substrate have a smaller splicing seam.

[0222] For example, when the functional device 310 is a Micro LED, a plurality of different small-sized array substrates can be spliced ​​to form a large-sized display screen, and the splicing size of the display screen can be very small, thereby achieving a good display effect. The driving circuits of each array substrate, such as a driving circuit board and a driving chip disposed on the driving circuit board, can be electrically connected through a binding pad to achieve driving of the array substrate.

[0223] In one embodiment of the present disclosure, Fig.25 As shown, the binding layer may include a backside lead layer 610, an insulating layer 620 and a binding pad layer 630 sequentially stacked on the surface of the base substrate 100 away from the driving circuit layer 200, and the backside lead layer 610 may be connected to the fan-out lead ( Fig.25 The insulating layer 620 exposes a portion of the backside lead layer 610 so that the binding pad layer 630 can be electrically connected to the backside lead layer 610.

[0224] Optionally, the backside wiring layer 610 may also be provided with a backside alignment pattern, and the material of the backside alignment pattern may be the same as or different from that of the backside wiring layer 610. Exemplarily, the materials of the backside alignment pattern and the bonding pad layer 630 are both ITO.

[0225] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc., which shall all be considered as part of the present disclosure.

[0226] The present disclosure also provides an array substrate, such as Figure 1 and Figure 2 As shown, the array substrate comprises a base substrate 100, a driving circuit layer 200 and a functional device layer 300 which are stacked in sequence;

[0227] Among them, the driving circuit layer 200 includes at least one first lead layer 201, and any first lead layer 201 includes at least one first lead 2011; any first lead 2011 includes a seed lead 411 arranged on one side of the base substrate 100, and a growth lead 432 arranged away from the surface of the base substrate 100 away from the seed lead 411, and the orthographic projection of the growth lead 432 on the base substrate 100 coincides with the orthographic projection of the seed lead 411 on the base substrate 100.

[0228] The array substrate provided in the present disclosure can be prepared by any one of the preparation methods described in the above-mentioned array substrate preparation method implementation methods, and thus has the same or similar technical effects, which will not be described in detail in the present disclosure.

[0229] In one embodiment of the present disclosure, the thickness of the first lead 2011 is no greater than 5 times the width of the seed lead 411 .

[0230] In one embodiment of the present disclosure, the thickness of the first lead 2011 is 1.5 micrometers to 20 micrometers.

[0231] In one embodiment of the present disclosure, the width of the first lead 2011 at one end away from the base substrate 100 is smaller than the width of the first lead 2011 at one end close to the base substrate 100 .

[0232] In one embodiment of the present disclosure, Fig.17 and Fig.18 As shown, the driving circuit layer 200 includes:

[0233] A first lead layer 201a, disposed on one side of the base substrate 100;

[0234] The first planarization layer 241 is disposed on a side of the first wiring layer 201a away from the base substrate 100 and exposes at least a portion of the first wiring layer 201a;

[0235] The first transfer metal layer 261 is disposed on a side of the first planarization layer 241 away from the base substrate 100 and connected to the first lead layer 201a;

[0236] The second planarization layer 242 is disposed on a side of the first transfer metal layer 261 away from the base substrate 100 and is provided with a first connection via 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and the orthographic projection of the first connection via 251 on the first lead layer 201a does not overlap with the first lead layer 201a;

[0237] Another first lead layer 201 b is disposed on a surface of the second planarization layer 242 away from the base substrate 100 , and is connected to the first transfer metal layer 261 through a first connection via 251 .

[0238] In other words, the driving circuit layer 200 includes at least one first lead layer group, and any first lead layer group includes:

[0239] The first lead layer 201a is provided on one side of the base substrate 100;

[0240] The first planarization layer 241 is disposed on a side of the previous first wiring layer 201a away from the base substrate 100 and exposes at least a portion of the previous first wiring layer 201a;

[0241] The first transfer metal layer 261 is disposed on a side of the first planarization layer 241 away from the base substrate 100 and connected to the previous first lead layer 201a;

[0242] The second planarization layer 242 is disposed on a side of the first transfer metal layer 261 away from the base substrate 100 and is provided with a first connection via 251; the first connection via 251 exposes a portion of the first transfer metal layer 261, and the orthographic projection of the first connection via 251 on the previous first lead layer 201a does not overlap with the previous first lead layer 201a;

[0243] The latter first wiring layer 201 b is disposed on a surface of the second planarization layer 242 away from the base substrate 100 , and is connected to the first transfer metal layer 261 through the first connection via 251 .

[0244] In one embodiment of the present disclosure, Fig. 20 As shown, the driving circuit layer 200 includes:

[0245] The driving transistor 210 is disposed on one side of the substrate 100 . The driving transistor 210 includes a source-drain electrode layer consisting of a source electrode and a drain electrode.

[0246] The third planarization layer 243 is disposed on a side of the source-drain electrode layer away from the base substrate 100 and is provided with a third connection via 253 exposing at least a portion of the source-drain electrode layer;

[0247] The second transfer metal layer 262 is disposed on a side of the third planarization layer 243 away from the base substrate 100 and connected to the source-drain electrode layer through the third connection via 253;

[0248] The fourth planarization layer 244 is disposed on a side of the second transfer metal layer 262 away from the base substrate 100 and has a fourth connection via 254; the fourth connection via 254 exposes a portion of the second transfer metal layer 262, and the orthographic projection of the fourth connection via 254 on the base substrate 100 does not overlap with the orthographic projection of the third connection via 253 on the base substrate 100;

[0249] A first wiring layer 201 is disposed on a surface of the fourth planarization layer 244 away from the base substrate 100 , and is connected to the second transfer metal layer 262 through a fourth connection via 254 .

[0250] In one embodiment of the present disclosure, Fig. 22 As shown, the driving circuit layer 200 includes:

[0251] The driving transistor 210 is disposed on one side of the substrate 100 . The driving transistor 210 includes a source-drain electrode layer consisting of a source electrode and a drain electrode.

[0252] The third planarization layer 243 is disposed on a side of the source-drain electrode layer away from the base substrate 100 and is provided with a third connection via 253 exposing at least a portion of the source-drain electrode layer;

[0253] A first wiring layer 201 is disposed on a surface of the third planarization layer 243 away from the base substrate 100 and is connected to the source-drain electrode layer through a third connection via 253 .

[0254] In one embodiment of the present disclosure, Fig.24 As shown, the driving circuit layer 200 includes a driving transistor, and the driving transistor includes:

[0255] A semiconductor layer, disposed on one side of the substrate 100; the semiconductor layer includes a source contact region and a drain contact region;

[0256] An interlayer dielectric layer 220 is disposed on a side of the semiconductor layer away from the base substrate 100;

[0257] The first lead layer 201 is disposed on a side of the interlayer dielectric layer 220 away from the substrate, and is formed with a source and a drain; the source is connected to the source contact region, and the drain is connected to the drain contact region.

[0258] Other details and possible variations of the array substrate provided in the present disclosure have been described in detail in the above-mentioned array substrate preparation method implementation, and will not be repeated herein in the present disclosure.

[0259] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A method for preparing an array substrate, characterized in that: include: Providing a substrate; forming a driving circuit layer on one side of the base substrate; forming a functional device layer on a side of the driving circuit layer away from the base substrate; Wherein, forming a driving circuit layer on one side of the base substrate includes: forming at least one first lead layer on one side of the base substrate; forming any one first lead layer includes: forming a conductive seed layer on one side of the substrate; forming a removable pattern defining layer on a surface of the conductive seed layer away from the substrate, wherein the removable pattern defining layer is provided with a lead opening, and the lead opening exposes a portion of the conductive seed layer; Using an electroplating process, forming an electroplated metal layer located on the surface of the conductive seed layer in the lead opening; removing the removable pattern defining layer; In the case where the electroplated metal layer is not protected, removing the portion of the conductive seed layer not covered by the electroplated metal layer by an etching process; Wherein, the surface of the electroplated metal layer is partially etched during the etching process.

2. The method for preparing an array substrate according to claim 1, characterized in that: Forming a removable pattern defining layer on a surface of the conductive seed layer away from the substrate includes: forming a removable insulating material layer on a surface of the conductive seed layer away from the substrate; The removable insulating material layer is patterned to form the removable pattern defining layer.

3. The method for preparing an array substrate according to claim 2, characterized in that: Forming a removable insulating material layer on a surface of the conductive seed layer away from the substrate includes: Forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate; The patterning operation of the removable insulating material layer includes: The photoresist material layer is exposed and developed to form the removable pattern defining layer.

4. The method for preparing an array substrate according to claim 3, characterized in that: Forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate includes: Using a degradable photoresist material, forming a photoresist material layer on the surface of the conductive seed layer away from the substrate, wherein the degradable photoresist material is a photoresist material that can be dissolved in a degradation liquid after curing; Removing the removable pattern defining layer includes: The removable pattern defining layer is dissolved using the degradation liquid.

5. The method for preparing an array substrate according to claim 3, characterized in that: Forming a layer of photoresist material on a surface of the conductive seed layer away from the substrate includes: Using a negative photoresist material, forming a photoresist material layer on the surface of the conductive seed layer away from the substrate; Exposing and developing the photoresist material layer includes: The photoresist material layer is exposed and developed to form a removable pattern defining layer having a lead opening, so that the width of the lead opening at one end close to the base substrate is greater than the width of the end away from the base substrate.

6. The method for preparing an array substrate according to claim 1, characterized in that: Forming a removable pattern defining layer on a surface of the conductive seed layer away from the substrate includes: forming a removable pattern defining layer on a surface of the conductive seed layer away from the substrate, wherein the minimum value of the width of the lead opening is a first size value; The step of forming an electroplated metal layer on the surface of the conductive seed layer in the lead opening by using an electroplating process comprises: An electroplating process is adopted to form an electroplated metal layer on the surface of the conductive seed layer in the lead opening, so that the thickness of the electroplated metal layer is a second dimension value, and the second dimension value is not greater than 5 times the first dimension value.

7. The method for preparing an array substrate according to any one of claims 1 to 6, characterized in that: Forming at least one first lead layer on one side of the base substrate comprises: forming a first lead layer on one side of the base substrate; forming a first planarization layer on a side of the first wiring layer away from the substrate, wherein the first planarization layer exposes at least a portion of the first wiring layer; Forming a first transfer metal layer on a side of the first planarization layer away from the base substrate, wherein the first transfer metal layer is connected to the first lead layer; A second planarization layer is formed on a side of the first transfer metal layer away from the base substrate, wherein the second planarization layer has a first connection via hole; the first connection via hole exposes a portion of the first transfer metal layer, and an orthographic projection of the first connection via hole on the first lead layer does not overlap with the first lead layer; Another layer of the first lead layer is formed on a surface of the second planarization layer away from the base substrate, and the other layer of the first lead layer is connected to the first transfer metal layer through the first connecting via hole.

8. An array substrate, characterized in that: It includes a base substrate, a driving circuit layer and a functional device layer which are stacked in sequence; Wherein, the driving circuit layer includes at least one first lead layer, and any one of the first lead layers includes at least one first lead; Any one of the first leads includes a seed lead disposed on one side of the base substrate, and a growth lead disposed on the seed lead away from the surface of the base substrate, and the orthographic projection of the growth lead on the base substrate coincides with the orthographic projection of the seed lead on the base substrate; The seed lead and the growth lead are formed in the same etching process.

9. The array substrate according to claim 8, characterized in that: The thickness of the first lead is no greater than 5 times the width of the seed lead.

10. The array substrate according to claim 8, characterized in that: The width of the first lead at an end away from the base substrate is smaller than the width of the first lead at an end close to the base substrate.

11. The array substrate according to any one of claims 8 to 10, characterized in that: The driving circuit layer comprises: The first lead layer is provided on one side of the base substrate; A first planarization layer is provided on a side of the first lead layer away from the base substrate; A first transfer metal layer is provided on a side of the first planarization layer away from the base substrate and is connected to the first lead layer; A second planarization layer is provided on a side of the first transfer metal layer away from the base substrate and is provided with a first connection via; the first connection via exposes a portion of the first transfer metal layer, and an orthographic projection of the first connection via on the first lead layer does not overlap with the first lead layer; Another first lead layer is disposed on a surface of the second planarization layer away from the base substrate and is connected to the first transfer metal layer through the first connecting via.

12. The array substrate according to any one of claims 8 to 10, characterized in that: The driving circuit layer comprises: A driving transistor is disposed on one side of the substrate, wherein the driving transistor comprises a source-drain electrode layer consisting of a source electrode and a drain electrode; A third planarization layer is provided on a side of the driving transistor away from the substrate and is provided with a third connection via hole exposing at least a portion of the source-drain electrode layer; A second transfer metal layer is provided on a side of the third planarization layer away from the base substrate and is connected to the source-drain electrode layer through the third connection via; a fourth planarization layer, which is disposed on a side of the second transfer metal layer away from the base substrate and has a fourth connection via; the fourth connection via exposes a portion of the second transfer metal layer, and an orthographic projection of the fourth connection via on the base substrate does not overlap with an orthographic projection of the third connection via on the base substrate; The first lead layer is disposed on a surface of the fourth planarization layer away from the base substrate and is connected to the second transfer metal layer through the fourth connection via.

13. The array substrate according to any one of claims 8 to 10, characterized in that: The driving circuit layer comprises: A driving transistor is disposed on one side of the substrate, wherein the driving transistor comprises a source-drain electrode layer consisting of a source electrode and a drain electrode; A third planarization layer is provided on a side of the source-drain electrode layer away from the substrate and is provided with a third connection via hole exposing at least a portion of the source-drain electrode layer; A first wiring layer is disposed on a surface of the third planarization layer away from the base substrate and is connected to the source-drain electrode layer through the third connection via.

14. The array substrate according to any one of claims 8 to 10, characterized in that: The driving circuit layer includes a driving transistor, and the driving transistor includes: A semiconductor layer is disposed on one side of the substrate; the semiconductor layer includes a source contact region and a drain contact region; An interlayer dielectric layer, disposed on a side of the semiconductor layer away from the substrate; The first lead layer is arranged on a side of the interlayer dielectric layer away from the base substrate and is formed with a source and a drain; the source is connected to the source contact area, and the drain is connected to the drain contact area.

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