Backside illuminated image sensor chip and method of manufacturing the same

Abstract

The application provides an image sensor chip and a manufacturing method thereof, a step-shaped via hole or a step-shaped groove is formed on the back surface of a semiconductor substrate, a conductive layer is filled in the step-shaped via hole or the step-shaped groove to form a trace on the back surface or to form a pad at the same time, the height difference of the back surface of the semiconductor substrate is reduced, the influence on the color filter and the micro-lens topography of the pixel array edge in subsequent processes is reduced, the process reliability is improved, the color deviation risk is reduced, the thickness of the medium layer on the sidewall of the step-shaped via hole or the step-shaped groove is controllable, the electric leakage risk can be reduced, since the influence of the trace and the pad thickness on the height difference does not need to be considered, the resistance can be reduced by increasing the thickness of the trace and the pad, and better electrical performance of the device is brought. Since the topography and the width of the step-shaped via hole or the step-shaped groove formed by the method of the application are easy to control, excessive chip area waste is not caused.

Description

TECHNICAL FIELD

[0001] The present application relates to a back-illuminated image sensor chip and a manufacturing method thereof. BACKGROUND

[0002] CMOS image sensors are widely used in various emerging fields such as smart phones, tablets, automobiles, medical treatment, etc. as a device unit for converting optical signals into digital electrical signals. A typical image sensor converts incident photons into electrons or holes through a pixel array, and when an integration period is completed, the collected charges are converted into digital signals through analog and digital circuits and transmitted to the output terminal of the sensor.

[0003] A conventional image sensor adopts front-illumination, i.e. incident photons need to pass through a light path channel composed of multiple dielectric layers and / or a metal interconnection layer to be smoothly absorbed by a photodiode. At the same time, part of the incident photons will be reflected by the interface of the metal interconnection layer and bounce back into the air or even interfere with other pixel units, resulting in reduced sensitivity and / or color distortion of the image sensor.

[0004] With the continuous development of image sensor technology, the pixel unit size is reduced from 1.75 μm to 1.12 μm or even lower, and the dielectric layer light path channel through which the photons need to pass will be reduced at the same time, resulting in serious deterioration of the sensitivity and dark performance, etc. At this time, the back-illuminated image sensor can fundamentally solve the above problems due to its unique structure. In the back-illuminated image sensor, incident photons are incident from the back of the image sensor, which on the one hand avoids energy loss when passing through dielectric layers and / or metal interconnection layers, and on the other hand does not need to balance the area ratio of the photodiode and the metal interconnection layer, facilitating device design, thereby significantly improving the sensitivity and dark performance, etc. of the image sensor.

[0005] For the back-illuminated image sensor technology, the prior art mainly focuses on the active pixel area, the metal shielding area, the pad area and the wiring area. For the active pixel area, a large number of studies focus on structures such as metal grids or composite material grids, which can reduce optical crosstalk between pixels; the metal shielding area usually forms a metal layer above part of the pixel area through photolithography, and the main function is to collect non-optical signals such as dark current, heat generated signal, etc. under no light conditions, and to correct the output signal of the image sensor by subtracting the above non-optical signals. The pads and wires for bonding or testing also need to be formed on the back of the semiconductor substrate. Among them, the pad area needs to have a good conductive performance, and the thickness of the conductive layer is between about 3KÅ and about 15KÅ, and the wiring area is usually arranged at the periphery of the pixel array area, and is used to transmit power signals, ground signals or data signals.

[0006] In the prior art, the bonding pads and the traces are generally located on a medium layer on the back surface of the semiconductor substrate, and have a large thickness, and there is a significant height difference between the bonding pads and the traces and other regions (active pixel region, metal shielding region), which is likely to cause the color filter and the microlens at the edge of the pixel array to change in appearance during the spin coating process of the color filter layer and the microlens layer, and cause abnormal response of the pixels at the edge of the pixel array, and further cause image color deviation and other problems.

[0007] Based on this structure, the height difference between the bonding pad region, the trace region and the active pixel region, the metal shielding region can be reduced by reducing the thickness of the medium layer. However, reducing the thickness of the medium layer may cause the thickness of the medium layer coated on the sidewall of the via or the trench for connecting the back surface trace, the bonding pad and the front surface metal interconnection structure to be insufficient, and cause the risk of leakage between the back surface trace, the bonding pad and the semiconductor substrate. On the other hand, in addition to the thickness of the medium layer, the traces and the bonding pads themselves also have a certain thickness, and the height difference caused by the thickness of the traces and the bonding pads cannot be completely avoided, which is not conducive to the formation of the color filter and the microlens in the later stage.

[0008] In addition, for the above-mentioned problems of the bonding pad region, there is another solution that the semiconductor substrate material of the bonding pad region is etched completely and stopped on the STI layer (shallow trench isolation layer), and then a patterning and etching process is performed to form an opening through the STI layer and the ILD layer (interlayer dielectric layer) and reach the metal interconnection structure, and the bonding pad is formed in the opening, and the etched part needs to be filled in the subsequent process. This solution is relatively complex, and the semiconductor substrate material is etched completely, which cannot form a device structure using the semiconductor substrate material in this region, causing waste of chip area. If this solution is applied to the trace region, the same problem will also exist. SUMMARY

[0009] The purpose of the present application is to provide a back-illuminated image sensor chip and a manufacturing method thereof, which reduces the height difference of the back surface of the semiconductor substrate, improves the process reliability, reduces the color deviation risk, ensures the electrical performance of the device, and is simple and easy to implement, and saves chip area.

[0010] Based on the above considerations, one aspect of the present application provides a manufacturing method of a back-illuminated image sensor chip, comprising: providing a semiconductor substrate having a front surface and a back surface; forming a metal interconnection structure by completing a front surface process of the image sensor; forming a stepped via or a stepped trench on the back surface of the semiconductor substrate to expose part of the metal interconnection structure formed by the front surface process; and filling a conductive layer in the stepped via or the stepped trench to form a back surface trace.

[0011] Preferably, the back surface trace is in electrical communication with the metal interconnection structure on the front surface.

[0012] Preferably, the step of forming the step-shaped via or step-shaped trench comprises forming a first opening first and then forming a second opening in the first opening, or forming a second opening first and then forming a first opening around the second opening, wherein the bottom of the second opening is lower than the bottom of the first opening.

[0013] Preferably, the step of forming the step-shaped via or step-shaped trench comprises forming a first opening first and then forming a second opening in the first opening, or forming a second opening first and then forming a first opening around the second opening, wherein the bottom of the second opening is lower than the bottom of the first opening.

[0014] Preferably, a dielectric layer is formed on the bottom and sidewall of the first opening and the sidewall of the second opening before the conductive layer is filled.

[0015] Preferably, the sidewall of the second opening is selectively etched to the semiconductor substrate so that the sidewall of the second opening extends inwardly to the semiconductor substrate relative to other dielectric layers around, and a dielectric layer is formed on the sidewall of the second opening to control the thickness of the dielectric layer on the sidewall of the second opening.

[0016] Preferably, the thickness of the dielectric layer, the thickness of the conductive layer and the depth of the first opening are adjusted so that the surface height difference between the wiring area and other areas on the back of the semiconductor substrate is less than 0.5 μm.

[0017] Preferably, the other areas on the back of the semiconductor substrate include active pixel areas and metal shielding areas.

[0018] Preferably, the depth of the first opening does not penetrate the semiconductor substrate.

[0019] Preferably, the step of filling the conductive layer comprises forming a first conductive layer and a second conductive layer on the back of the semiconductor substrate in sequence, taking the first conductive layer as an etching stop layer, and removing the second conductive layer outside the step-shaped via or step-shaped trench.

[0020] Preferably, the method for manufacturing the back-illuminated image sensor chip further comprises forming a deep trench isolation structure in the active pixel areas and the metal shielding areas on the back of the semiconductor substrate.

[0021] Preferably, the method for manufacturing the back-illuminated image sensor chip further comprises forming a deep P-type doped well surrounding the step-shaped via or step-shaped trench in the semiconductor substrate, and a deep N-type doped well surrounding the deep P-type doped well.

[0022] Preferably, the metal interconnection structures on the front surface are connected to each other through the conductive layer in the first opening.

[0023] Preferably, the metal interconnection structures on the front surface are also connected to each other through the conductive layer in the second opening.

[0024] Preferably, the manufacturing method of the back-illuminated image sensor chip further comprises: forming a stepped via or a stepped trench around the metal shielding region on the back surface of the semiconductor substrate, and filling a conductive layer in the stepped via or the stepped trench.

[0025] Preferably, the manufacturing method of the back-illuminated image sensor chip further comprises: forming a stepped via or a stepped trench around the analog circuit region on the back surface of the semiconductor substrate, and filling a conductive layer in the stepped via or the stepped trench.

[0026] Another aspect of the present application provides a back-illuminated image sensor chip, comprising: a semiconductor substrate having a front surface and a back surface; a metal interconnection structure on the front surface of the semiconductor substrate; a stepped via or a stepped trench on the back surface of the semiconductor substrate, the stepped via or the stepped trench being filled with a conductive layer to form a trace on the back surface.

[0027] Preferably, the trace on the back surface is in electrical communication with the metal interconnection structure on the front surface.

[0028] Preferably, the back-illuminated image sensor chip further comprises: a pad structure of the image sensor chip formed by the conductive layer in the stepped via or the stepped trench.

[0029] Preferably, the stepped via or the stepped trench comprises a first opening and a second opening in the first opening, the bottom of the second opening being lower than the bottom of the first opening.

[0030] Preferably, the conductive layer is covered with a dielectric layer between the bottom of the first opening, the sidewall of the first opening, and the sidewall of the second opening.

[0031] Preferably, the surface height difference between the trace region and / or the pad region on the back surface of the semiconductor substrate and other regions is less than 0.5 μm.

[0032] Preferably, the other regions on the back surface of the semiconductor substrate comprise an active pixel region and a metal shielding region.

[0033] Preferably, the depth of the first opening does not penetrate the semiconductor substrate.

[0034] Preferably, the conductive layer in the stepped via or the stepped trench comprises a first conductive layer and a second conductive layer on the first conductive layer.

[0035] Preferably, the back-illuminated image sensor chip further comprises a deep trench isolation structure in the active pixel region and the metal shielding region on the back surface of the semiconductor substrate.

[0036] Preferably, the semiconductor substrate further comprises a deep P-type doped well surrounding the step-shaped via or step-shaped trench, and a deep N-type doped well surrounding the deep P-type doped well.

[0037] Preferably, the conductive layer in the first opening connects the metal interconnection structures on the front surface to each other.

[0038] Preferably, the conductive layer in the second opening connects the metal interconnection structures on the front surface to each other.

[0039] Preferably, the back-illuminated image sensor chip further comprises: a step-shaped via or step-shaped trench around the metal shielding area on the back surface of the semiconductor substrate, the step-shaped via or step-shaped trench being filled with a conductive layer.

[0040] Preferably, the back-illuminated image sensor chip further comprises: a step-shaped via or step-shaped trench around the analog circuit area on the back surface of the semiconductor substrate, the step-shaped via or step-shaped trench being filled with a conductive layer.

[0041] The back-illuminated image sensor chip and the manufacturing method thereof of the present application form a step-shaped via or step-shaped trench on the back surface of the semiconductor substrate, fill the step-shaped via or step-shaped trench with a conductive layer to form a trace or a pad on the back surface, reduce the height difference on the back surface of the semiconductor substrate, reduce the influence on the color filter and the microlens topography of the pixel array edge in the subsequent process, improve the process reliability, reduce the color cast risk, the thickness of the dielectric layer on the sidewall of the step-shaped via or step-shaped trench is controllable, which can reduce the risk of electric leakage, since the influence of the thickness of the trace or pad itself on the height difference does not need to be considered, the resistance can be reduced by increasing the thickness of the trace or pad, which brings better electrical performance of the device. In addition, the trace on the back surface formed by the present application can be used to connect the metal interconnection structures on the front surface to each other, which can effectively improve the driving ability of the signal and reduce the voltage drop in transmission; the trace on the back surface can also be used to form physical isolation of a specific area, and since the topography and width of the step-shaped via or step-shaped trench formed by the method of the present application are easy to control, there is no waste of excessive chip area. BRIEF DESCRIPTION OF DRAWINGS

[0042] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof, read in conjunction with the accompanying drawings.

[0043] Figures 1-8 A process schematic diagram of the manufacturing method of the back-illuminated image sensor chip of the present application;

[0044] Figure 9 A partial top view of the back-illuminated image sensor chip according to an embodiment of the present application;

[0045] Figure 10 is a sectional view along the line B1-B1 in Fig. 1; Figure 9

[0046] Figure 11 is a partial plan view of a back-illuminated image sensor chip according to another embodiment of the present application;

[0047] Figure 12 is a sectional view along the line B2-B2 in Fig. 2; Figure 11

[0048] Figure 13 is a partial sectional view of a back-illuminated image sensor chip according to still another embodiment of the present application;

[0049] Figure 14 is a partial sectional view of a back-illuminated image sensor chip according to still another embodiment of the present application.

[0050] In the drawings, like or similar elements are designated with the same reference numerals throughout the several views. DETAILED DESCRIPTION

[0051] To solve the problems in the prior art, the present application provides a back-illuminated image sensor chip and a manufacturing method thereof. A step-shaped via or a step-shaped trench is formed on the back surface of a semiconductor substrate, and a conductive layer is filled in the step-shaped via or the step-shaped trench to form a trace on the back surface. The height difference of the back surface of the semiconductor substrate is reduced, the influence on the color filter and the microlens topography of the pixel array edge in subsequent processes is reduced, the process reliability is improved, the color cast risk is reduced, the thickness of the dielectric layer on the sidewall of the step-shaped via or the step-shaped trench is controllable, the risk of electric leakage is reduced, and the electrical performance of the device is improved by increasing the thickness of the trace without considering the influence of the thickness of the trace itself on the height difference.

[0052] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings in which are shown by way of illustration, for purposes of exemplification and not limitation, specific embodiments in accordance with the present application. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0053] The present application will be described in detail below with reference to specific embodiments.

[0054] Reference is made to Figure 1 ​​, a semiconductor substrate 100 is provided, which has a front side 101 and a back side 102, and the routing area 100B, the pad area 100A and other areas 100C in the semiconductor substrate 100 are distinguished by dotted lines in the figure, wherein the other areas 100C can include active pixel areas, metal shielding areas. Those skilled in the art can understand that the specific settings of the location and size of each area can be selected as needed, and the shown in the figure is only an example and not a limitation.

[0055] On the semiconductor substrate 100, the metal interconnection structure 103 is formed by completing the front side process of the image sensor, and the metal interconnection structure 103 is located in the first dielectric layer 104, and only the metal interconnection structure 103 in the routing area 100B and the pad area 100A is shown, and the details of the other areas 100C are not shown.

[0056] Subsequently, the semiconductor substrate 100 is attached to another wafer or substrate (not shown) for support by bonding from the front side 101 of the semiconductor substrate 100, and the back side 102 of the semiconductor substrate 100 is thinned to reduce the optical path of the active pixel area. Preferably, a deep trench isolation structure (not shown) can be formed in the active pixel area and the metal shielding area of the back side 102 of the semiconductor substrate 100 to reduce the electrical crosstalk between the pixel units of the active pixel area and the metal shielding area.

[0057] Preferably, one or more high dielectric constant films (not shown) such as hafnium oxide, aluminum oxide or tantalum oxide are deposited on the thinned back side 102 of the semiconductor substrate 100, with a total thickness of about 40-1000 Å, for passivation of the back side 102 of the semiconductor substrate 100, and a second dielectric layer (not shown) is deposited on the high dielectric constant film to avoid damage to the passivation layer during subsequent etching.

[0058] Subsequently, the back side 102 of the semiconductor substrate 100 is etched to form a step-shaped via or a step-shaped trench 120, 121 to expose part of the metal interconnection structure 103 formed by the front side process. Figures 2-7 A preferred embodiment of forming a step-shaped via or a step-shaped trench 120, 121 on the back side 102 of the semiconductor substrate 100 to expose part of the metal interconnection structure 103 formed by the front side process is shown.

[0059] Specifically, as shown in Figure 2As shown, a first opening 120 with a depth of about 7000-15000A is formed in the trace area 100B and the pad area 100A of the back surface 102 of the semiconductor substrate 100 by etching, preferably, the depth of the first opening 120 does not penetrate the semiconductor substrate 100, the process is simpler to implement, and meanwhile, the semiconductor substrate material under the first opening 120 can be used to form a device structure, thereby improving the utilization of the silicon semiconductor substrate material. Subsequently, a third dielectric layer (not shown) and an etching stop layer (not shown) are sequentially deposited on the back surface 102 of the semiconductor substrate 100, wherein the third dielectric layer mainly functions to relieve the stress of the semiconductor substrate 100 caused by the deposition of the etching stop layer in the subsequent step, and the etching stop layer can be silicon nitride.

[0060] As shown in Figure 3 , a fourth dielectric layer 117 with a thickness of about 2000-5000A is deposited on the etching stop layer.

[0061] As shown in Figure 4 , the etching in the first opening 120 is continued to form a second opening 121, and the bottom of the second opening 121 is lower than that of the first opening 120. By etching to form the first opening 120, the thickness of the semiconductor substrate 100 in this area is thinned, so that the morphology and width of the second opening 121 formed by re-etching can be better controlled, and excessive area waste can be avoided.

[0062] Preferably, at this time, a certain thickness of the first dielectric layer 104 is still retained above the metal interconnection structure 103, so as to avoid the pollution of the exposed metal interconnection structure 103 to the semiconductor substrate 100 in the subsequent etching.

[0063] As shown in Figure 5 , the semiconductor substrate 100 on the side wall of the second opening 121 is selectively etched, so that the side wall of the second opening 121 extends inwardly to the semiconductor substrate 100 relative to the other dielectric layers (such as the first dielectric layer 104 and the fourth dielectric layer 117) around the second opening 121, so as to facilitate the control of the thickness of the dielectric layer on the side wall of the second opening 121 in the subsequent step and avoid the dielectric layer on the corner above the second opening 121 being too thin, thereby reducing the risk of electric leakage.

[0064] As shown in Figure 6 , a fifth dielectric layer is deposited on the back surface 102 of the semiconductor substrate 100, since the fifth dielectric layer has similar material and the same function as the fourth dielectric layer 117 and the first dielectric layer 104 below it, in the following description, the fifth dielectric layer is combined with the fourth dielectric layer 117 and the first dielectric layer 104 to be marked as a dielectric layer 118. Figure 6

[0065] As shown in Figure 7 ​As shown, the medium layer 118 at the bottom of the second opening 121 is continuously etched until the front metal interconnection structure 103 is exposed.

[0066] At this point, the stepped via or stepped trench 120, 121 of the wiring area 100B and the pad area 100A is formed, which includes the first opening 120 and the second opening 121 in the first opening 120, the bottom of the second opening 121 is lower than the bottom of the first opening 120, and the front metal interconnection structure 103 is exposed at the bottom of the second opening 121, and the bottom and sidewall of the first opening 120 and the sidewall of the second opening 121 are covered with a medium layer 118 of sufficient thickness to serve as insulation and protection, reducing the risk of electrical leakage.

[0067] In addition to the method shown in the above embodiments, in other embodiments not shown, a stepped via or stepped trench with a similar structure can also be formed by first forming the second opening 121 and then forming the first opening 120 around the second opening 121, wherein the bottom of the second opening 121 is lower than the bottom of the first opening 120.

[0068] As shown, the medium layer 118 at the bottom of the second opening 121 is continuously etched until the front metal interconnection structure 103 is exposed. Figure 8 As shown, the medium layer 118 at the bottom of the second opening 121 is continuously etched until the front metal interconnection structure 103 is exposed.

[0069] Specifically, the first conductive layer 133 and the second conductive layer 134 can be formed in sequence on the back surface 102 of the semiconductor substrate 100. The first conductive layer 133 can include a first barrier / adhesion layer, a metal layer, and a second barrier / adhesion layer (not shown) in sequence, the first barrier / adhesion layer and the second barrier / adhesion layer can include at least one of titanium, titanium nitride, tantalum, and tantalum nitride, and the thickness is about 400-700 Å, the metal layer can be tungsten, copper, nickel, or other metal materials that have sufficient etching selectivity with the second conductive layer 134, and the thickness is about 1000-3500 Å. The second conductive layer 134 can be composed of aluminum or other metal materials, or a combination of at least one of titanium, titanium nitride, tantalum, and tantalum nitride and aluminum, and the second conductive layer 134 needs to have a certain thickness to increase the stability of the conductive layer, and the thickness is preferably in the range of about 6000-12000 Å.

[0070] Then, a patterning step is performed to remove the second conductive layer 134 outside the stepped via or stepped trench 120, 121, leaving only the second conductive layer 134 in the stepped via or stepped trench 120, 121 (as shown in Figure 8 Fig. 6). A patterning step is performed on the first conductive layer 133 with the dielectric layer 118 as the etching stop layer to remove the first conductive layer 133 between the trace region 100B and the pad region 100A (as shown in Figure 8 Fig. 7), and between the trace region 100B and the other region 100C (not shown in Fig. 7). Thus, the first conductive layer 133 and the second conductive layer 134 in the stepped via or stepped trench 120, 121 form the backside trace or pad in electrical communication with the frontside metal interconnection structure 103.

[0071] The backside trace formed by the present application can be used to connect the frontside metal interconnection structure to each other, effectively improving the driving ability of the signal and reducing the voltage drop in transmission. Figures 9-12 Fig. 8 shows a specific implementation of the backside trace in the trace region 100B connecting the frontside metal interconnection structure 103 to each other. In Figure 9 , Figure 10 one preferred embodiment (as shown in Fig. 9), the frontside metal interconnection structure 103 can be connected to each other only by the conductive layer 133, 134 in the first opening 120; in Figure 11 , Figure 12 another preferred embodiment (as shown in Fig. 10), the frontside metal interconnection structure 103 can be connected to each other by both the conductive layer 133, 134 in the first opening 120 and the conductive layer 133, 134 in the second opening, further reducing the resistance of the current path and improving the electrical performance.

[0072] In addition, the backside trace can also be used to form physical isolation in a specific region, and since the shape and width of the stepped via or stepped trench formed by the method of the present application are easy to control, there is no excessive waste of chip area. In addition, other structures on the backside can be formed by conventional process steps, such as forming a composite grid, a color filter, and a microlens in the active pixel region of the other region 100C, and forming a shielding metal in the metal shielding region.

[0073] Therefore, by adjusting the thickness of the dielectric layer 118, the thickness of the conductive layers 133 and 134, and the depth of the first opening 120, the height of the wiring area 100B and the pad area 100A can be controlled, keeping the height difference between the wiring area 100B and the pad area 100A and the surface of other areas 100C on the back of the semiconductor substrate at a low level, for example, less than 0.5 μm. This is beneficial for the subsequent formation of color filters and microlenses, improves process reliability, and reduces the risk of color shift. Since the influence of the thickness of the wiring and pads themselves on the height difference does not need to be considered, the resistance can be reduced by increasing the thickness of the wiring and pads, resulting in better device electrical performance.

[0074] Those skilled in the art will understand that, in order to reduce the height difference on the back side of the semiconductor substrate, improve process reliability, and reduce the risk of color deviation, the back traces must be formed using the method of the present invention in the back trace area 100B. In the above embodiments, the technical solution of forming the pad structure of the image sensor chip while filling the stepped via or stepped trench with a conductive layer to form the back traces is only a preferred embodiment of the present invention and not a limitation.

[0075] Preferably, the manufacturing method of the back-illuminated image sensor chip of the present invention can also form a deep P-type doped well surrounding the stepped via or stepped trench 120, 121 in the semiconductor substrate 100 by ion implantation, and a deep N-type doped well surrounding the deep P-type doped well, and ground the deep P-type doped well to the deep N-type doped well to the high voltage, so as to reduce the leakage risk caused by defects generated by etching the semiconductor substrate 100.

[0076] like Figure 13 As shown, according to another preferred embodiment of the present invention, stepped vias or stepped trenches 120, 121 can also be formed around the metal shielding area 200 on the back side of the semiconductor substrate 100, and a conductive layer 135 (which may or may not be connected to the metal interconnect structure 103 on the front side) can be filled in the stepped vias or stepped trenches 120, 121 to reduce the influence of stress in the conductive layer 135 and to achieve better light shielding and electrical isolation for the metal shielding area 200.

[0077] like Figure 14 As shown, according to another preferred embodiment of the present invention, stepped vias or stepped trenches 120, 121 can also be formed around the analog circuit region 300 on the back side of the semiconductor substrate 100, and a conductive layer 135 (which may or may not be connected to the metal interconnect structure 103 on the front side) can be filled in the stepped vias or stepped trenches 120, 121 to provide better light shielding for the analog circuit region 300 and reduce the interference of light-induced noise on the signal.

[0078] Another aspect of the present invention provides a back-illuminated image sensor chip, a preferred embodiment of which is, for example... Figure 8 As shown, it includes: a semiconductor substrate 100 having a front side 101 and a back side 102; a metal interconnect structure 103 located on the front side 101 of the semiconductor substrate 100; stepped vias or stepped trenches 120, 121 located on the back side 102 of the semiconductor substrate 100, wherein the stepped vias or stepped trenches 120, 121 are filled with conductive layers 133, 134 to form traces on the back side; the traces on the back side 102 are electrically connected to the metal interconnect structure 103 on the front side 101.

[0079] Preferably, the back-illuminated image sensor chip further includes a pad structure of the image sensor chip formed by the conductive layers 133 and 134 in the stepped vias or stepped trenches 120 and 121.

[0080] The stepped via or stepped trench includes a first opening 120 and a second opening 121 located within the first opening 120, wherein the bottom of the second opening 121 is lower than the bottom of the first opening 120. Preferably, the depth of the first opening 120 does not penetrate the semiconductor substrate 100. A dielectric layer 118 covers the conductive layers 133 and 134 with the bottom of the first opening 120, the sidewall of the first opening 120, and the sidewall of the second opening 121.

[0081] Preferably, the surface height difference between the wiring area 100B on the back surface 102 of the semiconductor substrate 100 and other areas 100C is less than 0.5 μm. The other areas 100C include active pixel areas and metal shielding areas. More preferably, deep trench isolation structures are provided in the active pixel areas and metal shielding areas.

[0082] Preferably, the semiconductor substrate further includes a deep P-type doped well surrounding the stepped via or stepped trench 120, 121, and a deep N-type doped well surrounding the deep P-type doped well. By grounding the deep P-type doped well and connecting the deep N-type doped well to a high voltage, the risk of leakage caused by defects generated by etching the semiconductor substrate 100 can be reduced.

[0083] In a preferred embodiment, the front metal interconnect structure 103 can be connected to each other only through the conductive layers 133 and 134 in the first opening 120; in another preferred embodiment, the front metal interconnect structure 103 can be connected to each other through both the conductive layers 133 and 134 in the first opening 120 and the conductive layers 133 and 134 in the second opening 121, thereby further reducing the resistance of the current path and improving the electrical performance.

[0084] In such Figure 13In another preferred embodiment shown, the back-illuminated image sensor chip further comprises: a stepped via or a stepped trench 120, 121 around the metal shielding area 200 on the back side of the semiconductor substrate 100, the stepped via or the stepped trench 120, 121 being filled with a conductive layer 135 (the conductive layer 135 can be in communication with or not in communication with the metal interconnection structure 103 on the front side), so as to reduce the influence of stress in the conductive layer 135 and achieve better light shielding effect and electrical isolation for the metal shielding area 200.

[0085] In the back-illuminated image sensor chip shown in the preferred embodiment, the semiconductor substrate 100 is provided with a stepped via or a stepped trench 120, 121 on the back side of the semiconductor substrate 100, and the stepped via or the stepped trench 120, 121 is filled with a conductive layer 135 to form a trace or a pad on the back side of the semiconductor substrate 100. Figure 14 In another preferred embodiment shown, the back-illuminated image sensor chip further comprises: a stepped via or a stepped trench 120, 121 around the metal shielding area 200 on the back side of the semiconductor substrate 100, the stepped via or the stepped trench 120, 121 being filled with a conductive layer 135 (the conductive layer 135 can be in communication with or not in communication with the metal interconnection structure 103 on the front side), so as to reduce the influence of stress in the conductive layer 135 and achieve better light shielding effect and electrical isolation for the metal shielding area 200.

[0086] In another preferred embodiment shown, the back-illuminated image sensor chip further comprises: a stepped via or a stepped trench 120, 121 around the metal shielding area 200 on the back side of the semiconductor substrate 100, the stepped via or the stepped trench 120, 121 being filled with a conductive layer 135 (the conductive layer 135 can be in communication with or not in communication with the metal interconnection structure 103 on the front side), so as to reduce the influence of stress in the conductive layer 135 and achieve better light shielding effect and electrical isolation for the metal shielding area 200.

[0087] It is apparent for those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and the present application can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive. Moreover, it is apparent that the word "comprising" does not exclude other elements and steps, and the word "a" or "one" does not exclude plural. Multiple elements set forth in a device claim can also be implemented by one element. The terms first, second, etc. are used to distinguish names, not to show a particular order.

Claims

1. A method for manufacturing a back-illuminated image sensor chip, characterized in that, include: Provides a semiconductor substrate with a front side and a back side; Complete the front-side process of the image sensor to form a metal interconnect structure; Forming stepped vias or stepped trenches on the back side of the semiconductor substrate to expose a portion of the metal interconnect structure formed by the front side process includes first forming a first opening and then forming a second opening in the first opening. Alternatively, a second opening can be formed first, and then a first opening can be formed around the second opening, wherein the bottom of the second opening is lower than the bottom of the first opening; A conductive layer is filled into the stepped vias or stepped trenches to form trench-shaped traces on the back side. The method includes sequentially forming a first conductive layer and a second conductive layer on the back side of the semiconductor substrate, using the first conductive layer as an etch stop layer to remove the second conductive layer located outside the stepped via or stepped trench. Both the first conductive layer and the second conductive layer are trench-shaped. The projection pattern of the second conductive layer in the horizontal plane is located inside the projection pattern of the first opening in the horizontal plane, and the projection pattern of the second opening in the horizontal plane is located inside the projection pattern of the second conductive layer in the horizontal plane. The thickness of the second conductive layer is 6000-12000 Å. Before filling the conductive layer, a dielectric layer is covered at the bottom and sidewalls of the first opening and at the sidewalls of the second opening; By adjusting the thickness of the dielectric layer, the conductive layer, and the depth of the first opening, the surface height difference between the trace area and other areas on the back side of the semiconductor substrate is made less than 0.5 μm.

2. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, The traces on the back are electrically connected to the metal interconnect structure on the front.

3. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, While filling the stepped vias or stepped trenches with a conductive layer to form back traces, the pad structure of the image sensor chip is also formed.

4. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, The semiconductor substrate of the second opening sidewall is selectively etched so that the second opening sidewall extends into the semiconductor substrate relative to the surrounding dielectric layers, and then a dielectric layer is covered on the second opening sidewall to control the thickness of the dielectric layer of the second opening sidewall.

5. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, Other areas on the back side of the semiconductor substrate include active pixel areas and metal shielding areas.

6. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, The depth of the first opening does not penetrate the semiconductor substrate.

7. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, Also includes: A deep trench isolation structure is formed in the active pixel region and the metal shielding region on the back side of the semiconductor substrate.

8. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, Also includes: A deep P-type doped well surrounding the stepped via or stepped trench is formed in the semiconductor substrate, and a deep N-type doped well surrounding the deep P-type doped well.

9. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, The conductive layer in the first opening connects the front metal interconnect structures to each other.

10. The method for manufacturing a back-illuminated image sensor chip as described in claim 9, characterized in that, The metal interconnect structures on the front are also connected to each other through the conductive layer in the second opening.

11. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, Also includes: A stepped via or a stepped trench is formed around the metal shielding area on the back side of the semiconductor substrate, and a conductive layer is filled in the stepped via or the stepped trench.

12. The method for manufacturing a back-illuminated image sensor chip as described in claim 1, characterized in that, Also includes: A stepped via or stepped trench is formed around the analog circuit area on the back side of the semiconductor substrate, and a conductive layer is filled in the stepped via or stepped trench.

13. A back-illuminated image sensor chip, fabricated using the method described in any one of claims 1-12, characterized in that, include: A semiconductor substrate having a front and a back side; Metal interconnect structure located on the front side of the semiconductor substrate; A stepped via or stepped trench located on the back side of the semiconductor substrate, wherein the stepped via or stepped trench is filled with a conductive layer to form traces on the back side.

14. The back-illuminated image sensor chip as described in claim 13, characterized in that, The traces on the back are electrically connected to the metal interconnect structure on the front.

15. The back-illuminated image sensor chip as described in claim 13, characterized in that, Also includes: The pad structure of the image sensor chip is formed through the conductive layer in the stepped vias or stepped trenches.

16. The back-illuminated image sensor chip as described in claim 13, characterized in that, The stepped through-hole or stepped groove includes a first opening and a second opening located in the first opening, wherein the bottom of the second opening is lower than the bottom of the first opening.

17. The back-illuminated image sensor chip as described in claim 16, characterized in that, A dielectric layer covers the conductive layer between the bottom of the first opening, the sidewall of the first opening, and the sidewall of the second opening.

18. The back-illuminated image sensor chip as described in claim 13, characterized in that, The height difference between the trace area on the back side of the semiconductor substrate and other areas is less than 0.5 μm.

19. The back-illuminated image sensor chip as described in claim 18, characterized in that, Other areas on the back side of the semiconductor substrate include active pixel areas and metal shielding areas.

20. The back-illuminated image sensor chip as described in claim 16, characterized in that, The depth of the first opening does not penetrate the semiconductor substrate.

21. The back-illuminated image sensor chip as described in claim 13, characterized in that, The conductive layer in the stepped through-hole or stepped trench includes a first conductive layer and a second conductive layer located on the first conductive layer.

22. The back-illuminated image sensor chip as described in claim 13, characterized in that, It also includes a deep trench isolation structure located in the active pixel region and the metal shielding region on the back side of the semiconductor substrate.

23. The back-illuminated image sensor chip as described in claim 13, characterized in that, The semiconductor substrate further includes a deep P-type doped well surrounding the stepped via or stepped trench, and a deep N-type doped well surrounding the deep P-type doped well.

24. The back-illuminated image sensor chip as described in claim 16, characterized in that, The conductive layer in the first opening connects the metal interconnect structures on the front side to each other.

25. The back-illuminated image sensor chip as described in claim 24, characterized in that, The conductive layer in the second opening connects the metal interconnect structures on the front side to each other.

26. The back-illuminated image sensor chip as described in claim 13, characterized in that, Also includes: A stepped via or stepped trench is located around a metal shielding area on the back side of the semiconductor substrate, and the stepped via or stepped trench is filled with a conductive layer.

27. The back-illuminated image sensor chip as described in claim 13, characterized in that, Also includes: Stepped vias or stepped trenches are located around the analog circuit area on the back side of the semiconductor substrate, and the stepped vias or stepped trenches are filled with a conductive layer.

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