Transistor with segmented extension regions

Abstract

The present invention relates to a transistor with a segmented extension region, to a structure of a field effect transistor and a method for forming the structure of a field effect transistor. A gate structure is formed above a channel region of a substrate. A first source / drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source / drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes a first and a second segment respectively overlapping the first source / drain region. The first and second segments of the extension region are separated along the longitudinal axis of the gate structure. A portion of the channel region is positioned between the first and second segments of the extension region along the longitudinal axis of the gate structure.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to a structure of a field effect transistor and a method for forming the structure of a field effect transistor. Background Art

[0002] A combination of p-type and n-type field effect transistors can be created using complementary metal-oxide-semiconductor (CMOS) processes and used as devices to construct, for example, logic cells. A field effect transistor typically includes a source, a drain, a body providing a channel region between the source and the drain, and a gate electrode overlapping the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and the drain, thereby generating a device output current.

[0003] As device size increases, the capacitance of the device when "off" (i.e., Coff) increases, and the resistance of the device when "on" (i.e., Ron) decreases, but the product of Coff and Ron (i.e., the figure of merit) remains constant. Historical approaches to improving the figure of merit include strain engineering for higher carrier mobility, gate oxide scaling, and different device geometries (e.g., FinFETs).

[0004] There is a need for improved field effect transistor structures and methods of forming field effect transistor structures. Summary of the invention

[0005] In one embodiment of the present invention, a structure of a field effect transistor is provided. The structure includes a gate structure located above a channel region of a substrate. The gate structure has a longitudinal axis, a first sidewall, and a second sidewall opposite to the first sidewall. The structure also includes: a first source / drain region located in the substrate adjacent to the first sidewall of the gate structure, a second source / drain region located in the substrate adjacent to the second sidewall of the gate structure, and an extension region located in the substrate. The extension region includes a first section and a second section respectively overlapping the first source / drain region. The first section and the second section of the extension region are separated along the longitudinal axis of the gate structure. A portion of the channel region is positioned between the first section and the second section of the extension region along the longitudinal axis of the gate structure.

[0006] In one embodiment of the present invention, a method for forming a structure of a field effect transistor is provided. The method includes: forming a gate structure, the gate structure being disposed above a channel region of a substrate; forming a first source / drain region in the substrate adjacent to a first sidewall of the gate structure; forming a second source / drain region in the substrate adjacent to a second sidewall of the gate structure; and forming an extension region in the substrate. The extension region includes a first section and a second section respectively overlapping the first source / drain region, and the first section and the second section of the extension region are separated along a longitudinal axis of the gate structure. A portion of the channel region is positioned between the first section and the second section of the extension region along the longitudinal axis of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention given above and the detailed description of the embodiments given below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0008] Figure 1 A top view showing the structure of a field effect transistor according to an embodiment of the present invention.

[0009] Figure 2 Display the approximate Figure 1 A cross-sectional view taken along line 2-2.

[0010] Figure 3 Display in Figure 1 Top view of the structure at a later stage of fabrication.

[0011] Figure 4 Display the approximate Figure 3 A cross-sectional view taken along line 4-4.

[0012] Figure 4A Display the approximate Figure 3 A cross-sectional view taken along line 4A-4A.

[0013] Figure 5 A top view of the structure of a field effect transistor according to an alternative embodiment of the present invention is shown.

[0014] Figure 6 Display the approximate Figure 5 A cross-sectional view taken along line 6-6.

[0015] Fig. 6A Display the approximate Figure 5 A cross-sectional view taken along line 6A-6A in FIG. DETAILED DESCRIPTION

[0016] Please refer to Figure 1 , 2 According to an embodiment of the present invention, the structure 10 of the field effect transistor includes a gate structure 12 disposed above a substrate 14. The substrate 14 may be composed of a lightly doped (e.g., lightly p-type doped) single crystal semiconductor material (e.g., single crystal silicon). A shallow trench isolation region 16 may surround an active region of the substrate 14. The shallow trench isolation region 16 may be formed by defining a trench in the substrate 14 using a photolithography and etching process, depositing a layer composed of a dielectric material (e.g., silicon dioxide) by chemical vapor deposition, and planarizing using chemical mechanical polishing.

[0017] The gate structure 12 extends laterally along a longitudinal axis 18 over and through the active region of the substrate 14. The gate structure 12 may include a gate electrode 20 composed of a conductor, such as doped polysilicon (i.e., polysilicon) or a work function metal, and a gate dielectric 22 composed of an electrical insulator, such as silicon dioxide, or a high-k dielectric material, such as hafnium oxide. Sidewall spacers 24 are disposed adjacent to the side surfaces or sidewalls 19, 21 of the gate structure 12. The sidewall spacers 24 may be formed by depositing a conformal layer composed of a dielectric material, such as silicon nitride, over the gate structure 12 and etching the deposited conformal layer using an anisotropic etching process, such as reactive ion etching.

[0018] The structure 10 includes a source / drain region 26 and a source / drain region 28 disposed adjacent to the gate structure 12 with opposing spacer-enclosed sidewalls 19. As used herein, the term "source / drain region" refers to a doped region of a semiconductor material that can serve as a source or drain of a field effect transistor. In one embodiment, the source / drain region 26 can provide a source in the structure 10, and the source / drain region 28 can provide a drain in the structure 10. In an alternative embodiment, the source / drain region 26 can provide a drain in the structure 10, and the source / drain region 28 can provide a source in the structure 10.

[0019] The source / drain regions 26, 28 are doped to have the same polarity conductivity type. To this end, the source / drain regions 26, 28 may be formed simultaneously in corresponding portions of the substrate 14 by an ion implantation process. The source / drain regions 26, 28 contain a concentration of n-type or p-type dopants and may be heavily doped. In one embodiment, the source / drain regions 26, 28 may be formed in the substrate 14 by implanting ions of a p-type dopant (e.g., boron) that provides p-type electrical conductivity. In one embodiment, the source / drain regions 26, 28 may be formed in the substrate 14 by implanting ions of an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. The dopant concentrations of the source / drain regions 26 and the source / drain regions 28 may be equal or substantially equal.

[0020] Ion implantation introduces energetic ions, as indicated by a single arrow, with the ion trajectory stopping above a certain depth range in the substrate 14. The ions may be generated from a suitable source gas and implanted into the substrate 14 using an ion implantation tool under given implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to adjust the characteristics (e.g., depth profile) of the source / drain regions 28. The gate structure 12 may be used in the ion implantation process for self-aligning the formation of the source / drain regions 26, 28.

[0021] The source / drain regions 26, 28 may have top surfaces that coincide with the top surface 11 of the substrate 14, and the source / drain regions 26, 28 may be completely located at and below the top surface 11 of the substrate 14. The channel region 17 provided by a portion of the substrate 14 is laterally disposed between the source / drain regions 26 and the source / drain regions 28. The source / drain regions 26 have a boundary 30 that defines an interface where the conductivity type changes from the conductivity type of the source / drain regions 26 to the conductivity type of the channel region 17. The source / drain regions 28 also have a boundary 30 that defines an interface where the conductivity type changes from the conductivity type of the source / drain regions 28 to the conductivity type of the channel region 17. The boundary 30 extends to a depth d1 relative to the top surface 11 of the substrate 14.

[0022] Please refer to Figure 3 , 4 , 4A, wherein similar reference numerals denote Figure 1 , 2 , and in the next manufacturing stage, the extension region 32 may be disposed adjacent to the source / drain region 26, and the extension region 34 may be disposed adjacent to the source / drain region 28. The extension regions 32, 34 may be formed in the patterned segments 38 by a masked ion implantation process. To this end, an implantation mask 36 may be formed by a photolithography process, the implantation mask including openings disposed above the unmasked portions of the substrate 14 (in which the segments of the extension regions 32, 34 are formed). The implantation mask 36 may include, for example, an organic photoresist layer, which is laid down by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. After the implantation mask 36 is formed, the segments 38 of the extension region 32 and the segments 38 of the extension region 34 may be formed in the unmasked portions of the substrate 14 by ion implantation.

[0023] Sections 38 of extension regions 32, 34 contain a concentration of dopants having the same electrical conductivity type (i.e., polarity type) as the dopants included in source / drain regions 26, 28, and may be heavily doped. In one embodiment where source / drain regions 26, 28 have p-type electrical conductivity, sections 38 of extension regions 32, 34 may be formed in substrate 14 by implanting ions of a p-type dopant (e.g., boron) that provides p-type electrical conductivity. In an alternative embodiment where source / drain regions 26, 28 have n-type electrical conductivity, sections 38 of extension regions 32, 34 may be formed in substrate 14 by implanting ions of an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type electrical conductivity. The dopant concentrations of sections 38 of extension regions 32 and sections 38 of extension regions 34 may be equal or substantially equal.

[0024] The ion implantation process introduces energetic ions, as indicated schematically by a single arrow, with the ion trajectory stopping above a certain depth range in the substrate 14. The ions may be generated from a suitable source gas and implanted into the substrate 14 using an ion implantation tool under given implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to adjust the characteristics (e.g., depth profile) of the segments 38 of the extension regions 32, 34. The implantation mask 36 has a thickness sufficient to stop the energetic ions before they reach the masked portion of the substrate 14. After the segments 38 of the extension regions 32, 34 are formed, the implantation mask 36 may then be removed, for example, by ashing.

[0025] The segments 38 of the extension regions 32, 34 are positioned at spaced locations below the gate structure 12 and its side spacers 24 that reflect the locations of the openings in the implant mask 36. Each segment 38 of the extension region 32 and each segment 38 of the extension region 34 have a boundary 33 that defines an interface where the conductivity type changes from the conductivity type of the extension regions 32, 34 to the conductivity type of the substrate 14. The boundary 33 extends to a depth d1 relative to the top surface 11 of the substrate 14. The segments 38 of the extension regions 32, 34 effectively shorten the gate length at the location of the segments 38 and the width dimension of the channel region 17.

[0026] The segments 38 of the extension regions 32 overlap the source / drain regions 26 and extend laterally from the source / drain regions 26 to terminate at the side edges of the boundary 33. The segments 38 of the extension regions 32 are laterally positioned in a spaced arrangement along the longitudinal axis 18 of the gate structure 12. The segments 38 of the extension regions 32 are positioned below the sidewall spacers 24 at the sidewalls 19 of the gate structure 12 and below a portion of the gate structure 12 in a direction transverse to the longitudinal axis 18.

[0027] Segments 38 of extension regions 34 overlap source / drain regions 28 and extend laterally from source / drain regions 28 to terminate at side edges of boundary 33. Segments 38 of extension regions 34 are also spaced apart along longitudinal axis 18 (i.e., along a direction parallel to longitudinal axis 18) of gate structure 12. Segments 38 of extension regions 32 are also positioned below sidewall spacers 24 at sidewalls 21 of gate structure 12 and below portions of gate structure 12 in a direction transverse to longitudinal axis 18.

[0028] In one embodiment, the segments 38 of the extension regions 32, 34 may have a constant pitch along the longitudinal axis 18 of the gate structure 12. In one embodiment, the segments 38 of the extension regions 32, 34 may have a variable pitch along the longitudinal axis 18 of the gate structure.

[0029] Portions 40 of channel region 17 are laterally positioned along longitudinal axis 18 of gate structure 12 between segments 38 of extension region 32. Portions 40 of channel region 17 may completely separate adjacent segments 38 of extension region 32 from one another and may coexist with source / drain region 26 over a portion of boundary 30 of source / drain region 26 (i.e., share a common boundary with the source / drain region). Portions 40 of channel region 17 are also laterally positioned along longitudinal axis 18 between segments 38 of extension region 34 and may coexist with source / drain region 28 over a portion of boundary 30 of source / drain region 28 (i.e., share a common boundary with the source / drain region). Portions 40 may completely separate adjacent segments 38 of extension region 34 from one another. Portions 40 span from one end at boundary 30 of source / drain region 26 to another end at boundary 30 of source / drain region 28 in a direction transverse to longitudinal axis 18.

[0030] Portion 41 of channel region 17 is laterally positioned between segments 38 of extension region 32 and between segments 38 of extension region 34 along a direction transverse to longitudinal axis 18. Portion 40 of channel region 17 may be wider than portion 41 along the transverse direction, and portion 40 may extend from a boundary 30 shared with source / drain region 26 to a boundary 30 shared with source / drain region 28.

[0031] When combined, the segment 38 of the extension region 32 and the portion 40 of the channel region 17 provide a modulated doping profile along a direction parallel to the longitudinal axis 18 of the gate structure 12 and adjacent to the sidewall 19 of the gate structure 12. Similarly, when combined, the segment 38 of the extension region 34 and the portion 40 of the channel region 17 provide a modulated doping profile along a direction parallel to the longitudinal axis 18 of the gate structure 12 and adjacent to the sidewall 21 of the gate structure 12. Due to masking during their formation, the different modulated doping profiles match in the direction along the longitudinal axis 18.

[0032] Segmented extension regions 32, 34 can provide significant improvement in quality factor compared to unsegmented extension regions through capacitance (Coff) reduction. This improvement can be achieved without strain engineering or gate oxide scaling, and without resorting to different device geometries (e.g., FinFETs).

[0033] In an alternative embodiment, extension region 32 may be formed in an asymmetrical manner with respect to extension region 34. In this regard, extension region 32 may be formed with segment 38, while extension region 34 may be formed entirely without masking so that extension region 34 does not have segment 38. Thus, extension region 34 may be continuous and not have portion 40 of channel region 17.

[0034] Next, middle-of-line (MOL) and back-end-of-line (BEOL) processes are performed, which include forming metal features of interconnect structures coupled to the field effect transistor, such as contacts, vias, and lines. The interconnect structures can be formed by depositing interlayer dielectric layers composed of dielectric materials and forming the metal features in the various interlayer dielectric layers to define metallization levels.

[0035] Please refer to Figure 5 , 6 , 6A, wherein similar reference numerals denote Figure 4 , 4A 1 and 12 , and in accordance with an alternative embodiment of the present invention, structure 10 may include ring region 42 and ring region 44, each formed with segment 48 by ion implantation using implant mask 36 in place. Segment 48 of ring region 42 may be coincident and overlapped with segment 38 of extension region 32. Segment 48 of ring region 44 may be coincident and overlapped with segment 38 of extension region 34. Ring regions 42, 44 extend to a greater depth in substrate 14 than extension regions 32, 34.

[0036] The segments 48 of the ring regions 42, 44 may be laterally positioned along the longitudinal axis 18 of the gate structure 12 and separated by unimplanted portions 40 of the channel region 17. The segments 48 of the ring regions 42, 44 are generally located below the boundaries 33 of the extension regions 32, 34 and below at least a portion of the boundaries of the source / drain regions 26, 28. Portions 40 of the channel region 17 are laterally positioned along the longitudinal axis 18 of the gate structure 12 between the segments 48 of the ring regions 42. The portions 40 completely separate adjacent segments 48 of the ring regions 42 from one another. Portions 40 of the channel region 17 are also laterally positioned along the longitudinal axis 18 of the gate structure 12 between the segments 48 of the ring regions 44. The portions 40 completely separate adjacent segments 48 of the ring regions 44 from one another. Portion 43 of channel region 17 is also laterally positioned between segment 48 of ring region 42 and segment 48 of ring region 44 in a direction transverse to longitudinal axis 18 of gate structure 12. Portion 40 is wider than portion 43 in the transverse direction, and portion 41 ( Figure 4A ) is also wider than portion 43 along this transverse direction.

[0037] Ring regions 42, 44 contain a concentration of dopants having an electrical conductivity type (i.e., polarity type) opposite to the dopants contained in source / drain regions 26, 28 and extension regions 32, 34. Ring regions 42, 44 have the same conductivity type as channel region 17 and locally increase the doping concentration of channel region 17. In the latter aspect, ring regions 42, 44 have a higher dopant concentration than unimplanted channel region 17. In one embodiment where source / drain regions 26, 28 and extension regions 32, 34 have p-type electrical conductivity, ring regions 42, 44 may be formed by implanting ions of n-type dopants (e.g., phosphorus and / or arsenic) that provide n-type electrical conductivity. In an alternative embodiment where source / drain regions 26, 28 and extension regions 32, 34 have n-type electrical conductivity, ring regions 42, 44 may be formed by implanting ions of p-type dopants (e.g., boron) that provide p-type conductivity. Ring region 42 and ring region 44 have equal or substantially equal dopant concentrations.

[0038] The ion implantation process introduces energetic ions, as indicated by the single arrow, and the ion trajectory stops above a certain depth range in the substrate 14. The ions can be generated from a suitable source gas and implanted into the substrate 14 using an ion implantation tool under given implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) can be selected to adjust the characteristics (e.g., depth profile) of the annular regions 42, 44. The implantation mask 36 has a thickness sufficient to stop the energetic ions before they reach the masked portion of the substrate 14. After the extension regions 32, 34 and the annular regions 42, 44 are formed, the implantation mask 36 can then be removed by, for example, ashing.

[0039] In an alternative embodiment, extension regions 32, 34 and ring regions 42, 44 may be formed in an asymmetrical manner. In this regard, extension region 32 may be formed with segment 38 and ring region 42 may be formed with segment 48, while extension region 34 and ring region 44 may be formed integrally without masking, such that extension region 34 does not have segment 38 and ring region 44 does not have segment 48. Extension region 34 and ring region 44 are continuous along longitudinal axis 18 of the gate structure and do not have portion 40 of channel region 17.

[0040] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is provided in a single-chip package (e.g., a plastic carrier having pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0041] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0042] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0043] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intervening feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intervening features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intervening feature.

[0044] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure of a field effect transistor, comprising: a substrate including a channel region; A gate structure located above the channel region, the gate structure having a longitudinal axis, a first sidewall, and a second sidewall opposite to the first sidewall; a first source / drain region located in the substrate adjacent to the first sidewall of the gate structure; a second source / drain region located in the substrate adjacent to the second sidewall of the gate structure; as well as a first extension region located in the substrate and adjacent to the first source / drain region, the first extension region comprising a first section and a second section, and the first section and the second section of the first extension region are separated along the longitudinal axis of the gate structure, wherein the channel region includes a first portion located along the longitudinal axis of the gate structure between the first section and the second section of the first extension region, and The first section and the second section of the first extension region contain dopants having a concentration of the same electrical conductivity type as dopants contained in the first source / drain region and the second source / drain region.

2. The structure of claim 1, wherein: The first portion of the channel region is coextensive with the first source / drain region, and the first extension region is coextensive with the first source / drain region.

3. The structure of claim 1, wherein: The first portion of the channel region completely separates the first section of the first extension region from the second section of the first extension region.

4. The structure of claim 1, wherein: The first extension region has a first conductivity type, and the channel region has a second conductivity type opposite to the first conductivity type.

5. The structure of claim 1, further comprising: The second extension region is located in the substrate and adjacent to the second source / drain region. The second extension region includes a first segment and a second segment. The first segment and the second segment of the second extension region are separated along the longitudinal axis of the gate structure.

6. The structure of claim 5, wherein: The channel region includes a second portion located along the longitudinal axis of the gate structure between the first segment and the second segment of the second extension region.

7. The structure of claim 5, wherein: The channel region includes a fourth portion positioned transversely to the longitudinal axis of the gate structure between the first segment of the first extension region and the first segment of the second extension region, and the channel region includes a third portion positioned transversely to the longitudinal axis of the gate structure between the second segment of the first extension region and the second segment of the second extension region.

8. The structure of claim 1, further comprising: A first annular region is located in the substrate, and the first annular region includes a first segment and a second segment. The first segment of the first annular region is below the first segment of the first extension region, and the second segment of the first annular region is below the second segment of the first extension region, and the first segment and the second segment of the first annular region are separated along the longitudinal axis of the gate structure.

9. The structure of claim 8, wherein: The channel region includes a fifth portion located along the longitudinal axis of the gate structure between the first segment and the second segment of the first annular region.

10. The structure of claim 8, further comprising: The second extension region is located in the substrate and adjacent to the second source / drain region. The second extension region includes a first section and a second section. The first section and the second section of the second extension region are separated along the longitudinal axis of the gate structure.

11. The structure of claim 10, further comprising: A second annular region is located in the substrate, and the second annular region includes a first segment and a second segment. The first segment of the second annular region is below the first segment of the second extension region, and the second segment of the second annular region is below the second segment of the second extension region, and the first segment and the second segment of the second annular region are separated along the longitudinal axis of the gate structure.

12. The structure of claim 11, wherein: The channel region includes a sixth portion located along the longitudinal axis of the gate structure between the first segment and the second segment of the second annular region.

13. The structure of claim 8, wherein: The first extension region has a first conductivity type, the channel region and the first ring region have a second conductivity type opposite to the first conductivity type, and the first ring region contains a higher dopant concentration than the channel region.

14. A method of forming a structure of a field effect transistor, the method comprising: forming a gate structure disposed above a channel region of the substrate; forming a first source / drain region in the substrate adjacent to a first sidewall of the gate structure; forming a second source / drain region in the substrate adjacent to a second sidewall of the gate structure; and forming a first extension region in the substrate adjacent to the first source / drain region, wherein the first extension region includes a first section and a second section, the first section and the second section of the first extension region are separated along the longitudinal axis of the gate structure, and the channel region includes a first portion located along the longitudinal axis of the gate structure between the first section and the second section of the first extension region, and The first section and the second section of the first extension region contain dopants having a concentration of the same electrical conductivity type as dopants contained in the first source / drain region and the second source / drain region.

15. The method of claim 14, wherein: Forming the first extension region in the substrate includes: forming a patterned mask over the substrate; and Dopants are introduced into the substrate using the patterned mask over the substrate to form the first section and the second section of the first extension region.

16. The method of claim 15, wherein: The dopant is introduced by an ion implantation process.

17. The method of claim 14, further comprising: forming a second extension region in the substrate adjacent to the second source / drain region, Wherein, the second extension region includes a first segment and a second segment, the first segment and the second segment of the second extension region are separated along the longitudinal axis of the gate structure, and the channel region includes a second part positioned along the longitudinal axis of the gate structure between the first segment and the second segment of the second extension region.

18. The method of claim 14, further comprising: forming a first annular region in the substrate, Wherein, the first annular region includes a first segment and a second segment, the first segment of the first annular region is below the first segment of the first extension region, the second segment of the first annular region is below the second segment of the first extension region, the first segment and the second segment of the first annular region are separated along the longitudinal axis of the gate structure, and the channel region includes a fifth portion positioned between the first segment and the second segment of the first annular region along the longitudinal axis of the gate structure.

19. The method of claim 18, further comprising: forming a second extension region in the substrate adjacent to the second source / drain region, Wherein, the second extension region includes a first segment and a second segment, the first segment and the second segment of the second extension region are separated along the longitudinal axis of the gate structure, and the channel region includes a second part positioned along the longitudinal axis of the gate structure between the first segment and the second segment of the second extension region.

20. The method of claim 19, further comprising: forming a second annular region in the substrate, Wherein, the second annular region includes a first segment and a second segment, the first segment of the second annular region is below the first segment of the second extension region, the second segment of the second annular region is below the second segment of the second extension region, the first segment and the second segment of the second annular region are separated along the longitudinal axis of the gate structure, and the channel region includes a sixth portion positioned between the first segment and the second segment of the second annular region along the longitudinal axis of the gate structure.

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