A method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region

Abstract

The present invention relates to a method for manufacturing a back-contact heterojunction solar cell, which includes step A, and the specific process is as follows: step a1, sequentially setting a first conductive film layer and a first insulating layer in a first conductive region; step a2, sequentially setting a second conductive film layer and a second protective layer on the first main surface of the semiconductor substrate processed by step a1; step a3, setting a second anti-corrosion layer on the surface of the second protective layer in the region where the second conductive film layer needs to be retained; step a4, first removing the exposed second protective layer by chemical etching, and then removing the exposed second conductive film layer and the second anti-corrosion layer by chemical etching; step a5, removing the remaining second protective layer and the exposed first insulating layer by chemical etching. The purpose of the present invention is to provide a method for manufacturing a back-contact heterojunction solar cell, which uses a chemical etching method to realize the opening of the first conductive region, so that the damage to the bottom semiconductor layer is minimized.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a back contact heterojunction solar cell by chemically etching to expose a first conductive area. Background Art

[0002] Back-contact heterojunction solar cells (HBC) are back-contact solar cells made based on silicon-based high-efficiency heterojunction technology, with both positive and negative electrodes set on the back of the cell. Because both positive and negative electrodes are on the back of the cell, and there is no electrode on the front of the cell to block the light, the maximum light absorption area can be achieved, effectively improving the efficiency of the solar cell. The highest laboratory efficiency of back-contact heterojunction solar cells can reach 26.67%, which is the highest conversion efficiency of silicon-based single-junction cells in the laboratory, and has attracted much attention in the industry.

[0003] Although back-contact heterojunction solar cells have the highest conversion efficiency, their process is extremely cumbersome and complex, and mass production progress is slow. Currently, the common back-contact heterojunction cell manufacturing methods can be divided into two categories: one is a manufacturing method that uses mask and corrosive liquid etching alternately, and the other is a manufacturing method that replaces some of the corrosive liquid etching steps with laser etching. In laser etching, it is inevitable that the laser will damage the bottom semiconductor layer through the insulating layer, which to a certain extent limits the further improvement of the conversion efficiency of back-contact heterojunction solar cells. Therefore, if we want to promote the development of back-contact heterojunction solar cells, it is particularly important to propose a manufacturing method that reduces the impact of lasers on conversion efficiency, has simple processes, and is simple in manufacturing. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a back contact heterojunction solar cell by exposing a first conductive region by chemical etching, wherein the first conductive region is opened by chemical etching to minimize damage to the bottom semiconductor layer.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] A method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose a first conductive region, comprising step A, providing a first conductive region of a first conductive type on a portion of a first main surface of a semiconductor substrate, and providing a second conductive region of a second conductive type on the other portion of the first main surface of the semiconductor substrate, wherein the specific process is as follows:

[0007] Step a1, sequentially disposing a first conductive type film layer and a first insulating layer on a first conductive region of a first main surface of a semiconductor substrate;

[0008] Step a2, sequentially disposing a second conductive type film layer and a second protective layer on the first main surface of the semiconductor substrate processed in step a1;

[0009] Step a3, providing a second anti-corrosion layer on the surface of the second protective layer in the area where the second conductive film layer needs to be retained;

[0010] Step a4, first remove the exposed second protective layer by chemical etching, and then remove the exposed second conductive film layer and the second anti-corrosion layer by chemical etching; or first remove the exposed second protective layer and the second conductive film layer covering the second protective layer by chemical etching, and then remove the second anti-corrosion layer by chemical etching;

[0011] Step a5: remove the remaining second protective layer and the exposed first insulating layer by chemical etching.

[0012] Compared with the prior art, the advantages of the present invention are:

[0013] (1) By adding a second insulating layer and a second anti-corrosion layer, the first conductive region is opened in cooperation with a chemical etching process, so that damage to the semiconductor layer at the bottom of the first conductive region is minimized. In particular, when the first conductive region is a P-type semiconductor layer, this is beneficial to shortening the process time and improving production capacity.

[0014] (2) Combining laser technology, chemical etching technology and texturing and cleaning technology to simplify the production process of the first conductive area and the second conductive area patterns and shorten the process.

[0015] (3) When the process of first making the P-type conductive area is adopted, the P-type semiconductor layer is patterned by laser technology, and the P-type semiconductor layer which is difficult to corrode is removed by utilizing the fast and efficient characteristics of laser etching, thereby shortening the process time and improving production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a simplified flow chart of a method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose a first conductive region.

[0017] Figure 2 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0018] Figure 3 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0019] Figure 4 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0020] Figure 5 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0021] Figure 6 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0022] Figure 7 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0023] Figure 8 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0024] Fig. 9 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0025] Fig.10 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0026] Fig.11 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0027] Fig.12 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0028] Fig.13 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0029] Fig.14 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention.

[0030] Fig.15 It is a cross-sectional schematic diagram of a manufacturing process of a solar cell unit of the present invention. DETAILED DESCRIPTION

[0031] A method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose a first conductive region, comprising step A, providing a first conductive region of a first conductive type on a portion of a first main surface of a semiconductor substrate, and providing a second conductive region of a second conductive type on the other portion of the first main surface of the semiconductor substrate, wherein the specific process is as follows:

[0032] Step a1, sequentially disposing a first conductive type film layer and a first insulating layer on a first conductive region of a first main surface of a semiconductor substrate;

[0033] Step a2, sequentially disposing a second conductive type film layer and a second protective layer on the first main surface of the semiconductor substrate processed in step a1;

[0034] Step a3, providing a second anti-corrosion layer on the surface of the second protective layer in the area where the second conductive film layer needs to be retained;

[0035] Step a4, first remove the exposed second protective layer by chemical etching, and then remove the exposed second conductive film layer and the second anti-corrosion layer by chemical etching; or first remove the exposed second protective layer and the second conductive film layer covering the second protective layer by chemical etching, and then remove the second anti-corrosion layer by chemical etching;

[0036] Step a5: remove the remaining second protective layer and the exposed first insulating layer by chemical etching.

[0037] Before the step a2 is performed, the first main surface and the second main surface of the semiconductor substrate are double-sided textured to form a pyramid texture surface on the exposed surface of the semiconductor substrate.

[0038] The step a2 also includes sequentially disposing a third conductive film layer and a third insulating layer on the second main surface of the semiconductor substrate.

[0039] The specific method of step a1 is to sequentially form a first conductive film layer and a first insulating layer on the first main surface of the semiconductor substrate, and then remove the first insulating layer and the first conductive film layer in the area outside the first conductive region by laser etching to form a first conductive region with the first insulating layer attached to the surface;

[0040] The first conductive film layer is composed of a first passivation layer and a first semiconductor layer formed in sequence from bottom to top with the first main surface of the semiconductor substrate as the base, and the first semiconductor layer is a P-type amorphous silicon layer or a P-type microcrystalline silicon layer; the second conductive film layer is composed of a second passivation layer and a second semiconductor layer formed in sequence from bottom to top with the first main surface of the semiconductor substrate as the bottom, and the second semiconductor layer is an N-type amorphous silicon layer or an N-type microcrystalline silicon layer; the first passivation layer and the second passivation layer are respectively at least one layer of an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer.

[0041] The first insulating layer and the second protective layer are made of materials that can be removed by an acid solution;

[0042] In step a3, the second anti-corrosion layer is made of a material that can be removed by an alkaline solution by screen printing, roller coating, inkjet printing or pad printing;

[0043] In the step a4, the exposed second protective layer is firstly removed by etching with an acidic solution, and then the second anti-corrosion layer and the exposed second conductive film layer are removed by etching with an alkaline solution; or, the exposed second protective layer and the second conductive film layer covered thereunder are firstly directly etched with a printed etching paste, and then the remaining part and the second anti-corrosion layer are removed by etching with an alkaline solution;

[0044] In the step a5, the remaining second protective layer and the exposed first insulating layer are removed by etching with an acid solution.

[0045] The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region also includes the following steps:

[0046] Step B, after the treatment in step A, a conductive layer is provided on the surface of the first conductive area and the second conductive area;

[0047] Step C, providing an anti-deposition layer at the junction of the first conductive area and the second conductive area by printing;

[0048] Step D, forming an electrode on the surface of the conductive layer in the area not covered by the anti-deposition layer;

[0049] Step E: groove the conductive layer in the anti-deposition layer by laser etching or a combination of laser etching and chemical etching; the groove forms a separation insulation between the first conductive area and the second conductive area.

[0050] The specific method of step B is to sequentially form a transparent conductive film and a metal conductive film on the first main surface of the semiconductor substrate processed in step A to form a conductive layer.

[0051] The specific method of step C is to print anti-electroplating ink on the conductive layer obtained by the treatment of step B, and the thickness of the anti-electroplating ink is 3-15um.

[0052] The specific method of step D is to respectively manufacture the first conductive area electrode and the second conductive area electrode by electroplating on the first conductive area and the second conductive area treated in step C, wherein the thickness of the first conductive area electrode and the second conductive area electrode is 3-20 um.

[0053] The specific method of step E is that after the processing of step D, a groove is formed on the anti-deposition layer by laser etching, and then the conductive layer in the grooved area is etched by chemical etching to form an insulating groove between the first conductive area and the second conductive area.

[0054] The present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0055] like Figures 1 to 15 FIG. 1 is a schematic diagram of an embodiment of a method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose a first conductive region provided by the present invention.

[0056] like Fig.15As shown, a back-contact heterojunction solar cell comprises: an N-type silicon wafer substrate 1; a pyramid velvet surface, a semiconductor layer 3-1 and an insulating layer 3-2 arranged in sequence on the front side of the substrate; a first conductive area and a second conductive area alternately arranged on the back side of the substrate, wherein the surface of the first conductive area is a quasi-plane and the second conductive area is a pyramid velvet surface; an intrinsic semiconductor layer 2-1, a P-type doped semiconductor layer 2-2, an insulating layer 2-3, a transparent conductive layer 5-1, a metal conductive layer 5-2 and a metal electrode 7-1 arranged in sequence in the first conductive area; an intrinsic semiconductor layer 4-1, an N-type doped semiconductor layer 4-2, a transparent conductive layer 5-1, a metal conductive layer 5-2 and a metal electrode 7-2 arranged in sequence in the second conductive area; wherein the transparent conductive layer 5-1 and the metal conductive layer 5-2 in the first conductive area and the second conductive area are separated by an insulating groove 8.

[0057] An embodiment of the method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region has the following specific steps:

[0058] Step S1 (fabrication of the first conductive region)

[0059] Step S101, cleaning substrate 1, conventional RCA cleaning (see Figure 2 )

[0060] a. The substrate 1 is of N-type; it can be a single crystal silicon wafer, or a multi-crystalline or cast single crystal silicon wafer.

[0061] Step S102: On one side of the substrate, semiconductor layers 2-1, 2-2 and an insulating layer 2-3 are sequentially formed (see Figure 3 )

[0062] a. The side where the film is deposited serves as the back side of the cell;

[0063] b.2-1 is an intrinsic layer of amorphous silicon or microcrystalline silicon;

[0064] c.2-2 is P-type amorphous silicon or P-type microcrystalline silicon;

[0065] d. The insulating layer 2-3 is silicon nitride, silicon oxide, silicon oxynitride or silicon oxycarbide;

[0066] e. The semiconductor layers 2-1, 2-2 and the insulating layer 2-3 are manufactured by PECVD, LPCVD or HWCVD.

[0067] Step S103, using laser 9 to etch the semiconductor layers 2-1, 2-2 and the insulating layer 2-3, laser opening to make a pattern (see Figure 4 )

[0068] a. Preferably, a green light of 532nm nanosecond or picosecond laser is used, and a UV light of 355nm nanosecond or picosecond laser may also be used;

[0069] b. The laser unetched area serves as the first conductive area, and the laser etched area serves as the second conductive area.

[0070] Step S104: Double-sided velveting is performed on the patterned substrate (see Figure 5 )

[0071] a. The entire front surface of the substrate is a pyramid velvet surface, the area on the back of the substrate with laser openings produces a pyramid velvet surface, and the area without laser openings has no velvet surface;

[0072] b. Texturing refers to the formation of a pyramid-shaped velvet surface by anisotropic corrosion of the substrate surface through a texturing liquid. In the area where no laser opening is performed, the texturing liquid cannot texturize the surface of the substrate because of the obstruction of the insulating layer 2-3. Therefore, the first conductive area naturally formed in this step is still a quasi-plane, and the second conductive area is a pyramid velvet surface.

[0073] Step S201: deposit a semiconductor layer 3-1 and an insulating layer 3-2 on the front side, and deposit semiconductor layers 4-1, 4-2 and a protective layer 4-3 on the back side (see Figure 6 )

[0074] a. The semiconductor layer 3-1 may be a film layer of intrinsic amorphous silicon or microcrystalline silicon, or may be composed of intrinsic amorphous silicon or microcrystalline silicon and N-type amorphous silicon or N-type microcrystalline;

[0075] b. The insulating layer 3-2 is silicon nitride, silicon oxide or silicon oxynitride;

[0076] c. The semiconductor layer 4-1 is intrinsic amorphous silicon;

[0077] d. The semiconductor layer 4-2 is N-type amorphous silicon or N-type microcrystalline silicon;

[0078] e. The protective layer 4-3 is silicon nitride, silicon oxide, silicon oxynitride or silicon oxycarbide;

[0079] f. The manufacturing order of the semiconductor layer 3-1, the insulating layer 3-2, the semiconductor layers 4-1, 4-2, and the protective layer 4-3 is as follows: the semiconductor layer 3-1 may be deposited first, then the semiconductor layers 4-1, 4-2, and the protective layer 4-3 may be manufactured, and finally the insulating layer 3-2 may be manufactured; or the semiconductor layers 4-1, 4-2 may be manufactured first, then the semiconductor layer 3-1, the insulating layer 3-2 may be manufactured, and finally the protective layer 4-3 may be manufactured;

[0080] g. The semiconductor layer 3-1 and the back-deposited semiconductor layers 4-1 and 4-2 are made by PECVD, LPCVD or HWCVD; the insulating layer 3-2 and the protective layer 4-3 are made by PECVD, LPCVD, HWCVD or PVD.

[0081] Step S202, making a protective layer 6-1 (protecting the opened second conductive area and exposing part of the first conductive area) (see Figure 7 )

[0082] a. The material of the protective layer is ink, photosensitive glue or resin, which can be removed with alkali solution;

[0083] b. The production method adopted is screen printing, roller coating, inkjet printing or pad printing;

[0084] c. The thickness of the protective layer 6-1 is 2-10 um.

[0085] Step S203, corroding the protective layer 4-3 (see Figure 8 )

[0086] a. The corrosion solution used is hydrofluoric acid solution;

[0087] b. Using a single-sided etching process, only one side of the substrate of the protective layer 4-3 is corroded, and the side of the insulating layer 3-2 is not corroded;

[0088] c. The semiconductor layer 4-1 / 4-2 does not react with the hydrofluoric acid solution. When the protective layer 4-3 is completely corroded, the corrosion stops naturally. The corrosion process in this step has excellent selectivity.

[0089] Step S204: remove the protective layer 6-1 and etch the exposed semiconductor layers 4-1 and 4-2 (see Fig. 9 )

[0090] a. The solution used is an alkaline cleaning solution, which is an alkaline solution comprising at least one of KOH, NaOH, Na2CO3, NaHCO3 and BDG solution;

[0091] b. Alkaline solution can effectively dissolve the protective layer 6-1. In particular, the alkaline solution containing BDG can effectively remove the residue of the protective layer 6-1 on the substrate and improve the cleaning effect;

[0092] c. In step S203, the area where the protective layer 4-3 is removed and the exposed portion of the semiconductor layer 4-1 / 4-2 is easily corroded by the alkaline solution in this step, thereby exposing the insulating layer 2-3 at the bottom;

[0093] d. The protective layer 4-3 and the insulating layer 2-3 hardly react with the alkaline solution. Therefore, after removing the protective layer 6-1 and the exposed 4-1; 4-2, the corrosion of the alkaline cleaning agent stops naturally. The corrosion process in this step has excellent selectivity.

[0094] Step S205: remove the remaining protective layer 4-3 and etch the insulating layer 2-3 in the exposed area (see Fig.10 )

[0095] a. The corrosion solution used is hydrofluoric acid solution;

[0096] b. Using a single-sided etching process, only one side of the substrate of the protective layer 4-3 and the insulating layer 2-3 is corroded, and the insulating layer 3-2 is not corroded;

[0097] c. The semiconductor layers 4-1 / 4-2 and 2-1 / 2-2 do not react with the hydrofluoric acid solution. When the protective layer 4-3 and the exposed insulating layer 2-3 are completely corroded, the corrosion stops naturally. The corrosion process in this step has excellent selectivity.

[0098] Step S3 (fabrication of electrodes of the first conductive region and the second conductive region and insulation groove between the electrodes)

[0099] Step S301: Deposit a transparent conductive film layer 5-1 and a metal conductive film layer 5-2 (see Fig.11 )

[0100] a. The transparent conductive film layer 5-1 is a doped indium oxide film, such as tin-doped indium oxide, tungsten-doped indium oxide, zinc-doped indium oxide, gallium-doped indium oxide, or titanium-doped indium oxide;

[0101] b. The metal conductive film layer 5-2 comprises a metal layer and an anti-oxidation layer, wherein the metal layer is Cu; the anti-oxidation layer covers the surface of the metal layer, and the anti-oxidation layer can be a transparent conductive film layer, such as ITO / IWO / IZO / AZO / ATO, etc., or a metal or alloy material, such as nickel, nickel-copper, nickel-chromium, etc.

[0102] Step S302: Print anti-plating ink (see Fig.12 )

[0103] a. The thickness of the anti-plating ink is 3-15um.

[0104] Step S303: Use electroplating to make the first conductive area electrode 7-1 and the second conductive area electrode 7-2 (see Fig.13 )

[0105] a. The electrode is composed of a conductive layer and a protective layer, the conductive layer is copper metal, and the protective layer is a metal plating layer containing at least one of tin, silver, nickel and the like; the conductive layer is formed on the surface of the metal conductive film layer 5-2, and the protective layer is formed on the surface of the conductive layer;

[0106] b. The total thickness of the electrode is 3-20um.

[0107] Step S304: Use laser 11 to etch the anti-electroplating ink layer, and use solution etching to etch the metal conductive film layer 5-2 and the transparent conductive film layer 5-1 in the grooved area to form an insulating groove 8 (see FIG. Fig.14 )

[0108] a. The laser used is an infrared (1064nm) laser or a green (532nm) laser, which can be a nanosecond laser or a picosecond laser;

[0109] b. The etching solution is a mixed solution, including at least one aqueous solution of hydrochloric acid, sulfuric acid, hydrogen peroxide, ammonia, copper ions, iron ions, etc.; the metal conductive film layer 5-2 and the transparent conductive film layer 5-1 can be etched at one time with one mixed solution, or the metal conductive film layer 5-2 and the transparent conductive film layer 5-1 can be etched separately with mixed solutions of different proportions to form an insulating groove 8.

[0110] Step S305: remove the remaining anti-plating ink and the exposed semiconductor layers 4-1 and 4-2 in the insulating groove 8 area (see Fig.15 )

[0111] a. The solution used is an alkaline solution, comprising at least one alkaline solution of KOH, NaOH, Na2CO3, and NaHCO3;

[0112] b. The exposed semiconductor layers 4-1 and 4-2 at the bottom of the insulating groove 8 are easily reacted with the alkaline solution and are easily completely or partially removed in this step;

[0113] c. The remaining anti-plating ink may not be removed and may remain on the battery cell.

Claims

1. A method for manufacturing a back contact heterojunction solar cell by chemical etching to expose the first conductive region, characterized in that: The method comprises step A, providing a first conductive region of a first conductive type on a portion of a first main surface of a semiconductor substrate, and providing a second conductive region of a second conductive type on the other portion of the first main surface of the semiconductor substrate, and the specific process is as follows: Step a1, sequentially disposing a first conductive type film layer and a first insulating layer on a first conductive region of a first main surface of a semiconductor substrate; Step a2, sequentially disposing a second conductive film layer and a second protective layer on the first main surface of the semiconductor substrate processed in step a1; the first insulating layer and the second protective layer are made of a material that can be removed by an acidic solution; Step a3, providing a second anti-corrosion layer on the surface of the second protective layer in the area where the second conductive film layer needs to be retained; The second anti-corrosion layer is made of a material that can be removed by an alkaline solution by screen printing, roller coating, inkjet printing or pad printing; Step a4, firstly remove the exposed second protective layer by etching with an acid solution, and then remove the second anti-corrosion layer and the exposed second conductive film layer by etching with an alkaline solution; or, firstly directly etch the exposed second protective layer and most of the second conductive film layer covered thereunder by using a printed etching paste, and then remove the remaining part and the second anti-corrosion layer by etching with an alkaline solution; Step a5, removing the remaining second protective layer and the exposed first insulating layer by etching with an acid solution.

2. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 1, characterized in that: The specific method of step a1 is to sequentially form a first conductive film layer and a first insulating layer on the first main surface of the semiconductor substrate, and then use laser etching to remove the first insulating layer and the first conductive film layer outside the first conductive area to form a first conductive area with the first insulating layer attached to the surface.

3. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 2, characterized in that: The first conductive film layer is composed of a first passivation layer and a first semiconductor layer formed in sequence from bottom to top with the first main surface of the semiconductor substrate as the base, and the first semiconductor layer is a P-type amorphous silicon layer or a P-type microcrystalline silicon layer; the second conductive film layer is composed of a second passivation layer and a second semiconductor layer formed in sequence from bottom to top with the first main surface of the semiconductor substrate as the bottom, and the second semiconductor layer is an N-type amorphous silicon layer or an N-type microcrystalline silicon layer; the first passivation layer and the second passivation layer are respectively at least one layer of an intrinsic amorphous silicon layer and an intrinsic microcrystalline silicon layer.

4. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 1, characterized in that: The step a2 also includes sequentially disposing a third conductive film layer and a third insulating layer on the second main surface of the semiconductor substrate.

5. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 1, characterized in that: It also includes the following steps, Step B, after the treatment in step A, a conductive layer is provided on the surface of the first conductive area and the second conductive area; Step C, providing an anti-deposition layer at the junction of the first conductive area and the second conductive area by printing; Step D, forming an electrode on the surface of the conductive layer in the area not covered by the anti-deposition layer; Step E: groove the conductive layer in the anti-deposition layer by laser etching or a combination of laser etching and chemical etching; the groove forms a separation insulation between the first conductive area and the second conductive area.

6. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 5, characterized in that: The specific method of step B is to sequentially form a transparent conductive film and a metal conductive film on the first main surface of the semiconductor substrate processed in step A to form a conductive layer.

7. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 5, characterized in that: The specific method of step C is to print anti-electroplating ink on the conductive layer obtained by the treatment of step B, wherein the thickness of the anti-electroplating ink is 3-15 μm.

8. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 7, characterized in that: The specific method of step D is to respectively manufacture the first conductive area electrode and the second conductive area electrode by electroplating on the first conductive area and the second conductive area treated in step C, wherein the thickness of the first conductive area electrode and the second conductive area electrode is 3-20 μm.

9. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to claim 5, characterized in that: The specific method of step E is to use laser etching to open grooves on the anti-deposition layer after step D, and then use chemical etching to etch the conductive layer in the grooved area to form an insulating groove between the first conductive area and the second conductive area.

10. The method for manufacturing a back-contact heterojunction solar cell by chemically etching to expose the first conductive region according to any one of claims 2 to 9, characterized in that: Before the step a2 is performed, the first main surface and the second main surface of the semiconductor substrate are double-sided textured to form a pyramid texture surface on the exposed surface of the semiconductor substrate.

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