Circuit comprising a pressure drop element

Abstract

The present application relates to a circuit comprising: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, in particular a DC-coupled operational amplifier (OPAMP), coupled in a feedforward path of the circuit between the circuit input and the circuit output for driving the at least one feedback loop to establish a function of the circuit. The feedforward path of the circuit comprises a second node (Vx) and a first node, wherein the second node and the first node are internal nodes of the active element and coupled between the circuit input and the circuit output, the first node having a first voltage which is a function of the circuit output.

Description

[0001] This application is a divisional application. The original application has the application number 201680085575.5 and the application date is May 12, 2016. The original application is entitled "Circuit with Voltage Drop Component". The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This invention relates to a circuit with a voltage drop element that can be used for linear extension and noise reduction in a DC-coupled system. The invention also relates to analog circuit design, specifically to a DC-coupled voltage amplifier. Background Technology

[0003] Figure 1 A typical DC-coupled analog baseband chain 100 is depicted. In these systems, the signal is amplified by a programmable gain amplifier (PGA) 101, filtered by a low-pass filter (LPF) 102, and then sent to a driver (DRV) 103. Active blocks are obtained through closed-loop DC-coupled voltage amplifiers or operational amplifiers (OPAMPs) 111, 112, and 113. Key characteristics of OPAMPs include noise, linearity, and power consumption.

[0004] Since the useful signal also includes a DC component, the DC common mode must propagate along the chain, and each block on the chain (PGA 101, LPF 102, and DRV 103) needs to conform to this DC common mode. This also applies to OPAMP111, 112, and 113 used in analog blocks.

[0005] Key performance characteristics of the analog block, such as noise, linearity, and power consumption, are also determined by the performance of the OPAMP 111, 112, and 113 used. Typically, for a given power consumption, there is a trade-off between noise and linearity. Figure 2 a and Figure 2 b shows a simulation of PGA 200 ( Figure 2 a) and its OPAMP 201 ( Figure 2 b). The PGA 200 is Figure 1 The implementation of PGA 101 is shown below. It should be noted that OPAMPs with low output impedance require a voltage output stage to be specified.

[0006] The PGA 200 includes an operational amplifier 201 having a first (non-inverting, +) input VIN+, a second (inverting, –) input VIN–, a first (non-inverting, +) output VOUT+, and a second (inverting, –) output VOUT–. A first feedback path, including resistor R2, is coupled between the output VOUT+ and the input VIN+, and a second feedback path, including resistor R2, is coupled between the output VOUT– and the input VIN–. The first input VIN+ of the OPAMP 201 is coupled to the first input VC_IN+ of the PGA 200 via resistor R1. The second input VIN– of the OPAMP 201 is coupled to the second input VC_IN– of the PGA 200 via resistor R1. The first output VOUT+ of the OPAMP 201 is the first output of the PGA 200, and the second output VOUT– of the OPAMP 201 is the second output of the PGA 200.

[0007] The OPAMP 201 includes a non-inverting input path between the drive voltage VDD and ground GND, comprising a first (non-inverting) current source MP+, a first (non-inverting) transistor Q1+, and a second current source Io. The control terminal of Q1+ is coupled to the first input terminal VIN+ of the OPAMP 201. The OPAMP 201 also includes a non-inverting output path between the drive voltage VDD and ground GND, comprising a second (non-inverting) transistor QF+ and a third current source Iout. The control terminal of QF+ is coupled to the first (non-inverting) internal node Vx of the OPAMP 201 located between MP+ and Q1+. The first terminal of QF+ is coupled to the first output terminal VOUT+ of the OPAMP 201, and the second terminal of QF+ is coupled to the drive voltage VDD. The above components can also be used in the reverse manner as described below.

[0008] The OPAMP 201 also includes an inverting input path between the drive voltage VDD and ground GND, comprising a first (inverting) current source MP–, a first (inverting) transistor Q1–, and a second current source Io. The control terminal of Q1– is coupled to the second input terminal VIN– of the OPAMP 201. The OPAMP 201 includes an inverting output path between the drive voltage VDD and ground GND, comprising a second (inverting) transistor QF– and a third current source Iout. The control terminal of QF– is coupled to the first (inverting) internal node Vx– of the OPAMP 201 located between MP– and Q1–. The first terminal of QF– is coupled to the second output terminal VOUT– of the OPAMP 201, and the second terminal of QF– is coupled to the drive voltage VDD.

[0009] Capacitor Cs and resistor Rs are coupled in parallel between the first terminal of Q1+ and the first terminal of Q1–.

[0010] It should be noted that the OPAMP 201 can be implemented as follows: Figure 2 The described differential OPAMP can be implemented as a non-differential OPAMP. The non-differential OPAMP 201 contains only a first current source MP, a first transistor Q1, a second current source Io, a third current source Iout, an input terminal, and an output terminal, and does not contain any components that distinguish between non-inverting and inverting.

[0011] Figure 3 yes Figure 1 and Figure 2 The circuit diagram of the OPAMP 201 shown in a / b is shown. The OPAMP 201 can be used for... Figure 1 The low-pass filter 102 shown is typically used in closed-loop systems such as PGAs or DRVs, for example... Figure 1 The PGA 101 or DRV 103 are shown. Referring to the OPAMP 201, a typical tradeoff in noise linearity can be achieved by adjusting the equivalent input noise...

[0012]

[0013] Where, the overdrive voltage Vov(MP) = Vgs(MP) – Vth(MP) is the difference between the gate-source voltage of MP and its threshold voltage; gm(Q1) is the transconductance of transistor Q1; and Io is the bias current.

[0014] By observing the equation above, it is clear that when Vov(MP) is at its maximum, the voltage reference input noise is reduced.

[0015] In terms of linearity, OPAMP 201 will be linear until MP is used as a current mirror, i.e., MP is in the saturation region. This condition satisfies Vds(MP) > Vov(MP). Since Vds(MP) will be set based on the maximum signal level, this means that linearity is maximized when Vov(MP) is minimized.

[0016] The trade-off in selecting the overdrive voltage Vov(MP) means that noise and linearity are conflicting requirements.

[0017] The requirement for increased DC common-mode complicates matters further. In practice, to prevent DC current from entering or leaving the LPF, the common-mode of the input and output signals must be identical. Furthermore, the input and output common-mode of the LPF are also determined by the preceding and following stages: this, coupled with the requirement for identical common-mode input and output signals, presents a considerable challenge, as the input and output DC voltages that maximize linearity are not necessarily the same.

[0018] Due to the implementation of DC coupling, other constraints on linear performance are... Figure 4 a and Figure 4 As shown in b. Assuming the preamplifier stage is set to common mode VDD / 2 = 1.25V, the voltage Vx at the base of the voltage output unit will be ~2.05V. This voltage will cause transistor MP to compress earlier than transistor Q1, so it is not a linearly optimal choice.

[0019] In this particular case, a lower common-mode voltage at the input will improve the margin and bus performance of the MP transistor (in Figure 4 At the equivalent input signal level, the current generators at the emitters of Q1 and Q2 still have sufficient margin, such as... Figure 5 a and Figure 5 As shown in b. Furthermore, as mentioned earlier, however, when using filters in a communication system, the DC point can be a function of the preceding / following stages, and therefore it is not always possible to set them to the stages that maximize linearity. Summary of the Invention

[0020] The object of this invention is to provide an improved circuit design, particularly an amplifier circuit design, to increase linearity under DC common-mode constraints, especially for applications applicable to... Figure 1 The operational amplifiers of the DC-coupled voltage amplifiers in the PGA, LPF, and / or DRV components of the simulated baseband chain are shown.

[0021] This objective is achieved through the features of the independent claim. Further implementations are apparent from the appended claims, description, and drawings.

[0022] The basic idea of ​​this invention is to generate a DC voltage drop across the first and second stages of an OPAMP to increase linearity. Using this technique, an optimal DC bias point can be achieved in both stages, maximizing linearity for a given supply voltage. Furthermore, the phase margin of the OPAMP is improved by adding a capacitor in parallel with the resistor used for the voltage drop.

[0023] To describe the invention in detail, the following terms, abbreviations, and symbols will be used:

[0024] OPAMP: Operational Amplifier

[0025] PGA: Programmable Gain Amplifier

[0026] DRV: Drive

[0027] LPF: Low-pass filter

[0028] Vov: Overdrive voltage

[0029] Vds: Drain-source voltage

[0030] According to a first aspect, the present invention relates to a circuit comprising: a circuit input terminal; a circuit output terminal; at least one passive feedback loop coupled between the circuit output terminal and the circuit input terminal; and an active element, particularly a DC-coupled operational amplifier (OPAMP), coupled in a feedforward path of the circuit between the circuit input terminal and the circuit output terminal, for driving the at least one feedback loop to establish a function of the circuit. The feedforward path of the circuit includes a second node and a first node, wherein the second node and the first node are internal nodes of the active element and coupled between the circuit input terminal and the circuit output terminal, the first node having a first voltage, the first voltage being a function of the circuit output terminal. The active element includes a first voltage drop element coupled between the second node and the first node, wherein the first voltage drop element is used to decouple the DC level of the first node from the DC level of the second node and provide a DC level of the first node independent of the DC level of the second node.

[0031] By introducing the first voltage drop element, an improved amplifier circuit design can be provided that increases the linearity of the DC common-mode. Such a circuit offers the following advantages: 1) Linearity is maximized because the optimal DC points can be selected for the first and second stages respectively. 2) Greater flexibility in accommodating differences in the DC common-mode of the preceding and following stages. 3) A higher gain-bandwidth product, and improved phase margin because the additional zeros can cancel out the high-frequency poles of the secondary stage. 4) The relationship between OPAMP performance and temperature can be controlled by using appropriate thermal coefficients for Rb and the current generator. 5) Reduced noise performance under certain conditions.

[0032] In a first possible implementation of the circuit provided in the first aspect, the first voltage drop element is adjustable and can be used to provide an adjustable voltage drop between the first node and the second node.

[0033] When the first voltage drop element is adjustable, fine-tuning can improve linearity.

[0034] According to a first implementation of the first aspect, in a second possible implementation of the circuit provided in the first aspect, the first voltage drop element includes a voltage drop resistor and a voltage drop capacitor coupled in parallel between the first node and the second node; and a first current source coupled to the first node.

[0035] Such a voltage drop element can be easily implemented in chip design. The voltage drop element generates a voltage drop between the first and second stages of an active element, such as an OPAMP.

[0036] The voltage drop resistor and the current generator allow for an increase in the overdrive voltage of the current generator, thereby reducing the equivalent input noise. The voltage drop generated by the voltage drop resistor and the current generator allows for optimization of the first and second stage DC operating points, respectively, thus enabling higher linearity.

[0037] According to the second implementation of the first aspect, in a third possible implementation of the circuit, the first current source is used to generate a current flowing into the first node, such that the DC voltage at the first node is higher than the DC voltage at the second node.

[0038] This provides the following advantage: the DC voltage at the first node is decoupled from the DC voltage at the second node.

[0039] According to the second implementation of the first aspect, in the fourth possible implementation of the circuit, the first current source is used to generate a current flowing out of the first node, such that the DC voltage at the first node is lower than the DC voltage at the second node.

[0040] This provides the following advantage: the DC voltage at the first node is decoupled from the DC voltage at the second node.

[0041] According to any one of the second to fourth implementations of the first aspect, in a fifth possible implementation of the circuit, the voltage drop resistor and the voltage drop capacitor are used to introduce zero into the transfer function of the active element.

[0042] The zero in the transfer function stabilizes the circuit. This zero increases the phase margin and increases the gain × bandwidth product.

[0043] According to any one of the second to fifth implementations of the first aspect, in a sixth possible implementation of the circuit, the thermal coefficient of the first current source is positive, so that the voltage at the second node remains approximately constant with temperature.

[0044] This provides the advantage of improved linearity that is not limited by temperature.

[0045] According to any one of the second to sixth implementations of the first aspect, in a seventh possible implementation of the circuit, the active element includes: a first transistor coupled to a first input terminal of the active element; and a second transistor coupled to a first output terminal of the active element, wherein the first transistor is coupled to the second transistor via the at least one feedback loop.

[0046] This transistor design can be easily implemented using, for example, bipolar or FET transistor technology.

[0047] According to the seventh implementation of the first aspect, in the eighth possible implementation of the circuit, the first transistor includes a first terminal, a second terminal, and a control terminal, wherein the control terminal is coupled to a first input terminal of the active element; the second transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to a first output terminal of the active element; and the control terminal is coupled to the first node.

[0048] This transistor design can be efficiently implemented using technologies such as bipolar or FET transistors.

[0049] According to the eighth implementation of the first aspect, in the ninth possible implementation of the circuit, the circuit includes a coupling circuit coupled between the first node and the second terminal of the first transistor, wherein the coupling circuit includes at least the voltage drop resistor and the voltage drop capacitor connected in parallel.

[0050] This type of coupling circuit can be easily implemented in chip design.

[0051] According to any one of the seventh to ninth implementations of the first aspect, in the tenth possible implementation of the circuit, the active element includes: a second current source coupled between the second terminal of the first transistor and the power supply voltage; a third current source coupled between the first terminal of the first transistor and the ground terminal; and a fourth current source coupled between the first terminal of the second transistor and the ground terminal.

[0052] Such active components can be easily implemented using only a small number of electronic components.

[0053] According to any one of the seventh to tenth implementations of the first aspect, in the eleventh possible implementation of the circuit, the active element further includes a load capacitor coupled between the power supply voltage and the second terminal of the first transistor.

[0054] This type of load capacitor can be used for the phase margin of an OPAMP.

[0055] According to any one of the seventh to eleventh implementations of the first aspect, in the twelfth possible implementation of the circuit, the active element is a differential voltage active element, further comprising: a third transistor coupled to a first differential input terminal of the active element; a fourth transistor coupled to a first differential output terminal of the active element; and a second voltage drop element corresponding to the first voltage drop element, wherein the third transistor is coupled to the fourth transistor via the second voltage drop element.

[0056] Differential voltage active components can improve linearity.

[0057] According to the twelfth implementation of the first aspect, in the thirteenth possible implementation of the circuit, the active element further includes a common-source, common-gate circuit coupled between the second terminal of the first transistor and the second terminal of the third transistor.

[0058] The cascode circuit can decouple the inverting and non-inverting components, thereby improving linearity and stability.

[0059] According to a second aspect, the present invention relates to an analog baseband circuit comprising: a programmable gate array (PGA); a low-pass filter (LPF); and a driver (DRV) that are DC series coupled, wherein each of the PGA, LPF, and DRV includes the circuit described in any of the foregoing implementations of the first aspect.

[0060] This provides the following advantage: the circuit can be easily applied to provide analog baseband circuits with increased linearity.

[0061] According to the third aspect, the method relates to increasing the linearity of the OPAMP by using the circuitry in the first aspect or any implementation thereof, particularly by using the first voltage drop element in the first aspect or any implementation thereof.

[0062] This method can increase the linearity of the OPAMP, increase the gain-bandwidth product of the OPAMP, and reduce the noise of the OPAMP.

[0063] This method can be implemented using a resistor Rb, a capacitor Cb connected in parallel with Rb, and a current generator Mb, which generate a voltage drop between the first and second stages of the OPAMP. The voltage drop generated by Rb and the current generator Mb can optimize the DC operating points of the first and second stages, respectively, thus achieving higher linearity. The arrangement of the resistor Rb and the capacitor Cb synthesizes a zero in the OPAMP closed-loop transfer function. This zero improves the phase margin and increases the gain × bandwidth product. Rb and the current generator can increase the overdrive voltage of the current generator MP, thereby reducing the equivalent input noise. Attached Figure Description

[0064] Further embodiments of the present invention will be described in conjunction with the following drawings, wherein:

[0065] Figure 1 A circuit diagram of a DC-coupled analog baseband chain 100 is shown;

[0066] Figure 2 a and Figure 2 b shows the programmable gain amplifier (PGA) 200 ( Figure 2 a) and its operational amplifier (OPAMP) 201 ( Figure 2 b) Circuit diagram;

[0067] Figure 3 It shows Figure 2 The circuit diagram of the OPAMP 201 of the PGA 200 is shown below;

[0068] Figure 4 a and Figure 4 b shows Figure 3 The specific voltage settings of the OPAMP 201 ( Figure 4 a) and the voltage change over time at the internal node Vx– of the OPAMP 201 ( Figure 4 b);

[0069] Figure 5 a and Figure 5 b shows Figure 3 Another specific voltage setting of the OPAMP 201 ( Figure 5 a) and the voltage change over time at the internal node Vx– of the OPAMP 201 ( Figure 4 b);

[0070] Figure 6 A circuit diagram of circuit 600 provided in a first implementation of the present invention is shown;

[0071] Figure 7 A circuit diagram of circuit 700 provided in the second implementation of the present invention is shown. Detailed Implementation

[0072] The following is a detailed description in conjunction with the accompanying drawings, which are an integral part of the description and illustrate specific aspects in which the invention can be practiced. It is understood that other aspects can be utilized and structural or logical changes can be made without departing from the scope of the invention. Therefore, the following detailed description is not intended to be limiting, and the scope of the invention is defined by the appended claims.

[0073] It is understood that comments relating to the described device, circuit, or system also apply to the corresponding method, and vice versa. For example, if a specific method step is described, the corresponding device may include units for performing the described method steps, even if such units are not explicitly illustrated or described in the accompanying drawings. Furthermore, it is understood that features of the various exemplary aspects described herein may be combined with each other unless otherwise specified.

[0074] Figure 6 A circuit diagram of a circuit 600 provided in a first implementation of the present invention is shown. The circuit 600 includes an active element 601, which can correspond to the above... Figures 1 to 5 The described OPAMP 201. The active element 601 is coupled in the feedforward path of the circuit 600 between the circuit input terminals VIN+, VIN– and the circuit output terminals VOU–, VOUT+. At least one feedback path 602a, 602b is coupled between the circuit output terminals VOUT–, VOUT+ and the circuit input terminals VIN+, VIN–. The feedback paths 602a, 602b can be combined... Figure 1 To achieve this. Unlike the OPAMP 201, the active element 601 also includes one or more voltage drop elements 603a, 603b on the feedforward path of the active element 601, for decoupling the DC level at the first node Vy from the DC level at the second node Vx of the active element 601, and providing a DC level at the first node Vy independent of the DC level at the second node Vx.

[0075] The active element 601 includes a non-inverting input terminal VIN+ and an inverting input terminal VIN– as input terminals of the circuit 600, and a non-inverting output terminal VOUT+ and an inverting output terminal VOUT– as output terminals of the circuit 600.

[0076] The first feedback path 602a may include a resistor R2 coupled between the output terminal VOUT+ and the input terminal VIN+, as described above. Figure 2 As described in a. The second feedback path 602b may include a resistor R2 coupled between the output terminal VOUT– and the input terminal VIN–, as described above. Figure 2 As described in a. The first input terminal VIN+ of the active element 601 can be coupled to the first input terminal VC_IN+ of the circuit 600 via resistor R1, as described above. Figure 2 As described in a. The second input terminal VIN– of the active element 601 can be coupled to the second input terminal VC_IN– of the circuit 600 via resistor R1, as described above. Figure 2 As described in a.

[0077] The active element 601 includes a non-reverse input path between the drive voltage VDD and ground GND, comprising a first (non-reverse) current source MP+, a first (non-reverse) transistor Q1+, and a second current source Io. The control terminal of Q1+ is coupled to the first input terminal VIN+ of the active element 601. The active element 601 also includes a non-reverse output path between the drive voltage VDD and ground GND, comprising a second (reverse) transistor QF– and a third current source Iout. The control terminal of QF– forms a first (non-reverse) internal node Vy– and is coupled to the second (reverse) internal node Vx– of the active element 601 located between MP+ and Q1+ via the first voltage drop element 603a. The first terminal of QF– is coupled to the second output terminal VOUT– of the active element 601, and the second terminal of QF– is coupled to the drive voltage VDD.

[0078] The non-reverse input path and the non-reverse output path are coupled by a first voltage drop element 603a, which is included between a first (reverse) internal node Vy– and a second (reverse) internal node Vx– located at the control terminal QF–. The first voltage drop element 603a includes a parallel circuit of a capacitor Cb and a resistor Rb coupled between the first (reverse) internal node Vy– and the second (reverse) internal node Vx–, and a (non-reverse) current source MP+ coupled between the first (reverse) internal node Vy– and ground GND.

[0079] The above components can also be used in the reverse manner as described below.

[0080] The active element 601 also includes a reverse input path between the drive voltage VDD and ground GND, comprising a first (reverse) current source MP–, a first (reverse) transistor Q1–, and a second current source Io. The control terminal of Q1– is coupled to the second input terminal VIN– of the active element 601. The active element 601 also includes a reverse output path between the drive voltage VDD and ground GND, comprising a second (non-reverse) transistor QF+ and a third current source Iout. The control terminal of QF+ forms a first (non-reverse) internal node Vy+ and is coupled to the second (non-reverse) internal node Vx+ of the active element 601 located between MP– and Q1– via the second voltage drop element 603b. The first terminal of QF+ is coupled to the second output terminal VOUT+ of the active element 601, and the second terminal of QF+ is coupled to the drive voltage VDD.

[0081] The inverting input path and the inverting output path are coupled by a second voltage drop element 603b, which is included between a first (non-inverting) internal node Vy+ and a second (non-inverting) internal node Vx+ located at the control terminal of QF+. The second voltage drop element 603b includes a parallel circuit of a capacitor Cb and a resistor Rb coupled between the first (non-inverting) internal node Vy+ and the second (non-inverting) internal node Vx+, and a (reverse) current source MB– coupled between the first (non-inverting) internal node Vy+ and ground GND.

[0082] Capacitor Cs and resistor Rs are coupled in parallel between the first terminal of Q1+ and the first terminal of Q1–.

[0083] It should be noted that the active element 601 can be as follows: Figure 6 The differential OPAMP shown can be implemented as a non-differential OPAMP. The non-differential OPAMP 601 has only a first current source MP, a first transistor Q1, a second current source Io, a third current source Iout, an input terminal, and an output terminal, without any components that distinguish between non-inverting and inverting.

[0084] The first and / or second transistors Q1+, Q1–, QF+, and QF– can be implemented as bipolar transistors. In this case, the control terminal is the base terminal, the first terminal is the emitter terminal, and the second terminal is the collector terminal. Alternatively, the first and / or second transistors Q1+, Q1–, QF+, and QF– can be implemented as field-effect transistors. In this case, the control terminal is the gate terminal, the first terminal is the source terminal, and the second terminal is the drain terminal.

[0085] It should be noted that the active element 601 can be implemented as a differential active element or as a non-differential active element. The differential active element is as follows: Figure 6 As shown, however, non-differential active components include, for example... Figure 6 The half of the components shown, namely a first current source MP, a first transistor Q1, a second current source Iin, a third current source Iout, an input terminal, and an output terminal, does not include components that distinguish between non-inverting and inverting.

[0086] The basic design of the circuit 600 can be described as follows: The circuit 600 includes: a circuit input terminal VIN; a circuit output terminal VOUT; at least one passive feedback loop 602a, 602b coupled between the circuit output terminal and the circuit input terminal; and an active element 601, particularly a DC-coupled operational amplifier (OPAMP), coupled in the feedforward path of the circuit 600 between the circuit input terminal and the circuit output terminal, for driving the at least one feedback loop to establish the function of the circuit. The feedforward path of the circuit 600 includes a second node Vx and a first node Vy, wherein the second node Vx and the first node Vy are internal nodes of the active element 601 and coupled between the circuit input terminal and the circuit output terminal, and the first node Vy has a first voltage, which is a function of the circuit output terminal. The active element 601 includes a first voltage drop element 603a coupled between the second node Vx and the first node Vy. The first voltage drop element 603a is used to decouple the DC level of the first node from the DC level of the second node and provide the DC level of the first node independent of the DC level of the second node Vx.

[0087] The first voltage drop element 603a may be adjustable and may be used to provide an adjustable voltage drop between the first node Vy and the second node Vx. The first voltage drop element 603a may include: a voltage drop resistor Rb and a voltage drop capacitor Cb coupled in parallel between the first node Vy and the second node Vx; and a first current source Mb coupled to the first node Vy.

[0088] The first current source Mb can generate a current Io flowing into the first node Vy, such that the DC voltage at the first node Vy is higher than the DC voltage at the second node Vx. Alternatively, the first current source Mb can generate a current flowing out of the first node Vy, such that the DC voltage at the first node Vy is lower than the DC voltage at the second node Vx.

[0089] The voltage drop resistor Rb and the voltage drop capacitor Cb can be used to introduce zero into the transfer function of the active element 601. The thermal coefficient of the first current source Mb can be positive so that the voltage at the second node Vx remains approximately constant with temperature.

[0090] The active element 601 may include: a first transistor Q1+ coupled to a first input terminal Vin+ of the active element 601; and a second transistor QF- coupled to a first output terminal Vout- of the active element 601. The first transistor Q1+ may be coupled to the second transistor QF- via the at least one feedback loop 602a.

[0091] The first transistor Q1+ may include a first terminal, a second terminal, and a control terminal, wherein the control terminal may be coupled to the first input terminal Vin+ of the active element 601. The second transistor QF– may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to the first output terminal Vout– of the active element 601. The control terminal may be coupled to the first node Vy.

[0092] The circuit 600 may further include a coupling circuit coupled between the second terminal of the first node Vy and Q1+, wherein the coupling circuit may include at least the voltage drop resistor Rb and the voltage drop capacitor Cb connected in parallel.

[0093] The active element 601 may include: a second current source MP+ coupled between the second terminal of Q1+ and the power supply voltage; a third current source Io coupled between the first terminal of Q1+ and the ground terminal; and a fourth current source Iout coupled between the first terminal of QF– and the ground terminal.

[0094] The active element 601 may further include a load capacitor Cp coupled between the power supply voltage and the second terminal of Q1+. The active element 601 may be a differential voltage active element, further including: a third transistor Q1- coupled to the first differential input terminal Vin- of the active element; a fourth transistor QF+ coupled to the first differential output terminal Vout+ of the active element; and a second voltage drop element corresponding to the first voltage drop element. The third transistor Q1- may be coupled to the fourth transistor QF+ via the second voltage drop element.

[0095] The active element 601 may further include a common source cascode circuit coupled between the second terminal of Q1+ and the second terminal of Q1–.

[0096] The circuit 600 can be used in analog baseband circuits, for example... Figure 1The analog baseband circuit 100 described herein may include: a programmable gate array (PGA) 101; a low-pass filter (LPF) 102; and a driver (DRV) 103, which are DC series coupled. Each of the PGA 101, LPF 102, and DRV 103 includes the circuit 600 described above.

[0097] The circuit 600 addresses the aforementioned problems by introducing voltage drop elements 603a and 603b, namely a combination of resistor Rb, capacitor Cb, and an additional current generator. The voltage drop elements 603a and 603b function in the following ways: 1) Rb and the current generator Mb generate a DC voltage drop, which simultaneously optimizes the DC operating point of the first and second stages. 2) Rb and Cb introduce zeros at high frequencies, which improves the phase margin of the OPAMP, i.e., the active element 601. 3) Rb and the current generator Mb can have suitable thermal coefficients to provide the desired DC bias point for node Vx. This feature ensures the desired linear performance for different temperatures. 4) Under certain conditions (high gain of the OPAMP), the circuit 600 improves noise performance.

[0098] Regarding point (3), Rb and the current generator can have suitable thermal coefficients to provide the desired DC bias point for node Vx. This feature ensures the desired linear performance at different temperatures. Below is one example. The DC voltage Vx can be expressed as:

[0099] Vx = VOUT + Vbe(QF) + R*Io*α

[0100] Its derivative with temperature can be expressed as:

[0101] dVx / dT=dVOUT / dT+dVbe(QF) / dT+R*α*dIo / dT.

[0102] Assuming a constant DC value is required for temperature Vx, and the DC voltage VOUT does not change with temperature, dVx / dt=0 limits dIo / dT=–dVbe / dT / (α*R), therefore the current generator needs to have a positive temperature coefficient (dVbe / dT is negative).

[0103] In practice, the circuit 600 is capable of temperature control of the DC voltage at node Vx in order to provide the desired performance for temperature.

[0104] As expected, under certain conditions, the circuit simultaneously improves both linearity and noise performance (point 4). This can be achieved by comparing the circuit 300 without a voltage drop element with the circuit 600 including a voltage drop element and obtaining the input voltage-to-noise equation:

[0105] Input equivalent voltage noise V IN –Circuit 300:

[0106]

[0107] Input equivalent voltage noise Vinv IN – Circuit 600 (with very high gm(Q1)*Rds(MP), as in the case of a typical OPAMP)

[0108]

[0109] To compare these two equations, the input equivalent voltage noise of circuit 300 can be rewritten as follows:

[0110]

[0111] Because transistor MP has more available margin (due to DC voltage drop), the Vov(MP) of circuit 600 can be greater than the Vov(MP) of circuit 300, making Vinv IN <V IN In summary, under certain conditions, the disclosed circuit 600 also offers better noise performance.

[0112] It should be noted that all the above considerations are as follows: Figure 6 The same principle applies when two cascaded transistors Q2+ / Q2– are included between Vx– and Vx+. The same principle can also be applied to non-DC coupled systems using voltage drop elements.

[0113] Therefore, the circuit 600 has the following advantages: linearity is maximized because the optimal DC points can be selected for the first and second stages respectively; greater flexibility in adapting to the difference in DC common mode between the front and rear stages; a higher gain × bandwidth product, and improved phase margin because the additional zeros can cancel out the high-frequency poles of the secondary stage; control of the relationship between OPAMP performance and temperature by using appropriate thermal coefficients for Rb and the current generator; and reduced noise performance under certain conditions.

[0114] Figure 7 A circuit diagram of circuit 700 provided in the second implementation of the present invention is shown.

[0115] The circuit 700 corresponds to the above Figure 6The circuit 600 is described. However, the current sources MB+ and MB– of the voltage drop elements 603a and 603b are not coupled to the reference voltage VDD, but rather MB+ and MB– are coupled to ground GND. These different voltage drop elements used in the circuit 700 are referred to as 703a and 703b.

[0116] While specific features or aspects of the invention may have been disclosed in combination with only one of several implementations, such features or aspects may be combined with one or more features or aspects of other implementations, provided that they are necessary or advantageous for any given or particular application. Furthermore, to a certain extent, the terms “comprising,” “having,” “having,” or other variations of these words are used in the detailed specification or claims, and such terms are similar to the term “comprising,” both indicating inclusion. Similarly, the terms “exemplarily,” “for example,” are used only as examples and not as best or preferred. The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical contact or electrical contact, or whether they are not in direct contact with each other.

[0117] While specific aspects have been illustrated and described herein, those skilled in the art will understand that various alternatives and / or equivalent embodiments may be implemented without departing from the scope of the invention regarding the specific aspects shown and described. This application is intended to cover any modifications or alterations to the specific aspects discussed herein.

[0118] Although the elements in the following claims are listed in a particular order by means of their corresponding labels, these elements are not necessarily limited to being implemented in the particular order unless the formulation of the claims otherwise implies the specific order in which some or all of these elements are implemented.

[0119] Based on the above description, many alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that numerous other applications of the invention exist besides those described herein. Although the invention has been described with reference to one or more specific embodiments, those skilled in the art will recognize that many changes can be made to the invention without departing from its scope. Therefore, it should be understood that the invention can be practiced in ways other than those specifically described herein, as long as it remains within the scope of the appended claims and their equivalents.

Claims

1. An operational amplifier circuit, characterized in that, include: The first stage and the second stage of the operational amplifier circuit are coupled with a first voltage drop element, which is used to generate a DC voltage drop between the first stage and the second stage. The first stage includes the amplification stage circuit of the operational amplifier circuit, the second stage includes the output stage circuit of the operational amplifier circuit, the first voltage drop element is coupled to the second stage at a first node, and the first voltage drop element is coupled to the first stage at a second node; The first voltage drop element is used to decouple the DC level of the first node from the DC level of the second node, and to provide the DC level of the first node independent of the DC level of the second node; The first voltage drop element is adjustable and can be used to provide an adjustable voltage drop between the first node and the second node.

2. The operational amplifier circuit according to claim 1, characterized in that, The first voltage drop element includes: A voltage drop resistor and a voltage drop capacitor are coupled in parallel between the first node and the second node; A first current source coupled to the first node.

3. The operational amplifier circuit according to claim 2, characterized in that, The first current source is used to generate current flowing into the first node, such that the DC voltage at the first node is higher than the DC voltage at the second node.

4. The operational amplifier circuit according to claim 2, characterized in that, The first current source is used to generate current flowing out of the first node, such that the DC voltage at the first node is lower than the DC voltage at the second node.

5. The operational amplifier circuit according to any one of claims 2–4, characterized in that, The voltage drop resistor and the voltage drop capacitor are used to introduce zero into the transfer function of the operational amplifier circuit.

6. The operational amplifier circuit according to claim 5, characterized in that, The thermal coefficient of the first current source is positive so that the voltage at the second node remains constant under temperature changes.

7. The operational amplifier circuit according to claim 6, characterized in that, Also includes: A first transistor coupled to the first input terminal of the operational amplifier circuit; A second transistor coupled to the first output terminal of the operational amplifier circuit; The first transistor is coupled to the second transistor via at least one feedback loop of the operational amplifier circuit.

8. The operational amplifier circuit according to claim 7, characterized in that, The first transistor includes a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first transistor is coupled to the first input terminal of the operational amplifier circuit, the first terminal of the first transistor is coupled to the ground terminal, and the second terminal of the first transistor is coupled to the power supply voltage. The second transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the first output terminal of the operational amplifier circuit, and the second terminal of the second transistor is coupled to the power supply voltage; The control terminal of the second transistor is coupled to the first node.

9. The operational amplifier circuit according to claim 8, characterized in that, Also includes: A second current source coupled between the second terminal of the first transistor and the power supply voltage; A third current source coupled between the first terminal of the first transistor and the ground terminal; A fourth current source coupled between the first terminal and the ground terminal of the second transistor.

10. The operational amplifier circuit according to claim 9, characterized in that, Also includes: The load capacitance coupled between the power supply voltage and the second terminal of the first transistor.

11. The operational amplifier circuit according to claim 10, characterized in that, include: A third transistor coupled to the first differential input terminal of the operational amplifier circuit; A fourth transistor coupled to the first differential output terminal of the operational amplifier circuit; A second voltage drop element corresponding to the first voltage drop element; The third transistor is coupled to the fourth transistor via the second voltage drop element.

12. The operational amplifier circuit according to claim 11, characterized in that, The operational amplifier circuit also includes: A common-source, common-gate circuit coupled between the second terminal of the first transistor and the second terminal of the third transistor.

13. An analog baseband circuit, characterized in that, The device includes a programmable gate array, a low-pass filter, and a driver that are connected in series. The programmable gate array, the low-pass filter, and the driver all include an operational amplifier circuit. The operational amplifier circuit includes a first stage and a second stage. A first voltage drop element is coupled between the first stage and the second stage of the operational amplifier circuit. The first voltage drop element is used to generate a DC voltage drop between the first stage and the second stage. The first stage includes the amplification stage circuit of the operational amplifier circuit, the second stage includes the output stage circuit of the operational amplifier circuit, the first voltage drop element is coupled to the second stage at a first node, and the first voltage drop element is coupled to the first stage at a second node; The first voltage drop element is used to decouple the DC level of the first node from the DC level of the second node, and to provide the DC level of the first node independent of the DC level of the second node; The first voltage drop element includes a voltage drop resistor and a voltage drop capacitor coupled in parallel between the first node and the second node. The first voltage drop element is adjustable and can be used to provide an adjustable voltage drop between the first node and the second node. The first voltage drop element is used to introduce a zero value in the high-frequency part of the transfer function of the operational amplifier circuit. The zero value is used to stabilize the circuit, improve the phase margin, and increase the gain × bandwidth product.

14. A first voltage drop element applied in an operational amplifier circuit, characterized in that, The first voltage drop element includes a voltage drop resistor and a voltage drop capacitor coupled in parallel between the first node and the second node, and also includes a first current source. The first current source is used to generate a current flowing into the first node, such that the DC voltage at the first node is higher than the DC voltage at the second node. The first node is coupled to the first terminal of the second transistor, the second terminal of the second transistor is connected to the power supply, the third terminal of the second transistor is coupled to ground through the current source, and the third terminal of the second transistor is also coupled to the input terminal of the operational amplifier circuit through a feedback circuit. The first voltage drop element is coupled to the output stage circuit of the operational amplifier circuit at the first node, and the first voltage drop element is coupled to the amplification stage circuit of the operational amplifier circuit at the second node.

15. The first voltage drop element according to claim 14, characterized in that, The DC voltage Vx of the operational amplifier circuit satisfies the following functional relationship: ； Where VOUT is the output voltage of the operational amplifier circuit, Vbe(QF) is the bias voltage of the second transistor, and R is the resistance value of the voltage drop resistor. The output current of the first current source is denoted as .

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