Impedance Correction Circuit

Abstract

The present invention provides an impedance correction circuit, including a first correction circuit and a second correction circuit, a switch circuit and a control circuit. The first correction circuit is suitable for coupling an external resistor through a pad and generating a first voltage. The second correction circuit generates a second voltage and a third voltage. The switch circuit is coupled to the first and second correction circuits, and the switch circuit selectively provides the first, second and third voltages to the first and second nodes. The control circuit is coupled to the first and second nodes, and the control circuit generates the first, second and third control signals according to the voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages to the first and second nodes respectively.

Description

Technical Field

[0001] The invention relates to a circuit, and in particular to an impedance correction circuit. Background Art

[0002] In conventional techniques, when performing impedance calibration (e.g., ZQ calibration) of a memory, the memory can only be calibrated in a limited cycle to calibrate the internal impedance value of the memory to be close to a preset impedance. However, when the calibration is performed in a limited cycle, the calibration result is usually not accurate enough and the impedance value has a considerable error, thereby causing the internal impedance of the memory device to not meet the specification. Summary of the invention

[0003] The present invention is directed to an impedance correction circuit for performing impedance correction on a memory device.

[0004] According to an embodiment of the present invention, an impedance correction circuit includes a first correction circuit, a second correction circuit, a switch circuit and a control circuit. The first correction circuit is suitable for coupling an external resistor through a pad and generating a first voltage according to a first control signal. The second correction circuit generates a second voltage and a third voltage according to the first control signal, the second control signal and the third control signal. The switch circuit couples the first correction circuit and the second correction circuit, and the switch circuit selectively provides the first voltage, the second voltage and the third voltage to the first node and the second node. The control circuit couples the switch circuit to the first node and the second node, and the control circuit compares the voltages of the first node and the second node with the first reference signal and the second reference signal respectively. The control circuit generates a first control signal, a second control signal and a third control signal according to the comparison result, wherein in the first time interval, the switch circuit provides the first voltage to the first node and the second node; wherein in the second time interval, the switch circuit provides the second voltage to the first node and the second node, or provides the second voltage and the third voltage to the first node and the second node respectively.

[0005] Based on the above, the impedance correction circuit of the present invention can perform multiple comparison operations simultaneously, effectively reducing the time required for impedance correction and increasing the accuracy of impedance correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a schematic diagram of an impedance correction circuit according to an embodiment of the present invention;

[0007] Figure 1B is a diagram showing the relationship between the impedance value of the correction circuit and the voltage of the control signal according to an embodiment of the present invention;

[0008] Figure 1C A schematic diagram of an operation cycle of an impedance correction circuit according to an embodiment of the present invention;

[0009] Figure 1D A schematic diagram of switching of an impedance correction circuit in a time interval according to an embodiment of the present invention;

[0010] Figure 1E A schematic diagram of switching of an impedance correction circuit in a time interval according to an embodiment of the present invention;

[0011] Figure 1F A schematic diagram of switching of an impedance correction circuit in a time interval according to another embodiment of the present invention;

[0012] Figure 2A is a schematic diagram of an impedance correction circuit according to an embodiment of the present invention;

[0013] Figure 2B A schematic diagram of switching of an impedance correction circuit in a time interval according to an embodiment of the present invention;

[0014] Figure 2C A schematic diagram of switching of an impedance correction circuit in a time interval according to an embodiment of the present invention;

[0015] Figure 2D FIG. 4 is a schematic diagram of switching of an impedance correction circuit in a time interval according to another embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1A Schematic diagram of an impedance correction circuit 1 according to an embodiment of the present invention. The impedance correction circuit 1 includes a correction circuit 10, a correction circuit 11, a switch circuit 12, and a control circuit 13. The correction circuit 10 is coupled to the external resistor Rext through the pad PD, and can receive a control signal Vc1 to adjust the impedance value of the correction circuit 10, so that it can be biased with the external resistor Rext to generate a voltage V1. The voltage V1 is transmitted to the control circuit 13 through the switch circuit 12, and the control circuit 13 adjusts the control signal Vc1 transmitted to the correction circuit 10 accordingly to adjust the impedance value of the correction circuit 10. The correction circuit 11 can receive control signals Vc1, Vc2, and Vc3 to adjust the impedance value of the correction circuit 11, so that the correction circuit 11 is biased according to the corrected control signal Vc1 to generate voltages V2 and V3. The control circuit 13 adjusts the control signals Vc2 and Vc3 transmitted to the correction circuit 10 accordingly to adjust the impedance value of the correction circuit 11. Furthermore, the control circuit 13 can perform multiple comparison operations simultaneously to reduce the time for the impedance correction circuit 1 to correct the impedance.

[0018] In detail, the calibration circuit 10 includes a transistor P0, one end of the transistor P0 receives an operating voltage Vdd and the other end is coupled to the pad PD, and the control end of the transistor P0 receives a control signal Vc1 to adjust the impedance value of the transistor P0. Therefore, the transistor P0 adjusts its impedance value according to the control signal Vc1, and generates a corresponding voltage V1 after being biased with the external resistor Rext.

[0019] The correction circuit 11 includes bias circuits 110 and 111. The bias circuit 110 can receive control signals Vc1 and Vc2 to generate a voltage V2, and the bias circuit 111 can receive control signals Vc1 and Vc3 to generate a voltage V3. The bias circuit 110 includes transistors P1 and N1. One end of the transistor P1 receives an operating voltage Vdd and the other end is coupled to one end of the transistor N1, and the other end of the transistor N1 receives a ground voltage Gnd. The control ends of the transistors P1 and N1 receive control signals Vc1 and Vc2, respectively, to adjust the impedance values ​​of the transistors P1 and N1. The bias circuit 111 includes transistors P2 and N2. One end of the transistor P2 receives an operating voltage Vdd and the other end is coupled to one end of the transistor N2, and the other end of the transistor N2 receives a ground voltage Gnd. The control ends of the transistors P2 and N2 receive control signals Vc1 and Vc3, respectively, to adjust the impedance values ​​of the transistors P2 and N2. Therefore, the transistors P1 and N1 in the bias circuit 110 can adjust their respective impedance values ​​according to the control signals Vc1 and Vc2 to bias the node where the transistors P1 and N1 are coupled to generate the voltage V2. The transistors P2 and N2 in the bias circuit 111 can adjust their respective impedance values ​​according to the control signals Vc1 and Vc3 to bias the node where the transistors P2 and N2 are coupled to generate the voltage V3.

[0020] The switch circuit 12 includes switches SW1 to SW4. The switch circuit 12 can selectively provide voltages V1 to V3 to nodes A1 and A2. The switch SW1 is coupled between the correction circuit 10 and the node A1. The switch SW2 is coupled between the bias circuit 110 in the correction circuit 11 and the node A1. The switch SW3 is coupled between the bias circuit 111 in the correction circuit 11 and the node A2. The switch SW4 is coupled between the node A1 and the node A2.

[0021] The control circuit 13 includes comparators Amp1, Amp2, and an operation circuit 130. One input terminal of the comparator Amp1 is coupled to the node A1, and the other input terminal receives the reference signal Vref1, and generates a comparison result Comp1 of the two input terminals at the output terminal. One input terminal of the comparator Amp2 is coupled to the node A2, and the other input terminal receives the reference signal Vref2, and generates a comparison result Comp2 of the two input terminals at the output terminal. The operation circuit 130 is coupled to the comparators Amp1 and Amp2, receives the comparison results Comp1 and Comp2, and generates control signals Vc1, Vc2, and Vc3 accordingly.

[0022] The control signals Vc1, Vc2, Vc3 and the operation circuit 130 can be used in conjunction with the implementation of the correction circuits 10, 11 to implement the signal types of the control signals Vc1, Vc2, Vc3 in a corresponding manner. In one embodiment, when the transistors P0, P1, P2, N1, N2 in the correction circuits 10, 11 can receive analog control signals Vc1, Vc2, Vc3, the operation circuit 130 can include a digital-to-analog converter (DAC) to convert the calculated digital signal into an analog signal to adjust the transistors P0, P1, P2, N1, N2 in the correction circuits 10, 11. In another embodiment, the transistors P0, P1, P2, N1, and N2 may include a plurality of transistors connected in parallel. The transistors connected in parallel may be designed to have the same or different sizes and current driving capabilities. Accordingly, the operation circuit 130 may provide the control signals Vc1, Vc2, and Vc3 of the corresponding coding type to the transistors P0, P1, P2, N1, and N2 in a bit sequence. For example, the control signals Vc1, Vc2, and Vc3 may be one-hot, thermometer code, binary, or other suitable digital coding types. Therefore, the present invention does not limit the signal types of the control signals Vc1, Vc2, and Vc3.

[0023] Figure 1B FIG. 1 is a diagram showing the relationship between the impedance value of the calibration circuit 10 and the voltage of the control signal Vc1 according to an embodiment of the present invention. When the transistor P0 can receive the analog control signal Vc1, the operation circuit 130 converts the binary value of the control signal Vc1 into an analog voltage value to provide to the transistor P0, so that the transistor P0 generates a corresponding impedance value. Please refer to Figure 1BOn the left side, it shows the relationship between the impedance value of transistor P0 and the change of control signal Vc1, wherein the vertical axis is the impedance value of transistor P0 and the horizontal axis is the control value of control signal Vc1. The control value of control signal Vc1 can be converted by a digital-to-analog converter to generate an analog voltage to control transistor P0. When the control value of control signal Vc1 is low, the impedance of transistor P0 is high. As the control value of control signal Vc1 increases, the impedance of transistor P0 decreases nonlinearly.

[0024] Please refer to Figure 1B The middle shows Figure 1B The enlarged schematic diagram of the dotted circle on the left. Since the voltage value of the control signal Vc1 is converted by a digital signal, the control value of the control signal Vc1 is discretely distributed. When the control value of the control signal Vc1 is N-1, N, and N+1, the corresponding voltage value after conversion is provided to the transistor P0, so that the transistor P0 can generate a corresponding impedance value.

[0025] Please refer to Figure 1B The right side of FIG. 1 shows the relationship between the voltage V2 generated by the correction circuit 10 and the control value of the control signal Vc1. Figure 1B As shown in the middle, as the control value of the control signal Vc1 increases (that is, the voltage of the control signal Vc1 increases), the impedance of the transistor P0 will decrease accordingly. Therefore, the voltage V2 generated by the bias of the transistor P0 and the external resistor Rext will increase as the impedance value of the transistor P0 decreases. Therefore, the control circuit 13 can determine the impedance value of the transistor P0 based on the level of the voltage V2.

[0026] Figure 1C Schematic diagram of the operation cycle of the impedance correction circuit 1 according to an embodiment of the present invention. Specifically, in the time interval T10, the impedance correction circuit 1 can perform circuit settings, and in the time interval T11, the impedance correction circuit 1 can correct the setting parameters inside the circuit (for example, correct the deviation of the comparator). In the time interval T12, the impedance correction circuit 1 can perform a correction operation on the correction circuit 10, and in the time interval T13 after the time interval T12, the impedance correction circuit 1 can perform a correction operation on the correction circuit 11.

[0027] In detail, in the time interval T12, the control circuit 13 first provides a preset control signal Vc1 to the correction circuit 10, and adjusts the control signal Vc1 according to the bias voltage V1 generated by the correction circuit 10 and the external resistor Rext. The impedance correction circuit 1 first corrects the impedance value of the P-type metal oxide semiconductor transistor, so that the impedance value of the transistor P0 can be adjusted to be close to the preset impedance. Then, in the time interval T13, the adjusted control signal Vc1 is provided to the transistors P1 and P2 of the bias circuits 110 and 111 in the correction circuit 11. The impedance correction circuit 1 then corrects the impedance value of the N-type metal oxide semiconductor transistor, and adjusts the control signals Vc2 and Vc3 according to the voltages V2 and V3 generated by the correction circuit 11, so that the impedance values ​​of the transistors N1 and N2 can be adjusted to be close to the preset impedance. In short, in the time interval T12, the impedance correction circuit 1 can correct the impedance value of the P-type metal oxide semiconductor transistor in the correction circuit 10 through the external resistor Rext to generate a control signal Vc1 suitable for correcting the P-type metal oxide semiconductor transistor. Then, in the time interval T13, the corrected control signal Vc1 is provided to the P-type transistors P1 and P2 in the bias circuits 110 and 111 of the correction circuit 11. The impedance correction circuit 1 can calibrate the correction circuit 11 in the time interval T13 to generate control signals Vc2 and Vc3 suitable for correcting the N-type metal oxide semiconductor transistor.

[0028] Figure 1DSchematic diagram of the switching of the impedance correction circuit 1 in the time interval T12 according to an embodiment of the present invention. In the time interval T12, the impedance correction circuit 1 can calibrate the correction circuit 10, and the switch circuit 12 can provide the voltage V1 to the nodes A1 and A2, so the switches SW1 and SW4 in the switch circuit 12 can be turned on, and the switches SW2 and SW3 can be turned off. The comparator Amp1 can receive the voltage V1 at the node A1 to compare with the reference signal Vref1, and the comparator Amp2 can receive the voltage V1 at the node A2 to compare with the reference signal Vref2. In one embodiment, the operation circuit 130 can adjust the control signal Vc1 and the reference signals Vref1 and Vref2 by binary approximation to adjust the impedance value of the transistor P0 to be close to the preset impedance. For example, the operation circuit 130 may first set the impedance value of the transistor P0 with a preset control signal Vc1 voltage (e.g., half of the operating voltage Vdd) and generate a voltage V1, and after comparing the voltage V1 with the reference signals Vref1 and Vref2, recursively adjust the control signal Vc1 and the reference signals Vref1 and Vref2, and then generate an appropriate control signal Vc0 in the time interval T12 to adjust the impedance value of the transistor P0. Therefore, in this embodiment, the control circuit 13 may perform multiple comparison operations simultaneously in the time interval T12, compare the comparison voltage V1 with multiple reference signals Vref1 and Vref2, and reduce the required period for adjusting the impedance value of the transistor P0, thereby effectively improving the speed of the impedance correction circuit 1.

[0029] Figure 1E Schematic diagram of the switching of the impedance correction circuit 1 in the time interval T13 according to an embodiment of the present invention. In this embodiment, the switch circuit 12 can transmit the voltage V2 to the nodes A1 and A2 in the time interval T13, so the switches SW2 and SW4 in the switch circuit 12 can be turned on, the switches SW1 and SW3 can be turned off, and the comparators Amp1 and Amp2 can receive the voltage V2 at the nodes A1 and A2, and the comparators Amp1 and Amp2 can compare the voltage V2 with the reference signals Vref1 and Vref2 respectively. In this embodiment, the control circuit 13 can adjust the control signal Vc2 and the reference signals Vref1 and Vref2 by a recursive comparison operation in a manner similar to the correction transistor P0, and then generate an appropriate control signal Vc2 in the time interval T13 to adjust the impedance value of the transistor N1 to be close to the preset impedance. Therefore, in this embodiment, the control circuit 13 can simultaneously perform multiple comparison operations in the time interval T13 to compare the voltage V2 generated by the bias circuit 110 in the correction circuit 11 with the multiple reference signals Vref1 and Vref2, which can reduce the required period for adjusting the impedance values ​​of the transistors N1 and N2, thereby effectively improving the speed of the impedance correction circuit 1.

[0030] in addition, Figure 1F FIG. 1 is a schematic diagram of the switching of the impedance correction circuit 1 in the time interval T13 according to another embodiment of the present invention. In this embodiment, the switch circuit 12 can transmit the voltage V2 to the node A1 and transmit the voltage V3 to the node A2 in the time interval T13, so the switches SW2 and SW3 in the switch circuit 12 can be turned on, the switches SW1 and SW4 can be turned off, the comparator Amp1 can receive the voltage V2 to compare with the reference signal Vref1, and the comparator Amp2 can receive the voltage V3 to compare with the reference signal Vref2. At this time, the reference signals Vref1 and Vref2 received by the comparators Amp1 and Amp2 can be switched to the same voltage level to compare with the voltages V2 and V3. In this embodiment, the control circuit 13 can set the impedance values ​​of the transistors N1 and N2 by the preset control signals Vc2 and Vc3 to generate the voltages V2 and V3, and then adjust the control signals Vc2 and Vc3 and the reference signals Vref1 and Vref2 through a recursive comparison operation, thereby generating appropriate control signals Vc2 and Vc3 in the time interval T13 to adjust the impedance values ​​of the transistors N1 and N2 to be close to the preset impedance. Therefore, in this embodiment, the control circuit 13 can perform multiple comparison operations simultaneously in the time interval T13, compare the multiple voltages V2 and V3 generated by the bias circuit 110 in the correction circuit 11 with the reference signals Vref1 and Vref2 of the same level, and effectively reduce the time for correcting the impedance value.

[0031] Figure 2A Schematic diagram of an impedance correction circuit 2 according to an embodiment of the present invention. The difference between the impedance correction circuit 2 and the impedance correction circuit 1 is that the correction circuit 21, the switch circuit 22 and the control circuit 23 in the impedance correction circuit 2 replace the correction circuit 11, the switch circuit 12 and the control circuit 13 in the impedance correction circuit 1 respectively. The impedance correction circuit 2 includes the correction circuits 10, 21, the switch circuit 22 and the control circuit 23. The same components in the impedance correction circuit 2 as those in the impedance correction circuit 1 are marked with the same symbols, so please refer to the above-mentioned relevant paragraphs for the relevant content.

[0032] In detail, the correction circuit 21 includes bias circuits 110, 111, and 212. The correction circuit 21 can generate a voltage V4 through the bias circuit 212. The bias circuit 212 includes transistors P3 and N3. One end of the transistor P3 receives an operating voltage Vdd and the other end is coupled to one end of the transistor N3, and the other end of the transistor N3 receives a ground voltage Gnd. The control ends of the transistors P3 and N3 receive control signals Vc1 and Vc4, respectively, to adjust the impedance values ​​of the transistors P3 and N3. The transistors P3 and N3 can generate a voltage V4 through mutually coupled nodes.

[0033] The switch circuit 22 includes switches SW5 and SW6 in addition to switches SW1 to SW4. The switch SW5 is coupled between the bias circuit 212 and the node A3 in the calibration circuit 21. The switch SW6 is coupled between the node A1 and the node A3.

[0034] The control circuit 23 includes comparators Amp1, Amp2, Amp3, and an operation circuit 230. One input terminal of the comparator Amp3 is coupled to the node A3, and the other input terminal receives the reference signal Vref3, and generates a comparison result Comp3 of the two input terminals at the output terminal. The operation circuit 230 receives the comparison results Comp1, Comp2, Comp3 and generates control signals Vc1, Vc2, Vc3, Vc4 accordingly to adjust the impedance value in the impedance correction circuit 2.

[0035] Please refer to Figure 1B and Figure 2A , to help understand the correction process of the impedance correction circuit 2. Specifically, the impedance correction circuit 2 can be set in the time interval T10 and correct the setting parameters (such as the deviation of the correction comparator) in the time interval T11, and correct the correction circuit 10 in the time interval T12 after the time interval T11, and correct the circuit 11 in the time interval T13 after the time interval T12. In detail, the impedance correction circuit 2 can correct the correction circuit 10 according to the external resistor Rext in the time interval T12 to generate a control signal Vc1 suitable for correcting the P-type metal oxide semiconductor transistor. The P-type transistors P0, P1, P2, and P3 in the bias circuits 110, 111, and 212 are set according to the corrected control signal Vc1. The impedance correction circuit 2 can correct the correction circuit 21 in the time interval T13 after the time interval T12 to generate control signals Vc2, Vc3, and Vc4 suitable for correcting the N-type metal oxide semiconductor transistor.

[0036] Figure 2B Schematic diagram of the switching of the impedance correction circuit 2 in the time interval T12 according to an embodiment of the present invention. In the time interval T12, the impedance correction circuit 2 can calibrate the correction circuit 10, and the switch circuit 22 can provide the voltage V1 to the nodes A1, A2, and A3, so the switches SW1, SW4, and SW6 in the switch circuit 12 can be turned on, and the switches SW2, SW3, and SW5 can be turned off. The comparators Amp1, Amp2, and Amp3 can receive the voltage V1 at their respective receiving ends through the nodes A1, A2, and A3, respectively, and compare them with the reference signals Vref1, Vref2, and Vref3, respectively, to generate comparison results Comp1, Comp2, and Comp3, and determine the control signal Vc1 through the recursive binary approximation method.

[0037] Specifically, the control signal Vc1 in this embodiment may have six control bits, and in the first cycle of the time interval T12, the control circuit 23 may set the control signal Vc1 to [100000], and the reference signals Vref1, Vref2, and Vref3 provided to the comparator may be set to 1 / 4 Vdd, 1 / 2 Vdd, and 3 / 4 Vdd, respectively, and the first two bits of the control signal Vc1 are determined by the comparison results Comp1, Comp2, and Comp3 of the comparators Amp1 to Amp3 in the first cycle. Then, the reference signals Vref1, Vref2, and Vref3 are adjusted to corresponding voltage levels according to the first two bits determined by the control signal Vc1 to determine the next two bits of the control signal Vc1. By recursively performing the operation in this way, the impedance correction circuit 2 only needs three cycles to accurately determine the six-bit control signal Vc1.

[0038] In addition, although not shown Figure 2B However, the impedance correction circuit 2 can perform an additional fine-tuning comparison operation on the control signal Vc1 of the correction circuit 11 after the time interval T12. In detail, the control circuit 23 can adjust the control signal Vc1 through the binary approximation method so that the impedance value of the transistor P0 can approach the target impedance value to be adjusted, until the target impedance value to be adjusted falls between the binary value of the control signal Vc1 (for example, [010010]) and the binary value of the control signal Vc1 plus one (for example, [010011]). However, when the control signal Vc1 in digital form adjusts the impedance value of the transistor P0, it will be limited by the resolution of the control signal Vc1, and it is impossible to determine whether the target impedance value is closer to the control signal Vc1 or closer to the binary value of the control signal Vc1 plus one. Therefore, the impedance correction circuit 2 can further improve the accuracy of the impedance correction circuit 2 by performing an additional fine-tuning comparison operation after the time interval T12.

[0039] In detail, the control circuit 13 can adjust the reference signals Vref1, Vref2, and Vref3 so that the difference between the three is half of the minimum voltage resolution. For example, the voltage of Vref1 can be set to Vdd / 2-VLSB / 2, the voltage of Vref2 can be set to Vdd / 2, and the voltage of Vref3 can be set to Vdd / 2+VLSB / 2. In this way, the control circuit 13 can adjust the least significant bit (LSB) of the control signal Vc1 through two additional cycles. In the first cycle, the control signal Vc1 is set to the binary value generated by the time interval T12 and compared with the reference signals Vref1, Vref2, and Vref3 with doubled resolution. In the second cycle, the control signal Vc1 is set to the binary value generated by the time interval T12 plus one and compared with the reference signals Vref1, Vref2, and Vref3 with doubled resolution. Therefore, the control circuit 13 can more accurately set the least significant bit of the control signal Vc1 through two additional cycles, so that the impedance value of the transistor P0 can be calibrated to be closer to the target impedance value.

[0040] Figure 2C Schematic diagram of the switching of the impedance correction circuit 2 in the time interval T13 according to an embodiment of the present invention. In the time interval T13, the impedance correction circuit 2 can calibrate the correction circuit 11, and the switch circuit 22 can provide the voltage V2 to the nodes A1, A2, and A3, so the switches SW2, SW4, and SW6 in the switch circuit 12 can be turned on, and the switches SW1, SW3, and SW5 can be turned off. The comparators Amp1, Amp2, and Amp3 can receive the voltage V2 at their respective receiving ends through the nodes A1, A2, and A3, respectively, and compare them with the reference signals Vref1, Vref2, and Vref3, respectively, to generate comparison results Comp1, Comp2, and Comp3. The control circuit 23 can determine the two bits of the control signal Vc2 in each cycle comparison through the binary approximation method.

[0041] Specifically, the generation process of the control signal Vc2 is similar to the generation process of the control signal Vc1 in the previous paragraph. In the first cycle of the time interval T13, the control circuit 23 can set the control signal Vc2 to [100000], and the reference signals Vref1, Vref2, and Vref3 provided to the comparator can be set to 1 / 4Vdd, 1 / 2Vdd, and 3 / 4Vdd respectively. The first two bits of the control signal Vc2 are determined by the comparison results Comp1, Comp2, and Comp3 of the comparators Amp1 to Amp3 in the first cycle. The reference signals Vref1, Vref2, and Vref3 are adjusted to the corresponding voltage levels according to the first two bits determined by the control signal Vc2 to determine the next two bits of the control signal Vc2. By recursively performing the operation in this way, the impedance correction circuit 2 only needs three cycles to accurately determine the six-bit control signal Vc2.

[0042] in addition, Figure 2D Schematic diagram of the switching of the impedance correction circuit 2 in the time interval T13 according to another embodiment of the present invention. In this embodiment, the impedance correction circuit 2 can calibrate the correction circuit 21. In this embodiment, the switch circuit 22 can transmit the voltage V2 to the node A1, transmit the voltage V3 to the node A2, and transmit the voltage V4 to the node A3, so the switches SW2, SW3, and SW5 in the switch circuit 22 can be turned on, and the switches SW1, SW4, and SW6 can be turned off. The comparator Amp1 can receive the voltage V2 to compare with the reference signal Vref1, the comparator Amp2 can receive the voltage V3 to compare with the reference signal Vref2, and the comparator Amp3 can receive the voltage V4 to compare with the reference signal Vref3. At this time, the reference signals Vref1, Vref2, and Vref3 received by the comparators Amp1, Amp2, and Amp3 can be switched to the same voltage level to compare with the voltages V2, V3, and V4.

[0043] Specifically, in the first cycle of the time interval T13, the control circuit 23 can set the control signals Vc2, Vc3, and Vc4 to [010000], [100000], and [110000], respectively, and the reference signals Vref1, Vref2, and Vref3 provided to the comparator can all be set to 1 / 2Vdd. The first two bits of the control signals Vc1 to Vc3 are determined by the comparison results Comp1, Comp2, and Comp3 of the comparators Amp1 to Amp3 in the first cycle, and the reference signals Vref1, Vref2, and Vref3 are further adjusted to the corresponding voltage levels to determine the next two bits of the control signals Vc2 to Vc4. By recursively performing the operation in this way, the impedance correction circuit 2 only needs three cycles to accurately determine the six-bit control signals Vc2 to Vc4.

[0044] In summary, the impedance correction circuit can perform multiple comparison operations simultaneously through the operation of the correction circuit, the switch circuit and the operation circuit, thereby effectively improving the speed of correcting the impedance value and improving the accuracy of the correction.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An impedance correction circuit, comprising: A first calibration circuit, adapted to be coupled to an external resistor via a pad and to generate a first voltage according to a first control signal; A second correction circuit generates a second voltage and / or a third voltage according to the first control signal, the second control signal and the third control signal; a switch circuit coupled to the first correction circuit and the second correction circuit, wherein the switch circuit selectively provides the first voltage, the second voltage and / or the third voltage to a first node and a second node; as well as a control circuit coupled to the switch circuit at the first node and the second node, the control circuit comparing the voltages of the first node and the second node with a first reference signal and a second reference signal respectively, and generating the first control signal, the second control signal and / or the third control signal according to the comparison result, wherein in a first time interval, the switch circuit provides the first voltage to the first node and the second node, and compares the first voltage with the first reference signal and the second reference signal to adjust the first control signal, wherein the difference between the first reference signal and the second reference signal is gradually reduced in the first time interval until it is reduced to half of the minimum voltage resolution corresponding to the first control signal; wherein in a second time interval after the first time interval, the switch circuit provides the second voltage to the first node and the second node, the first reference signal and the second reference signal have different levels, and the control circuit adjusts the second control signal by comparing the second voltage with the first reference signal and comparing the second voltage with the second reference signal; or In the second time interval after the first time interval, the switching circuit provides the second voltage and the third voltage to the first node and the second node respectively, the first reference signal and the second reference signal have the same level, and the control circuit adjusts the second control signal by comparing the second voltage with the first reference signal, and adjusts the third control signal by comparing the third voltage with the first reference signal.

2. The impedance correction circuit according to claim 1, wherein the switching circuit first provides the first voltage to the first node and the second node, so that the control circuit compares the first voltage with the voltage of the first reference signal and the second reference signal to generate the first control signal, and then provides the second voltage to the first node and the second node, so that the control circuit compares the second voltage with the voltage of the first reference signal and the second reference signal to generate the second control signal.

3. The impedance correction circuit according to claim 1, wherein the switching circuit first provides the first voltage to the first node and the second node, so that the control circuit compares the first voltage with the voltages of the first reference signal and the second reference signal to generate the first control signal, and then provides the second voltage and the third voltage to the first node and the second node, so that the control circuit compares the second voltage and the third voltage with the voltages of the first reference signal and the second reference signal respectively to generate the second control signal and the third control signal.

4. The impedance correction circuit according to claim 1, wherein the first correction circuit includes a first transistor, a first end of the first transistor receives an operating voltage, a second end of the first transistor is coupled to the pad, a control end of the first transistor receives the first control signal to adjust the impedance value of the first transistor, and the first voltage is generated at the second end of the first transistor.

5. The impedance correction circuit according to claim 1, wherein the second correction circuit comprises: A first bias circuit includes a first transistor and a second transistor, wherein a first terminal of the first transistor receives an operating voltage, a second terminal of the first transistor is coupled to a first terminal of the second transistor, a second terminal of the second transistor receives a ground voltage, a control terminal of the first transistor receives the first control signal, and a control terminal of the second transistor receives the second control signal; as well as a second bias circuit, comprising a third transistor and a fourth transistor, wherein a first terminal of the third transistor receives the operating voltage, a second terminal of the third transistor is coupled to a first terminal of the fourth transistor, a second terminal of the fourth transistor receives the ground voltage, a control terminal of the third transistor receives the first control signal, and a control terminal of the fourth transistor receives the third control signal, The first bias circuit generates the second voltage at the second end of the first transistor, and the second bias circuit generates the third voltage at the second end of the third transistor.

6. The impedance correction circuit according to claim 5, wherein the switch circuit comprises: a first switch, wherein a first end of the first switch is coupled to the pad to receive the first voltage, and a second end of the first switch is coupled to the first node; a second switch, wherein a first end of the second switch is coupled to the first bias circuit to receive the second voltage, and a second end of the second switch is coupled to the first node; a third switch, a first end of the third switch being coupled to the second bias circuit to receive the third voltage, and a second end of the third switch being coupled to the second node; as well as A fourth switch, wherein a first end of the fourth switch is coupled to the first node, and a second end of the fourth switch is coupled to the second node. 7 . The impedance correction circuit according to claim 6 , wherein when the switch circuit provides the first voltage to the first node and the second node, the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off. 8 . The impedance correction circuit according to claim 6 , wherein when the switch circuit provides the second voltage to the first node and the second node, the first switch and the third switch are turned off, and the second switch and the fourth switch are turned on.

9. The impedance correction circuit according to claim 6, wherein when the switch circuit provides the second voltage and the third voltage to the first node and the second node respectively, the first switch and the fourth switch are turned off, and the second switch and the third switch are turned on.

10. The impedance correction circuit according to claim 6, wherein the control circuit comprises: a first comparator, wherein a first input terminal of the first comparator is coupled to the first node, and a second input terminal of the first comparator receives the first reference signal to generate a comparison result at an output terminal of the first comparator; a second comparator, wherein a first input terminal of the second comparator is coupled to the second node, and a second input terminal of the second comparator receives the second reference signal to generate a comparison result at an output terminal of the second comparator; as well as The operation circuit is coupled to the output terminals of the first comparator and the second comparator to generate the first control signal and the second control signal according to the comparison results of the first comparator and the second comparator.

11. The impedance correction circuit according to claim 10, wherein the second correction circuit further generates a fourth voltage according to a fourth control signal, and the second correction circuit further comprises: a third bias circuit, comprising a fifth transistor and a sixth transistor, wherein a first terminal of the fifth transistor receives the operating voltage, a second terminal of the fifth transistor is coupled to a first terminal of the sixth transistor, a second terminal of the sixth transistor receives the ground voltage, and control terminals of the fifth transistor and the sixth transistor receive the first control signal and the fourth control signal, respectively; The third bias circuit generates the fourth voltage at the second end of the fifth transistor.

12. The impedance correction circuit according to claim 11, wherein the switch circuit further comprises: a fifth switch, wherein a first end of the fifth switch is coupled to the third bias circuit to receive the fourth voltage, and a second end of the fifth switch is coupled to the third node; as well as a sixth switch, a first end of the sixth switch being coupled to the first node, a second end of the sixth switch being coupled to the third node, When the switch circuit provides the first voltage to the first node and the second node, the fifth switch is turned off and the sixth switch is turned on, so that the switch circuit also provides the first voltage to the third node. When the switch circuit provides the second voltage to the first node and the second node, the fifth switch is turned off and the sixth switch is turned on, so that the switch circuit also provides the second voltage to the third node. When the switch circuit provides the second voltage and the third voltage to the first node and the second node respectively, the fifth switch is turned on and the sixth switch is turned off, so that the switch circuit also provides the fourth voltage to the third node.

13. The impedance correction circuit according to claim 12, wherein the control circuit is further coupled to the switch circuit at the third node, the control circuit compares the voltage of the third node with a third reference signal to generate the fourth control signal, and the control circuit further comprises: a third comparator, wherein a first input terminal of the third comparator is coupled to the third node, a second input terminal of the third comparator receives the third reference signal, and an output terminal of the third comparator generates a comparison result. The operation circuit is further coupled to the output terminal of the third comparator to generate the third control signal according to the comparison result of the third comparator.

14. The impedance correction circuit of claim 1, wherein the first time interval precedes the second time interval.

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