Scheduling method, device, computer equipment, network on chip and storage medium

Abstract

The present disclosure provides a scheduling method, apparatus, computer equipment, on-chip network and storage medium, wherein the method comprises: determining a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network respectively; determining performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method, and the mapping positions; and determining a target node division method, and target mapping positions corresponding to multiple target computing nodes corresponding to the target node division method respectively based on the performance information.

Description

Technical Field

[0001] The present disclosure relates to the field of neural network technology, and in particular to a scheduling method, apparatus, computer equipment, on-chip network and storage medium. Background Art

[0002] When using a network-on-chip (NoC) to perform computing tasks corresponding to a neural network model, it is necessary to schedule the data processing cores in the NoC to determine the mapping positions of the various computing nodes of the neural network in the NoC. The current scheduling method for the data processing cores in the NoC results in poor performance when using the NoC to perform computing tasks corresponding to the neural network. Summary of the invention

[0003] The embodiments of the present disclosure at least provide a scheduling method, apparatus, computer equipment, network on chip, and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides a scheduling method, comprising: determining a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on an on-chip network; based on association relationship information between multiple computing nodes corresponding to the node division method, and the mapping positions, determining performance information when the target neural network is run using the on-chip network; based on the performance information, determining a target node division method, and target mapping positions corresponding to multiple target computing nodes corresponding to the target node division method.

[0005] In an optional implementation, the scheduling method further includes: mapping the target neural network in the on-chip network based on the target computing node and the target mapping position.

[0006] In an optional implementation, the node division method for dividing computing nodes into multiple network layers of the target neural network includes: determining the node division method based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network; wherein there is at least one computing node corresponding to any network layer.

[0007] In an optional embodiment, the node division method is determined based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, including: executing multiple iteration cycles as follows, and performing the following process in each iteration cycle: in response to the current iteration cycle being the first iteration cycle, based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, randomly dividing multiple network layers in the target neural network to obtain the node division method of the target neural network in the first iteration cycle; or, in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, obtaining the node division method of the target neural network in the current iteration cycle.

[0008] In an optional embodiment, in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, the node division method of the target neural network in the current iteration cycle is obtained, including: determining the parent computing node group of the current iteration cycle; taking the number of network layers as the minimum number of child computing nodes in the child computing node group and the number of data processing cores as the maximum number of child computing nodes in the child computing node group, performing a first genetic crossover process on the parent computing node group to obtain at least one group of child computing node groups; and determining the node division method of the target neural network in the current iteration cycle based on each child computing node in the at least one group of child computing node groups.

[0009] In an optional embodiment, there are at least two parent computing node groups; determining the parent computing node group of the current iteration cycle includes: determining the child computing node group obtained by dividing the previous iteration cycle as the parent computing node group of the current iteration cycle; and / or, based on the performance information corresponding to the parent computing node groups respectively determined in at least one historical iteration cycle, determining the parent computing node group of the current iteration cycle from the parent computing node groups respectively determined in the at least one historical iteration cycle.

[0010] In an optional implementation, the first genetic crossover processing is performed on the parent computing node group to obtain a child computing node group, including: forming a computing node chain based on the parent computing nodes in the parent computing node group; and determining a first position of the genetic crossover in the computing node chain; for any two computing node chains, based on the first position of the genetic crossover, determining a first computing node subchain from the first computing node chain, and determining a second computing node subchain from the second computing node chain; based on the first computing node subchain and the second computing node subchain, generating the child computing node group.

[0011] In an optional implementation, the generation of the child computing node group based on the first computing node subchain and the second computing node subchain includes: splicing the first computing node subchain and the second computing node subchain to generate an alternative computing node chain; detecting whether the alternative computing node chain includes computing nodes corresponding to all network layers respectively; in response to the alternative computing node chain including computing nodes corresponding to all network layers respectively, determining the child computing node group based on the alternative computing node chain; in response to the alternative computing node chain not including computing nodes corresponding to all network layers respectively, determining a marked computing node that meets preset conditions from the first computing node subchain or the second computing node subchain; replacing the parent computing node corresponding to the marked computing node with the missing computing node in the alternative computing node chain to generate a target computing node chain; and determining the child computing node group based on the target computing node chain.

[0012] In an optional implementation, the method further includes: determining the marked computing node from the candidate computing node chain based on the number of computing nodes in the candidate computing node chain corresponding to the network layers included in the candidate computing node chain.

[0013] In an optional implementation, determining the mapping positions of the plurality of computing nodes in the on-chip network includes: executing a plurality of the following iteration cycles, and performing the following process in each iteration cycle: in response to the current iteration cycle being the first iteration cycle, randomly determining the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the first iteration cycle; or determining the mapping positions of the plurality of computing nodes in the on-chip network based on the association relationship information between the plurality of computing nodes; in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the previous iteration cycle, obtaining the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the current iteration cycle.

[0014] In an optional embodiment, the mapping position of the computing node in the on-chip network includes: the position of the data processing core that executes the computing task corresponding to the computing node in the on-chip network; the mapping positions of the multiple computing nodes corresponding to the node division method in the previous iteration cycle in the on-chip network are obtained, and the mapping positions of the multiple computing nodes corresponding to the node division method in the current iteration cycle are obtained, including: determining the parent mapping position group of the current iteration cycle; based on the multiple computing nodes corresponding to the division method in the current iteration cycle, performing a second genetic crossover processing on the parent mapping position group to obtain a child mapping position group; based on the child mapping position group, obtaining the mapping positions of the multiple computing nodes corresponding to the node division method in the current iteration cycle in the on-chip network.

[0015] In an optional embodiment, there are at least two parent mapping position groups; determining the parent mapping position group includes: determining the parent mapping position group of the current iteration cycle based on the child mapping position group determined in the previous iteration cycle; and / or, based on the performance information corresponding to the parent mapping position groups respectively determined in at least one historical iteration cycle, determining the parent mapping position group of the current iteration cycle from the parent mapping position groups respectively determined in the at least one historical iteration cycle.

[0016] In an optional implementation, the multiple computing nodes determined based on the current iteration cycle perform a second genetic crossover processing on the parent mapping position group to obtain a child mapping position group, including: based on the parent mapping position group, forming a mapping position chain, and determining a second position of the genetic crossover in the mapping position chain; for any two mapping position chains, based on the second position, determining a first mapping position subchain from the first mapping position chain, and determining a second mapping position subchain from the second mapping position chain; based on the first mapping position subchain, the second mapping position subchain, and the multiple computing nodes determined in the current iteration cycle, obtaining the child mapping position group.

[0017] In an optional implementation, determining the second mapping position sub-chain from the second mapping position chain includes: determining, from the second mapping position chain, a target mapping position that is not included in the first mapping position sub-chain; and determining the second mapping position sub-chain based on the order of the target mapping position in the second mapping position chain.

[0018] In an optional implementation, the offspring mapping position group is obtained based on the first mapping position subchain, the second mapping position subchain, and multiple computing nodes determined in the current iteration cycle, including: splicing the first mapping position subchain and the second mapping position subchain to obtain a target mapping position chain; and obtaining the offspring mapping position group using each mapping position in the target mapping position chain and multiple computing nodes determined in the current iteration cycle.

[0019] In an optional implementation, the target node division method and the target mapping positions respectively corresponding to the multiple target computing nodes corresponding to the target node division method are determined based on the performance information, including: for the last iteration cycle, based on the node division method in the last iteration cycle and the performance information at the corresponding mapping positions, the target division method is determined, and the mapping positions respectively corresponding to the multiple target computing nodes corresponding to the determined target node division method are determined as the target mapping positions.

[0020] In a second aspect, an embodiment of the present disclosure also provides a scheduling device, comprising: a first determination module, used to determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and a mapping position of multiple computing nodes corresponding to the node division method on the on-chip network; a second determination module, used to determine performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method, and the mapping position; a third determination module, used to determine a target node division method, and a target mapping position corresponding to multiple target computing nodes corresponding to the target node division method, based on the performance information.

[0021] In a third aspect, an optional implementation of the present disclosure further provides an on-chip network, comprising: a controller and multiple data processing cores; the controller is used to determine a node division method for dividing computing nodes into multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method in multiple data processing cores of the on-chip network respectively; and based on the association relationship information between the multiple computing nodes corresponding to the node division method, and the mapping positions, determining performance information when the target neural network is run using the on-chip network; and based on the performance information, determining a target node division method, and target mapping positions corresponding to the multiple target computing nodes corresponding to the target node division method respectively.

[0022] In a fourth aspect, an optional implementation of the present disclosure further provides a computer device, comprising: a processor, a memory, the memory storing machine-readable instructions executable by the processor, the processor being configured to execute the machine-readable instructions stored in the memory, and when the machine-readable instructions are executed by the processor, the machine-readable instructions perform the steps in the above-mentioned first aspect, or any possible implementation of the first aspect; or

[0023] Including: the on-chip network provided by the fourth aspect.

[0024] In a fifth aspect, an optional implementation of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, the steps of the above-mentioned first aspect, or any possible implementation of the first aspect are executed.

[0025] For a description of the effects of the above-mentioned scheduling device, computer equipment, on-chip network and computer-readable storage medium, please refer to the description of the above-mentioned scheduling method, which will not be repeated here.

[0026] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0028] Figure 1 A flowchart of a scheduling method provided by an embodiment of the present disclosure is shown;

[0029] Figure 2 A schematic diagram of a DNN provided by an embodiment of the present disclosure is shown;

[0030] Figure 3 A schematic diagram of a network on chip provided by an embodiment of the present disclosure is shown;

[0031] Figure 4 A flowchart of a node division method for determining a current iteration cycle provided by an embodiment of the present disclosure is shown;

[0032] Figure 5A schematic diagram of a method for dividing different computing nodes of the same target neural network provided by an embodiment of the present disclosure is shown;

[0033] Figure 6 A flowchart of determining a child computing node group provided by an embodiment of the present disclosure is shown;

[0034] Figure 7 A flowchart of determining a specific child computing node group provided by an embodiment of the present disclosure is shown;

[0035] Figure 8 A schematic diagram showing a mapping position of a determined computing node in an on-chip network provided by an embodiment of the present disclosure is shown;

[0036] Fig. 9 A specific flow chart of determining mapping positions of multiple computing nodes determined in a current iteration cycle in an on-chip network provided by an embodiment of the present disclosure is shown;

[0037] Fig.10 A specific flow chart of determining a child mapping position provided by an embodiment of the present disclosure is shown;

[0038] Fig.11 A schematic diagram showing the mapping positions of multiple computing nodes in the on-chip network under a determined node partitioning method provided by an embodiment of the present disclosure;

[0039] Fig.12 A schematic diagram of a scheduling code and a mapping code provided by an embodiment of the present disclosure is shown;

[0040] Fig.13 A schematic diagram of a scheduling device provided by an embodiment of the present disclosure is shown;

[0041] Fig.14 A schematic diagram of a computer device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the present disclosure claimed for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0043] Research has found that on-chip networks provide a lot of flexibility for the computation and communication of neural networks. However, for different neural networks, since the computation and communication modes of different network layers in the neural network are different, how to reasonably map the neural network to the on-chip network nodes has become an urgent problem to be solved. On the one hand, since the neural network contains a large number of computing tasks, there are many optional division methods when dividing the various network layers of the neural network into different computing nodes, and there are also many optional mapping methods when determining the mapping positions of different computing nodes in the on-chip network, which leads to a large search space for division and mapping methods; on the other hand, since the neural network mapped on the on-chip network node also needs to be executed according to the logical processing order of multiple network layers in the neural network when actually processing data, the actual corresponding performance information of different division and mapping methods in the search space is also different. At present, the division and mapping strategy of the neural network is usually determined by randomly determining the division method once, and then searching for the scheduling method of the neural network for the determined division method; such a mapping method is limited to the determined division method, resulting in poor performance of the obtained on-chip network when executing the computing tasks corresponding to the neural network.

[0044] Based on the above research, the present disclosure provides a scheduling method, apparatus, computer equipment, on-chip network and storage medium, which determines the node division method of the computing nodes and the mapping positions of the computing nodes corresponding to the node division method on the on-chip network, so as to determine the performance information of the on-chip network when running the target neural network under the determined node division method and mapping method, and adjust the node division method and mapping method, so as to improve the performance of the on-chip network when executing the corresponding computing tasks of the neural network after mapping the neural network to the on-chip network.

[0045] In addition, when the embodiment of the present disclosure uses performance information to adjust the node division method and mapping method, a genetic algorithm is used for iteration to achieve a more efficient search of the search space. Due to the algorithm logic of the target neural network and the communication limitations of the on-chip network, the node division method and mapping method in multiple iteration cycles are directly determined by genetic crossover. The obtained offspring results often cannot meet the actual division and mapping requirements. The embodiment of the present disclosure repairs the offspring individuals and retains the individuals that do not meet the requirements. While reducing the waste of data resources, the repaired offspring individuals can also retain as many characteristics of the parent generation as possible, and obtain better node division methods and mapping methods in the genetic crossover process of multiple iteration cycles.

[0046] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0047] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0048] To facilitate understanding of this embodiment, a scheduling method disclosed in the embodiment of the present disclosure is first introduced in detail. The execution subject of the scheduling method provided in the embodiment of the present disclosure is generally a computer device with certain computing capabilities, and the computer device includes, for example: a terminal device or a server or other processing device, and the terminal device can be a user equipment (User Equipment, UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. In some possible implementations, the scheduling method can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0049] The scheduling method provided by the embodiment of the present disclosure is described below.

[0050] See also Figure 1 FIG. 1 is a flowchart of a scheduling method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S104, wherein:

[0051] S101: Determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network respectively;

[0052] S102: Determine performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method and the mapping position;

[0053] S103: Based on the performance information, determine a target node division method and target mapping positions corresponding to a plurality of target computing nodes corresponding to the target node division method.

[0054] The disclosed embodiment determines the node division method for dividing the computing nodes of multiple network layers in the target neural network, and the mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network, so as to determine the performance information of the on-chip network when running the target neural network, so as to adjust the node division method and the mapping position of the nodes according to the performance information, and obtain the target mapping positions corresponding to each target computing node. In this way, the node division method and the mapping method can be adjusted according to the performance information, so as to improve the performance of the on-chip network when executing the computing tasks corresponding to the neural network after the neural network is mapped to the on-chip network.

[0055] The above S101 to S103 are described in detail below.

[0056] For the above S101, in different application scenarios, the corresponding target neural network to be mapped is also different. For example, in an image processing scenario, such as when applied to image recognition, the target neural network may include a convolutional neural network (CNN) or a deep neural network (DNN); in a natural semantic processing scenario, such as when applied to speech recognition, the target neural network may include a self-attention mechanism model (Transformer) or a recurrent neural network (RNN). The specific details can be determined according to the actual situation and will not be repeated here.

[0057] The following takes the target neural network as DNN as an example. Figure 2 FIG. 1 is a schematic diagram of a DNN provided in an embodiment of the present disclosure. To simplify the description, the DNN provided in an embodiment of the present disclosure includes four network layers, including an input layer N 1 , convolutional layer N 2 , pooling layer N 3 , and the output layer N 4 Each network layer has multiple neurons, correspondingly, each network layer N i (1≤i≤4) The number of neurons corresponding to is n i , for example, corresponding to the input layer N 1 , the corresponding number of neurons is n 1 When the target neural network processes the input data, it is actually a process in which neurons in different network layers in the target neural network process the received data in an orderly manner.

[0058] The on-chip network for mapping the target neural network may include, for example, a single-layer or multi-layer network structure. For example, see Figure 3 FIG. 1 is a schematic diagram of a network on chip provided by an embodiment of the present disclosure. Figure 3 The network on chip shown in the figure includes 3×2 data processing cores u, where the i-th data processing core is represented by u i , 0≤i≤5, each data processing core corresponds to a communication route R, where data processing core u i The corresponding communication route is represented by R i , 0≤i≤5. When mapping the target neural network on the on-chip network, the data processing cores on the on-chip network will be responsible for the specific tasks of data processing, and the communication routes corresponding to the data processing cores will complete the data transmission between different data processing cores. Here, if the area of ​​the on-chip network is large and there are many corresponding data processing cores, some data processing cores may not be responsible for the specific tasks of data processing, but their corresponding communication routes still need to complete the data transmission.

[0059] In one possible case, since the number of data processing cores of the on-chip system is limited and the neurons in the same network layer of the target neural network have similar processing processes when processing data, when mapping the target neural network on the on-chip network, multiple neurons in any network layer in the target neural network can be divided into at least one computing node, and a corresponding data processing core can be determined for each computing node.

[0060] Specifically, when determining a node division method for dividing multiple network layers of a target neural network, for example, the following method can be adopted: determining the node division method based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network; wherein, there is at least one computing node corresponding to any network layer.

[0061] In the following, the target neural network has 4 layers and the number of data processing cores in the on-chip network is 6. When determining the node division method for multiple network layers in the target neural network, the method that can be used may vary according to different iteration cycles, including but not limited to the following two cases (A1) and (A2):

[0062] (A1): For the first iteration cycle, a random partitioning method is used to determine multiple computing nodes of the target neural network.

[0063] In a specific implementation, for example, the following method can be adopted: based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, multiple network layers in the target neural network are randomly divided to obtain the node division method of the target neural network in the first iteration cycle.

[0064] Among them, since each network layer of the target neural network should be mapped on the on-chip network, the number of data processing cores allocated to the target neural network should be greater than or equal to the number of network layers of the target neural network; in addition, since the number of data processing cores in the on-chip network is limited, the number of data processing cores that can be allocated to the target neural network may be less than or equal to the number of data processing cores in the on-chip network.

[0065] Therefore, the number of data processing cores that the on-chip network can allocate to the target neural network can be 4, 5 or 6. In the case of allocating 4 data processing cores to the target neural network, for example, a corresponding data processing core can be determined for each network layer; in the case of allocating 5 data processing cores to the target neural network, for example, 2 data processing cores can be allocated to any network layer in the target neural network, and a corresponding data processing core can be allocated to each of the other network layers; in the case of allocating 6 data processing cores to the target neural network, for example, 3 data processing cores can be allocated to any network layer in the target neural network, and a corresponding data processing core can be allocated to each of the other network layers, or 2 data processing cores can be allocated to each of the two network layers in the target neural network, and a corresponding data processing core can be allocated to each of the other network layers.

[0066] In the case of allocating at least two data processing cores to a network layer, the neurons of the network layer can also be evenly divided according to the number of allocated data processing cores, and a corresponding computing node is determined for the data processing task corresponding to the evenly divided neurons. 2 If the second network layer N 2 There are 100 neurons, each of which has a specific data processing task. When determining the computing nodes, one computing node can be determined for 50 of the neurons, and another computing node can be determined for the remaining 50 neurons. In this way, by determining the number of data processing cores for the network layer, the number of computing nodes determined for the network layer and the neurons corresponding to each computing node can be determined more quickly, so this method of determining the node division method is more efficient.

[0067] In addition, when determining the corresponding computing nodes for the network layer of the target neural network, for example, the neurons corresponding to each network layer may be randomly divided according to the number of data processing cores allocated to the network layer. For example, when determining the second network layer N 2 When two data processing cores are determined, the second network layer N 239 neurons out of the corresponding 100 neurons determine a corresponding computing node, and then another computing node is determined for the remaining 61 neurons. In this way, the node division method can be determined more randomly, and the division space for dividing the computing nodes can be expanded by improving the randomness, so as to determine different node division methods, so as to have more possible search spaces when using genetic algorithms later.

[0068] Here, the specific method of determining the node division method by determining the computing nodes corresponding to the target neural network can be determined according to the actual situation and will not be repeated here.

[0069] (A2): For other iteration cycles except the first iteration cycle, the node division method corresponding to the current iteration cycle is determined according to the node division method determined in the previous iteration cycle.

[0070] Specifically, for example, the following method can be adopted: based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, the node division method of the target neural network in the current iteration cycle is obtained.

[0071] In this case, see Figure 4 As shown, it is a flowchart of a node division method for determining the current iteration cycle provided by an embodiment of the present disclosure; wherein:

[0072] S401: Determine the parent computing node group of the current iteration cycle.

[0073] In order to perform the first genetic crossover process on the parent computing node group in the current iteration cycle, at least two parent computing node groups can be obtained in the previous iteration cycle. Each parent computing node group includes computing nodes corresponding to each network layer in the target neural network.

[0074] Among them, for one iteration cycle T in multiple iteration cycles i First, determine the iteration period T i At least two corresponding parent computing node groups, and in this iteration period T i In the above example, the iteration period T can be obtained by cross-inheriting at least two groups of parent generation computing node groups. i The corresponding child computing node group. For the iteration period T i The next iteration cycle T i+1 If we continue to perform the genetic crossover operation, we can i+1 The last iteration cycle T i The child computing node group obtained in is used as the iteration period Ti+1 The corresponding parent computing node group; or, it can also be from the iteration cycle T i+1 The previous iteration cycle, that is, iteration cycle T i and iteration period T i In the previous iteration cycle, some corresponding parent generation computing node groups are selected and used as the iteration cycle T i+1 The corresponding parent generation computes a part of the node group, and then according to the iteration period T i+1 Determine the crossover inheritance of the parent generation computing node group and obtain the iteration period T i+1 The corresponding child computing node group, and so on. For details, please refer to the following description of determining the parent computing node group, which will not be repeated here.

[0075] Specifically, when determining the parent computing node group, for example, the following method can be used: the child computing node group obtained by dividing the previous iteration cycle is determined as the parent computing node group of the current iteration cycle; and / or, based on the performance information corresponding to the parent computing node groups respectively determined in at least one historical iteration cycle, the parent computing node group of the current iteration cycle is determined from the parent computing node groups respectively determined in the at least one historical iteration cycle.

[0076] Here, taking the second iteration cycle as the current iteration cycle as an example, determining the parent computing node group of the second iteration cycle is described.

[0077] In the case where the child computing node group obtained by the previous iteration cycle is determined as the parent computing node group of the current iteration cycle, the parent computing node group of the second iteration cycle includes the child computing node group obtained in the first iteration cycle.

[0078] With respect to the performance information corresponding to the parent computing node groups respectively determined based on at least one historical iteration cycle, the parent computing node group of the current iteration cycle is determined from the parent computing node groups respectively determined in the at least one historical iteration cycle. For the third iteration cycle, when determining the parent computing node group of the third iteration cycle, the parent computing node group corresponding to the third iteration cycle can be determined from the parent computing node groups corresponding to the first iteration cycle and the second iteration cycle by determining the performance information corresponding to each parent computing node group according to the parent computing node groups corresponding to all previous historical iteration cycles (that is, the first iteration cycle and the second iteration cycle).

[0079] The manner of determining the corresponding performance information for the parent computing node group is described in detail in the following description of S102, which will not be repeated here. By determining the performance information corresponding to the parent computing node groups in the first iteration cycle, some parent computing node groups with better performance information can be determined from the parent computing node groups corresponding to the first iteration cycle as the parent computing node groups corresponding to the second iteration cycle, so as to retain the characteristics of the parent computing node groups with better performance through genetic crossover.

[0080] Here, the number of parent computing node groups selected from the first iteration cycle can be determined based on actual conditions. Specifically, they can be screened according to a certain proportion based on the performance information corresponding to the parent computing node groups in the first iteration cycle, or they can be screened based on the performance information corresponding to the parent computing node groups in the first iteration cycle and a preset performance information threshold. No limitation is made here.

[0081] When determining the parent computing node group corresponding to the second iteration cycle, the above two possible situations can also be combined accordingly to determine more parent computing node groups for the first genetic crossover processing, and correspondingly retain the characteristics of the child computing node group obtained through genetic crossover, as well as the characteristics of the parent computing node group determined in the previous iteration cycle.

[0082] In the specific embodiment of the present disclosure, a specific example is provided. In this example, in the first iteration cycle, for example, at least two groups of computing nodes can be determined by random division. Exemplarily, in the first iteration cycle, for example, it can be determined that the number of computing nodes in the two computing node groups is 6. For the convenience of representation, the computing nodes are labeled V. i (0≤i≤5), which means it can be divided into V 0 ~V 5 There are 6 computing nodes in total.

[0083] In order to ensure that each group of computing nodes includes computing nodes corresponding to each network layer in the target neural network, in the first iteration cycle, for example, corresponding computing nodes can be determined for each of the four network layers of the target neural network. Figure 5 As shown, it is a schematic diagram of a method for dividing different computing nodes for the same target neural network provided by an embodiment of the present disclosure.

[0084] Below, Figure 5 The following diagram is explained using (a) as an example. Figure 5 In the division method shown in (a), 5 of the 6 computing nodes correspond to different network layers in the target neural network. Specifically, the first network layer N 1 Determine a corresponding computing node V 1, is the second network layer N 2 Determine a corresponding computing node V 0 , is the third network layer N 3 Determine the corresponding two computing nodes V 2 and V 3 , is the fourth network layer N 4 Determine a corresponding computing node V 5 ; In addition, the calculation node V 4 Does not correspond to any network layer.

[0085] Here, for Figure 5 The different computing nodes determined in (a) and (b) are different because the computing nodes determined for different layers are different, and for the same layer of the target neural network, the number of computing nodes corresponding to (a) and (b) is also different. Therefore, in (a) and (b), the computing nodes with the same number are actually different. 1 , in Figure (a), it corresponds to the first network layer N 1 , and correspondingly corresponds to the first network layer N 1 n 1 neurons; while in Figure (b), V 1 Corresponding to the third network layer N 3 , and since the third network layer corresponds to two computing nodes, V 1 The corresponding third network layer N 3 n 3 Some of the neurons in a neuron.

[0086] Assume that the target neural network obtains two groups of computing nodes in the first iteration cycle, namely Figure 5 The two different groups of computing nodes shown in (a) and (b) determine that the two groups of computing nodes can be used as parent computing nodes in the first iteration cycle.

[0087] S402: Taking the number of network layers as the minimum number of child computing nodes in a child computing node group and taking the number of data processing cores as the maximum number of child computing nodes in a child computing node group, performing a first genetic crossover process on the parent computing node group to obtain at least one group of child computing node groups.

[0088] Among them, when the number of computing nodes is constrained according to the number of network layers and the number of data processing cores, the method of determining the number of computing nodes is similar to the method in (A1) above, and will not be repeated here.

[0089] By performing the first genetic crossover process on the parent computing node group, at least one group of child computing node groups can be obtained. In the following, for a clearer description, a group of child computing node groups determined by performing the first genetic crossover process on the parent computing node group is used as an example for description. Figure 6 As shown, it is a flowchart of determining a child computing node group provided by an embodiment of the present disclosure; wherein,

[0090] S601: constructing a computing node chain based on the parent computing nodes in the parent computing node group; and determining a first position of a genetic crossover in the computing node chain.

[0091] Specifically, for the above Figure 5 The parent computing node groups corresponding to (a) and (b) can respectively determine multiple parent computing nodes in the parent computing node groups, and determine corresponding computing node chains for different parent computing node groups through the parent computing nodes corresponding to each parent computing node group. When forming computing node chains according to parent computing nodes, for example, V 0 ~V 5 The corresponding network layers are determined respectively.

[0092] For example, for the above Figure 5 The parent computing node group shown in (a) can be, for example, based on the computing nodes V in the parent computing node group. 0 ~V 5 The corresponding network layers and V 0 ~V 5 The order of , determines the corresponding computing node chain a0 as:

[0093] a0: V 0 (N 2 )-V 1 (N 1 )-V 2 (N 3 )-V 3 (N 3 )-V 4 (×)-V 5 (N 4 ).

[0094] Among them, the parent computing node V i After "(N i )" indicates the parent computing node V i The corresponding network layer; "(×)" means that the corresponding parent computing node does not correspond to any network layer. Figure 5 The parent computing node shown in (b) can similarly determine the corresponding computing node chain b0 as:

[0095] b0: V0 (N 4 )-V 1 (N 3 )-V 2 (N 1 )-V 3 (N 2 )-V 4 (N 3 )-V 5 (N 2 ).

[0096] After determining the computing node chain using the parent computing nodes in the parent computing node group, the first position of the genetic crossover can also be determined in the computing node chain accordingly. In order to complete the genetic crossover, the first position that can be selected can include, for example, the position between any two adjacent parent computing nodes in the computing node chain. For example, taking computing node chain a0 as an example, the first position can include, for example, the parent computing node V 0 Compute node V with the parent 1 The position between 0 (N 2 ) and V 1 (N 1 ) between the .

[0097] Here, for the sake of convenience, the five genetic crossover positions that can be used as the first position between the six parent computing nodes are represented as the first position 1, the first position 2, ..., the first position 5 according to the order in the computing node chain. Taking computing node chain a0 as an example, the first position 3 indicates V 2 (N 3 ) and V 3 (N 3 ) is the first position between .

[0098] S602: For any two computing node chains, based on the first position of the genetic crossover, determine a first computing node subchain from the first computing node chain, and determine a second computing node subchain from the second computing node chain.

[0099] For example, the first position 3 is selected as the first position for explanation. By using the selected first position 3, the first computing node subchain a0-1 can be determined in the first computing node chain:

[0100] a0-1: V 0 (N 2 )-V 1 (N 1 )-V 2 (N 3 ),

[0101] That is, the front end subchain is intercepted from the first computing node chain using the first position 3 as the first computing node subchain. In addition, the second computing node subchain b0-1 can also be determined in the second computing node chain using the selected first position 3:

[0102] b0-1: V 3 (N 2 )-V 4 (N 3 )-V 5 (N 2 ),

[0103] That is, the first position of No. 3 is used to intercept the back-end sub-chain from the second computing node chain as the second computing node sub-chain.

[0104] In one possible case, when performing the first genetic crossover processing on the parent computing node, the back-end sub-chain can be intercepted from the first computing node chain as the first computing node sub-chain according to the first position, and the front-end sub-chain can be intercepted from the second computing node chain as the second computing node sub-chain, and similarly, another group of child computing nodes can be determined according to the instructions in the following steps, which will not be repeated here.

[0105] S603: Generate the descendant computing node group based on the first computing node sub-chain and the second computing node sub-chain.

[0106] When the first computing node sub-chain and the second computing node sub-chain are determined according to the above method, the first computing node sub-chain and the second computing node sub-chain can be used to generate a descendant computing node group.

[0107] In a specific implementation, when using the first computing node subchain and the second computing node subchain to generate a child computing node, refer to Figure 7 As shown, it is a flowchart of a specific method of determining a child computing node group provided by an embodiment of the present disclosure; wherein,

[0108] S701: Connect the first computing node sub-chain and the second computing node sub-chain to generate a candidate computing node chain.

[0109] Next, the first computing node subchain a0-1 determined above: V 0 (N 2 )-V 1 (N 1 )-V 2 (N 3 ) and the second computing node subchain b0-1: V 3 (N 2 )-V 4 (N 3 )-V 5 (N2 When the first computing node subchain a0-1 and the second computing node subchain b0-1 are spliced, for example, the splicing can be performed according to the position of the first computing node subchain a0-1 in the first computing node chain and the position of the second computing node subchain b0-1 in the second computing node chain.

[0110] Specifically, since the first computing node subchain a0-1 is located at the front end of the first computing node chain and the second computing node subchain b0-1 is located at the back end of the second computing node chain, when splicing the first computing node subchain and the second computing node subchain, the splicing can be performed in the order of a0-1→b0-1 to generate the alternative computing node chain a1, that is:

[0111] a1: V 0 (N 2 )-V 1 (N 1 )-V 2 (N 3 )-V 3 (N 2 )-V 4 (N 3 )-V 5 (N 2 ).

[0112] S702: Detect whether the candidate computing node chain includes computing nodes corresponding to all network layers respectively.

[0113] For example, for the determined candidate computing node chain a1, it can be determined that it includes the first network layer N 1 、The second network layer N 2 , and the third network layer N 3 The corresponding computing nodes, but there is no fourth network layer N 4 Corresponding computing nodes. In this case, the computing nodes determined for the target neural network using this alternative computing node chain do not include the fourth network layer. When the target neural network is actually mapped, the target neural network cannot work properly due to the missing network layer. That is, the alternative computing node chain obtained in the current iteration cycle does not meet the requirements.

[0114] Therefore, after determining the candidate computing node chain, it is also possible to detect whether the computing nodes corresponding to all network layers of the target neural network are included in the candidate computing node chain. Specifically, when performing the detection, for example, multiple computing nodes in the candidate computing node chain can be traversed according to the number of network layers included in the target neural network. If there is a network layer that does not correspond to the computing node, it is determined that the candidate computing node chain fails to include the computing nodes corresponding to all network layers.

[0115] In one possible case, if the determined alternative computing node chain contains computing nodes corresponding to each network layer of the target neural network, it can be determined that the alternative computing node chain obtained in the current iteration cycle meets the requirements, and the child computing node group can be determined accordingly based on the alternative computing node chain, that is, the specific steps of S703 can be executed.

[0116] In another possible case, if the determined candidate computing node chain fails to include computing nodes corresponding to all network layers, such as the candidate computing node chain a1 described above, in order to enable the candidate computing node chain to retain more features of the parent node and reduce the waste of resources caused by abandoning the candidate computing node chain, in this case, the candidate computing node chain can also be repaired to make it a candidate computing node chain that meets the requirements. Specifically, please refer to the description of S704 below.

[0117] S703: In response to the candidate computing node chain including computing nodes corresponding to all network layers respectively, determine the child computing node group based on the candidate computing node chain.

[0118] In the case where the candidate computing node chain includes computing nodes corresponding to all network layers, since the candidate computing node chain meets the requirements, the child computing nodes can be directly determined according to the corresponding computing nodes in the candidate computing node chain, and the child computing node group can be determined accordingly.

[0119] Exemplarily, it is assumed that the determined candidate computing node chain b1 includes:

[0120] b1: V 0 (N 4 )-V 1 (N 3 )-V 2 (N 1 )-V 3 (N 3 )-V 4 (N 2 )-V 5 (N 4 ).

[0121] Then, it can be determined that the child computing nodes in the child computing node group include: the first network layer N 1 The corresponding computing node V 2 , the second network layer N 2 The corresponding computing node V 4 , the third network layer N 3 The corresponding computing node V 1 and V 3 , the fourth network layer N4 The corresponding computing node V 0 and V 5 .

[0122] Here, since new computing nodes are re-divided for different network layers, the computing nodes V in the child computing node group determined here are 0 ~V 5 The corresponding relationship with the neurons in each network layer in the target neural network also changes accordingly. For example, with the computing node V in the computing node chain a 5 In comparison, V in the candidate computing node chain b1 5 Although it also corresponds to the fourth network layer N 4 , but for computing node chain a, since there is only computing node V 5 Corresponding to the fourth network layer N 4 , so calculate the node V 5 Corresponding to the fourth network layer N 4 n 4 neurons; for the candidate computing node chain b1, since there are two computing nodes V 0 and V 5 Corresponding to the fourth network layer N 4 , so calculate the node V 5 Corresponding to the fourth network layer N 4 n 4 Some of the neurons in a neuron.

[0123] S704: In response to the fact that the candidate computing node chain does not include computing nodes corresponding to all network layers respectively, determine a marked computing node that meets preset conditions from the first computing node sub-chain or the second computing node sub-chain; replace the parent computing node corresponding to the marked computing node with the missing computing node in the candidate computing node chain to generate a target computing node chain; and determine the child computing node group based on the target computing node chain.

[0124] In case that the candidate computing node chain does not include computing nodes corresponding to all network layers, such as the candidate computing node chain a1, the candidate computing node chain can also be repaired to serve as a candidate computing node chain that meets the requirements.

[0125] Specifically, after determining the candidate computing node chain, the corresponding computing nodes in the candidate computing node chain can be determined based on the candidate computing node chain, and the network layers not included in the candidate computing node chain can be determined based on all determined network layers. Therefore, in this step, for example, a marked computing node that meets the preset conditions can be determined among the computing nodes corresponding to the not included network layers, and the parent computing node corresponding to the marked computing node can be replaced with the computing node corresponding to the not included network layer, that is, the missing computing node, to generate the target computing node chain.

[0126] Here, when selecting a marked computing node, since the parent computing node corresponding to the marked computing node will be replaced by the computing node corresponding to the network layer that is not included, in order to ensure that the computing nodes corresponding to other network layers will not be lost due to the replacement of the parent computing node corresponding to the marked computing node, the preset conditions may include: the network layer corresponding to the marked computing node corresponds to at least two computing nodes.

[0127] For example, for the candidate computing node chain a1, the first network layer N 1 、The second network layer N 2 , and the third network layer N 3 The network layers corresponding to the computing nodes in the candidate computing node chain are all included. The computing nodes corresponding to the network layers not included are N 4 . Since the first network layer N 1 The corresponding computing node has only one V 1 , so V is not selected 1 As a marking computing node, and in the second layer network layer N 2 , and the third network layer N 3 Select the marked compute node from the corresponding compute nodes.

[0128] When specifically selecting the marked computing node, for example, the following method can be used: based on the number of computing nodes corresponding to the network layers included in the candidate computing node chain in the candidate computing node chain, the marked computing node is determined from the candidate computing node chain.

[0129] For example, in the candidate computing node chain a1, the second network layer N 2 And the third network layer N 3 The corresponding number of computing nodes is 3 and 2 respectively. Generally, we can first determine the network layer with a larger number of computing nodes, that is, the second network layer N 2 ; Then determine the marked computing node among the multiple computing nodes corresponding to the determined network layer, for example, in the second network layer N 2 The corresponding three computing nodes V 0 、V 3 , and V5 Determine the label computing node V 5 In this way, the number of computing nodes corresponding to each network layer can be better balanced so that each computing node can undertake moderate data processing tasks accordingly.

[0130] Here, in another possible manner, any one of the computing nodes that can be used as a marking computing node can also be used as a marking computing node. For example, for the candidate computing node chain a1, except for V 1 The remaining computing nodes, such as the second network layer N 2 And the third network layer N 3 The corresponding computing nodes can be used as marked computing nodes accordingly. In this way, the marked computing nodes can be determined more simply and efficiently.

[0131] Exemplarily, when determining the marking computing node V 5 After that, the parent computing node corresponding to the marked computing node in the first computing node subchain or the second computing node subchain can be replaced with the computing node corresponding to the network layer not included in the candidate computing node chain. 5 It is obtained by inheriting the second computing node subchain b-1, so the marking computing node V in the second computing node subchain b-1 can be 5 The corresponding parent computing node V 5 (N 2 ) is replaced by the network layer not included in the alternative computing node chain (that is, the fourth network layer N 4 ) corresponds to the computing node V 5 (N 4 ). Accordingly, the candidate computing node chain a1 is replaced by a1':

[0132] a1': V 0 (N 2 )-V 1 (N 1 )-V 2 (N 3 )-V 3 (N 2 )-V 4 (N 3 )-V 5 (N 4 )

[0133] As the target compute node chain.

[0134] Here, when determining the child computing node according to the target computing node chain, the multiple computing nodes that can be determined include:

[0135] The first layer, network layer N 1The corresponding computing node V 1 ;

[0136] The second layer, network layer N 2 The corresponding computing node V 0 and V 3 ;

[0137] The third layer, network layer N 3 The corresponding computing node V 2 and V 4 ;

[0138] The fourth layer, network layer N 4 The corresponding computing node V 5 .

[0139] In this way, multiple computing nodes can be determined, and the child computing node groups can be determined accordingly.

[0140] Following the above S402:

[0141] S403: Determine a node partitioning method of the target neural network in a current iteration cycle based on each of the child computing nodes in the at least one group of child computing nodes.

[0142] Here, since the child computing node group can be determined in S401-S402, each child computing node in the determined child computing node group can be directly used as multiple computing nodes of the target neural network in the current iteration cycle. In this way, the division of multiple network layers in the target neural network can be completed to determine the node division method of the target neural network in the current iteration cycle.

[0143] In another embodiment of the present disclosure, when determining the mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network, the mapping positions of the computing nodes in the on-chip network include: the position of the data processing core corresponding to the computing node in the on-chip network, wherein the data processing core corresponding to the computing node actually executes the computing task corresponding to the computing node in the on-chip network, and the position of the data processing core that executes the computing task corresponding to the computing node in the on-chip network is not smooth. The method used when determining the corresponding mapping position of the computing node can be determined, for example, according to the corresponding iteration cycle, specifically including but not limited to the following (B1) to (B3):

[0144] (B1): For the first iteration cycle, randomly determine the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node partitioning method in the first iteration cycle.

[0145] When mapping positions in the on-chip network are randomly determined for a plurality of computing nodes, for example, the plurality of computing nodes may be respectively mapped to different data processing core positions of the corresponding on-chip network.

[0146] In this way, through random mapping, it is relatively easy to determine the mapping positions corresponding to multiple computing nodes in the on-chip network, and the efficiency is also high.

[0147] (B2): For the first iteration cycle, based on the association relationship information between the plurality of computing nodes, the mapping positions of the plurality of computing nodes in the on-chip network are determined.

[0148] In this case, for example, the association relationship information between the nodes can be calculated to determine the mapping positions of multiple computing nodes in the on-chip network.

[0149] For example, Figure 5 Take the computing node shown in (a) as an example. Figure 5 When the computing nodes shown in (a) determine the mapping positions in the on-chip network, for example, the mapping positions in the on-chip network can be determined for multiple computing nodes based on the association relationship information between the computing nodes.

[0150] When determining the association relationship information, for example, it can be determined according to the network layers corresponding to the computing nodes. 1 and V 0 , data is computed by node V 1 Flow to V 0 ; Similarly, the data flow direction between other computing nodes can be determined, and according to the data flow direction between different computing nodes, the association relationship information between multiple computing nodes can be correspondingly determined.

[0151] See also Figure 8 As shown, it is a schematic diagram of a mapping position of a determined computing node in an on-chip network provided by an embodiment of the present disclosure.

[0152] Among them, according to Figure 5 (a) shows the association relationship information of the computing nodes, the first layer network layer N 1 Corresponding computing node V 1 , and the first network layer is the first network layer, then the computing node V 1 The location of the first data processing core assigned to the on-chip network, for example, assigned to the communication router R 0 The location of the corresponding data processing core. For computing node V 1 , and its corresponding data flows to the second network layer N 2 The corresponding computing node V 0 , then the calculation node V 0 Distributed to neighboring computing nodes V in the on-chip network 1 The location of the data processing core, for example, assigned to the communication router R 1The corresponding data processing core is located. Similarly, the remaining computing nodes can be allocated accordingly to determine Figure 8 Schematic diagram of the mapping location shown in .

[0153] In this way, since the association relationship information between different computing nodes is taken into consideration when determining the mapping positions of multiple computing nodes in the on-chip network, it is possible to achieve an effect of better performance information under this mapping method.

[0154] In addition, the method of determining the mapping positions of multiple computing nodes in the on-chip network corresponding to (B2) is used as the method of mapping the positions of the computing nodes in the on-chip network corresponding to the first iteration cycle. Since the mapping position with better performance information can be determined in the first iteration cycle, after the genetic crossover processing is performed in the subsequent iteration cycles, the offspring individuals with better performance information can also be inherited accordingly.

[0155] (B3): For other iteration cycles except the first iteration cycle, based on the mapping positions of multiple computing nodes corresponding to the node division method in the previous iteration cycle in the on-chip network, the mapping positions of multiple computing nodes corresponding to the node division method in the current iteration cycle in the on-chip network are obtained.

[0156] Exemplarily, the current iteration cycle is taken as the second iteration cycle for description.

[0157] Specifically, see Fig. 9 As shown, it is a specific flow chart of determining the mapping positions of multiple computing nodes determined in the current iteration cycle in the on-chip network provided by the embodiment of the present disclosure; wherein,

[0158] S901: Determine the parent mapping position group of the current iteration cycle.

[0159] There are at least two parent mapping position groups. When performing the first genetic crossover process on the parent mapping position group, similar to the first genetic crossover process on the parent computing node group, for example, at least two different child mapping position groups can be determined.

[0160] Specifically, when determining the parent mapping position group, for example, the following method can be used: determine the parent mapping position group of the current iteration cycle based on the child mapping position group determined in the previous iteration cycle; and / or, based on the performance information corresponding to the parent mapping position groups respectively determined in at least one historical iteration cycle, determine the parent mapping position group of the current iteration cycle from the parent mapping position groups respectively determined in the at least one historical iteration cycle.

[0161] Here, taking the second iteration cycle as the current iteration cycle as an example, determining the parent generation mapping position group corresponding to the second iteration cycle is described.

[0162] In one possible case, if the parent mapping position group of the current iteration cycle is determined based on the child mapping position group determined in the previous iteration cycle, the parent mapping position group of the second iteration cycle includes the child mapping position group obtained in the first iteration cycle.

[0163] In another possible case, when the parent mapping position group of the current iteration cycle is determined from the parent mapping position groups determined in at least one historical iteration cycle based on the performance information corresponding to the parent mapping position groups respectively determined in at least one historical iteration cycle, for example, from the parent mapping position groups in all previous historical iteration cycles (here, all previous historical iteration cycles are also the first iteration cycle), the parent mapping position group corresponding to the second iteration cycle is determined from the parent mapping position groups corresponding to the first iteration cycle by determining the performance information corresponding to the parent mapping position groups respectively.

[0164] Similarly, the manner of determining the corresponding performance information for the parent mapping position group is detailed in the following description of S102 and will not be repeated here.

[0165] By determining the performance information corresponding to the parent mapping position groups in the first iteration cycle, some parent mapping position groups with better performance information can be determined from the parent mapping position groups corresponding to the first iteration cycle as the parent mapping position groups corresponding to the second iteration cycle, so as to retain the characteristics of the parent mapping position groups with better performance through genetic crossover.

[0166] Here, the number of parent mapping position groups selected from the first iteration cycle can be determined based on actual conditions. Specifically, they can be screened according to a certain ratio based on the performance information corresponding to the parent mapping position groups in the first iteration cycle, or they can be screened based on the performance information corresponding to the parent mapping position groups in the first iteration cycle and a preset performance information threshold. No limitation is made here.

[0167] When determining the parent mapping position group corresponding to the second iteration cycle, the above two possible situations can also be combined accordingly to determine more parent mapping position groups for the first genetic crossover processing, and correspondingly retain the characteristics of the offspring mapping position group obtained through genetic crossover, as well as the characteristics of the parent mapping position group determined in the previous iteration cycle.

[0168] In the specific embodiment of the present disclosure, a specific example is provided. In this example, the computing node is V i Indicates that the data processing core in the on-chip network refers to Figure 5 with ui Indicates that the parent mapping position group can also use V accordingly, for example i (u i ) indicates that the calculation node V i Determine the mapping in the on-chip network u i Specifically, the parent generation mapping position group may include, for example, computing node V 0 Mapping in the on-chip network 0 The corresponding mapping position will calculate the node V 1 Mapping in the on-chip network 5 The corresponding mapping position will calculate the node V 2 Mapping in the on-chip network 4 The corresponding mapping position, etc.

[0169] S902: Based on a plurality of computing nodes corresponding to the division method in the current iteration cycle, a second genetic crossover process is performed on the parent generation mapping position group to obtain a child generation mapping position group.

[0170] For a clearer description, the following is described by taking the second genetic crossover process on the parent generation mapping position group to determine one of the offspring generation mapping position groups as an example.

[0171] Specifically, when the parent generation mapping position group is subjected to the second genetic crossover process to obtain the offspring generation mapping position group, refer to Fig.10 As shown, it is a specific flow chart of determining the child mapping position provided by the embodiment of the present disclosure; wherein,

[0172] S1001: Based on the parent generation mapping position group, a mapping position chain is constructed, and a second position of the genetic crossover is determined in the mapping position chain.

[0173] Exemplarily, according to two groups of parent mapping position groups, for example, two mapping position chains including the following p0 and q0 may be formed:

[0174] p0: V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 )-V 3 (u 2 )-V 4 (u 1 )-V 5 (u 3 );

[0175] q0: V 0 (u 1 )-V 1 (u5 )-V 2 (u 3 )-V 3 (u 0 )-V 4 (u 4 )-V 5 (u 2 ).

[0176] In the case of determining the mapping position chain, the second position of the genetic crossover can also be determined in the mapping position chain accordingly. Similar to the above determination of the first position, the second position that can be selected can include, for example, any position between two adjacent parent mapping positions in the mapping position chain.

[0177] Here, for the sake of convenience, the five genetic crossover positions generated between the six parent mapping positions that can be used as the second position are represented as the 1st second position, the 2nd second position, ..., the 5th second position according to the order in the mapping position chain. Taking the mapping position chain p0 as an example, the 3rd second position indicates V 2 (u 4 ) and V 3 (u 2 ) is the first position between .

[0178] S1002: For any two mapping position chains, based on the second position, determine a first mapping position subchain from the first mapping position chain, and determine a second mapping position subchain from the second mapping position chain.

[0179] Specifically, after the second position is determined according to the above S1001, for example, the first mapping subchain can be determined from the first mapping position chain through the second position. For example, if the first mapping position chain includes p0 and the second mapping position chain includes q0, if the determined second position includes the second position 3, the front subchain p0-1 can be intercepted in the first mapping position chain p0 accordingly:

[0180] p0-1: V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 ),

[0181] As the first mapping position subchain.

[0182] When determining the second mapping position subchain from the second mapping position chain, the second position is directly used to intercept the rear end subchain q0-1 from the second mapping position chain q0:

[0183] q0-1: V 3 (u 0 )-V4 (u 4 )-V 5 (u 2 ),

[0184] The position chain obtained by concatenating the obtained subchain with the first mapping position subchain is as follows:

[0185] V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 )-V 3 (u 0 )-V 4 (u 4 )-V 5 (u 2 ).

[0186] In one possible case, when performing a second genetic crossover processing on the parent mapping position, the rear end sub-chain can be intercepted from the first mapping position chain as the first mapping position sub-chain according to the second position, and based on the order of the target mapping position in the second mapping position chain, for example, the front end sub-chain can be intercepted from the second mapping position chain as the second mapping position sub-chain, and similarly, another set of offspring mapping positions can be determined according to the instructions in the following steps, which will not be repeated here.

[0187] In the above determined position chain V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 )-V 3 (u 0 )-V 4 (u 4 )-V 5 (u 2 ), there is a situation where a mapping position corresponds to multiple computing nodes, for example, corresponding to u 0 The corresponding mapping position corresponds to the computing node V 0 and V 3 ; corresponds to u 4 The corresponding mapping position corresponds to the computing node V 2 and V 4. In fact, since the computing nodes have been divided corresponding to the network layers, mapping multiple computing nodes in the same mapping position may destroy the association relationship information between the nodes. For example, it is not compliant to map the computing nodes of different network layers in the same mapping position. Therefore, when determining the second mapping position subchain from the second mapping position chain, for example, the following method can be used: determine the target mapping position not included in the first mapping position subchain from the second mapping position chain; determine the second mapping position subchain based on the order of the target mapping position in the second mapping position chain.

[0188] In a specific implementation, the mapping positions not included in the first mapping position subchain p0-1 may be determined in the second mapping position chain q0, where:

[0189] q0: V 0 (u 1 )-V 1 (u 5 )-V 2 (u 3 )-V 3 (u 0 )-V 4 (u 4 )-V 5 (u 2 );

[0190] p0-1: V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 ),

[0191] The corresponding unincluded mapping locations include u in the on-chip network 1 、u 3 、u 2 The corresponding mapping positions are determined and the determined mapping positions are used as target mapping positions. After the target mapping positions are determined, the determined target mapping sequence can be rearranged according to the sequence of the target mapping positions in the second mapping position chain to determine the second mapping position subchain.

[0192] Specifically, using the determined target mapping position, the second mapping position subchain q0-2 can be determined according to the order in the second mapping position chain q0:

[0193] q0-2: V 3 (u 1 )-V 4 (u 3 )-V 5 (u 2 ).

[0194] In this way, the obtained second mapping position sub-chain can retain the relative position relationship in the second mapping position chain q0 to a large extent.

[0195] S1003: Based on the first mapping position sub-chain, the second mapping position sub-chain, and a plurality of computing nodes determined in the current iteration cycle, obtain the descendant mapping position group.

[0196] After determining the first mapping position subchain and the second mapping position subchain, the target mapping position chain can also be determined by splicing to determine the offspring mapping position group. Specifically, the offspring mapping position group can be determined by the following method: splicing the first mapping position subchain and the second mapping position subchain to obtain the target mapping position chain; using each mapping position in the target mapping position chain and multiple computing nodes determined in the current iteration cycle to obtain the offspring mapping position group.

[0197] For example, when the first mapping position subchain is determined to be p0-1 and the second mapping position subchain is q0-2, it is determined that:

[0198] p0-1: V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 );

[0199] q0-2: V 3 (u 1 )-V 4 (u 3 )-V 5 (u 2 ),

[0200] Then, the first mapping position subchain p0-1 and the second mapping position subchain q0-2 can be spliced ​​according to the interception position of the first mapping position subchain p0-1 in the first mapping position chain p0. Since the first mapping position subchain p0-1 is intercepted from the front end of the first mapping position chain p0, the splicing order can be determined to be p0-1→q0-2. The target mapping position chain obtained includes, for example:

[0201] p1: V 0 (u 0 )-V 1 (u 5 )-V 2 (u 4 )-V 3 (u 1 )-V 4 (u 3 )-V5 (u 2 )

[0202] For the target mapping position chain p1, it can be determined in the current iteration cycle:

[0203] The computation node V 0 Mapping in the on-chip network 0 The corresponding mapping position;

[0204] The computation node V 1 Mapping in the on-chip network 5 The corresponding mapping position;

[0205] The computation node V 2 Mapping in the on-chip network 4 The corresponding mapping position;

[0206] The computation node V 3 Mapping in the on-chip network 1 The corresponding mapping position;

[0207] The computation node V 4 Mapping in the on-chip network 3 The corresponding mapping position;

[0208] The computation node V 5 Mapping in the on-chip network 2 The corresponding mapping location.

[0209] According to the comparison with the above mapping position chain p0 and mapping position chain q0, it can be determined that the target mapping position chain p1 determined according to the mapping position chain p0 and mapping position chain q0 can better retain the relative position relationship of the mapping positions allocated to the computing nodes in the mapping position chain p0 and mapping position chain q0. Here, the obtained target mapping position chain p1 can also be used as the mapping position chain corresponding to the next iteration cycle.

[0210] In this way, compared with the method of directly performing genetic crossover and eliminating non-compliant offspring individuals, this method can reduce resource waste while achieving the above Fig.10 The corresponding genetic crossover method in the corresponding embodiment repairs the non-compliant offspring individuals into compliant offspring individuals that can better inherit the characteristics of the parent individuals, and further serves as the parent individuals of the next iteration cycle to continue the iteration of genetic crossover. After completing multiple iteration cycles, the mapping positions of the multiple computing nodes determined by the current iteration cycle in the on-chip network are also better.

[0211] Following the above S901, the method for determining the mapping positions of the plurality of computing nodes determined in the current iteration cycle in the on-chip network further includes:

[0212] S903: Based on the child mapping position group, obtain mapping positions of multiple computing nodes in the on-chip network corresponding to the node division method in the current iteration cycle.

[0213] After determining the child mapping position group according to the above S901~S902, correspondingly, in the current iteration cycle, the node division method in the current iteration cycle can be determined according to any of the above methods (A1) and (A2), so the mapping positions of multiple computing nodes determined in the current iteration cycle in the on-chip network can be determined.

[0214] For example, taking the second iteration cycle described above as an example, in the second iteration cycle, the node division method determined includes:

[0215] The first layer, network layer N 1 The corresponding computing node V 1 ;

[0216] The second network layer N 2 The corresponding computing node V 0 and V 3 ;

[0217] The third layer, network layer N 3 The corresponding computing node V 2 and V 4 ;

[0218] The fourth layer, network layer N 4 The corresponding computing node V 5 .

[0219] In addition, the groups of child mapping locations that can be determined include:

[0220] The computation node V 0 Mapping in the on-chip network 0 The corresponding mapping position;

[0221] The computation node V 1 Mapping in the on-chip network 5 The corresponding mapping position;

[0222] The computation node V 2 Mapping in the on-chip network 4 The corresponding mapping position;

[0223] The computation node V 3 Mapping in the on-chip network 1 The corresponding mapping position;

[0224] The computation node V 4 Mapping in the on-chip network3 The corresponding mapping position;

[0225] The computation node V 5 Mapping in the on-chip network 2 The corresponding mapping location.

[0226] For ease of presentation, see Fig.11 As shown, it is a schematic diagram of the mapping positions of multiple computing nodes in the on-chip network under a certain node division method provided by an embodiment of the present disclosure; wherein, Fig.11 (a) shows the computing nodes V allocated to multiple network layers. 0 ~V 5 ,exist Fig.11 (b) shows multiple computing nodes V 0 ~V 5 The specific mapping location in the on-chip network.

[0227] With respect to the above S102, when the node division method and the mapping positions of the plurality of computing nodes on the on-chip network under the node division method are determined, the performance information when the target neural network is run using the on-chip network can be determined.

[0228] Since the number of computing nodes divided for each network layer is different when dividing the target neural network into multiple network layers, the actual data processing tasks of each computing node are different, and since the computing nodes have corresponding data transmission relationships when executing the algorithm logic of the target neural network, when the mapping position of the computing nodes on the on-chip network is determined, the communication data volume and communication direction between the various data processing cores in the on-chip network can be determined. Therefore, when the node division radial pattern and mapping position are determined, the performance information of the on-chip network when running the target neural network can be determined accordingly.

[0229] In a specific implementation, for any iteration cycle, when determining the performance information corresponding to the iteration cycle, since the node division method and the mapping positions of multiple computing nodes under the node division method can be determined, the corresponding performance information can be determined in the following manner: based on the association relationship information between the multiple computing nodes, the topological structure between the data processing cores in the on-chip network, and the mapping positions of the computing nodes on the on-chip network, the link communication volume of the physical communication link between the data processing cores in the on-chip network is determined; and based on the association relationship information and the data calculation amount corresponding to each network layer in the target neural network, the ideal throughput when the on-chip network is used to execute the data processing task corresponding to the target neural network is determined; based on the link communication volume and the ideal throughput, the performance information when the on-chip network is used to run the target neural network.

[0230] Among them, the link communication volume of the physical communication link is determined according to the data transmission volume between different network layers. The determined performance information may include, for example, communication limitation, computation limitation and full-load transmission. Among them, when the performance information is determined to be communication limitation, it can be determined that when the on-chip network runs the target neural network, the physical communication link with the greatest impact on communication has the problem that the actual link bandwidth cannot meet the actual communication needs; when the performance information is determined to be computation limitation, it can be determined that when the on-chip network runs the target neural network, the physical communication link with the greatest impact on communication has the problem of failing to achieve a high data transmission utilization rate; when the performance information includes full-load transmission, it can be determined that when the on-chip network runs the target neural network, it can be transmitted at the maximum transmission volume. Among them, the physical communication link is a communication link between two data processing cores that are physically adjacent in the on-chip network. For multiple physical communication links of the on-chip network, the physical communication link that has the greatest impact on communication will affect the overall data transmission of the on-chip network, so the on-chip network can be evaluated using performance information.

[0231] With respect to the above S103, during the iterative process of genetic crossover, as the number of iterations increases, the performance information of the on-chip network when running the target neural network will also be improved accordingly, that is, optimized in the direction of full-load transmission. After a certain number of iterations, if it is determined that the iteration stop condition is met, the node division method corresponding to the last iteration cycle can be determined as the target node division method, and the mapping positions corresponding to the multiple target computing nodes under the target node division method can be determined as the target mapping positions.

[0232] Specifically, for example, the following method can be adopted: for the last iteration cycle, based on the node division method in the last iteration cycle and the performance information at the corresponding mapping position, the target division method is determined, and the mapping positions corresponding to the multiple target computing nodes corresponding to the determined target node division method are determined as the target mapping positions.

[0233] In a specific implementation, the conditions for stopping iteration may include, for example, at least one of the following: the number of iterations reaches a preset iteration number threshold; the performance information corresponding to the current iteration cycle reaches a preset performance information threshold.

[0234] If the condition for stopping iteration includes that the number of iterations reaches a preset iteration threshold, the corresponding iteration threshold N can be determined according to actual needs or experimental tests, where N is a positive integer. After N iteration cycles, the genetic crossover operation is terminated, and the node partitioning method corresponding to the last iteration cycle is determined, as well as the mapping positions of multiple computing nodes on the on-chip network under the node partitioning method.

[0235] If the condition for stopping iteration includes that the performance information corresponding to the current iteration cycle reaches a preset performance information threshold, wherein the performance information threshold can be set to a value close to full load transmission according to actual conditions, and the details are not repeated here.

[0236] In the case of determining the last iteration cycle after multiple iteration cycles, since the number of offspring individuals that can be determined after genetic crossover of multiple iteration cycles may be large, it is possible to determine multiple different node division methods and the mapping positions corresponding to multiple computing nodes under the node division methods. In this case, the performance information of the on-chip network under each node division method and the corresponding mapping position can be determined respectively, so as to select the best offspring individual from the offspring individuals corresponding to the last iteration cycle according to the performance information corresponding to each node division method and the corresponding mapping position of the on-chip network, and accordingly use the corresponding node division method as the target node division method, and use the mapping positions corresponding to multiple computing nodes under the target node division method as the target mapping positions.

[0237] In this way, after executing at least one iterative cycle of genetic crossover operations, the node division method with better corresponding performance information and the target mapping positions corresponding to the multiple target computing nodes corresponding to the target node division method can be determined based on the multiple node division methods and corresponding mapping positions obtained by genetic crossover in the last iterative cycle.

[0238] In another embodiment of the present disclosure, a specific embodiment of determining the node division method corresponding to the current iteration cycle and the mapping positions of multiple computing nodes on the on-chip network through genetic crossover in the iteration cycle is also provided. In this embodiment, the on-chip network includes 7 data processing cores, and genetic crossover is performed by digital coding, which is easier to execute and operate the computer device.

[0239] Specifically, see Fig.12 As shown, it is a schematic diagram of a scheduling code and a mapping code provided by an embodiment of the present disclosure. Among them, the scheduling code can be used to determine multiple computing nodes, and the mapping code can be used to determine the mapping positions of multiple computing nodes in the on-chip network. That is, using the scheduling code and mapping code of the current iteration cycle, the multiple computing nodes corresponding to the current iteration cycle and the mapping positions of the multiple computing nodes on the on-chip network can be correspondingly determined. The scheduling code and the mapping code can form a gene chain. Exemplarily, Fig.12 A gene chain (a) is shown, including the corresponding scheduling code a1 part and the mapping code b1 part; another gene chain (b) is also shown, including the corresponding scheduling code a2 part and the mapping code b2 part.

[0240] Taking gene chain (a) as an example, the scheduling code a1 part shows that multiple computing nodes V 0 ~V 6 The corresponding network layers, such as computing node V 0 Corresponding to the first network layer, computing node V 1 Corresponding to the fourth network layer, that is, the computing node V 0 ~V 6 The corresponding numbers 1 to 4 are the labels of the corresponding network layers. 5 If it does not correspond to any network layer, it is correspondingly written as "-1" during coding, indicating that the computing node does not correspond to any network layer. In specific implementations, it can also be coded as "0" or other codes that can independently indicate that the computing node does not correspond to any network layer, which is not specifically limited here.

[0241] The mapping code b1 in gene chain (b) shows the mapping positions of multiple computing nodes in the on-chip network. In the case where the on-chip network includes 7 data processing cores, the positions of the 7 data processing cores can be encoded as a to g. It can be seen from the mapping code b1 that the gene chain (b) determines to map the computing node V 0 Mapped at position a in the on-chip network, the computing node V 1 Mapped at the f position in the on-chip network, etc.

[0242] Here, for the sake of distinction, the specific encoding methods of the scheduling encoding part and the mapping encoding part are described as two different methods: digital encoding and letter encoding. In specific implementations, the encoding method used can be determined according to actual conditions, such as selecting data encoding or letter encoding, or other encoding methods can also be used, which are not specifically limited here.

[0243] In the case where the two gene chains (a) and (b) are used as the parent individuals corresponding to the current iteration cycle, the first position and the second position for performing genetic crossover can be determined accordingly. According to the description in the above embodiment, it can be known that the first position refers to the position where genetic crossover is performed in the scheduling code, and the second position refers to the position where genetic crossover is performed in the mapping code. Among them, in the iterative process of a genetic crossover, for example, only the genetic crossover of the scheduling code part can be performed, or only the genetic crossover of the mapping code part can be performed. In addition, since the genetic crossover of the scheduling code part and the mapping code part do not interfere with each other, the genetic crossover of the scheduling code and the mapping code part can also be performed in parallel.

[0244] The following is an example of genetic crossover for simultaneous scheduling coding and mapping coding. Fig.12The positions indicated by arrows on a1, b1, a2, and b2 are shown in the figure.

[0245] For the scheduling code part, through the first position, the a1-1 code part can be intercepted in the scheduling code a1, and the a2-1 code part can be intercepted in the scheduling code. The a1-1 code part and the a2-1 code part are connected to obtain the code a1'. Since the code a1' does not contain at least one computing node assigned to the second layer network layer, it is also necessary to make repair adjustments to it. Specifically, the code position that needs to be repaired and adjusted can be determined according to the method of determining the target computing node in the above embodiment, for example, the computing node V in the code a1' is 5 The corresponding code is adjusted to "2", indicating that the calculation node V 5 Assigned to the second network layer and obtain the target scheduling code a3.

[0246] For the mapping code part, through the second position, the b1-1 code part can be intercepted in the mapping code b1. For the part of the mapping code b1 except the b1-1 code, it is connected to the b1-1 code in sequence according to the order in the mapping code b2 to determine the target mapping code b3.

[0247] After determining the target scheduling code a3 and the target mapping code b3, the gene chain (c) can be spliced. Here, gene chain (c) is the offspring gene chain determined according to the parent gene chains (a) and (b) in the current iteration cycle. In addition, if the first half of the code is intercepted from a2 and b2 respectively, and the second half of the code is intercepted from a1 and b1 respectively, another gene chain splicing method can be obtained, for example, Fig.12 Another group of offspring gene chains (d) is determined based on the parent gene chains (a) and (b) as shown in the figure; the method for determining the offspring gene chain (d) is similar to the method for determining the offspring gene chain (c) described above, and the specific details will not be repeated.

[0248] In this way, through digital coding, when using computer equipment to actually complete the genetic crossover operation, the logic is simpler and the computing power required is less; at the same time, by setting the relevant adjustment and repair logic in the genetic crossover, the probability of errors in coding can be reduced, ensuring the accuracy of the obtained gene chain, so as to obtain a better offspring gene chain, thereby making the final gene chain performance information better.

[0249] It can be seen that in one iteration cycle, the node division method of the target neural network corresponding to the current iteration cycle and the mapping position corresponding to the current iteration cycle are determined respectively. Only when the node division method and the mapping position are determined can the performance information be determined accordingly. In one iteration cycle (taking two parent computing nodes as an example), the two parent computing node groups can determine at least two child computing nodes through genetic crossover, for example Fig.12 (c) and (d) in the figure are two offspring individuals determined by an iteration cycle ( Fig.12 Take two as an example). If the method of performance reaching a threshold is used to determine whether to end the iteration, the specific steps include determining the performance information corresponding to (c) and (d), respectively. If either of them exceeds the performance information threshold, it can be considered that the offspring individuals that can meet the requirements are determined through genetic crossover, and the iteration process can be stopped accordingly.

[0250] Furthermore, in the above description of the embodiment of the present disclosure, for a clearer description, the determination of the node partitioning method and the corresponding target mapping position are described separately. In a possible case, the determination of the node partitioning method and the corresponding target mapping positions of the multiple target computing nodes can be executed in parallel. Exemplarily, the two information chains of the scheduling code and the mapping code can be linked, and the linked information chain can be used to perform genetic crossover processing.

[0251] In another embodiment of the present disclosure, after determining the target computing node division method and the target mapping positions corresponding to the multiple target computing nodes corresponding to the target node division method, the target neural network can also be mapped in the on-chip network. In this way, since a mapping method with better performance information can be determined, the performance information of the target neural network mapped to the on-chip network under such a mapping method is better.

[0252] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0253] Based on the same inventive concept, a scheduling device corresponding to the scheduling method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned scheduling method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0254] Reference Fig.13 , which is a schematic diagram of a scheduling device provided by an embodiment of the present disclosure, the device includes: a first determination module 131, a second determination module 132, and a third determination module 133; wherein,

[0255] A first determination module 131 is used to determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network respectively;

[0256] A second determination module 132 is used to determine performance information when the target neural network is run using the on-chip network based on the association relationship information between the multiple computing nodes corresponding to the node division method and the mapping position;

[0257] The third determination module 133 is used to determine the target node division method and the target mapping positions corresponding to the multiple target computing nodes corresponding to the target node division method based on the performance information.

[0258] In an optional implementation, the scheduling device further includes a mapping module 134, which is used to map the target neural network in the on-chip network based on the target computing node and the target mapping position.

[0259] In an optional embodiment, when determining a node division method for dividing computing nodes into multiple network layers of a target neural network, the first determination module 131 is used to: determine the node division method based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network; wherein there is at least one computing node corresponding to any network layer.

[0260] In an optional embodiment, when determining the node division method based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, the first determination module 131 is used to: execute multiple of the following iteration cycles, and perform the following process in each iteration cycle: in response to the current iteration cycle being the first iteration cycle, based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, randomly divide the multiple network layers in the target neural network to obtain the node division method of the target neural network in the first iteration cycle; or, in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, obtain the node division method of the target neural network in the current iteration cycle.

[0261] In an optional embodiment, in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, the first determination module 131 obtains the node division method of the target neural network in the current iteration cycle based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, and is used to: determine the parent computing node group of the current iteration cycle; use the number of network layers as the minimum number of child computing nodes in the child computing node group and the number of data processing cores as the maximum number of child computing nodes in the child computing node group, perform a first genetic crossover process on the parent computing node group to obtain at least one group of child computing node groups; and determine the node division method of the target neural network in the current iteration cycle based on each child computing node in the at least one group of child computing node groups.

[0262] In an optional implementation, there are at least two parent computing node groups; when determining the parent computing node group of the current iteration cycle, the first determination module 131 is used to: determine the child computing node group obtained by dividing the previous iteration cycle as the parent computing node group of the current iteration cycle; and / or, based on the performance information corresponding to the parent computing node groups respectively determined in at least one historical iteration cycle, determine the parent computing node group of the current iteration cycle from the parent computing node groups respectively determined in the at least one historical iteration cycle.

[0263] In an optional embodiment, when the first determination module 131 performs a first genetic crossover processing on the parent computing node group to obtain a child computing node group, it is used to: form a computing node chain based on the parent computing nodes in the parent computing node group; and determine the first position of the genetic crossover in the computing node chain; for any two computing node chains, based on the first position of the genetic crossover, determine the first computing node subchain from the first computing node chain, and determine the second computing node subchain from the second computing node chain; based on the first computing node subchain and the second computing node subchain, generate the child computing node group.

[0264] In an optional embodiment, when the first determination module 131 generates the child computing node group based on the first computing node subchain and the second computing node subchain, it is used to: splice the first computing node subchain and the second computing node subchain to generate an alternative computing node chain; detect whether the alternative computing node chain includes computing nodes corresponding to all network layers respectively; in response to the alternative computing node chain including computing nodes corresponding to all network layers respectively, determine the child computing node group based on the alternative computing node chain; in response to the alternative computing node chain not including computing nodes corresponding to all network layers respectively, determine a marked computing node that meets preset conditions from the first computing node subchain or the second computing node subchain; replace the parent computing node corresponding to the marked computing node with the missing computing node in the alternative computing node chain to generate a target computing node chain; and determine the child computing node group based on the target computing node chain.

[0265] In an optional implementation, the first determination module 131 is further used to determine the marked computing node from the candidate computing node chain based on the number of computing nodes corresponding to the network layers included in the candidate computing node chain in the candidate computing node chain.

[0266] In an optional embodiment, when determining the mapping positions of the plurality of computing nodes in the on-chip network, the first determination module 131 is used to: execute a plurality of the following iteration cycles, and perform the following process in each iteration cycle: in response to the current iteration cycle being the first iteration cycle, randomly determine the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the first iteration cycle; or determine the mapping positions of the plurality of computing nodes in the on-chip network based on the association relationship information between the plurality of computing nodes; in response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the previous iteration cycle, obtain the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node division method in the current iteration cycle.

[0267] In an optional implementation, the mapping position of the computing node in the on-chip network includes: the position of the data processing core that executes the computing task corresponding to the computing node in the on-chip network; when the first determination module 131 obtains the mapping positions of the multiple computing nodes corresponding to the node division method in the current iteration cycle based on the mapping positions of the multiple computing nodes corresponding to the node division method in the previous iteration cycle in the on-chip network, the mapping position of the multiple computing nodes corresponding to the node division method in the current iteration cycle is used to: determine the parent mapping position group of the current iteration cycle; based on the multiple computing nodes corresponding to the division method in the current iteration cycle, perform a second genetic crossover processing on the parent mapping position group to obtain a child mapping position group; based on the child mapping position group, obtain the mapping positions of the multiple computing nodes corresponding to the node division method in the current iteration cycle in the on-chip network.

[0268] In an optional embodiment, there are at least two parent mapping position groups; when determining the parent mapping position group, the first determination module 131 is used to: determine the parent mapping position group of the current iteration cycle based on the child mapping position group determined in the previous iteration cycle; and / or, based on the performance information corresponding to the parent mapping position groups respectively determined in at least one historical iteration cycle, determine the parent mapping position group of the current iteration cycle from the parent mapping position groups respectively determined in the at least one historical iteration cycle.

[0269] In an optional embodiment, when the first determination module 131 performs a second genetic crossover processing on the parent mapping position group based on multiple computing nodes determined in the current iteration cycle to obtain a child mapping position group, it is used to: construct a mapping position chain based on the parent mapping position group, and determine the second position of the genetic crossover in the mapping position chain; for any two mapping position chains, determine the first mapping position sub-chain from the first mapping position chain based on the second position, and determine the second mapping position sub-chain from the second mapping position chain; obtain the child mapping position group based on the first mapping position sub-chain, the second mapping position sub-chain, and the multiple computing nodes determined in the current iteration cycle.

[0270] In an optional embodiment, when determining the second mapping position sub-chain from the second mapping position chain, the first determination module 131 is used to: determine, from the second mapping position chain, a target mapping position that is not included in the first mapping position sub-chain; and determine the second mapping position sub-chain based on the order of the target mapping position in the second mapping position chain.

[0271] In an optional embodiment, when the first determination module 131 obtains the child mapping position group based on the first mapping position subchain, the second mapping position subchain, and multiple computing nodes determined by the current iteration cycle, it is used to: splice the first mapping position subchain and the second mapping position subchain to obtain a target mapping position chain; and obtain the child mapping position group using each mapping position in the target mapping position chain and multiple computing nodes determined by the current iteration cycle.

[0272] In an optional implementation, when the third determination module 133 determines the target node division method and the target mapping positions respectively corresponding to the multiple target computing nodes corresponding to the target node division method based on the performance information, it is used to: for the last iteration cycle, based on the node division method in the last iteration cycle and the performance information at the corresponding mapping positions, determine the target division method and determine the mapping positions respectively corresponding to the multiple target computing nodes corresponding to the determined target node division method as the target mapping positions.

[0273] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0274] The disclosed embodiment also provides a network on chip, including: a controller and a plurality of data processing cores;

[0275] The controller is used to determine a node division method for dividing computing nodes into multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method in multiple data processing cores of the on-chip network respectively; and

[0276] Determining performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method and the mapping position; and

[0277] Based on the performance information, a target node division method and target mapping positions respectively corresponding to a plurality of target computing nodes corresponding to the target node division method are determined.

[0278] The on-chip network provided by the present disclosure can, after acquiring the target neural network, determine the division method of computing nodes for the target neural network and the mapping positions of multiple computing nodes in multiple data processing cores, and then execute subsequent computing tasks.

[0279] The present disclosure also provides a computer device, such as Fig.14 FIG. 1 is a schematic diagram of a computer device structure provided in an embodiment of the present disclosure, including:

[0280] A processor 10 and a memory 20; the memory 20 stores machine-readable instructions executable by the processor 10, and the processor 10 is used to execute the machine-readable instructions stored in the memory 20. When the machine-readable instructions are executed by the processor 10, the processor 10 performs the following steps:

[0281] Determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and respective mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network; determine performance information when the target neural network is run using the on-chip network based on association relationship information between the multiple computing nodes corresponding to the node division method, and the mapping positions; determine a target node division method, and respective target mapping positions corresponding to the multiple target computing nodes corresponding to the target node division method based on the performance information.

[0282] The above-mentioned memory 20 includes an internal memory 210 and an external memory 220; the internal memory 210 here is also called an internal memory, which is used to temporarily store the calculation data in the processor 10, as well as the data exchanged with the external memory 220 such as a hard disk. The processor 10 exchanges data with the external memory 220 through the internal memory 210.

[0283] The specific execution process of the above instructions can refer to the steps of the scheduling method described in the embodiment of the present disclosure, which will not be repeated here.

[0284] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the scheduling method described in the above method embodiment are executed. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0285] The present disclosure also provides a computer program product that carries a program code. The program code includes instructions that can be used to execute the steps of the scheduling method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0286] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0287] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0288] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0289] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0290] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0291] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A scheduling method, characterized in that: include: Determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network respectively; Determine performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method and the mapping position; Based on the performance information, determine a target node division method and target mapping positions corresponding to a plurality of target computing nodes corresponding to the target node division method; The determining of mapping positions of the plurality of computing nodes in the on-chip network comprises: Perform the following iterations and in each iteration: In response to the current iteration cycle being the first iteration cycle, randomly determining the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node partitioning method in the first iteration cycle; or determining the mapping positions of the plurality of computing nodes in the on-chip network based on the association relationship information between the plurality of computing nodes; In response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the previous iteration cycle in the network on chip, the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the current iteration cycle in the network on chip are obtained; Determining a target node division method and target mapping positions corresponding to a plurality of target computing nodes corresponding to the target node division method based on the performance information includes: For the last iteration cycle, based on the node division method in the last iteration cycle and the performance information at the corresponding mapping position, the target division method is determined, and the mapping positions corresponding to the multiple target computing nodes corresponding to the determined target node division method are determined as the target mapping positions.

2. The scheduling method according to claim 1, characterized in that: The scheduling method further includes: mapping the target neural network in the on-chip network based on the target computing node and the target mapping position.

3. The scheduling method according to claim 1 or 2, characterized in that: The step of determining a node partitioning method for partitioning computing nodes of multiple network layers of a target neural network includes: The node division method is determined based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network; wherein there is at least one computing node corresponding to any network layer.

4. The scheduling method according to claim 3, characterized in that: The determining the node division method based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network includes: Perform the following iterations and in each iteration: In response to the current iteration cycle being the first iteration cycle, based on the number of network layers of the target neural network and the number of data processing cores in the on-chip network, a plurality of network layers in the target neural network are randomly divided to obtain a node division method of the target neural network in the first iteration cycle; In response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, the node division method of the target neural network in the current iteration cycle is obtained.

5. The scheduling method according to claim 4, characterized in that: In response to the current iteration cycle being another iteration cycle except the first iteration cycle, based on the number of network layers of the target neural network, the number of data processing cores in the on-chip network, and the node division method determined in the previous iteration cycle, obtaining the node division method of the target neural network in the current iteration cycle includes: Determine the parent computing node group of the current iteration cycle; Taking the number of network layers as the minimum number of child computing nodes in a child computing node group and taking the number of data processing cores as the maximum number of child computing nodes in a child computing node group, performing a first genetic crossover process on the parent computing node group to obtain at least one group of child computing node groups; Based on each of the child computing nodes in the at least one group of child computing nodes, a node partitioning method of the target neural network in a current iteration cycle is determined.

6. The scheduling method according to claim 5, characterized in that: There are at least two groups of parent computing nodes; The step of determining the parent computing node group of the current iteration cycle includes: The child computing node group obtained by the previous iteration cycle is determined as the parent computing node group of the current iteration cycle; and / or, Based on the performance information respectively corresponding to the parent computing node groups respectively determined in at least one historical iteration period, the parent computing node group of the current iteration period is determined from the parent computing node groups respectively determined in the at least one historical iteration period.

7. The scheduling method according to claim 5 or 6, characterized in that: The step of performing a first genetic crossover process on the parent computing node group to obtain a child computing node group includes: Forming a computing node chain based on the parent computing nodes in the parent computing node group; and determining a first position of a genetic crossover in the computing node chain; For any two computing node chains, based on the first position of the genetic crossover, determining a first computing node subchain from the first computing node chain, and determining a second computing node subchain from the second computing node chain; The descendant computing node group is generated based on the first computing node sub-chain and the second computing node sub-chain.

8. The scheduling method according to claim 7, characterized in that: The generating the descendant computing node group based on the first computing node sub-chain and the second computing node sub-chain includes: Connecting the first computing node subchain and the second computing node subchain to generate a candidate computing node chain; Detecting whether the candidate computing node chain includes computing nodes corresponding to all network layers respectively; In response to the candidate computing node chain including computing nodes corresponding to all network layers respectively, determining the child computing node group based on the candidate computing node chain; In response to the fact that the candidate computing node chain does not include computing nodes corresponding to all network layers respectively, a marked computing node that meets preset conditions is determined from the first computing node sub-chain or the second computing node sub-chain; the parent computing node corresponding to the marked computing node is replaced with the missing computing node in the candidate computing node chain to generate a target computing node chain; based on the target computing node chain, the child computing node group is determined.

9. The scheduling method according to claim 8, characterized in that: Also includes: The marked computing node is determined from the candidate computing node chain based on the number of computing nodes in the candidate computing node chain corresponding to the network layers included in the candidate computing node chain respectively.

10. The scheduling method according to claim 1, characterized in that: The mapping position of the computing node in the on-chip network includes: the position of the data processing core that executes the computing task corresponding to the computing node in the on-chip network; The obtaining of the mapping positions of the plurality of computing nodes in the on-chip network respectively corresponding to the node division method in the current iteration cycle based on the mapping positions of the plurality of computing nodes in the on-chip network respectively corresponding to the node division method in the previous iteration cycle comprises: Determine the parent mapping position group of the current iteration cycle; Based on a plurality of computing nodes corresponding to the division mode in the current iteration cycle, performing a second genetic crossover process on the parent generation mapping position group to obtain a child generation mapping position group; Based on the child mapping position group, mapping positions of multiple computing nodes in the on-chip network corresponding to the node division method in the current iteration cycle are obtained.

11. The scheduling method according to claim 10, characterized in that: There are at least two groups of parent mapping position groups; The determining of the parent mapping position group comprises: Determine the parent generation mapping position group of the current iteration cycle according to the child generation mapping position group determined in the previous iteration cycle; and / or, Based on the performance information respectively corresponding to the parent mapping position groups respectively determined in at least one historical iteration cycle, the parent mapping position group of the current iteration cycle is determined from the parent mapping position groups respectively determined in the at least one historical iteration cycle.

12. The scheduling method according to claim 10 or 11, characterized in that: The method further comprises: performing a second genetic crossover process on the parent generation mapping position group based on the plurality of computing nodes determined in the current iteration cycle to obtain a child generation mapping position group. Based on the parent generation mapping position group, forming a mapping position chain, and determining a second position of the genetic crossover in the mapping position chain; For any two mapping position chains, based on the second position, determining a first mapping position subchain from the first mapping position chain, and determining a second mapping position subchain from the second mapping position chain; The descendant mapping position group is obtained based on the first mapping position sub-chain, the second mapping position sub-chain, and a plurality of computing nodes determined in the current iteration cycle.

13. The scheduling method according to claim 12, characterized in that: The determining of the second mapping position subchain from the second mapping position chain includes: Determine, from the second mapping position chain, a target mapping position that is not included in the first mapping position subchain; Based on the order of the target mapping positions in the second mapping position chain, the second mapping position sub-chain is determined.

14. The scheduling method according to claim 12, characterized in that: The obtaining of the descendant mapping position group based on the first mapping position subchain, the second mapping position subchain, and a plurality of computing nodes determined in the current iteration cycle includes: splicing the first mapping position subchain and the second mapping position subchain to obtain a target mapping position chain; The descendant mapping position group is obtained by using each mapping position in the target mapping position chain and a plurality of computing nodes determined in the current iteration cycle.

15. A scheduling device, characterized in that: include: A first determination module is used to determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method on the on-chip network respectively; A second determination module is used to determine performance information when the target neural network is run using the on-chip network based on the association relationship information between the multiple computing nodes corresponding to the node division method and the mapping position; A third determination module is used to determine, based on the performance information, a target node division method and target mapping positions corresponding to a plurality of target computing nodes corresponding to the target node division method; The first determination module is specifically configured to: execute the following iteration cycle, and execute the following process in each iteration cycle: In response to the current iteration cycle being the first iteration cycle, randomly determining the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node partitioning method in the first iteration cycle; or determining the mapping positions of the plurality of computing nodes in the on-chip network based on the association relationship information between the plurality of computing nodes; In response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the previous iteration cycle in the network on chip, the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the current iteration cycle in the network on chip are obtained; The third determination module is specifically used to: for the last iteration cycle, determine the target division method based on the node division method in the last iteration cycle and the performance information at the corresponding mapping position, and determine the mapping positions corresponding to the multiple target computing nodes corresponding to the determined target node division method as the target mapping positions.

16. A network on chip, characterized in that: include: controller and multiple data processing cores; The controller is used to determine a node division method for dividing computing nodes of multiple network layers of a target neural network, and mapping positions of multiple computing nodes corresponding to the node division method in multiple data processing cores of the on-chip network respectively; as well as Determine performance information when the target neural network is run using the on-chip network based on association relationship information between multiple computing nodes corresponding to the node division method and the mapping position; as well as Based on the performance information, determine a target node division method and target mapping positions corresponding to a plurality of target computing nodes corresponding to the target node division method; The controller, when determining the mapping positions of the plurality of computing nodes in the on-chip network, is used to: Perform the following iterations and in each iteration: In response to the current iteration cycle being the first iteration cycle, randomly determining the mapping positions of the plurality of computing nodes in the on-chip network corresponding to the node partitioning method in the first iteration cycle; or determining the mapping positions of the plurality of computing nodes in the on-chip network based on the association relationship information between the plurality of computing nodes; In response to the current iteration cycle being an iteration cycle other than the first iteration cycle, based on the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the previous iteration cycle in the network on chip, the mapping positions of the multiple computing nodes corresponding to the node partitioning method in the current iteration cycle in the network on chip are obtained; The controller, when determining the target node division method and the target mapping positions respectively corresponding to the plurality of target computing nodes corresponding to the target node division method based on the performance information, is used to: For the last iteration cycle, based on the node division method in the last iteration cycle and the performance information at the corresponding mapping position, the target division method is determined, and the mapping positions corresponding to the multiple target computing nodes corresponding to the determined target node division method are determined as the target mapping positions.

17. A computer device, characterized in that: include: A processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and the processor is used to execute the machine-readable instructions stored in the memory, and when the machine-readable instructions are executed by the processor, the processor executes the steps of the scheduling method according to any one of claims 1 to 14; or Comprising a network on chip as claimed in claim 16.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program. When the computer program is executed by a computer device, the computer device executes the steps of the scheduling method according to any one of claims 1 to 14.

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