Image sensor having a pixel having dual output circuit therein

Abstract

An image sensor pixel includes a substrate, a photodiode in the substrate, and a pixel circuit. The pixel circuit includes: a transfer element electrically connected between the photodiode and a floating diffusion node, the floating diffusion node accumulating charge generated by the photodiode in response to light incident on the substrate; and a drive element electrically connected to the floating diffusion node. An output circuit is also provided, which is electrically connected between a column line and the pixel circuit. The output circuit includes: a switch element electrically connected to an output terminal of the drive element; a primary capacitor electrically connected to the switch element; a secondary capacitor selectively connected to or disconnected from the switch element based on an on / off switching state of a first enabling element; and a first selection element electrically connected between the switch element and the column line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0074099, filed on Jun. 18, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The inventive concept relates to an integrated circuit device, and more particularly, to an image sensor device. Background Art

[0004] Image sensors are typically semiconductor-based sensors that receive light and generate electrical signals in response to the light. These sensors may include a pixel array having a plurality of pixels, a logic circuit that drives the pixel array and generates image data, and the like. The logic circuit may control the image sensor using a global shutter method in which image data is obtained by exposing a plurality of pixels to light simultaneously. An image sensor operating in global shutter mode may eliminate image jitter (also known as the "jello effect"), and may capture the precise shape of an object and output the captured object shape as image data. Summary of the invention

[0005] Example embodiments provide an image sensor in which noise characteristics, operation speed, and quality of a resulting image can be improved by using capacitors in respective pixels to operate in a global shutter mode and by changing the capacitance of the capacitor as necessary.

[0006] According to example embodiments, there is provided an image sensor including a plurality of pixels. Each of the plurality of pixels includes: (i) at least one photodiode configured to generate charge in response to light; (ii) a pixel circuit including a transfer element connected between the photodiode and a floating diffusion node (in which charge is accumulated) and a driving element connected to the floating diffusion node; (iii) a first output circuit connected between a first column line and the pixel circuit and including a first switching element, a first primary capacitor, a first secondary capacitor, and a first selection element, the first switching element being connected to an output terminal of the driving element, the first primary capacitor being connected to the first switching element, the first secondary capacitor being connected to the first switching element or being disconnected from the first switching element based on on / off switching of a first enabling element, and the first selection element being connected between the first switching element and the first column line; and (iv) a second output circuit connected between the pixel circuit and a second column line different from the first column line and including a second switching element, a second primary capacitor, a second secondary capacitor, and a second selection element, the second switching element being connected to the output terminal of the driving element, the second primary capacitor being connected to the second switching element, the second secondary capacitor being connected to the second switching element or being disconnected from the second switching element based on on / off switching of the second enabling element, and the second selection element being connected between the second switching element and the second column line.

[0007] According to another exemplary embodiment, an image sensor is provided, comprising: a pixel array; and a logic circuit configured to drive the pixel array to obtain image data. Each of the plurality of pixels comprises: (i) a photodiode that generates charge in response to light; (ii) a transfer element connected between the photodiode and a floating diffusion node that accumulates charge; (iii) a drive element that is connected to the floating diffusion node and generates an output voltage by amplifying the voltage of the floating diffusion node; (iv) a first output circuit that is connected between a first column line and the drive element and comprises a first switch element, a first capacitor connected to the first switch element, and a first selection element connected between the first capacitor and the first column line; and (v) a second output circuit that is connected between the drive element and a second column line different from the first column line and comprises a second switch element, a second capacitor connected to the second switch element, and a second selection element connected between the second capacitor and the second column line. Advantageously, when the intensity of the light is a first intensity, the logic circuit sets the first capacitor to have a first capacitance, and when the intensity of the light is a second intensity greater than the first intensity, the logic circuit sets the first capacitor to have a second capacitance less than the first capacitance.

[0008] According to an example embodiment, an image sensor includes: a pixel array including a plurality of pixels; and a logic circuit that simultaneously exposes the plurality of pixels to light within an exposure time and obtains image data. Each of the plurality of pixels includes: a photodiode; a pixel circuit that is connected to the photodiode and generates a reset voltage and a pixel voltage; a first output circuit that includes a first capacitor that stores the reset voltage and is connected between a first column line and the pixel circuit; and a second output circuit that includes a second capacitor that stores the pixel voltage and is connected between a second column line and the pixel circuit. The logic circuit adjusts the capacitance of each of the first capacitor and the second capacitor based on the exposure time. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram of an image sensor according to an example embodiment;

[0011] Figure 2 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0012] Figure 3 is a schematic circuit diagram of a pixel included in an image sensor according to example embodiments;

[0013] Figures 4 to 6 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0014] Figure 7 is a schematic circuit diagram of a pixel included in an image sensor according to example embodiments;

[0015] Figure 8 is a schematic block diagram of an image sensor according to an example embodiment;

[0016] Fig. 9 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0017] Figures 10 to 12 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0018] Fig.13 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0019] Figures 14 to 16 is a diagram provided to illustrate the operation of an image sensor according to example embodiments;

[0020] Fig.17is a diagram illustrating a portion of a pixel included in an image sensor according to example embodiments;

[0021] Fig.18 and Fig.19 is a diagram schematically illustrating an image sensor according to example embodiments;

[0022] Fig. 20 is a diagram illustrating a portion of a pixel included in an image sensor according to example embodiments;

[0023] Fig.21 and Fig. 22 is a diagram illustrating a portion of a pixel included in an image sensor according to example embodiments; and

[0024] Fig.23 and Fig.24 is a diagram schematically illustrating an electronic device including an image sensor according to example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0026] Figure 1 is a schematic block diagram of an image sensor according to an example embodiment. Figure 1 , the image sensor 1 may include a pixel array 10, a logic circuit 20, etc. The pixel array 10 may include a plurality of pixels PX arranged in an array shape in a plurality of rows and columns. Each of the plurality of pixels PX may include: at least one photoelectric conversion element that generates charges in response to incident light; and a plurality of elements that generate pixel signals corresponding to the charges generated by the photoelectric conversion element. The photoelectric conversion element may be formed of a semiconductor material or an organic material, and may include, for example, a photodiode.

[0027] In some embodiments, each of the pixels PX may include a floating diffusion node, a transfer transistor, a reset transistor, a drive transistor, and a select transistor. However, the configuration of the pixel PX may be changed according to an exemplary embodiment of the present invention. For example, each of the pixels PX may include an organic photodiode containing (one or more) organic materials, or may be implemented as a digital pixel. When the pixel PX is implemented as a digital pixel, each of the pixels PX may include an analog-to-digital converter for outputting a digital pixel signal.

[0028] The logic circuit 20 may include a circuit for controlling the pixel array 10. For example, the logic circuit 20 may include a row driver 21, a readout circuit 22, a column driver 23, a control logic 24, etc. The row driver 21 may drive the pixel array 10 in units of row lines. For example, the row driver 21 may generate a transfer control signal for controlling a transfer transistor of each pixel PX and a selection control signal for controlling a selection transistor, etc., so as to input the generated signal to the pixel array 10 in units of row lines. In addition, the row driver 21 may simultaneously input a reset control signal for controlling a reset transistor to the entire pixel array 10 to simultaneously reset the pixel PX and expose the pixel to light. In this case, the image sensor 1 may operate in a global shutter method.

[0029] The readout circuit 22 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), and the like. The correlated double sampler may be connected to the pixel PX through a column line. According to an example embodiment, the pixel PX may be connected to two or more correlated double samplers through two or more column lines, respectively. The correlated double sampler may read a pixel signal from the pixel PX connected to a row line selected by a row line selection signal of the row driver 21 through the column line. The analog-to-digital converter may convert the pixel signal detected by the correlated double sampler into a digital pixel signal and send the converted signal to the column driver 23.

[0030] The column driver 23 may include a latch capable of temporarily storing a digital pixel signal, or a buffer circuit and an amplification circuit, and may process the digital pixel signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 may be controlled by the control logic 24. The control logic 24 may include a timing controller for controlling the operation timing of the row driver 21, the readout circuit 22, and the column driver 23.

[0031] Among the pixels PX, the pixels PX disposed in the same position in the first direction (lateral direction) may share column lines with each other. For example, the pixels PX disposed in the same position in the second direction (longitudinal direction) are simultaneously selected by the row driver 21 during the readout operation, and pixel signals may be output through the column lines. In an example embodiment, the readout circuit 22 may simultaneously obtain pixel signals from the pixels PX selected by the row driver 21 through the column lines. The pixel signal may include a reset voltage and a pixel voltage, and the pixel voltage may be a voltage in which charges generated in response to light in each of the pixels PX are reflected in the reset voltage.

[0032] When the image sensor 1 operates in a global shutter method, each of the pixels PX may include a storage element such as a capacitor capable of storing a reset voltage and a pixel voltage. When the capacitor has a relatively large capacitance, the noise characteristics of the pixel signal can be improved, but the time required to store the reset voltage and the pixel voltage in the capacitor will increase, which means that the operating speed of the image sensor 1 may be reduced. Conversely, reducing the capacitance of the capacitor may improve the operating speed of the image sensor 1, but the noise characteristics may deteriorate.

[0033] In an example embodiment, the capacitance of the capacitor included in each of the pixels PX can be adjusted to advantageously implement operations optimized for each imaging environment. For example, in a high illumination environment where noise is not expected to be excessive, the capacitance of the capacitor can be reduced to ensure a fast operating speed of the image sensor 1; however, in a low illumination environment, the capacitance of the capacitor can be increased to improve noise characteristics, but at the expense of possibly reducing the operating speed.

[0034] Figure 2 2 is a diagram provided to illustrate the operation of an image sensor according to example embodiments. Figure 2 1 may be provided to illustrate the global shutter operation of the image sensor 1. Figure 1 and Figure 2 , the photodiodes of the plurality of pixels PX included in the pixel array 10 may be simultaneously reset during the reset time TRST. For example, the row driver 21 may reset the photodiodes by turning on reset elements included in the pixels PX to eliminate charges from the photodiodes.

[0035] When the photodiodes are reset, the photodiodes included in the plurality of pixels PX may be reset during the exposure time T EX The exposure time T may be determined by the operating environment of the image sensor 1, the shutter speed, the aperture value, etc. EX .

[0036] At exposure time T EX During the exposure time T, the charge generated by the photodiode in response to light can be stored in a capacitor included in the pixel PX. EX The time during which the photodiode is exposed to light and the time during which the charge generated by the photodiode is stored in the capacitor may be included. For example, a reset voltage in which the charge generated by the photodiode is not reflected may be stored in a first capacitor, and a pixel voltage in which the charge generated by the photodiode is reflected in the reset voltage may be stored in a second capacitor different from the first capacitor.

[0037] When the exposure time T EXThe row driver 21 may scan the plurality of corresponding row lines when the time T elapses. The readout circuit 22 may perform a readout operation on the plurality of corresponding pixels PX according to the order in which the row driver 21 scans the plurality of row lines. The readout circuit 22 may perform a readout operation on the plurality of corresponding pixels PX at the readout time T RO During this period, reset voltages and pixel voltages stored in a plurality of corresponding pixels PX are read.

[0038] Figure 3 is a schematic circuit diagram of a pixel included in an image sensor according to an example embodiment. Figure 3 In an image sensor according to example embodiments, a pixel 100 may include a pixel circuit 105 connected to a photodiode PD, a first output circuit 110 connected to the pixel circuit 105, a second output circuit 120 connected to the pixel circuit 105, etc. The first output circuit 110 and the second output circuit 120 may be connected to the pixel circuit 105 in parallel.

[0039] The pixel circuit 105 may include a floating diffusion node FD, a transfer element TX, a reset element RX, a driving element DX, a bias element BX, etc. The floating diffusion node FD may be a node in which charges generated by the photodiode PD are accumulated, and the transfer element TX may be connected between the floating diffusion node FD and the photodiode PD. When the transfer element TX is turned on by the transfer control signal TG, the charges generated by the photodiode PD may move and may be accumulated in the floating diffusion node FD.

[0040] The reset element RX may be connected between the power node 101 supplying the power supply voltage VDD and the floating diffusion node FD. When the reset element RX is turned on by the reset control signal RG, the charge of the floating diffusion node FD is eliminated and the voltage of the floating diffusion node FD may be reset.

[0041] The driving element DX includes a gate electrode connected to the floating diffusion node FD and can operate as a source follower amplifier. The driving element DX can amplify and output the voltage of the floating diffusion node FD, and the first output circuit 110 and the second output circuit 120 can be connected to the output terminal of the driving element DX. In addition, the driving element DX is connected to a supply bias voltage V BIAS The bias element BX of the drive element DX can be turned on by the bias control signal BG while the drive element DX is being operated.

[0042] The first output circuit 110 may be connected between the pixel circuit 105 and the first column line COL1. The first output circuit 110 may include a first switch element SW1, a first primary capacitor MC1, a first secondary capacitor VC1, a first selection element SX1, a first output drive element DX1, etc. The first secondary capacitor VC1 may be connected in series to the first enabling element EX1, and the first secondary capacitor VC1 and the first enabling element EX1 may be connected in parallel to the first primary capacitor MC1.

[0043] The first primary capacitor MC1, the first enabling element EX1, and the first secondary capacitor VC1 may provide a first capacitor of the first output circuit 110. When the first enabling element EX1 is turned off, only the first primary capacitor MC1 is connected to the first switching element SW1, and when the first enabling element EX1 is turned on, the first primary capacitor MC1 and the first secondary capacitor VC1 may be connected together to the first switching element SW1. Therefore, the capacitance of the first capacitor may be changed based on the on / off switching of the first enabling element EX1.

[0044] The first output driver element DX1 receives the power supply voltage VDD, and the gate of the first output driver element DX1 can be connected to the first switch element SW1. Therefore, the first output driver element DX1 can operate as a source follower amplifier based on the voltage stored in the first primary capacitor MC1 (or the first primary capacitor MC1 and the first secondary capacitor VC1). The first selection element SX1 connected between the first column line COL1 and the first output driver element DX1 can be controlled by the first selection signal SEL1.

[0045] The second output circuit 120 may be connected between the pixel circuit 105 and the second column line COL2. The second output circuit 120 may include a second switch element SW2, a second primary capacitor MC2, a second secondary capacitor VC2, a second selection element SX2, a second output drive element DX2, etc. The configuration and operation of the second output circuit 120 may be similar to the configuration and operation of the first output circuit 110. For example, the second primary capacitor MC2, the second enabling element EX2, and the second secondary capacitor VC2 may provide a second capacitor of the second output circuit 120, and the capacitance of the second capacitor may change based on the on / off switching of the second enabling element EX2.

[0046] In an example embodiment, the first output circuit 110 may sample a reset voltage output from the pixel circuit 105, and the second output circuit 120 may sample a pixel voltage output from the pixel circuit 105. For example, the first switch element SW1 may be turned on after the floating diffusion node FD is reset and before the transfer element TX is turned on, and the reset voltage may be sampled to the first capacitor. The second switch element SW2 may be turned on after the transfer element TX is turned on and the charge of the photodiode PD moves to the floating diffusion node FD, and the pixel voltage may be sampled to the second capacitor.

[0047] The first output circuit 110 and the second output circuit 120 may output a reset voltage and a pixel voltage at the same time. In detail, while the first output circuit 110 outputs the reset voltage to the first column line COL1, the second output circuit 120 may output the pixel voltage to the second column line COL2. For example, the first column line COL1 may be connected to a first analog-to-digital converter, and the second column line COL2 may be connected to a second analog-to-digital converter. The logic circuit of the image sensor may calculate the difference between the first digital signal output from the first analog-to-digital converter and the second digital signal output from the second analog-to-digital converter to obtain image data of the pixel 100.

[0048] The capacitance of the first primary capacitor MC1 may be smaller than the capacitance of the first secondary capacitor VC1. Similarly, the capacitance of the second primary capacitor MC2 may be smaller than the capacitance of the second secondary capacitor VC2. According to example embodiments, the capacitances of the first primary capacitor MC1 and the second primary capacitor MC2 may be the same or different from each other. Similarly, the capacitances of the first secondary capacitor VC1 and the second secondary capacitor VC2 may be the same or different from each other.

[0049] Referring to the first output circuit 110 as an example, when the first enabling element EX1 is turned off, only the first primary capacitor MC1 can be connected to the first switch element SW1. Therefore, the capacitance of the first output circuit 110 for sampling the reset voltage output from the driving element DX is reduced, and the sampling time can be shortened, while the noise based on the on / off switching operation of the first switch element SW1 may increase. On the contrary, when the first enabling element EX1 is turned on, the capacitance of the first output circuit 110 is increased by the first secondary capacitor VC1, so that the sampling time increases, but the noise based on the on / off switching operation of the first switch element SW1 can be advantageously eliminated. The operation of the second output circuit 120 can also be understood similarly.

[0050] The logic circuit of the image sensor may determine the capacitance of each of the first capacitor and the second capacitor taking into account at least one of various parameters such as light intensity, exposure time, and sensitivity. For example, when the light intensity is a first intensity, the first capacitor may be set to have a first capacitance, and when the light intensity is a second intensity greater than the first intensity, the first capacitor may be set to have a second capacitance lower than the first capacitance. Similarly, when the light intensity is a first intensity, the second capacitor may be set to have a third capacitance, and when the light intensity is a second intensity, the second capacitor may be set to have a fourth capacitance lower than the third capacitance. The first to fourth capacitances may be determined based on the corresponding capacitances of the first primary capacitor MC1, the first secondary capacitor VC1, the second primary capacitor MC2, and the second secondary capacitor VC2, respectively. As an example, when the first primary capacitor MC1 and the second primary capacitor MC2 have the same capacitance, and the first secondary capacitor VC1 and the second secondary capacitor VC2 have the same capacitance, the first capacitance and the third capacitance may be the same, and the second capacitance and the fourth capacitance may be the same.

[0051] As another example, the logic circuit may compare the exposure time with a predetermined reference time to set the capacitance of each of the first capacitor and the second capacitor. For example, when the exposure time is longer than the reference time, the capacitance of the first capacitor and the second capacitor may be set to be relatively large, and when the exposure time is shorter than the reference time, the capacitance of the first capacitor and the second capacitor may be set to be relatively small. Alternatively, the capacitance of the first capacitor and the second capacitor may be determined according to an ISO value representing sensitivity. In an example embodiment, when the ISO value is less than a predetermined reference value, the capacitance of the first capacitor and the second capacitor may be reduced, and when the ISO value is greater than the reference value, the capacitance of the first capacitor and the second capacitor may be increased. However, this is merely an example embodiment, and the capacitance of the first capacitor and the second capacitor may also be determined by the logic circuit in consideration of various other parameters.

[0052] Figures 4 to 6 is a diagram provided to illustrate the operation of an image sensor according to an example embodiment. Figure 3 The operation of the image sensor is described with reference to the pixel 100. Figure 4, the reset element RX and the transfer element TX are turned on by the reset control signal RG and the transfer control signal TG, so that the floating diffusion node FD and the photodiode PD can be reset. When the reset element RX and the transfer element TX are turned off, the first exposure time EIT1 starts, and during the first exposure time EIT1, the photodiode reacts to light to generate charges. During the first exposure time EIT1, the transfer element TX maintains an off state, and the reset element RX is turned on at least once or multiple times to reset the voltage of the floating diffusion node FD again. When the reset element RX is turned off, the first switch element SW1 is turned on by the first switch control signal SG1 to store the reset voltage in the first output circuit 110. When the first exposure time EIT1 starts, the bias element BX can be turned on by the bias control signal BG so that the driving element DX of the pixel circuit 105 can operate. The bias element BX can be turned on during the storage time ST for storing the reset voltage and the pixel voltage.

[0053] The time when the first switch element SW1 is turned on can be defined as the reset sampling time RST. Figure 4 In the example embodiment shown in , the first enabling element EX1 may also be turned on together with the first switching element SW1. Therefore, the reset voltage may be stored in the first primary capacitor MC1 and the first secondary capacitor VC1.

[0054] Reference Figure 4 , the first switch element SW1 and the second switch element SW2 can be turned on together. Therefore, the reset voltage can also be stored in the second output circuit 120. Since the second enabling element EX2 is turned on together with the second switch element SW2, the reset voltage can be stored in the second primary capacitor MC2 and the second secondary capacitor VC2.

[0055] When the first exposure time EIT1 ends, the transfer element TX is turned on by the transfer control signal TG, and the charge generated by the photodiode PD during the first exposure time EIT1 can be moved to the floating diffusion node FD. When electrons are the main charge carriers, the voltage of the floating diffusion node FD can be reduced from the reset voltage. The first switch element SW1 can be turned off before the transfer element TX is turned on (for example, before the first exposure time EIT1 ends). Therefore, before the charge of the photodiode PD moves to the floating diffusion node FD, the first output circuit 110 can be separated from the pixel circuit 105.

[0056] On the other hand, even when the first exposure time EIT1 ends and the transfer element TX is turned on so that the charge of the photodiode PD moves to the floating diffusion node FD, the second switch element SW2 can maintain the on state. When the transfer element TX is turned off, the pixel voltage determined by the charge transferred from the photodiode PD can be stored in the second output circuit 120 during the pixel sampling time PIX. For example, in the second output circuit 120, the voltages of the second primary capacitor MC2 and the second secondary capacitor VC2 can be reduced by the charge accumulated in the floating diffusion node FD.

[0057] And, when the pixel sampling time PIX elapses, the bias element BX may be turned off. Thereafter, a readout operation may be performed during the readout time RT in which the first selection element SEL1 and the second selection element SEL2 are turned on. The readout operation may include: comparing each of the reset voltage stored in the first output circuit 110 and the pixel voltage stored in the second output circuit 120 with the ramp voltage RMP, and converting the comparison result into a digital signal through an analog-to-digital converter. For example, a first sampler connected to the first column line COL1 may compare the reset voltage with the ramp voltage RMP, and may output the comparison result to the first analog-to-digital converter. In addition, a second sampler connected to the second column line COL2 may compare the pixel voltage with the ramp voltage RMP, and may output the comparison result to the second analog-to-digital converter. Therefore, the readout operation for the first output circuit 110 and the second output circuit 120 may be performed simultaneously. During the readout time RT, the bias element BX is turned on to supply the bias current required for the readout operation.

[0058] exist Figure 4 In the example embodiment shown in , the reset voltage may be stored in the first primary capacitor MC1 and the first secondary capacitor VC1 during the storage time ST, and the pixel voltage may be stored in the second primary capacitor MC2 and the second secondary capacitor VC2 during the storage time ST. Therefore, until the readout operation is terminated, the first enabling element EX1 and the second enabling element EX2 may maintain a turned-on state.

[0059] On the other hand, Figure 4 Unlike the example embodiment shown in , during the storage time ST, the second switch element SW2 may be turned on at a timing different from that of the first switch element SW1. As an example, the second switch element SW2 may be turned on after the transfer element TX is turned on and the charge of the photodiode PD moves to the floating diffusion node FD.

[0060] Next, refer to Figure 5 , the photodiode PD may be exposed to light during a second exposure time EIT2 shorter than the first exposure time EIT1 to generate charges. Figure 4 The described example embodiments may be example embodiments for describing the operation of an image sensor in a low illumination environment (eg, an imaging environment in which the intensity of light is relatively weak). Figure 5 The described example embodiments may be example embodiments for describing the operation of an image sensor in a high illumination environment (eg, an imaging environment in which the intensity of light is relatively strong).

[0061] In an imaging environment where the intensity of light is strong, more charges can be generated in the photodiode PD than in an imaging environment where the intensity of light is weak. Figure 5 As shown in FIG. 1 , the second exposure time EIT2 can be set to be shorter than the first exposure time EIT1. When the second exposure time EIT2 is set to be relatively short, Figure 4 Compared with the example embodiment shown in , the reset sampling time RST for the first output circuit 110 to sample the reset voltage can be reduced. Figure 4 Compared with the exemplary embodiment shown in , the pixel sampling time PIX for the second output circuit 120 to sample the pixel voltage can also be reduced. Figure 5 In the example embodiment shown in Figure 4 Compared with the example embodiment shown in , the storage time ST can be reduced.

[0062] Reference Figure 5 During the storage time ST and the readout time RT, the first enabling element EX1 and the second enabling element EX2 may maintain an off state. Figure 5 The example embodiment shown in FIG. 1 may be a high illumination environment in which the intensity of light is relatively strong, and in this case, Figure 4 Compared with the example embodiment shown in , the signal strength can be improved and the noise can be weakened. Therefore, by turning off the first enabling element EX1 in the first output circuit 110 and connecting only the first primary capacitor MC1 to the first switch element SW1, the stabilization time required for sampling the reset voltage to the first primary capacitor MC1 can be reduced, and the operation speed of the image sensor can be improved. Similarly, also in the second output circuit 120, only the second primary capacitor MC2 is connected to the second switch element SW2 to shorten the stabilization time.

[0063] Next, refer to Figure 6 , two read operations can be performed at the first read time RT1 and the second read time RT2. Figure 6 In the example embodiment shown in FIG. 1 , the operation of the pixel 100 during the exposure time EIT and the storage time ST may be the same as described above with reference to FIG. Figure 4 and Figure 5During the first readout time RT1 , the logic circuit of the image sensor may read the reset voltage from the first output circuit 110 through the first column line COL1 , and may read the pixel voltage from the second output circuit 120 through the second column line COL2 .

[0064] Since the first output circuit 110 includes the first output driving element DX1 and the second output circuit 120 includes the second output driving element DX2, an offset component due to a difference between the first output driving element DX1 and the second output driving element DX2 may be included between a voltage output from the first output circuit 110 and a voltage output from the second output circuit 120. For example, the offset component may occur due to a difference in threshold voltage between the first output driving element DX1 and the second output driving element DX2. Figure 6 In the example embodiment shown in , the offset component can be eliminated by performing a first readout operation during a first readout time RT1 and performing a second readout operation during a second readout time RT2.

[0065] During the first readout time RT1, the logic circuit of the image sensor can obtain the reset voltage and the pixel voltage. During the intermediate reset time MRT after the first readout time RT1, the reset element RX, the first switch element SW1 and the second switch element SW2 are turned on, and a predetermined reference voltage can be input to the first output circuit 110 and the second output circuit 120 together. The first output drive element DX1 and the second output drive element DX2 can be operated as a source follower amplifier by the reference voltage. After that, the reset element RX, the first switch element SW1 and the second switch element SW2 are turned off, and the logic circuit can read the reference voltage from the first output circuit 110 and the second output circuit 120 through the first column line COL1 and the second column line COL2.

[0066] An offset component due to a difference in threshold voltage between the first output driver element DX1 and the second output driver element DX2 may occur in both the first readout operation and the second readout operation. When the reset voltage, the pixel voltage, the reference voltage, and the offset component are taken into consideration, the first analog-to-digital converter connected to the first column line COL1 sequentially outputs the reset voltage and the reference voltage, and the second analog-to-digital converter connected to the second column line COL2 may sequentially output (pixel voltage+offset component) and (reference voltage+offset component). The above example may be an example embodiment in which an offset component based on a difference between the first output driver element DX1 and the second output driver element DX2 is reflected in the second output driver element DX2.

[0067] For example, the first original image signal obtained by calculating the difference between the output of the first analog-to-digital converter during the first readout time RT1 and the output of the second analog-to-digital converter during the first readout time RT1 can be calculated as (reset voltage-pixel voltage-offset component). On the other hand, the second original image signal obtained by calculating the difference between the output of the first analog-to-digital converter during the second readout time RT2 and the output of the second analog-to-digital converter during the second readout time RT2 can be calculated as (reference voltage-reference voltage-offset component). Therefore, by calculating the difference between the first original image signal and the second original image signal, the offset component can be eliminated, and image data corresponding to (reset voltage-pixel voltage) can be accurately obtained.

[0068] exist Figure 6 In the example embodiment shown in , the first enabling element EX1 and the second enabling element EX2 may maintain the on state during the storage time ST and the readout time RT. However, according to the example embodiment, for example, in the example embodiment in which the exposure time EIT is reduced due to an increase in the light intensity in the imaging environment, the first enabling element EX1 and the second enabling element EX2 may also be maintained in the off state.

[0069] Figure 7 is a schematic circuit diagram of a pixel included in an image sensor according to an example embodiment. Figure 7 In the example embodiment of the pixel 100 shown in FIG. 1 , the pixel circuit 105 may be the same as that described above with reference to FIG. Figure 3 The pixel circuit 105 in the exemplary embodiment described is the same as Figure 3 Unlike the example embodiment shown in Figure 7 In the example embodiment shown in , the first output circuit 110A and the second output circuit 110B may share one enable element EX. The enable element EX is controlled by an enable signal EN and may be connected to a power node 101 supplying a power supply voltage VDD, as shown.

[0070] When the enabling element EX is turned off, only the first primary capacitor MC1 and the second primary capacitor MC2 are connected to the pixel circuit 105, and the first secondary capacitor VC1 and the second secondary capacitor VC2 can be separated from the pixel circuit 105. As described above, when a relatively long exposure time is required, the enabling element EX can be turned on (for example, in a low-illuminance imaging environment where the intensity of light is weak). When a relatively short exposure time is required, the enabling element EX can be turned off (for example, in a high-illuminance imaging environment where the intensity of light is strong).

[0071] Figure 8 is a schematic block diagram of an image sensor according to an example embodiment. Figure 8In the example embodiment shown in FIG. 1 , the image sensor 1A may include a pixel array 10, a logic circuit 20, a light source 30, etc. The configuration and operation of the pixel array 10 may be similar to those of FIG. Figure 1 The configuration and operation of the described pixel array 10 are similar.

[0072] The light source 30 may be operated by a control signal CNT output from the control logic 24. For example, the control signal CNT may be a square wave signal, and the light source 30 may output light in the infrared band. While the light source 30 outputs light by the control signal CNT, the logic circuit 20 may expose the pixel PX to light. Light output from the light source 30 and reflected by an object may be incident on the pixel PX, and the photodiode may react to the light to generate charge.

[0073] according to Figure 8 The image sensor 1A of the example embodiment shown in the figure can be applied to various fields (such as camera devices for facial recognition, autonomous vehicles, and vehicle driver monitoring). In addition, the logic circuit 20 can obtain a first digital pixel signal from a first pixel voltage corresponding to a charge generated by the photodiode while the light source 30 is operating, and can obtain a second digital pixel signal from a second pixel voltage corresponding to a charge generated by the photodiode while the light source 30 is not operating. The logic circuit 20 can generate image data by calculating the difference between the first digital pixel signal and the second digital pixel signal, and can eliminate the influence of ambient light other than the light output from the light source 30.

[0074] Fig. 9 2 are diagrams provided to describe operations of an image sensor according to example embodiments. Fig. 9 1A may be a diagram provided to illustrate the operation of the image sensor 1A including the light source 30. Referring together Figure 8 and Fig. 9 , the photodiodes of the plurality of pixels PX included in the pixel array 10 may be reset at the first reset time T RST1 For example, the row driver 21 may reset the photodiode by turning on a reset element included in the pixel PX to eliminate charges from the photodiode.

[0075] When the photodiodes are reset, the photodiodes included in the plurality of pixels PX may be exposed to light for the first exposure time T. EX1 During the first exposure time T EX1 During this time, the control logic 24 can operate the light source 30 by outputting the control signal CNT to the light source 30. EX1 Meanwhile, the photodiode may generate charges in response to light output from the light source 30 and reflected from an object, and ambient light other than the light output from the light source 30 .

[0076] The first output circuit included in each of the pixels PX may be used to detect the first exposure time T EX1 The first pixel voltage corresponding to the charge generated by the photodiode during the first exposure time T EX1 The time when the photodiode is exposed to light and the time when the first output circuit of each of the pixels PX samples the first pixel voltage corresponding to the charge generated by the photodiode may be included.

[0077] At the first exposure time T EX1 After the second reset time T RST2 During this period, the logic circuit 20 may reset the pixel PX included in the pixel array 10 again. When the pixel PX is reset to eliminate the charge from the photodiode, the logic circuit 20 may EX2 During the second exposure time T EX2 During this period, the light source 30 may not work. Therefore, during the second exposure time T EX2 During the exposure time T, the photodiode can generate charges in response to ambient light. The second output circuit included in each of the pixels PX can be used to generate charges in response to ambient light during the exposure time T. EX2 During this period, a second pixel voltage corresponding to the charge generated by the photodiode is sampled.

[0078] At the readout time T RO During the readout time T, the row driver 21 may scan a plurality of corresponding row lines. The readout circuit 22 may perform a readout operation for each of the pixels PX according to the order in which the row driver 21 scans the plurality of row lines. The readout circuit 22 may perform a readout operation for each of the pixels PX according to the order in which the row driver 21 scans the plurality of row lines. RO During this process, the first pixel voltage and the second pixel voltage stored in each of the pixels PX are compared with the ramp voltage to obtain the first digital pixel signal and the second digital pixel signal.

[0079] Figures 10 to 12 is a diagram provided to illustrate the operation of an image sensor according to an example embodiment. Fig.10 and Fig.11 , the pixel 200 of the image sensor may include a photodiode PD, a pixel circuit 205, a first output circuit 210, a second output circuit 220, etc. The configuration and operation of the pixel circuit 205, the first output circuit 210, and the second output circuit 220 may be the same as those described above with reference to Figure 3 Similar to those described.

[0080] Fig.10 may be a diagram for describing the operation of the pixel 200 while a light source included in the image sensor operates, Fig.112 is a diagram showing the operation of the pixel 200 while the light source included in the image sensor is not operating. Fig.10 , Fig.11 and Fig.12 The operation of pixel 200 will be described.

[0081] Reference Fig.12 , in the operation of the pixel 200, first, the reset element RX and the transfer element TX may be turned on by the reset control signal RG and the transfer control signal TG, and the charges of the photodiode PD and the floating diffusion node FD may be eliminated. When the charges of the photodiode PD and the floating diffusion node FD are eliminated and the reset operation is completed, the first exposure time EIT1 may start. During the first exposure time EIT1, the photodiode PD is exposed to light to generate charges, and when the first exposure time EIT1 elapses, the transfer element TX is turned on, and the charges of the photodiode PD may be moved to the floating diffusion node FD.

[0082] When the transfer element TX is turned off, the first switch element SW1 is turned on by the first switch control signal SG1 within the first sampling time T1, and the first output circuit 210 can sample the first pixel voltage output from the driving element DX, such as Fig.10 As shown in . The first pixel voltage may be a voltage corresponding to the charge generated by the photodiode PD during the first exposure time EIT1. On the other hand, while the first output circuit 210 samples the first pixel voltage, the bias element BX is turned on to supply a bias current required for the operation of the driving element DX. As an example, the bias element BX may be turned on for a first storage time ST1 longer than the first sampling time T1.

[0083] Reference Fig.12 , the light source may be operated by the control signal CNT during the first exposure time EIT1. Therefore, the first pixel voltage sampled by the first output circuit during the first sampling time T1 may be a voltage corresponding to the charge generated by the photodiode PD in response to the light output from the light source and the ambient light. Fig.12 The example embodiment in exemplifies that the light source may be turned on even during the first storage time ST1 and the first sampling time T1 , but unlike this, the light source may be turned on only during the first exposure time EIT1 .

[0084] When the first sampling time T1 and the first storage time ST1 are terminated, the reset element RX and the transfer element TX are turned on again, and the floating diffusion node FD and the photodiode PD can be reset. The photodiode PD can be exposed to light to generate charges during the second exposure time EIT2 after the reset operation. Since the light source does not work during the second exposure time EIT2, the photodiode PD can generate charges only in response to ambient light during the second exposure time EIT2 without being affected by the light source.

[0085] When the second exposure time EIT2 elapses, the transfer element TX is turned on, the charge of the photodiode PD moves to the floating diffusion node FD, and the driving element DX can operate as a source follower amplifier through the turned-on bias element BX. In addition, during the second sampling time T2, the second switching element SW2 can be turned on, and the second output circuit 220 can sample the second pixel voltage, such as Fig.11 The second pixel voltage may be a voltage corresponding to charges generated by the photodiode PD that responds only to ambient light without being affected by the light source.

[0086] When the second sampling time T2 and the second storage time ST2 elapse, the first pixel voltage and the second pixel voltage may be read during the first readout time RT1. During the first readout time RT1, the readout circuit of the image sensor may compare the first pixel voltage output through the first column line COL1 with the ramp voltage RMP to obtain a first digital pixel signal. In addition, the readout circuit may obtain a second digital pixel signal by comparing the second pixel voltage output through the second column line COL2 with the ramp voltage RMP during the first readout time RT1.

[0087] When the first readout time RT1 elapses, the reset element RX is turned on to reset the floating diffusion node FD. In this case, the first switch element SW1 and the second switch element SW2 are turned on together with the reset element RX, and thus, the reset voltage can be sampled to the capacitors MC1 and VC1 of the first output circuit 110 and the capacitors MC2 and VC2 of the second output circuit 120. The readout circuit can obtain a digital reset signal by comparing the reset voltage output from the first output circuit 210 and the second output circuit 220 with the ramp voltage RMP during the second readout time RT2.

[0088] The readout circuit can calculate the difference between the digital reset signal and the first digital pixel signal to obtain the first digital signal, and can calculate the difference between the digital reset signal and the second digital pixel signal to obtain the second digital signal. The first pixel voltage reflects the light output from the light source and the influence of the ambient light, while the second pixel voltage only reflects the effect of the ambient light, so that the difference between the first digital signal and the second digital signal is calculated to eliminate the influence of the ambient light. Therefore, the image sensor can obtain accurate image data generated by the light output from the light source.

[0089] On the other hand, refer to Fig.12 , the first enabling element EX1 and the second enabling element EX2 can maintain the off state. By maintaining the first enabling element EX1 and the second enabling element EX2 in the off state, the capacitance of the first output circuit 210 and the second output circuit 220 can be reduced, and the stabilization time required for the sampling operation can be reduced. Therefore, regardless of the two exposure times EIT1 and EIT2, the function of eliminating ambient light can be implemented while significantly suppressing the reduction in the operating speed of the image sensor.

[0090] Fig.13 is a diagram provided to describe the operation of an image sensor according to example embodiments. Fig.13 In the example embodiment shown in , the image sensor can be operated in a global shutter method. At the first reset time T RST1 During this time, the reset element and the transfer element included in the pixel are turned on to eliminate the charge from the photodiode and the floating diffusion node in each of the pixels. Therefore, the voltage of the floating diffusion node can be completely reset.

[0091] At the first exposure time T EX1 During the first exposure time T, the pixels can be simultaneously exposed to light, and the photodiodes can react to the light to generate charge. The first output circuit included in each of the pixels can be connected to the first exposure time T. EX1 The first pixel voltage corresponding to the charge generated by the photodiode during the exposure time T is sampled. EX1 The charges generated by the photodiode during this time may be stored in a capacitor included in the first output circuit.

[0092] When the first exposure time T EX1 When the second reset time T elapses, the reset element and the transfer element included in the pixel are turned on again to eliminate the charge from the photodiode and the floating diffusion node in each of the pixels. RST2 During this time, the charges from the photodiode and floating diffusion nodes are eliminated.

[0093] At the second exposure time T EX2 During this period, the operation of the pixel can be with the first exposure time TEX1 The operation is similar to that of the second exposure time T EX2 Can be shorter than the first exposure time T EX1 The second output circuit of each pixel can be used to generate the EX2 During the first exposure time T, the second pixel voltage corresponding to the charge generated by the pixel is sampled. EX1 With the second exposure time T EX2 The first pixel voltage and the second pixel voltage may be different from each other by a difference therebetween.

[0094] For example, at the first exposure time T EX1 The charge generated by the photodiode during the second exposure time T EX2 The image sensor can read out the charge generated by the photodiode during the readout time T RO During the period, the first pixel voltage and the second pixel voltage are read from the corresponding pixel, and the first pixel voltage and the second pixel voltage can be used to generate image data. For example, by using the first pixel voltage and the second pixel voltage to generate one image data, the dynamic range of the image data can be improved.

[0095] The image sensor can also be respectively EX1 and the second exposure time T EX2 For example, each of the pixels has a conversion gain of 0.0407 W at a first exposure time T . EX1 The first conversion gain during the second exposure time T may be less than each of the pixels in the second exposure time T EX2 The second conversion gain during

[0096] exist Fig.13 In the example embodiment shown in FIG. 1 , since the first output circuit of each pixel samples the first pixel voltage and the second output circuit samples the second pixel voltage, the readout circuit of the image sensor samples the first pixel voltage at the readout time T RO During this period, the first pixel voltage and the second pixel voltage may be read first, and then the reset voltage may be read later. In order to read the reset voltage, the first pixel voltage and the second pixel voltage may be read, and then, a reset operation may be performed.

[0097] Figures 14 to 16 is a diagram provided to illustrate the operation of an image sensor according to an example embodiment. Fig.14 and Fig.15 , the pixel 300 of the image sensor may include a photodiode PD, a pixel circuit 305, a first output circuit 310, a second output circuit 320, etc. The configuration and operation of the first output circuit 310 and the second output circuit 320 may be the same as that of the reference Figure 3 Similar to those described.

[0098] On the other hand, refer to Fig.14 and Fig.15 In addition to the transfer element TX, the reset element RX and the drive element DX, the pixel circuit 305 may further include a conversion gain control element DCX. The conversion gain control element DCX is connected between the reset element RX and the floating diffusion node FD and may be controlled by a conversion gain control signal DCG. For example, when the conversion gain control element DCX is turned on, the capacitance of the floating diffusion node FD may be increased, and the conversion gain of the pixel circuit 305 may be reduced. Conversely, when the conversion gain control element DCX is turned off, the capacitance of the floating diffusion node FD may be reduced, and the conversion gain of the pixel circuit 305 may be increased.

[0099] Fig.14 may be a diagram for describing the operation of pixel 300 during a relatively long exposure time, and Fig.15 300 during a relatively short exposure time. Fig.16 The operation of pixel 300 is described.

[0100] Reference Fig.16 , in the operation of the pixel 300, first, the reset element RX and the transfer element TX may be turned on by the reset control signal RG and the transfer control signal TG, and the charges of the photodiode PD and the floating diffusion node FD may be eliminated. When the reset operation is completed, the first exposure time EIT1 may start. During the first exposure time EIT1, the photodiode PD is exposed to light to generate charges, and when the first exposure time EIT1 elapses, the transfer element TX is turned on, and the charges of the photodiode PD may be moved to the floating diffusion node FD. When the first exposure time EIT1 starts, the conversion gain control element DCX is turned on, so that the conversion gain of the pixel circuit 305 may be reduced.

[0101] When the first exposure time EIT1 elapses, the transfer element TX may be turned off, and the first switch element SW1 may be turned on by the first switch control signal SG1 during the first sampling time T1. Fig.14 As shown in , the first output circuit 310 can sample the first pixel voltage output from the driving element DX. The first pixel voltage can be a voltage corresponding to the charge generated by the photodiode PD during the first exposure time EIT1. During the first sampling time T1, the first enabling element EX1 is turned on so that the first secondary capacitor VC1 can be connected to the first switching element SW1.

[0102] On the other hand, while the first output circuit 310 samples the first pixel voltage, the bias element BX is turned on to supply a bias current required for the operation of the driving element DX. As an example, the bias element BX may be turned on for a first storage time ST1 that is longer than the first sampling time T1. At least a portion of the first storage time ST1 may overlap with the first exposure time EIT1.

[0103] When the first sampling time T1 and the first storage time ST1 are completed, the reset element RX and the transfer element TX are turned on again, and the floating diffusion node FD and the photodiode PD can be reset. After the reset operation, the photodiode PD can be exposed to light during the second exposure time EIT2 to generate charges. The second exposure time EIT2 can be shorter than the first exposure time EIT1, and the conversion gain control element DCX can be non-conductive during the second exposure time EIT2.

[0104] When the second exposure time EIT2 elapses, the transfer element TX is turned on, the charge of the photodiode PD moves to the floating diffusion node FD, and the driving element DX can operate as a source follower amplifier through the turned-on bias element BX. In addition, the second switching element SW2 is turned on during the second sampling time T2, and the second output circuit 320 can sample the second pixel voltage, such as Fig.15 The second pixel voltage may be a voltage corresponding to charges generated by the photodiode PD during a second exposure time EIT2 shorter than the first exposure time EIT1.

[0105] When the second sampling time T2 and the second storage time ST2 elapse, the readout circuit of the image sensor can read the first pixel voltage and the second pixel voltage during the first readout time RT1. During the first readout time RT1, the readout circuit of the image sensor compares each of the first pixel voltage and the second pixel voltage with the ramp voltage RMP to obtain the first digital pixel signal and the second digital pixel signal.

[0106] When the first readout time RT1 elapses, the reset element RX is turned on to reset the floating diffusion node FD. At this time, the first switch element SW1 and the second switch element SW2 may be turned on together with the reset element RX, so that the reset voltage is sampled to the first output circuit 310 and the second output circuit 320. The readout circuit may obtain a digital reset signal by comparing the reset voltage outputted from the first output circuit 310 and the second output circuit 320 with the ramp voltage RMP during the second readout time RT2.

[0107] In reference Figures 14 to 16In the described example embodiment, the logic circuit of the image sensor may set a first exposure time EIT1 and a second exposure time EIT2 shorter than the first exposure time EIT1 during one frame period. The logic circuit may connect the first output circuit 310 to the pixel circuit 305 between the first exposure time EIT1 and the second exposure time EIT2, and may connect the second output circuit 320 to the pixel circuit 305 after the second exposure time EIT2. Therefore, the logic circuit may acquire the first digital pixel signal, the second digital pixel signal, and the digital reset signal during one frame period.

[0108] The logic circuit of the image sensor may calculate the difference between the digital reset signal and the first digital pixel signal to obtain the first digital signal, and may calculate the difference between the digital reset signal and the second digital pixel signal to obtain the second digital signal. The first digital signal may correspond to a relatively long first exposure time EIT1, and the second digital signal may correspond to a relatively short second exposure time EIT2. In addition, the first digital signal may be a signal generated under a relatively lower conversion gain condition than the second digital signal. By generating image data using the first digital signal and the second digital signal, the dynamic range of the image data may be improved.

[0109] Fig.17 is a diagram illustrating a portion of a pixel included in an image sensor according to example embodiments. Fig.17 , the image sensor 400 may include a semiconductor substrate 401, a photodiode 403 and an element 410 formed in the semiconductor substrate 401, metal wirings 411 and 412 connected to the element 410, an insulating layer 420 filling the element 410 and the metal wirings 411 and 412, etc. The semiconductor substrate 401 may be a substrate including a semiconductor material such as silicon, and the photodiode 403 may be formed in the semiconductor substrate 401. For example, the photodiode 403 may be formed by a process of implanting impurities into the semiconductor substrate 401, and the photodiode 403 may be connected to at least one of the elements 410.

[0110] The light-transmitting layer 405 and the microlens 407 may be formed on one surface of the semiconductor substrate 401. The light-transmitting layer 405 may include a color filter that selectively transmits light of a specific wavelength band. According to example embodiments, in at least some of the pixels disposed in different positions in the image sensor 400, the microlens 407 may be formed to have different radii of curvature. Therefore, in at least some of the pixels, the upper surface of the microlens 407 may be located at different heights.

[0111] Element 410 can provide a pixel circuit, a first output circuit, and a second output circuit. For example, element 410 may include a transfer element, a reset element, a drive element, a switch element, a selection element, an enable element, etc. Element 410 is connected to photodiode 403, and may also be connected to capacitor 413 buried in insulating layer 420 through metal wiring 411 and 412. As an example, capacitor 413 may be connected to the switch element and the enable element among element 410, and the primary capacitor among capacitor 413 may be connected to the wiring for supplying power supply voltage among metal wiring 411 and 412.

[0112] The manufacturing process of the capacitor 413 may include a process of forming a dielectric film. In order to improve the leakage characteristics of the capacitor 413, the process of forming the dielectric film may be performed at a relatively high temperature. In an example embodiment, the lower wiring 411 formed before forming the capacitor 413 may be formed of tungsten so that the dielectric film may be formed at a high temperature. On the other hand, the upper wiring 412 formed later than the formation of the capacitor 413 may be formed of copper or the like, which is only an example embodiment, and therefore, the lower wiring 411 and the upper wiring 412 may be formed of the same material.

[0113] Fig.18 and Fig.19 Schematically illustrates an image sensor according to an example embodiment. Fig.18 , an image sensor 500 according to an example embodiment may include a first layer 510 and a second layer 520. The first layer 510 and the second layer 520 may be stacked in a vertical direction. The first layer 510 may include a pixel array 511, and the second layer 520 may include logic circuits 521 and 522. The pixel array 511 includes a plurality of pixels, and the plurality of pixels may be connected to the logic circuit 521 through a plurality of row lines and a plurality of column lines. Fig.18 In the example embodiment shown in FIG. 5 , each of the pixels in the pixel array 511 disposed in the first layer 510 may include a pixel circuit, a first output circuit, and a second output circuit. Thus, each of the pixels may have the same configuration as described above with reference to FIG. Fig.17 The structure of the pixel in the described example embodiment is similar to the structure.

[0114] The logic circuits 521 and 522 may include a first logic circuit 521 and a second logic circuit 522. The first logic circuit 521 may include a row driver, a readout circuit, a column driver, and control logic necessary to drive the pixel array 511. The second logic circuit 522 may include a power circuit, an input / output interface, an image signal processor, etc. The areas occupied by the respective first logic circuits 521 and second logic circuits 522 and the arrangement forms may be modified variously.

[0115] Next, refer to Fig.19 , the image sensor 600 may include a first layer 610, a second layer 620, and a third layer 630 stacked sequentially. The first layer 610, the second layer 620, and the third layer 630 may be formed on different semiconductor substrates to be stacked on each other. The third layer 630 includes a first logic circuit 631 and a second logic circuit 632, and the configurations of the first logic circuit 631 and the second logic circuit 632 may be the same as those of the reference Fig.18 Similar to those described.

[0116] The first layer 610 may include a first pixel array 611, and the second layer 620 may include a second pixel array 621. The first pixel array 611 and the second pixel array 621 may be connected to each other to provide a plurality of pixels. As an example, each of the pixels may include a photodiode, a pixel circuit, a first output circuit, a second output circuit, etc., as in the other embodiments described above, and the photodiode and the pixel circuit may be provided in the first pixel array 611, and the first output circuit and the second output circuit may be provided in the second pixel array 621. The pixel circuit of the first pixel array 611 may be connected to the first output circuit and the second output circuit of the second pixel array 621 by a method such as Cu-Cu bonding.

[0117] The process of forming the capacitor included in the first output circuit and the second output circuit can be performed at a relatively high temperature to improve the leakage characteristics of the capacitor. Therefore, in the case where the pixel circuit, the first output circuit, and the second output circuit are all formed in one layer, the pixel circuit, the wiring pattern directly connected to the first output circuit, the second output circuit, and the pixel circuit can be required to be formed of tungsten.

[0118] At the same time, Fig.19 In the example embodiment shown in , since the processes of the pixel circuit, the first output circuit, and the second output circuit are separated from each other, the wiring patterns of the reset element, the transfer element, the drive element, etc. connected to the pixel circuit can be formed of copper or the like (whose melting point is lower than that of tungsten, but has excellent reflectivity and resistance properties). Since the wiring pattern formed of copper having relatively high reflectivity is disposed below the photodiode and the pixel circuit, the photoelectric conversion efficiency of the image sensor can be improved. In addition, according to the example embodiment, all elements included in the pixel circuit, the first output circuit, and the second output circuit can be formed in the first layer 610, and separately, the capacitor can be formed in the second layer 620. In this case, most of the metal wiring used to connect the elements and capacitors in the pixel circuit, the first output circuit, and the second output circuit can be formed of copper, and thus the resistance characteristics can be improved, which will be described below with reference to Fig. 20 and Fig.21 Describe in more detail.

[0119] Figure 20 to Figure 22 is a diagram showing some pixels included in an image sensor according to an example embodiment. Fig. 20 , the image sensor 700 according to example embodiments may include a first layer L1 and a second layer L2. According to example embodiments, a third layer on which a logic circuit is formed may be added to the second layer L2. Alternatively, the logic circuit may also be formed in the first layer L1 or the second layer L2 together with the pixel.

[0120] exist Fig. 20 In the example embodiment shown in , the first layer L1 may include a photodiode 703 and a pixel circuit among constituent elements of each of the pixels. Referring to the first layer L1, the photodiode 703 is formed in the first semiconductor substrate 701, and the light-transmitting layer 705 and the microlens 707 may be formed on one surface of the first semiconductor substrate 701. In addition, an element 710 included in the pixel circuit is formed on the first semiconductor substrate 701, and the element 710 and the metal wiring 711 connected to the element 710 may be buried in the insulating layer 720. The element 710 may provide a transfer element, a reset element, a drive element, a conversion gain control element, a floating diffusion node, etc.

[0121] The second layer L2 is disposed on the first layer L1, and may include a first output circuit and a second output circuit among constituent elements of each of the pixels. The second layer L2 may include an element 730 formed on the second semiconductor substrate 702 and included in the first output circuit or the second output circuit. The elements 730 are connected to each other through metal wiring 741, and the elements 730 and the metal wiring 741 may be buried in the insulating layer 750. At least a portion of the metal wiring 741 of the second layer L2 may be connected to at least a portion of the metal wiring 711 of the first layer L1 through a bonding pattern 760. In detail, the second layer L2 may be connected to the first layer L1 by a Cu-Cu bonding method or the like. For example, the bonding pattern 760 may be a node where the first switching element and the second switching element respectively included in the first output circuit and the second output circuit are connected to the driving element of the pixel circuit.

[0122] The second layer L2 may include a capacitor 755 buried in the insulating layer 750. The capacitor 755 is a component included in the first output circuit and the second output circuit; the capacitor 755 may be advantageously used to sample the pixel voltage and / or reset voltage generated by the pixel circuit of the first layer L1. For example, the capacitor 755 may include a primary capacitor and a secondary capacitor, the primary capacitor may be connected to the power node and the switching element, and the secondary capacitor may be connected to the enabling element and the switching element.

[0123] Next, refer to Fig.21, the image sensor 800 according to example embodiments may include a first layer L1 and a second layer L2. Hereinafter, the Fig. 20 Those similar or can refer to Fig. 20 Understand the description of the components. Fig.21 In the example embodiment shown in , only the capacitor 835 may be formed in the second layer L2, and the element 810 for setting the pixel circuit, the first output circuit, and the second output circuit may all be formed in the first layer L1 together with the photodiode 803. For example, the photodiode 803 and the element 810 included in the pixel circuit and the first output circuit and the second output circuit are formed in the first semiconductor substrate 801, and the metal wiring 811 and the insulating layer 820 may be formed. In this case, the bonding pattern 840 for connecting the capacitor 835 and the metal wiring 811 of the second layer L2 may be formed in the first layer L1.

[0124] In addition, the capacitor 835, the metal wiring 831, and the insulating layer 830 are formed on a second semiconductor substrate different from the first semiconductor substrate 801, and the bonding pattern 840 is connected to each other by Cu-Cu bonding, so that the first layer L1 and the second layer L2 can be attached to each other. When the first layer L1 and the second layer L2 are attached to each other, a partial area of ​​the first semiconductor substrate 801 is removed from the first layer L1 by a polishing process, etc., and the light-transmitting layer 805 and the microlens 807 can be formed. Alternatively, the second semiconductor substrate for forming the capacitor 835 can be removed by a polishing process, etc., and the insulating layer 830 can be exposed.

[0125] exist Fig.21 In the example embodiment shown in , a logic circuit for driving pixels and generating image data may be provided in at least one of the first layer L1 and the second layer L2. When at least a portion of the logic circuit is provided in the second layer L2, the second semiconductor substrate for forming the second layer L2 may not be removed by a polishing process or the like.

[0126] In addition, according to example embodiments, a logic circuit may be provided by a third layer L3 disposed on the second layer L2. Fig. 22 , the second semiconductor substrate for forming the second layer L2 of the image sensor 900 may be completely removed by a polishing process or the like, and the third layer L3 may be disposed on the second layer L2. The third layer L3 may include a third semiconductor substrate 902, an element 950 providing a logic circuit, a metal wiring 951, an insulating layer 960, and the like. In example embodiments, a portion of the metal wiring 951 of the third layer L3 may penetrate the insulating layer 930 of the second layer L2, and may be connected to at least one of the metal wirings 911 of the first layer L1 through a vertical via hole disposed on the outside of the pixel.

[0127] Fig.23 and Fig.24 Schematically illustrates an electronic device including an image sensor according to an example embodiment. Fig.23 , the electronic device 1000 may include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400. The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Although the accompanying drawings show example embodiments in which three camera modules 1100a, 1100b, and 1100c are provided, the example embodiments are not limited thereto. In some embodiments, the camera module group 1100 may be modified to include only two camera modules. In addition, in some embodiments, the camera module group 1100 may be modified and implemented to include n (where n is a natural number of 4 or greater) camera modules. In addition, in an example embodiment, at least one of the plurality of camera modules 1100a, 1100b, and 1100c included in the camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c according to the above reference. Figures 1 to 22 An image sensor in accordance with one of the example embodiments is described.

[0128] In the following, reference will be made to Fig.24 The detailed configuration of the camera module 1100b is described in more detail, but the following description may be equally applied to other camera modules 1100a and 1100c according to example embodiments. Fig.24 , the camera module 1100b includes a prism 1105, an optical path folding element (hereinafter referred to as “OPFE”) 1110, an actuator 1130, an image sensing device 1140 and a storage 1150.

[0129] The prism 1105 may include a reflective surface 1107 of a light-reflective material to change the path of light L incident from the outside thereof. In some embodiments, the prism 1105 may change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 rotates the reflective surface 1107 of the light-reflective material around the central axis 1106 in the A direction, or rotates the central axis 1106 in the B direction, to change the path of light L incident in the first direction X to the second direction Y as a vertical direction. In this case, the OPFE 1110 may also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0130] In some embodiments, as shown, the maximum rotation angle of the prism 1105 in the A direction may be equal to or less than 15 degrees in the positive (+) A direction, and may be greater than 15 degrees in the negative (-) A direction, but the embodiment is not limited thereto. In some embodiments, the prism 1105 may move between 20 degrees in the positive (+) B direction or the negative (-) B direction, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees. In this case, the prism 1105 may move at the same angle in the positive (+) B direction or the negative (-) B direction, or may move at almost similar angles within a range of about 1 degree.

[0131] In some embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0132] The OPFE 1110 may include, for example, an optical lens group including m (where m is a natural number) optical lenses. The m lenses may be moved in the second direction Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, by moving the m optical lenses included in the OPFE 1110, the optical zoom ratio of the camera module 1100b may be changed to 3Z, 5Z, or an optical zoom ratio greater than 5Z.

[0133] The actuator 1130 may move the OPFE 1110 or the optical lens (hereinafter, referred to as the optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0134] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b by a control signal provided via a control signal line CSLb.

[0135] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 may include information necessary for the camera module 1100b to generate image data using the light L provided from the outside thereof. The calibration data 1147 may include, for example, information about the above-mentioned rotation degree, information about the focal length, information about the optical axis, etc. When the camera module 1100b is implemented in the form of a multi-state camera whose focal length changes based on the position of the optical lens, the calibration data 1147 may include focal length values ​​for each position (each state) of the optical lens and information related to autofocus.

[0136] The storage 1150 may store image data sensed by the image sensor 1142. The storage 1150 may be provided outside the image sensing device 1140, and may be implemented in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the storage 1150 may be implemented as an electrically erasable programmable read-only memory (EEPROM), but the embodiment is not limited thereto.

[0137] Refer to Fig.23 and Fig.24 , in some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include calibration data 1147 that is the same as or different from each other based on the operation of the actuator 1130 included therein. In some other embodiments, one camera module (e.g., 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a and 1100c) may be vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiment is not limited thereto.

[0138] In an additional embodiment, one camera module (e.g., 1100c) among the plurality of camera modules 1100a, 1100b, and 1100c may be, for example, a vertical type depth camera for extracting depth information using infrared (IR) rays. In this case, the application processor 1200 combines the image data provided from the depth camera with the image data provided from another camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0139] In yet another embodiment, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. In this case, for example, optical lenses of at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but the configuration is not limited thereto.

[0140] In addition, in some embodiments, the fields of view of the multiple camera modules 1100a, 1100b, and 1100c may be different. In this case, the optical lenses included in each of the multiple camera modules 1100a, 1100b, and 1100c may also be different from each other, but the configuration is not limited thereto. In addition, the multiple camera modules 1100a, 1100b, and 1100c may be physically separated from each other and set. For example, the sensing area of ​​one image sensor 1142 is not divided and used by the multiple camera modules 1100a, 1100b, and 1100c, but an independent image sensor 1142 may be set inside each of the multiple camera modules 1100a, 1100b, and 1100c.

[0141] Return to reference Fig.23 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented by being separated from each other as separate semiconductor chips.

[0142] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c, an image generator 1214, and a camera module controller 1216. The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, and 1212c corresponding to the number of the plurality of camera modules 1100a, 1100b, and 1100c.

[0143] The image data generated from the camera modules 1100a, 1100b, and 1100c, respectively, may be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c through image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated from the camera module 1100a may be provided to the sub-image processor 1212a through the image signal line ISLa, the image data generated from the camera module 1100b may be provided to the sub-image processor 1212b through the image signal line ISLb, and the image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but the embodiment is not limited thereto.

[0144] On the other hand, in some embodiments, one sub-image processor may be provided to correspond to a plurality of camera modules. For example, the sub-image processor 1212a and the sub-image processor 1212c are implemented as opposed to being separately implemented from each other as shown, but are implemented by being integrated into one sub-image processor, and image data provided from the camera module 1100a and the camera module 1100c may be selected by a selection element (e.g., a multiplexer) or the like, and then the image data may be provided to the integrated sub-image processor.

[0145] The image data provided to the corresponding sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using the image data provided from the corresponding sub-image processors 1212a, 1212b, and 1212c according to the image generation information or the mode signal. Specifically, the image generator 1214 may merge at least some of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal to generate an output image. In addition, the image generator 1214 may generate an output image by selecting any one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different fields of view according to the image generation information or the mode signal.

[0146] In some embodiments, the image generation information may include a zoom signal or a zoom factor. In addition, in some embodiments, the mode signal may be, for example, a signal based on a mode selected from a user. And, when the image generation information is a zoom signal (zoom factor), and the camera modules 1100a, 1100b, and 1100c have different fields of view, the image generator 1214 may operate differently according to the type of the zoom signal. For example, when the zoom signal is a first signal; after merging the image data output from the camera module 1100a and the image data output from the camera module 1100c, the merged image signal may be used to generate an output image, and the image data output from the camera module 1100b is not used for merging. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, and any one of the image data output from the respective camera modules 1100a, 1100b, and 1100c may be selected to create an output image. However, the embodiment is not limited thereto, and the method for processing image data may be modified and implemented as needed.

[0147] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b and 1212c, and performs high dynamic range (HDR) processing on the multiple image data to generate merged image data with an increased dynamic range.

[0148] The camera module controller 1216 may provide control signals to the respective camera modules 1100a, 1100b, and 1100c. The control signals generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other.

[0149] Any one of the plurality of camera modules 1100a, 1100b, and 1100c may be designated as a master camera (e.g., 1100b) according to a mode signal or image generation information including a zoom signal, and the remaining camera modules (e.g., 1100a and 1100c) may be designated as slave cameras. Such information may be included in the control signal and may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through control signal lines CSLa, CSLb, and CSLc separated from each other.

[0150] The camera module operating as the main camera and the slave camera can be changed according to the zoom factor or mode signal. For example, when the field of view of the camera module 1100a is wider than the field of view of the camera module 1100b and indicates a zoom ratio with a relatively low zoom factor, the camera module 1100b can be operated as the main camera and the camera module 1100a is the slave camera. On the contrary, when the zoom factor indicates a high zoom ratio, the camera module 1100a can be operated as the main camera and the camera module 1100b can be operated as the slave camera.

[0151] In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may send a synchronization enable signal to the camera module 1100b. The camera module 1100b having received such a synchronization enable signal generates a synchronization signal based on the received synchronization enable signal, and may send the generated synchronization signal to the camera modules 1100a and 1100c via the synchronization signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may be synchronized using the synchronization signal to send image data to the application processor 1200.

[0152] In some embodiments, the control signal provided from the camera module controller 1216 to the plurality of camera modules 1100a, 1100b and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b and 1100c may operate in the first operation mode and the second operation mode with respect to the sensing speed.

[0153] In the first operation mode, the plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a first rate (e.g., generate image signals at a first frame rate), may encode the generated image signals at a second rate higher than the first rate (e.g., encode image signals having a second frame rate higher than the first frame rate), and may transmit the encoded image signals to the application processor 1200. In this case, the second rate may be 30 times or less than 30 times the first rate.

[0154] The application processor 1200 stores the received image signal (e.g., the encoded image signal) in the internal memory 1230 provided therein and the external memory 1400 provided outside the application processor 1200, and then reads the encoded image signal from the internal memory 1230 or the external memory 1400 and decodes the signal, and can display image data generated based on the decoded image signal. For example, the corresponding sub-image processors among the plurality of sub-image processors 1212a, 1212b, and 1212c in the image processing device 1210 can perform decoding, but can also perform image processing on the decoded image signal.

[0155] The plurality of camera modules 1100a, 1100b, and 1100c may generate image signals at a third rate lower than the first rate (e.g., generate image signals having a third frame rate lower than the first frame rate) in the second operation mode, and may transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be uncoded signals. The application processor 1200 may perform image processing on the received image signals, or may store the image signals in the internal memory 1230 or the external memory 1400.

[0156] The PMIC 1300 may supply power such as a power supply voltage to a plurality of corresponding camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a through a power signal line PSLa, supplies a second power to the camera module 1100b through a power signal line PSLb, and supplies a third power to the camera module 1100c through a power signal line PSLc.

[0157] The PMIC 1300 may generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and may also adjust the power level. The power control signal PCON may include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, and in this case, the power control signal PCON may include information about the camera module operating in the low power mode and at a set power level. The levels of power provided to the plurality of corresponding camera modules 1100a, 1100b, and 1100c may be the same or different from each other. In addition, the level of power may be changed dynamically.

[0158] As explained above, according to example embodiments, pixels are simultaneously exposed to light during an exposure time, and charges generated during the exposure time may be stored in a capacitor of each of the pixels. By adjusting the capacitance of the capacitor according to a shooting environment (such as the intensity of light incident to the image sensor or the intensity of an infrared light source operating in conjunction with the image sensor, the intensity of ambient light, etc.), the noise characteristics and operating speed of the image sensor and the quality of the resulting image output by the image sensor may be improved.

[0159] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. An image sensor, include: A plurality of pixels, each comprising: a photodiode configured to generate charge in response to light incident on the image sensor; a pixel circuit including a transfer element and a drive element, wherein the transfer element is electrically connected between the photodiode and a floating diffusion node accumulating the charges, and the drive element is electrically connected to the floating diffusion node; a first output circuit electrically connected between a first column line and the pixel circuit, the first output circuit comprising: a first switch element electrically connected to an output terminal of the driving element; a first primary capacitor electrically connected to the first switch element; a first secondary capacitor electrically connected to or disconnected from the first switch element based on an on / off switching state of a first enabling element; and a first selection element electrically connected between the first switch element and the first column line; and A second output circuit is electrically connected between the second column line and the pixel circuit, and the second output circuit includes: a second switching element, which is electrically connected to the output terminal of the driving element; a second primary capacitor, which is electrically connected to the second switching element; a second secondary capacitor, which is electrically connected to the second switching element or disconnected from the second switching element based on the on / off switching state of the second enabling element; and a second selection element, which is electrically connected between the second switching element and the second column line.

2. The image sensor according to claim 1, in, The capacitance of the first primary capacitor is smaller than the capacitance of the first secondary capacitor, and the capacitance of the second primary capacitor is smaller than the capacitance of the second secondary capacitor. 3 . The image sensor according to claim 1 , further comprising a first analog-to-digital converter and a second analog-to-digital converter, the first analog-to-digital converter being electrically coupled to the first column line and the second analog-to-digital converter being electrically coupled to the second column line.

4. The image sensor according to claim 1, in, The pixel circuit further includes: a reset element electrically connected between a power node and the floating diffusion node; and a bias element configured to supply a bias current to the drive element.

5. The image sensor according to claim 1, in, The first output circuit also includes a first output drive element, which is electrically connected between the first switch element and the first selection element; and wherein the second output circuit also includes a second output drive element, which is electrically connected between the second switch element and the second selection element.

6. The image sensor according to claim 1, further comprising: include: a logic circuit configured to: (i) drive the plurality of pixels to obtain image data therefrom; and (ii) exposing the plurality of pixels to light simultaneously during an exposure time, obtaining a reset voltage through the first column line, and obtaining a pixel voltage through the second column line.

7. The image sensor according to claim 6, in, The logic circuit is configured to: (i) turn on the first enabling element and the second enabling element when the intensity of the light is less than a predetermined reference intensity; and (ii) when the intensity of the light is greater than the reference intensity, turning off the first enabling element and the second enabling element.

8. The image sensor according to claim 6, in, The logic circuit is configured to: (i) obtain a predetermined reference voltage through each of the first column line and the second column line after obtaining the reset voltage and the pixel voltage; and (ii) generating the image data based on a difference between the reference voltage and the reset voltage and a difference between the reference voltage and the pixel voltage.

9. The image sensor according to claim 6, in, the logic circuit samples a first pixel voltage corresponding to the charge generated by the photodiode during a first exposure time to the first primary capacitor and the first secondary capacitor in each of the plurality of pixels, and samples a second pixel voltage corresponding to the charge generated by the photodiode during a second exposure time to the second primary capacitor in each of the plurality of pixels; wherein the second exposure time is shorter than the first exposure time; and Wherein, after the first exposure time, the logic circuit generates the image data based on the first pixel voltage and the second pixel voltage.

10. The image sensor according to claim 6, further comprising: include: a light source configured to illuminate light onto an object, the object reflecting the light to the plurality of pixels; Wherein, the logic circuit is configured to: (i) store the charge generated by the photodiode in each of the multiple pixels during a first exposure time when the light source is turned on in the first primary capacitor; (ii) store the charge generated by the photodiode in each of the multiple pixels during a second exposure time when the light source is turned off after the first exposure time in the second primary capacitor; and (iii) generate the image data based on a first pixel voltage and a second pixel voltage, wherein the first pixel voltage corresponds to the charge generated by the photodiode during the first exposure time, and the second pixel voltage corresponds to the charge generated by the photodiode during the second exposure time.

11. The image sensor according to claim 10, in, The logic circuit is configured to turn off the first enabling element and the second enabling element during the first exposure time and the second exposure time.

12. The image sensor according to claim 1, further comprising: include: A first semiconductor substrate, the photodiode and the pixel circuit are arranged on the first semiconductor substrate; as well as A second semiconductor substrate, the first output circuit and the second output circuit are disposed on the second semiconductor substrate, and the second semiconductor substrate is stacked with the first semiconductor substrate.

13. An image sensor, include: A pixel array having a plurality of pixels; as well as a logic circuit configured to drive the pixel array so as to obtain image data from the pixel array, Wherein, each of the plurality of pixels comprises: a photodiode configured to generate charge in response to light; a transfer element electrically connected between the photodiode and a floating diffusion node that accumulates charges generated by the photodiode; a driving element electrically connected to the floating diffusion node, the driving element being configured to generate an output voltage by amplifying a voltage of the floating diffusion node; a first output circuit electrically connected between a first column line and the driving element, the first output circuit comprising a first switching element, a first capacitor electrically connected to the first switching element, and a first selection element electrically connected between the first capacitor and the first column line; and a second output circuit electrically connected between a second column line and the driving element, the second output circuit comprising a second switching element, a second capacitor electrically connected to the second switching element, and a second selection element electrically connected between the second capacitor and the second column line; and The logic circuit is configured to set the first capacitor to have a first capacitance when the intensity of the light is a first intensity, and to set the first capacitor to have a second capacitance less than the first capacitance when the intensity of the light is a second intensity greater than the first intensity.

14. The image sensor according to claim 13, in, When the intensity of the light is the first intensity, the logic circuit sets the second capacitor to have a third capacitance, and when the intensity of the light is the second intensity, the logic circuit sets the second capacitor to have a fourth capacitance smaller than the third capacitance.

15. The image sensor according to claim 13, in, The first capacitor includes: a first primary capacitor; a first secondary capacitor having a capacitance smaller than that of the first primary capacitor; and a first enabling element electrically connected between the first primary capacitor and the first secondary capacitor.

16. The image sensor according to claim 13, in, The logic circuit includes a first analog-to-digital converter and a second analog-to-digital converter, the first analog-to-digital converter is electrically connected to the first column line, the second analog-to-digital converter is electrically connected to the second column line, and the logic circuit is configured to obtain the image data based on a difference between a first digital signal output from the first analog-to-digital converter and a second digital signal output from the second analog-to-digital converter.

17. An image sensor, include: A pixel array having a plurality of pixels; as well as a logic circuit configured to expose the plurality of pixels to light for an exposure time and obtain image data from the pixel array; Each of the plurality of pixels comprises: (i) a photodiode; (ii) a pixel circuit connected to the photodiode and configured to generate a reset voltage and a pixel voltage; (iii) a first output circuit comprising a first capacitor for storing the reset voltage and connected between a first column line and the pixel circuit; and (iv) a second output circuit comprising a second capacitor for storing the pixel voltage and connected between a second column line and the pixel circuit; and Wherein the logic circuit is configured to adjust the capacitance of each of the first capacitor and the second capacitor based on the duration of the exposure time.

18. The image sensor according to claim 17, in, When the exposure time is longer than a predetermined reference time, the logic circuit sets the capacitance of the first capacitor to a first capacitance, and when the exposure time is shorter than the predetermined reference time, the logic circuit sets the capacitance of the first capacitor to a second capacitance smaller than the first capacitance.

19. The image sensor according to claim 18, in, When the exposure time is longer than the predetermined reference time, the logic circuit sets the capacitance of the second capacitor to a third capacitance, and when the exposure time is shorter than the predetermined reference time, the logic circuit sets the capacitance of the second capacitor to a fourth capacitance that is smaller than the third capacitance.

20. The image sensor according to claim 17, in, During a frame period in which the logic circuit obtains the image data from the multiple pixels, the exposure time includes a first exposure time and a second exposure time that is shorter than the first exposure time; and wherein the logic circuit is configured to connect the first output circuit to the pixel circuit between the first exposure time and the second exposure time, and to connect the second output circuit to the pixel circuit after the second exposure time.

Images