III- nitride device integration design

Abstract

A semiconductor device includes a III-N device and a field effect transistor (FET). The III-N device includes a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on an opposite side of the III-N material structure from the substrate. The FET includes a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source is on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET directly contacts and is electrically connected to the first source of the III-N device, and a via is formed through a portion of the III-N material structure that exposes a portion of a top surface of the substrate, and the first gate is electrically connected to the substrate via the via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application Serial No. 62 / 821,946, filed on March 21, 2019. Technical Field

[0003] The disclosed technology relates to semiconductor electronic devices designed to achieve increased performance and reliability. Background Art

[0004] Currently, typical power semiconductor devices (including devices such as transistors, diodes, power MOSFETs, and insulated-gate bipolar transistors (IGBTs)) are manufactured using silicon (Si) semiconductor materials. In recent years, wide-bandgap materials (SiC, III-N, III-O, and diamond) have been considered for use in power devices due to their excellent properties. III-nitride or III-N semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates, capable of carrying large amounts of current, supporting high voltages, and offering extremely low on-resistance with fast switching times.

[0005] Most conventional III-N high electron mobility transistors (HEMTs) and related transistor devices are normally conductive (i.e., have a negative threshold voltage), meaning they can conduct current at zero gate voltage. These devices with a negative threshold voltage are referred to as depletion mode (D-type) devices. In power electronics, normally-off devices (i.e., devices with a positive threshold voltage) that do not conduct significant current at zero gate voltage are preferred to avoid damage to the device or other circuit components by preventing the device from accidentally turning on. Normally-off devices are often referred to as enhancement mode (E-type) devices.

[0006] Reliable fabrication and production of high voltage III-N E-type transistors has therefore proven to be extremely challenging. An alternative to a single high voltage E-type transistor is to combine a high voltage D-type III-N transistor with a low voltage E-type transistor (e.g. Figure 1 To form a hybrid device, a single high-voltage E-mode III-N transistor can be combined with a low-voltage silicon FET in a cascode circuit configuration as shown in the schematic diagram of FIG. 5 to form a hybrid device that can operate in the same manner as a single high-voltage E-mode III-N transistor and, in many cases, achieve the same or similar output characteristics as a single high-voltage E-mode III-N transistor. Figure 1The hybrid device includes a high-voltage D-mode III-N transistor 23 and a low-voltage E-mode transistor 22, each optionally housed in a single package 10, the package including a source lead 11, a gate lead 12, and a drain lead 13. A source electrode 31 of the low-voltage E-mode transistor 22 and a gate electrode 35 of the high-voltage D-mode III-N transistor 23 are electrically connected to the source lead 11. The gate electrode 32 of the low-voltage E-mode transistor 22 is electrically connected to the gate lead 12. A drain electrode 36 of the high-voltage D-mode III-N transistor 23 is electrically connected to the drain lead 13. A source electrode 34 of the high-voltage D-mode III-N transistor 23 is electrically connected to the drain electrode 33 of the low-voltage E-mode transistor 22. The low-voltage E-mode transistor 22 includes an intrinsic body diode 37 antiparallel to the channel of the transistor 22. Summary of the Invention

[0007] This article describes an integrated III-N device design in which a low-voltage enhancement-mode device and a high-voltage depletion-mode III-N device are integrated into a single electronic component package to form a hybrid device that can operate in the same manner and / or have the same output characteristics as a single high-voltage E-mode III-N transistor. The term device will be used generically for any transistor, switch, or diode unless a distinction is necessary.

[0008] In a first aspect, a semiconductor device is described. The semiconductor device includes a III-N device and a field effect transistor (FET). The III-N device includes a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET includes a second semiconductor material structure, a second gate, a second source, and a second drain, with the second source being on a side of the second semiconductor material structure opposite the second drain. The second drain of the FET directly contacts and is electrically connected to the first source of the III-N device, a via is formed through a portion of the III-N material structure that exposes a portion of a top surface of the substrate, and the first gate is at least partially formed in the via and is electrically connected to the substrate.

[0009] In a second aspect, an electronic component is described. The electronic component includes an enhancement-mode transistor. The electronic component also includes a depletion-mode transistor. The depletion-mode transistor includes a substrate. The electronic component also includes a package. The package includes a conductive structural package base, and the package encloses both the enhancement-mode transistor and the depletion-mode transistor. A drain electrode of the depletion-mode transistor is electrically connected to a drain lead of the package, a gate electrode of the enhancement-mode transistor is electrically connected to a gate lead of the package, and a source electrode of the enhancement-mode transistor is electrically connected to the conductive structural package base, wherein the gate electrode of the depletion-mode transistor is directly in contact with and electrically connected to the conductive substrate, the conductive substrate is directly in contact with and electrically connected to the conductive structural package base, and the conductive structural package base is electrically connected to the source lead of the package.

[0010] In a third aspect, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch connected to a high voltage node, a low-side switch connected to a ground node, and an inductor connected to a node between the high-side switch and the low-side switch. The low-side switch includes a low-voltage enhancement-mode transistor and a high-voltage depletion-mode transistor. The half-bridge circuit is configured such that, in a first operating mode, when the high-side switch is biased on and the low-side switch is biased off, current flows in a first direction through the high-side switch and through the inductor. In a second operating mode, when the high-side switch is biased off and the low-side switch is biased off, current flows in a second direction through the low-side switch and through the inductor. In a third operating mode, when the high-side switch is biased off and the low-side switch is biased off, current flows in a second direction through the low-side switch and through the inductor, wherein during the second operating mode, a reverse DC current through the low-side switch is greater than 50 A, and wherein during the third operating mode, the on-resistance of the III-N depletion-mode transistor increases by less than 5%.

[0011] In a fourth aspect, an electronic component enclosed in a package is described. The electronic component includes a hybrid III-N device. The hybrid III-N device includes a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a stacked configuration. The packaged electronic component is capable of blocking 600 V in the forward direction when the gate of the electronic component is biased off, and is capable of withstanding a current greater than 50 A in the reverse direction. After withstanding the current in the reverse direction when the gate of the electronic component is biased off, the electronic component has a resistance of less than 5% when the gate is biased on.

[0012] Each of the devices and transistors described herein may include one or more of the following features: The substrate may have a hole concentration greater than 1 x 10 19 holes / cm 3The III-N buffer layer may be p-type doped. The substrate may be electrically coupled to circuit ground. The III-N buffer layer may have a thickness greater than 4 μm and be capable of blocking greater than 600 V. The drain of the FET may be electrically connected to the source of the III-N device via solder, solder paste, or conductive epoxy. The gate electrode metal may include Ti / Al or Ni / Au. The III-N material structure may be oriented in a Ga polar orientation or an N polar orientation. The drain electrode of the enhancement mode transistor is directly in contact with and electrically connected to the source electrode of the depletion mode transistor. The source electrode of the enhancement mode transistor is coupled to the gate electrode of the depletion mode transistor through a conductive substrate. The enhancement mode transistor has a lower breakdown voltage than the depletion mode transistor. The gate electrode of the III-N depletion mode transistor may be electrically connected to the silicon substrate. The silicon substrate may be directly in contact with and electrically connected to the conductive structural packaging substrate, and the structural packaging substrate is configured to be connected to circuit ground. The enhancement mode transistor may be a silicon MOSFET.

[0013] As used herein, a "hybrid enhancement-mode electronic device or component," or simply a "hybrid device or component," is an electronic device or component formed from a depletion-mode transistor and an enhancement-mode transistor, wherein the depletion-mode transistor is capable of a higher operating and / or breakdown voltage than the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor having a breakdown and / or operating voltage as high as that of the depletion-mode transistor. That is, the hybrid enhancement-mode device or component includes at least three nodes having the following properties: When a first node (source node) and a second node (gate node) are maintained at the same voltage, the hybrid enhancement-mode device or component can block a positive high voltage (i.e., a voltage greater than the maximum voltage that the enhancement-mode transistor can block) applied to a third node (drain node) relative to the source node. When the gate node is maintained at a sufficiently positive voltage relative to the source node (i.e., greater than the threshold voltage of the enhancement-mode transistor), current passes from the source node to the drain node, or from the drain node to the source node when a sufficiently positive voltage is applied to the drain node relative to the source node. When the enhancement mode transistor is a low voltage device and the depletion mode transistor is a high voltage device, the hybrid component can operate similar to a single high voltage enhancement mode transistor. The breakdown and / or maximum operating voltage of the depletion mode transistor can be at least two times, at least three times, at least five times, at least ten times, or at least twenty times the breakdown and / or maximum operating voltage of the enhancement mode transistor.

[0014] As used herein, the term III-nitride or III-N materials, layers, devices, etc. are described according to the stoichiometric formula B w Al x In y Ga zN refers to materials or devices comprising compound semiconductor materials, where w+x+y+z is approximately 1, and 0≤w≤1, 0≤x≤1, 0≤y≤1, and 0≤z≤1. III-N materials, layers, or devices can be formed or prepared by growing directly on a suitable substrate (e.g., by metal organic chemical vapor deposition) or by growing on a suitable substrate that has been detached from the original substrate and bonded to another substrate.

[0015] As used herein, two or more contacts or other items (such as conductive channels or components) are said to be "electrically connected" if they are connected by a sufficiently conductive material to ensure that the electrical potential at each of the contacts or other items is intended to be the same (e.g., approximately the same) at all times under any bias conditions.

[0016] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a significant amount of current (such as a current 0.001 times greater than the operating current during regular conduction) from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component blocks the voltage applied across it, the total current through the transistor, device, or component will not be 0.001 times greater than the operating current during regular conduction. Devices with off-state currents greater than this value exhibit high losses and low efficiency and are generally unsuitable for many applications, particularly power switching applications.

[0017] As used herein, a "high voltage device" (e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS)) is an electronic device optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages (such as about 300 V or higher, about 600 V or higher, or about 1200 V or higher), and when the device is on, it has a sufficiently low on-resistance (R) for the application in which it is used. ON ), for example, it experiences sufficiently low conduction losses when a large amount of current is passed through the device. The high voltage device may be capable of blocking at least a voltage equal to the high voltage power supply or the maximum voltage in the circuit for which it is used. The high voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, the high voltage device may block voltages between 0V and at least V max All voltages between which V max is the maximum voltage that can be supplied by the circuit or power supply, and V max For example, it can be 300V, 600V, 1200V, 1700V, 2500V or other suitable blocking voltages required by the application. For bidirectional or four-quadrant switches, the blocking voltage can be any polarity less than a maximum value (±V max, such as ±300V or ±600V, ±1200V, etc.), and when the switch is on, the current can be in either direction.

[0018] As used herein, a "III-N device" is a device based on a III-N heterostructure. III-N devices can be designed to operate as transistors or switches in which the device's state is controlled by a gate terminal, or as two-terminal devices that block current flow in one direction and conduct current in the other direction without a gate terminal. III-N devices can be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., when the voltage on the gate relative to the source is less than the device threshold voltage), it is capable of supporting at least all source-drain voltages less than or equal to the high voltage in the application in which the device is used, which can be, for example, 100 V, 300 V, 600 V, 1200 V, 1700 V, 2500 V, or higher. When the high-voltage device is biased on (e.g., when the voltage on the gate relative to the source or an associated power terminal is greater than the device threshold voltage), it is capable of conducting significant current with a low turn-on voltage (i.e., a low voltage between the source and drain terminals or between the opposing power terminals). The maximum allowable on-state voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0019] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer relative to other layers. Thus, for example, a layer positioned above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Additionally, a layer positioned between two layers may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with the second layer. Furthermore, the relative position of one layer relative to other layers is provided assuming that operations are performed relative to a substrate, without regard to the substrate's absolute orientation.

[0020] In typical power switching applications using high-voltage switching transistors, the transistor spends most of its time in one of two states. In the first state, often referred to as the "on-state," the voltage at the gate electrode relative to the source electrode is higher than the transistor threshold voltage, and significant current flows through the transistor. In this state, the voltage difference between the source and drain is typically low, typically no more than a few volts, such as approximately 0.1-5 volts. In the second state, often referred to as the "off-state," the voltage at the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and no significant current (except for off-state leakage current) flows through the transistor. In this second state, the voltage between the source and drain can in any case be between approximately 0V and the value of the current high-voltage supply, which in some cases can be as high as 100V, 300V, 600V, 1200V, 1700V, or even higher, but can be less than the breakdown voltage of the transistor. In some applications, inductive elements in the circuit can cause the voltage between the source and drain to be even higher than the circuit high-voltage supply. In addition, there is a short time immediately after the gate is switched to on or off during which the transistor is in a transition mode between the two states described above. When the transistor is in the off state, it is referred to as a "blocking voltage" between the source and drain. As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a large amount of current (such as a current 0.001 times greater than the average operating current during regular on-state conduction) from flowing through the transistor, device, or component when a voltage is applied across the transistor, device, or component. In other words, when the transistor, device, or component blocks the voltage applied across it, the total current through the transistor, device, or component will not be greater than 0.001 times the average operating current during regular on-state conduction.

[0021] when Figure 1 When a hybrid enhancement-mode component is used in place of a conventional high-voltage E-type transistor, the hybrid device operates as follows. When the hybrid device is in the on-state, current flows through both the channel of the E-type transistor and the channel of the D-type transistor, and the voltage across each of the two transistors can be small, typically a few volts or less. When the hybrid device is in the off-state, the voltage blocked by the hybrid device is divided between the E-type transistor and the D-type transistor. The E-type transistor blocks approximately |V th,D |With V br,E The voltage between |V th,D | is the absolute value of the threshold voltage of the D-type transistor, and V br,E is the breakdown voltage of the E-type transistor. The remainder of the voltage across the hybrid device is blocked by the high voltage D-type transistor.

[0022] The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Additional features and variations may also be included in the implementation. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of electronic components in the prior art.

[0024] Figure 2A A cross-sectional view of a hybrid III-N device.

[0025] Figure 2B and Figure 2C They are Figure 2A Plan and cross-sectional views of a hybrid III-N device.

[0026] Figure 3 A perspective view of a packaged electronic component device.

[0027] Figure 4 A schematic diagram of an electronic component.

[0028] Figure 5A 、 Figure 5B and Figure 5C Schematic diagram showing the current path through a half-bridge buck converter circuit.

[0029] Figure 6A and Figure 6B Schematic diagram showing the current path through the low-side switch of a half-bridge buck converter during different operating modes.

[0030] Figure 7A 、 Figure 7B and Figure 7C Schematic diagram showing the current path through a half-bridge boost converter circuit.

[0031] Figure 8 A cross-sectional view of another configuration of a hybrid III-N device.

[0032] Figure 9 A cross-sectional view of another configuration of a hybrid III-N device.

[0033] Figure 10 A cross-sectional view of another configuration of a hybrid III-N device.

[0034] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0035] Described herein are hybrid enhancement-mode electronic components that include a depletion-mode transistor and an enhancement-mode transistor assembled into a single electronic component package. A depletion-mode transistor, which may be a high-voltage III-N device, and an enhancement-mode transistor, which may be a low-voltage silicon FET device, are arranged in a stacked circuit configuration to form a hybrid device that can operate in the same manner as a single high-voltage E-mode III-N transistor and, in many cases, achieve the same or similar output characteristics as a single high-voltage E-mode III-N transistor. The depletion-mode transistor has a larger breakdown voltage (e.g., at least three times larger) than the enhancement-mode transistor. The maximum voltage that can be blocked by the hybrid electronic component when in the off state is at least as large as the maximum blocking or breakdown voltage of the depletion-mode transistor. The hybrid electronic components described herein are configured to improve reliability and / or performance compared to conventional hybrid devices in a package while reducing the complexity and cost of the assembly process.

[0036] Figure 2A A cross-sectional view of an electronic device is shown that includes a low-voltage E-mode device 122 (e.g., a silicon FET device) electrically connected to a high-voltage D-mode III-N device 123 (e.g., a GaN HEMT device) to form a single high-voltage hybrid III-N device 100. The E-mode device 122 includes a semiconductor body layer 25, a FET source electrode 131 and a FET gate electrode 132 on a first side of the semiconductor body layer 25, and a FET drain electrode 133 on a side of the semiconductor body layer 25 opposite the FET source electrode 131.

[0037] Figure 2A The D-type III-N device 123 includes a III-N material structure 24 (e.g., a combination of GaN and AlGaN) grown on a suitable conductive substrate 14. The substrate 14 can be a conductive semiconductor such as silicon (e.g., p-type or n-type Si), GaN, or any other sufficiently conductive substrate. For example, the substrate can have a hole concentration greater than 1x10 19 holes / cm 3 The doping is p-type, or the substrate can have an electron concentration greater than 1x10 19 electrons / cm -3The substrate may have high thermal conductivity or low thermal conductivity. In the case of a low thermal conductivity substrate, the substrate may be thinned to improve heat dissipation. The substrate may have a lattice constant and / or thermal expansion coefficient that is similar to or different from the lattice constant and / or thermal expansion coefficient of any of the material layers of the III-N material structure 24. A back metal layer 42 (e.g., Ti / Ni / Ag) may be formed on the back side of the substrate opposite the III-N material structure 24. The back metal layer 42 may serve as a bonding layer that allows the substrate to be attached to a device package substrate (e.g., a lead frame) by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods, which achieves high-quality mechanical, thermal, and electrical connections from the device substrate 14 to the device package substrate.

[0038] The III-N material structure 24 may include a III-N buffer layer 15, such as GaN or AlGaN, grown over the substrate 14. The buffer layer 15 may be made insulating or substantially free of incidental n-type mobile carriers by including dislocations or point defects in the layer or by doping the layer with compensating elements such as Fe, C, and / or Mg. The buffer layer may have a substantially uniform composition throughout, or the composition may vary. For example, in some implementations, the buffer layer is compositionally graded, such as by grading the aluminum composition in the buffer layer (e.g., the substrate may be AlGaN). x G 1-x N, where x varies across the substrate). The thickness and composition of buffer layer 15 can be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the high-voltage power supply or the maximum voltage in the circuit in which it is used. For example, buffer layer 15 can be capable of blocking voltages greater than 600 V or greater than 900 V. Buffer layer 15 can have a thickness greater than 4 μm. For example, a III-N buffer layer can have a thickness between 5 μm and 8 μm.

[0039] The III-N material structure may further include a III-N channel layer 16 (e.g., GaN) above the III-N buffer layer 15, and a III-N barrier layer 17 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 16. The band gap of the III-N barrier layer 17 is larger than the band gap of the III-N channel layer 16. The III-N channel layer 16 has a different composition than the III-N barrier layer 17, and the thickness and composition of the III-N barrier layer 17 are selected so as to induce a two-dimensional electron gas (2DEG) channel 19 (caused by the ions) in the III-N channel layer 16 adjacent to the interface between the layers 17 and 16. Figure 2A (indicated by the dotted line in the figure).

[0040] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) in a reactor, or other techniques. The III-N material structure can be grown in a Group III polar (e.g., Ga polar) orientation, such as a [0 0 0 1] (C-plane) orientation, as shown in FIG. Figure 2A As shown in . That is, the source, gate, and drain contacts of the HEMT are formed above a III-N face (e.g., the [0 0 0 1] face) of the III-N material structure, which is typically on the side of the III-N material structure opposite the substrate on which the III-N layer is formed. Alternatively, the III-N HEMT can be formed on a III-N material structure grown in an N-polar (i.e., N-face) orientation, such as a [0 0 0-1] orientation (not shown). In this case, the source, gate, and drain contacts of the HEMT are formed above the N-face (e.g., the [0 0 0-1] face) of the III-N material structure. Here, the III-N material structure can include a III-N barrier layer above the III-N buffer layer, and a III-N channel layer 16 above the III-N barrier layer 17. The band gap of the III-N barrier layer 17 is larger than the band gap of the III-N channel layer 16, and the thickness and composition of the III-N barrier layer 17 are selected so as to induce a two-dimensional electron gas (2DEG) channel 19 in the III-N channel layer 16 adjacent to the interface between the III-N channel layer 16 and the III-N barrier layer 17. The N-polar III-N material has a polarization field with a direction opposite to that of the Group III polar III-N material, thereby enabling the implementation of III-N devices that cannot be manufactured using a Group III polar structure.

[0041] An insulating layer 18 (eg, a dielectric layer) is grown or deposited over the top surface of the III-N material structure. The insulator 18 may be formed of or include, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), SiO2, or a combination thereof. x N y 、Al 1- x Si x N, Al 1-x Si x O、Al 1-x Si xON or any other wide bandgap insulator. Although insulator 18 is shown as a single layer, it may alternatively be formed of several layers deposited during different processing steps to form a single combined insulating layer. Insulating layer 18 may be constant throughout or formed of various types of insulating materials, for example, the insulating layer may have a first portion formed of MOCVD SiN (e.g., SiN deposited by MOCVD) and a second portion formed of PECVD SiN (e.g., SiN deposited by PECVD).

[0042] Source and drain electrodes 134, 136 are formed on the side of device 100 opposite the substrate, such that device 100 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows through the device laterally between source 134 and drain 136). Source and drain electrodes 134, 136 make ohmic contacts and are electrically connected to the device 2DEG channel 19 formed in layer 16. Source and drain electrodes 134, 136 (e.g., source and drain contacts) can be formed from a metal stack. Recesses can be formed in III-N barrier layer 17 to provide improved ohmic contact of source and drain electrodes 134, 136 to the 2DEG channel 19. The metal stack can be Ti / Al / Ni / Au, Ti / Al, or other suitable metals. Source and drain contacts 134, 136 can be formed by metal evaporation and post-deposition annealing processes. Other ohmic contact processes may also be used, including sputtering and dry etching processes.

[0043] The device 100 also includes a gate electrode 135, such as a gate contact. The gate electrode 135 may be formed such that the insulating layer 18 is at least partially between the gate electrode and the III-N material structure 24, such as Figure 2A As shown in , or alternatively, the gate electrode 135 can be formed so that it contacts the III-N material structure 24 (not shown). The gate electrode 135 can be formed of a suitable conductive material, such as a metal stack, for example, titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au), and can be deposited by metal evaporation or sputtering or chemical vapor deposition or various atomic layer deposition (ALD) methods. The gate electrode 135 can alternatively be another conductive material or material stack, including one or more materials with a large work function, such as a semiconductor material with a large work function, such as p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride.

[0044] Gate electrode 135 is electrically connected to substrate 14 through a via 38 (eg, epi-via or TEV) formed through a portion of III-N material structure 24 that exposes a portion of the top surface of substrate 14. Figure 2AThe metal of the gate electrode 135 is at least partially formed in the through hole 38 so that the gate electrode 135 of the III-N device 23 is electrically connected to the substrate 14. Figure 2A The dashed area in FIG shows a through hole 38 passing through the 2DEG channel 19, but the through hole 38 is formed in a manner such that the 2DEG channel 19 is continuous between the source electrode 134 and the drain electrode 136 (for example, the through hole is formed in a region outside the active area of ​​the device), as shown in FIG. Figure 2B and Figure 2C Further shown in .

[0045] Figure 2B and Figure 2C Explanation Figure 2A A plan view and a cross-sectional view of a III-N device 123 are provided, wherein Figure 2C The cross-section diagram of Figure 2B The active area of ​​the device is indicated by the dotted area 26. Outside the active area, the semiconductor material is typically etched or otherwise processed (e.g., by ion implantation) so that no conductive channels exist, thereby preventing short circuits between parts of the device designed to be insulated from each other. Figure 2B and Figure 2C As seen in FIG. 1 , vias 38 and 38 ′ are formed outside of active region 26 and extend through III-N material structure 24 exposing a portion of the top surface of substrate 14. Gate electrode metal is at least partially formed in vias 38 and 38 ′ so that gate electrode 135 is electrically connected to substrate 14. As used herein, the “active region” of a transistor refers to the source and drain regions as well as the gate electrode. Figure 2B and Figure 2C The region (ie, region 26 ) containing the device channel is located between the source electrode 134 and the drain electrode 136 .

[0046] Now return to reference Figure 2A , the low voltage E-mode device 122 is electrically connected to the high voltage D-mode III-N device 123 to form the hybrid III-N device 100. Here, the drain electrode 133 of the E-mode device 122 directly contacts (e.g., is mounted on) and is electrically connected to the source electrode 134 of the III-N device 123 through a portion of a source contact, which is shown as a source pad 137 formed above a portion of the insulating layer 18. The source pad 137 may extend above the active area of ​​the D-mode device 123, as shown. Figure 2A, so that the E-type device 122 is mounted directly above the active area of ​​the D-type device 123. Alternatively, the insulating layer 18 may extend outside the active area of ​​the D-type device 123, the source pad 137 may extend above the insulating layer 18 outside the active area of ​​the D-type device 123, and the E-type device 122 may be mounted on the source pad 137 outside the active area of ​​the D-type device 123. The drain 133 of the E-type device 122 may be connected to the source pad 137 of the D-type device 123, for example, by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment methods, which achieves high-quality mechanical, thermal, and electrical connections between the FET drain electrode 133 and the source pad 137 of the source electrode 134. Conventional hybrid devices assembled in a single package are typically packaged side-by-side on a ceramic insulating substrate (such as an AlN pad) and require external wire connections for the FET drain and HEMT source connections. However, directly mounting the E-type device 122 on the D-type device 123 (eg Figure 2A This significantly reduces the parasitic inductance of the circuit, allowing for higher current ratings and faster switching speeds.

[0047] Figure 3 A perspective view of a hybrid III-N device 100 integrated into an electronic component package 200 is shown. Package 200 is a three-terminal package comprising a conductive structural package substrate 310 (e.g., an aluminum, copper, or nickel leadframe), a gate lead 312 (i.e., a first terminal), a source lead 311 (i.e., a second terminal), and a drain lead 313 (i.e., a third terminal). Gate lead 312 and drain lead 313 are electrically insulated from conductive structural package substrate 310, and source lead 311 is electrically connected to conductive structural package substrate 310. Mounting holes 29 may optionally be included. Additionally, package 200 may include a plastic or metal housing (not shown) enclosing the device. The substrate 14 of the hybrid device is directly mounted and electrically connected to the conductive structural package substrate 310. Substrate 14 may be mounted to the package substrate, for example, using solder, conductive epoxy, conductive tape, or other suitable attachment methods that provide a high-quality mechanical, thermal, and electrical connection between substrate 14 and the structural package substrate 310. Typically, in conventional hybrid device packaging methods, a ceramic or insulating substrate (e.g., an AlN pad) is used between the device substrate 14 and the package base 310 to insulate the substrate from the package. The package base 310 can be directly mounted to a heat sink (not shown) so that the package base 310 and the heat sink are in electrical and thermal contact, i.e., they are electrically connected, and heat generated by the hybrid device can be dissipated through the heat sink. The heat sink can also be a circuit ground, or it can be electrically connected to a circuit ground, in which case the package base 310, substrate 14, and the gate 135 of the III-N device are each electrically connected to the circuit ground.

[0048] The gate lead 312 of package 200 is coupled (e.g., electrically connected) to the gate electrode 132 of the E-type device 122 via connector 41. The drain lead 313 of package 200 is coupled (e.g., electrically connected) to the drain electrode 136 of the III-N device 123 via connector 43. The conductive structural package substrate 310 is coupled (e.g., electrically connected) to the source electrode 131 of the E-type device 122 via connector 42. The gate electrode 135 of the III-N device 123 is coupled (e.g., electrically connected) to the conductive structural package substrate 310 via the conductive substrate 14 and vias 38 / 38'. Connectors 41, 42, and 43 may include a single wire bond (as shown) or multiple parallel wire bonds, ribbons, conductive metal clips, or other connectors including conductive materials such as aluminum (Al), gold (Au), copper (Cu), or other suitable materials.

[0049] like Figure 3 As seen in FIG, the gate contact 135 of the D-type III-N device 123 is electrically connected to the substrate 14 through a via 38 / 38' formed through the III-N material structure 24. Furthermore, as previously described, the substrate 14 is mounted directly to the conductive structural packaging base 310 so that it is electrically connected. This configuration allows the gate electrode 135 of the III-N device to be electrically coupled (e.g., electrically connected) to the source lead 311 of the packaged device 200 without the use of external wire connections as required in conventional methods. This configuration also allows the gate electrode 135 to be electrically coupled (e.g., electrically connected) to the source electrode 131 of the E-type device 122. The gate electrode 135 may contain a top surface (e.g., a portion of the top surface) exposed to the D-type device 123 that is useful for device testing (e.g., device inspection). Figure 33 (shown in FIG 1 ), however, it may be preferable to completely encapsulate the top surface of the gate electrode 135 in a dielectric material (such as dielectric layer 18) so that no exposed area of ​​the gate electrode 135 exists on the top surface of the D-type device 123. Additionally, conventional hybrid device assembly methods typically use a ceramic or insulating backing plate (e.g., an AlN backing plate) between the device substrate 14 and the package base 310 to insulate the substrate from the package source lead 311. This requires the use of additional wire connections to connect the gate electrode 135 to the package source lead 311. When an insulating backing plate is included between the package base 310 and the substrate 14 of the D-type device, the substrate 14 is not held at a fixed voltage but rather at a floating potential (e.g., somewhere between the voltage of the gate 135 of the D-type device and the voltage of the drain 136 of the D-type device), thereby causing a voltage difference between the drain 136 of the D-type device and the substrate 14 of the D-type device to be substantially smaller than the voltage difference between the drain 136 of the D-type device and the gate 135 of the D-type device. Removing the ceramic backing plate and connecting the substrate 14 to the package base 310 fixes the substrate voltage at 0V (i.e., ground potential), resulting in the full gate-drain voltage being maintained across the III-N buffer layer 15. Consequently, careful design considerations regarding the III-N buffer layer 15 are required to maintain sufficient device breakdown voltage characteristics (e.g., the buffer layer 15 can be made thicker to prevent leakage and / or breakdown caused by the increased potential across the buffer layer). Consequently, the hybrid III-N device 100 can be assembled into a component package 200 without including a ceramic backing plate and with no more than three connections, whereas conventional assembly methods that require a ceramic backing plate or are assembled without vias 38 would require four or more connections. This reduces the number of required components (e.g., bill of materials or bill of materials) for the package, thereby reducing overall assembly costs. Figure 3 Component package 200 is shown as a leaded package, such as a TO-220 or TO-247. However, alternative embodiments with leadless packages, such as a quad flat no-lead package (QFN), a surface mount device (SMD), or a lossless package (LFPAK), may be used. Additionally, the components of package 200 may be oriented or arranged in a manner that best suits the designer's needs and the package type.

[0050] Figure 4 Show Figure 1 The circuit diagram of the hybrid device of FIG. 23 also indicates the various parasitic inductances and capacitances inherent in the device. The parasitic gate-drain capacitance (C GD ) is represented by capacitor 57. The intrinsic body diode of the E-type device 22 is represented by diode 37. The parasitic inductance of the source connection of the E-type device 22 is represented by inductor 54, and the parasitic inductance of the gate connection of the D-type device 23 is represented by inductor 53. Figure 4 The circuit is similar to Figure 3When implemented in a component package of the package 200, the inductor 54 represents a wire (e.g., a wire) connecting the source 131 of the E-type device 122 to the package substrate 310. Figure 3 The inductance of the wire 42 in Figure 4 The area enclosed by the dotted line 56 represents Figure 3 The package substrate 310 is shown. The package source lead 311 can be connected to circuit ground 55. To connect the gate electrode 35 of the D-type device 23 to the source electrode 31 of the E-type device 22, an external gate wire connection is used to connect the gate electrode 35 of the D-type device 23 to the package source lead 11 (or to the package substrate). This gate wire connection introduces significant inductance (represented by inductor 53) between the gate electrode 35 of the D-type device 23 and the package source lead 11 (or the package substrate). Parasitic inductances 53 and 54 can slow the device's turn-on and turn-off times and increase switching losses, thereby degrading device performance.

[0051] exist Figure 2A In the hybrid device 100 shown in FIG, the gate electrode 135 of the D-type device 123 is electrically connected to the substrate 14 by means of the through hole 38. Therefore, when the device 100 is implemented in the package 200, as shown in FIG. Figure 3 As shown in FIG, no external wire connection is required between the gate 135 of the D-type device 123 and the package base 310 because the gate 135 is electrically connected to the conductive substrate 14 and the conductive substrate 14 is directly mounted to (and thus electrically connected to) the package base 310. Figure 1 The parasitic inductance of the gate connection to the substrate 14 through the via 38 is significantly reduced compared to the parasitic inductance 53 of the external connection required for the device. Figure 1 Compared to the device of FIG. 1 , the device 100 enclosed in the component package 200 exhibits significantly improved switching characteristics, reduced on-resistance degradation, and significantly lower packaging cost. Some of these switching performance improvements are described further below.

[0052] Figure 5A 、 Figure 5B and Figure 5C Three different modes of operating a half-bridge buck converter circuit are shown. The half-bridge circuit includes a high-side switch 82 connected to a high voltage node 91 and a low-side switch 83 connected to a ground node 92. An inductor 93 is connected between a node 94 (which is between the low-side switch 83 and the high-side switch 82) and the output node V OUT The first capacitor 86 is connected between the high voltage node 91 and the DC ground 92. The second capacitor 87 is connected to the output node V OUT DC to ground 92. The low-side switch 83 is selected to have properties that improve the efficiency of the buck converter circuit. Specifically, the switch 83 should have a low on-resistance (R DS(ON)) and low switching losses. The switch 83 may be, for example, Figure 1 Alternatively, the switch 83 may be implemented as Figure 3 The components are assembled in package 200 Figures 2A-2C A hybrid device 100.

[0053] Figures 5A-5C The buck converter half-bridge can be operated as follows: Figure 5A In the first operating mode, the gate of the high-side switch 82 is biased to be on (ie, V GS 82>V TH ), and the gate of the low-side switch 83 is biased off (ie, V GS 83 <V TH ). Current 97 flows in the forward direction from high voltage node 91 through high side switch 83 to node 94. The current is blocked by low side switch 83 and flows through inductor 93 as shown by current path 97. When the device is operating in the first operating mode, if the gate-source voltage of high side switch 82 is switched low or off (i.e., switched to V GS 82 <V TH ), so that the gates of the two switches 82 and 83 are biased to be off, then the buck converter switches to Figure 5B The second operating mode is shown in . The current must continue to flow through the inductor 93.

[0054] Figure 6A Description Figure 5A and Figure 5B The current path through the low-side switch 83 during the transition time T1 between the first operation mode and the second operation mode shown in FIG. During the transition time T1, ( Figures 5A-5C The voltage at node 94 (shown in FIG) is pulled down until it becomes negative, and a displacement current flows through the parasitic gate-drain capacitor 57 of the D-type device 23, as shown in FIG. Figure 6A The current path I AC As shown. When the voltage at node 94 becomes sufficiently negative, the intrinsic body diode 37 of the E-type device 22 turns on and the switch 83 becomes reverse conducting. This is called reverse conduction mode (i.e., freewheeling diode mode). At the end of transition time T1, the switch 83 transitions from cutoff to reverse conduction, and the current suddenly transitions from displacement current through the gate-drain capacitor 57 of the D-type device 22 to a reverse DC current that flows through the intrinsic body diode 37 of the E-type device 22 and the channel of the D-type device 23, as shown. Figure 6B The current path I DCWhen the operating current through inductor 93 is high, the current path transition may result in a voltage spike and ringing across the gate of D-type device 23. This voltage spike will inject charge into the gate dielectric 18 of D-type device 23 and cause the on-resistance (R ON ) increases, thereby increasing the on-resistance of the hybrid device. Since the current in the inductor 93 must be continuous, even if the gate of the switch 83 is biased to be off, Figure 5B The reverse conduction of switch 83 is also required in the circuit.

[0055] Return Reference Figure 5C , after switching the gate of the high side 82 to cut-off (such as Figure 5B ), the low-side switch 83 is switched on (ie, switched to V GS 83>V TH ), thereby causing the buck converter to operate in a third operating mode in which current continues to flow through the low-side switch 83 in the same direction as in the second mode, but with the low-side switch 83 biased on (in the reverse direction). Biasing the low-side switch on during the third operating mode reduces the voltage drop across the E-type device 22 compared to the second operating mode and allows for higher efficiency compared to the second operating mode. Sufficient dead time between turning off the high-side switch 82 and turning on the low-side switch 83 is required to prevent an accidental high voltage rail short to ground.

[0056] The design of the device and the associated package can be a key factor in determining the performance of the low-side switch 83 during the reverse conduction mode. By implementing the device 100 in the package 200 as a low-side device 83 and thereby eliminating the need for an external gate wire between the D-type device 23 and the package substrate (because the D-type device gate is connected to the package substrate via a via 38), the parasitic inductance in the packaged device is reduced (shown by the inductor 53). This in turn reduces the voltage spikes and ringing experienced by the gate of the D-type device 23 during the current path transition between the first operating mode and the second operating mode. Surprisingly, compared to conventional packages with external gate wires, this is shown to significantly reduce the degradation (i.e., increase) of the on-resistance of the device operating under extremely high reverse DC currents. This result is unexpected. When the device 100 is implemented as a low-side switch 83 in the package 200, the switch 83 can operate with a reverse DC current greater than 50A or even greater than 70A during the second and third operating modes while exhibiting almost no increase in on-resistance. For example, the increase in on-resistance can be less than 5%. Conventional packages with external gate wire connections can typically exhibit an increase in on-resistance of greater than 30% or even greater when operated at a reverse DC current of 30 A or less. The low-side switch 83 is capable of blocking voltages greater than 600 V during the first operating mode. Additionally, the high-side switch 82 can be the same type of switch as the low-side switch 83 but is not subject to the same sudden current transient conditions and can be designed with less stringent requirements.

[0057] Figure 7A 、 Figure 7B and Figure 7C Three different modes of operating a half-bridge boost converter circuit are shown. The half-bridge circuit includes a high-side switch 84 connected to a high voltage node 91 and a low-side switch 85 connected to a ground node 92. An inductor 101 is connected between a node 102 (which is between the low-side switch 85 and the high-side switch 84) and an input node VIN of the circuit. A first capacitor 88 is connected between the input node VIN and the DC ground 92. A second capacitor 87 is connected between the high voltage node 91 and the DC ground 92. Here, unlike a buck converter, the high-side switch 84 needs to be carefully selected to improve the efficiency of the boost converter circuit. Specifically, the switch 84 should have a low on-resistance (R DS(ON) ) and low switching losses. The switch 85 may be, for example, Figure 1 Alternatively, the switch 85 may be implemented as Figure 3 The components are assembled in package 200 Figures 2A-2C A hybrid device 100.

[0058] Figures 7A-7C The boost converter half-bridge can be operated as follows: Figure 7A In the first operating mode, the gate of the high-side switch 84 is biased off (ie, VGS 84 <V TH ), and the gate of the low-side switch 85 is biased on (ie, V GS 85 <V TH ). Current flows through inductor 101 to node 102 and in the forward direction through low-side switch 85 to ground 92, as shown by current path 103. When the device is operating in the first operating mode, if the gate-source voltage of low-side switch 85 is switched to a low state (i.e., switched to V GS 85 <V TH ), so that the gates of the two switches 84 and 85 are biased to be off, then the boost converter switches to Figure 7B The second operating mode is shown in . The current must continue to flow through the inductor 101 .

[0059] The current path through the high-side switch 84 during the transition between the first and second operating modes may be similar to Figure 6A and Figure 6B During the transition, the voltage at node 102 is pulled higher and displacement current flows through the parasitic gate-drain capacitor of the D-type device used in switch 84. When the voltage at node 102 becomes sufficiently higher than the high voltage node 91, the intrinsic body diode of the E-type device used in switch 84 conducts and switch 84 becomes reverse conducting. The behavior and effects of high-side switch 84 during the transition from cutoff to reverse conduction are similar to Figures 5A-5C The pressure reducing converter and Figure 6A and Figure 6B The behavior and effects of the low-side switch are described in 83.

[0060] Return Reference Figure 7C , after the gate of the low-side switch 85 is switched off (eg Figure 7B ), the gate of the high-side switch 84 is switched to conduction (ie, V GS 84>V TH ), thereby causing the boost converter to operate in a third operating mode in which current flows through the high-side switch 84 in the same direction as in the second mode. Biasing the high-side switch to conduct during the third operating mode reduces the voltage drop across the E-type device of the switch 84 and achieves higher efficiency compared to the second operating mode. Sufficient dead time between turning off the low-side switch 85 and turning on the high-side switch 84 is required to prevent accidental shorting of the high voltage rail to ground. When the hybrid device package component 200 is used as the high-side switch 84, Figures 7A-7C The boost converter circuit is able to support Figures 5A-5CThe performance characteristics of the low-side switch 83 are similar to the performance characteristics described for the low-side switch 83. Additionally, the low-side switch 85 can be the same type of switch as the high-side switch 84 but is not subject to the same sudden current transition conditions and can be designed with less stringent requirements.

[0061] refer to Figure 8 , showing another configuration of a hybrid III-N device. Figure 8 The device 800 is similar to Figure 2A The device 100 is different in that the III-N material structure 24 is fabricated on an insulating substrate 814 (e.g., a sapphire substrate) or a semi-insulating substrate (having a resistivity of ≥1E5Ω·cm) (e.g., a silicon carbide substrate instead of a conductive silicon substrate), as shown in FIG. Figure 2A As previously mentioned for Figure 2A As discussed in connection with the packaged device 100 of FIG. 8 , the conductive silicon substrate 14 is grounded at 0V, resulting in the full gate-drain voltage being maintained across the buffer layer 15. This requires careful design consideration of the III-N buffer layer 15, which limits the high breakdown voltage of the device 100. By using a sapphire (or other insulating or semi-insulating) substrate in the device 800, the breakdown voltage of the device 800 can be significantly greater than the breakdown voltage of the device 100. For example, the breakdown voltage of the device 800 can be greater than 1200V, greater than 2400V, and in some specific design implementations, greater than 10kV. A typical sapphire substrate has a nominal thickness of ~700μm. However, the substrate 814 can be thinned to improve the thermal performance of the substrate. For example, the insulating substrate 814 can have a thickness of less than 200μm.

[0062] In device 800, gate via 838 extends through the entire thickness of III-N material structure 24 and the entire thickness of insulating substrate 814 to allow gate 135 of D-type device 123 to be electrically connected to backside metal layer 842. Backside metal layer 842 may have similar properties (e.g., conductivity) as backside metal layer 42 of device 100, or alternatively, layer 842 may be different. For example, backside metal layer 842 may be a plated material having a thickness greater than 6 μm, such as a Ni or Cu layer. Gate via 838 may be formed in a region of the device similar to gate via 38, such as outside the active area of ​​the device. Gate via 838 may be formed using a variety of different fabrication methods. For example, gate via 838 may be formed through III-N material structure 24 and substrate 814 by etching (e.g., dry or wet etching) or laser ablation (or a combination of both), thereby forming a hole through the side of the substrate opposite material structure 24.

[0063] Alternatively, the gate via 838 can be formed by etching through the entire thickness of the III-N material structure 24 and partially etching through the substrate 814 (e.g., by etching 200 μm to 700 μm into the substrate). Next, the gate via 838 is filled with a metal stack (such as Al, Ni, or Cu) by sputter deposition or plating. After the metal deposition step, the substrate 838 can be thinned by grinding the side of the substrate opposite the III-N material stack to a thickness of less than 200 μm, thereby exposing the metal stack on the back surface of the substrate. After the substrate is thinned, a back metal layer 842 can be deposited, wherein electrical connections are made to the gate metal stack formed in the gate via.

[0064] A backside metal layer 842 may be formed on the side of the substrate opposite the III-N material layer 24 before or after forming the gate via 838. The etching of the gate via 838 may be performed on the backside of the substrate 814 and at least partially after a metal deposition step that forms a metal stack from the backside gate via 838, where the metal stack contacts the gate metal 135 of the III-N device 123.

[0065] The front side of the device and the back side of the device can be double-sided Cu plated simultaneously so that the gate via 838 is plated from the front side of the device and the back metal layer 842 is plated from the back side of the device at the same time in a single process step. The plated Cu layer can have a thickness of 10 μm or more on both sides of the device. The gate via 838 extending through the entire thickness of the insulating substrate 814 allows the device 800 to be implemented in Figure 3 The device 200 is packaged in a similar package such that the gate 135 of the D-type III-N device 123 can be electrically connected to the package substrate 310 without the use of external gate wire connections.

[0066] refer to Figure 9 , showing another configuration of a hybrid III-N device. Figure 9 The device 900 is similar to Figure 2A 100, except that the low voltage E-mode device 122 and the high voltage D-mode III-N device 123 are packaged in a "side-by-side" configuration in device 900 as opposed to a "stacked" configuration for device 100. Figure 2A As discussed above with respect to device 100, the E-mode device 122 is mounted directly on the source pad 137 of the D-mode device 123 to eliminate the need for external wire connections connecting the source electrode 134 of the D-mode device to the FET drain electrode 133 of the E-mode device. However, in some applications, the D-mode III-N device 123 may be too small to allow sufficient area to mount the E-mode FET 122 directly to the source pad 137 on the top side of the D-mode device. For applications with these size limitations, hybrid devices can be arranged in a "side-by-side" configuration, such as Figure 9 As shown in .

[0067] A backing plate 291 is mounted between the E-type device 122 and the package substrate 310. The backing plate may include a ceramic or insulating layer 297 (e.g., AlN) with metal layers 298 and 299 on opposite sides of the insulating layer 297. The metal layer 299 acts as a bonding layer, allowing the backing plate to be attached to the device package substrate 310 using solder, solder paste, conductive epoxy, conductive tape, or another suitable attachment method, which allows for a high-quality mechanical and thermal connection of the backing plate 291 to the device package substrate 310. The drain electrode 133 of the device 122 is mounted to the metal layer 298 on the top side of the insulating backing plate 291 using solder, solder paste, conductive epoxy, conductive tape, or another suitable attachment method. The source electrode 134 of the III-N device 123 is electrically connected to the drain electrode 133 of the E-type device 122 via a wire connection 44 that extends from the source electrode 134 to the top metal surface 298 of the insulating backing plate 291. This results in the source electrode 134 being electrically connected to the FET drain electrode 133. The remaining wiring connections and configuration of the device 900 may be similar to Figure 2A The device 900 may have an advantage over the device 100 in that it may enable the use of a smaller / cheaper III-N HEMT. However, the device 900 may also require increased packaging complexity compared to the device 100.

[0068] Figure 10 Another hybrid III-N device 1000 is shown in FIG. Figure 10 The device 1000 is similar to Figure 9 1. The device 1000 is a device that implements an alternative design for a low voltage E-type device, such that the E-type device and the D-type device are packaged in a "side-by-side" configuration without the use of a ceramic spacer. A typical silicon MOSFET, such as FET 122 of device 900, is a vertical device fabricated such that the FET drain 133 is on the bottom side of the semiconductor body 25 and the FET gate 132 and FET source 131 are on the top side of the semiconductor body 25. However, device 1000 is implemented using a silicon MOSFET having an alternative semiconductor body 125, wherein the FET source electrode 231 is on one side of the semiconductor body 125 (e.g., the bottom side) and the FET gate electrode 232 and FET drain electrode 233 are on the same side of the semiconductor body 125 opposite the FET source electrode 231 (e.g., the top side) to form an inverted E-type FET 124. Thus, FET 124 can be implemented in device 1000 to eliminate the insulating spacer 291 and source connector 42 included in device 900.

[0069] like Figure 10As seen in FIG, the source electrode 231 of the inverted E-mode FET 124 is directly mounted and electrically connected to the conductive structural package substrate 310 by solder, solder paste, conductive epoxy, conductive tape, or another suitable attachment method, which achieves a high-quality mechanical, thermal, and electrical connection between the FET 124 and the package substrate 310. The source electrode 134 of the III-N device 123 is connected to the drain electrode 233 of the E-mode FET 124 by a wire connection 144. Device 1000 may be superior to device 900 in that several packaging components (including Figure 9 The insulating pad 291 and source connector 42 shown in FIG. 4 reduce packaging complexity and cost.

[0070] Many implementations have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the techniques and devices described herein. Accordingly, other implementations are within the scope of the following claims.

Claims

1. A semiconductor device comprising: a III-N device comprising a conductive substrate on a first side of a III-N material structure, and a first gate, a first source, and a first drain on a second side of the III-N material structure opposite the substrate, wherein the first source is electrically isolated from the conductive substrate; and a field effect transistor comprising a second semiconductor material structure, and a second gate, a second source, and a second drain, the second source and the second gate being on a side of the second semiconductor material structure opposite the second drain; The second drain of the field effect transistor is physically mounted and electrically connected to the first source of the III-N device; and a via extending through a portion of the III-N material structure and terminating at the conductive substrate, and A metal layer is at least partially formed in the through hole; wherein The first gate is electrically connected to the conductive substrate through the metal layer formed in the through hole.

2. The semiconductor device according to claim 1, wherein The substrate has a hole concentration greater than 1x10 19 holes / cm 3 of doped p-type.

3. The semiconductor device according to claim 2, wherein The substrate is configured to be electrically coupled to circuit ground through a backside metal layer.

4. The semiconductor device according to claim 1, wherein The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein the buffer layer is doped with iron, magnesium, or carbon.

5. The semiconductor device according to claim 4, wherein A composition difference between the III-N barrier layer and the III-N channel layer causes a lateral 2DEG channel to be induced in the III-N channel layer, and the first source and the first drain are electrically connected to the 2DEG. The semiconductor device according to claim 4 , wherein: The III-N buffer layer has a thickness greater than 4 μm.

7. The semiconductor device according to claim 1, wherein The second drain of the field effect transistor is electrically connected to the first source of the III-N device through solder, solder paste, or conductive epoxy.

8. The semiconductor device according to claim 1, wherein A top surface of the first gate is completely encapsulated in dielectric material.

9. The semiconductor device according to claim 1, wherein The III-N material structure is oriented in an N-polar orientation.

10. The semiconductor device according to claim 1, wherein The III-N device further includes an active region between the first source and the first drain, and the via is formed outside the active region. The semiconductor device according to claim 10 , wherein: The field effect transistor is at least partially over the active region of the III-N device.

12. An electronic component comprising: Enhancement mode transistors; a depletion mode transistor comprising a conductive substrate; as well as a package comprising a conductive structural packaging substrate, the package enclosing both the enhancement mode transistor and the depletion mode transistor; in The drain electrode of the depletion mode transistor is electrically connected to the drain lead of the package, the gate electrode of the enhancement mode transistor is electrically connected to the gate lead of the package, and the source electrode of the enhancement mode transistor is electrically connected to the conductive structural package substrate; in The gate electrode of the depletion mode transistor is directly in contact with and electrically connected to the conductive substrate through a metal layer at least partially formed in a via, the conductive substrate is directly in contact with and electrically connected to the conductive structural package base, and the conductive structural package base is electrically connected to a source lead of the package, wherein the via extends from the gate electrode of the depletion mode transistor through a portion of the material structure of the depletion mode transistor and terminates at the conductive substrate.

13. The electronic component according to claim 12, wherein The gate electrode of the depletion mode transistor is electrically connected to the source lead of the package without an external gate wire connection.

14. The electronic component according to claim 12, wherein The depletion mode transistor includes a III-N material structure on the conductive substrate.

15. The electronic component according to claim 14, wherein The gate electrode of the depletion mode transistor is on a side of the III-N material structure opposite the conductive substrate, the III-N material structure includes a via extending to the conductive substrate, and the gate electrode of the depletion mode transistor is electrically connected to the conductive substrate through the via.

16. The electronic component according to claim 15, wherein The via is outside the active area of ​​the depletion mode transistor.

17. The electronic component according to claim 12, wherein The drain electrode of the enhancement mode transistor is in direct contact with and electrically connected to the source electrode of the depletion mode transistor, and the enhancement mode transistor is at least partially over the active region of the depletion mode transistor.

18. The electronic component according to claim 15, wherein The source electrode of the enhancement mode transistor is coupled to the gate electrode of the depletion mode transistor through the conductive substrate.

19. The electronic component according to claim 17, wherein The enhancement mode transistor has a lower breakdown voltage than the depletion mode transistor.

20. The electronic component according to claim 14, wherein The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein the buffer layer is doped with iron, magnesium, or carbon.

21. The electronic component according to claim 20, wherein The composition difference between the III-N barrier layer and the III-N channel layer results in a lateral 2DEG channel being induced in the III-N channel layer.

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