Voltage level shifter

Abstract

A circuit includes first through fifth transistors. The first transistor (MN1) has a first control input and first and second current terminals. The second transistor (MN2) has a second control input and third and fourth current terminals. The third transistor (MP1) has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal and the fifth current terminal is coupled to a supply voltage node. The fourth transistor (MP2) has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal and the seventh current terminal is coupled to the supply voltage node. The fifth transistor (MN5) has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input and the tenth current terminal is coupled to the second current terminal.

Description

BACKGROUND

[0001] A voltage level shifter (or simply "level shifter") is a circuit that translates a signal from one voltage domain to another. The voltage of the output signal can be greater than or less than the voltage of the input signal. For example, a level shifter can be used when an input signal to a circuit has been generated according to a particular voltage domain that is different from the power supply voltage domain of the circuit itself. An n-type metal oxide semiconductor field effect transistor (NMOS) typically has its source connected to ground potential. As such, turning on an NMOS device only requires a gate voltage that exceeds the threshold voltage of the transistor, and turning off the NMOS device where the gate voltage is below the threshold, closer to ground. A p-type metal oxide semiconductor field effect transistor (PMOS) typically has its source connected to the power supply voltage. As such, turning off a PMOS device requires a gate voltage closer to the power supply voltage (i.e., within the threshold voltage of the transistor from the power supply voltage). In a level shifter, the voltage levels to turn on and off the NMOS device will therefore be different from the voltage levels to turn on and off the PMOS device. SUMMARY

[0002] In one example, a circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a power supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal is coupled to the power supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal is coupled to the second current terminal. BRIEF DESCRIPTION OF DRAWINGS

[0003] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0004] Figure 1 An example of a level shifter is described.

[0005] Figure 2 Another example of a level shifter is described.

[0006] Figure 3 Another example of a level shifter is described.

[0007] Figure 4 Another example of a level shifter is described. DETAILED DESCRIPTION

[0008] Figure 1 An example of a high-to-low level shifter 100 is shown, which converts incoming signals from a voltage domain lower than the supply voltage domain. The level shifter 100 includes NMOS transistors MN1, MN2, MN3, and MN4, PMOS transistors MP1 and MP2, and inverters 102, 104, and 106. Because the input signal is in a voltage domain higher than the output signal (OUT_HV2), MN1 and MN2 are high-voltage transistors for reliability reasons, and therefore the threshold voltages of MN1 and MN2 are higher than the threshold voltages of MN3, MN4, MP1, and MP2. The sources of MP1 and MP2 are connected to the supply voltage node 110 (VDDHV2). The drain of MP1 is connected to the drain of MN3 at node N1, and the drain of MP2 is connected to the drain of MN4 at node N2. The source of MN3 is connected to the drain of MN1, and the source of MN4 is connected to the drain of MN2. The sources of MN1 and MN2 are connected to ground node 115. The gate of MP1 is connected to N2, and the gate of MP2 is connected to N1. The gates of MN3 and MN4 are connected together and receive the enable (EN1) input signal. When EN1 is set high, both MN3 and MN4 are turned on; otherwise, when EN1 is low, both MN3 and MN4 are turned off, and the level shifter is disabled. The gate of MN1 is configured to receive the input signal IN_HV1. Inverter 102 inverts IN_HV1 to drive the gate of MN2. Thus, only one of MN1 and MN2 is turned on at any given time. Inverters 104 and 106, connected in series, are connected to N2, and the output of inverter 106 provides the output signal OUT_HV2 from level shifter 100.

[0009] When IN_HV1 is high, OUT_HV2 is also high, and when IN_HV1 is low, OUT_HV2 is also low. However, when high, IN_HV1 is at a different voltage than OUT_HV2. The voltage level of OUT_HV2 is typically lower than the voltage level of IN_HV1 (although in some cases, OUT_HV2 is higher than IN_HV1). VDDHV2 is the power supply voltage of level shifter 100 and indicates the voltage level of OUT_HV2. When IN_HV1 is a logic high, MN1 is on and MN2 is off. With EN1 asserted high, both MN3 and MN4 are on. With MN1 and MN3 on, N1 is pulled low to ground. When the voltage on N1 drives the gate of MP2, the gate-to-source voltage (VGS) of MP2 is high enough to turn on MP2. With MP2 on, N2 is pulled high to VDDHV2, and thus OUT_HV2 is also VDDHV2. Conversely, when IN_HV1 is a logic low, MN1 is off and MN2 is on. With MN2 and MN4 on, N2 is pulled low to ground, and thus OUT_HV2 is also low. When the voltage on N2 drives the gate of MP1, the VGS of MP1 is high enough to turn on MP1. With MP1 on, N1 is pulled high, which in turn turns off MP2.

[0010] NMOS devices MN1 and MN2 must be strong enough to discharge the drains of MP1 and MP2 when IN_HV1 transitions between low and high. For example, as explained above, if IN_HV1 is currently low, then MN2, MN4, and MP1 are on. In this state, N1 is pulled high toward VDDHV2. During a transition of IN_HV1 from low to high, MN1 is on, and the charge on the drain of MP1 should be discharged through MN3 and MN1 to ground. To discharge the drain of MP1, the drain current through MN1 (I1) should be greater than the drain current through MP1 (I2). I1 is the sum of I2 and the discharge current from the drain of MP1 (the source-to-drain of MP1 represents a capacitance that charges when MN1 is off and then discharges when MN1 is on).

[0011] The drain current through a MOS transistor is at least partially a function of its VGS and its size (size refers to the ratio of the transistor's channel width (W) to channel length (L)). Under normal operating conditions, the VGS of MN1 and MN2 is higher than the VGS of MP1, and can easily pull down the voltage on the drains of MP1 and MP2. Under conditions where the level shifter is enabled for a lower voltage value of VDDHV1 (close to the threshold voltage of MN1 and MN2), MN1 and MN2 are much weaker (compared to VDDHV1 at higher voltages) when their respective inputs become logic high. In this latter condition (low value of VDDHV1), since VDDHV1 is less than VDDHV2, when IN_HV1 transitions from low to high, the VGS of MP1 is greater than the VGS of MN1. Therefore, in order for the drain of MP1 to discharge, the size of MN1 must be substantially greater than the size of MP2, such that the drain current of MN1 will be greater than the drain current of MP1, which in turn will cause N1 to discharge. Thus, in Figure 1 the example level shifter 100 of FIG. 1, this problem is solved by making MN1 larger than MP1. For a high to low transition of IN_HV1, there is the same problem on the right hand side of level shifter 100, which causes MN2 to turn on to try to discharge the drain of MP2. MN1 and MN2 in this design are larger than MP1 and MP2. Thus, there is a size penalty for level shifter 100 of FIG. 1. Further, the leakage current and average switching current are also quite large. Figure 1

[0012] Figure 2 An example of a level shifter 200 that solves the above problems is shown. Level shifter 200 includes NMOS transistors MN1, MN2, and MN3A, PMOS transistors MP1, MP2, MP3, and MP4, and inverters 202, 204, and 206. The sources of MP1 and MP2 are connected to the power supply voltage node 110 (VDDHV2). The drain of MP1 is connected to the source of MP3 at an intermediate node int3, and the drain of MP2 is connected to the source of MP4 at an intermediate node int4. The drain of MP3 is connected to the drain of MN1 at an intermediate node int1, and the drain of MP4 is connected to the drain of MN2 at an intermediate node int2. The sources of MN1 and MN2 are connected to the drain of MN3A. The source of MN3 is connected to ground node 115, and an enable signal EN2 is provided to the gate of MN3A to enable operation of level shifter 200. EN2 high (e.g., greater than the threshold voltage of MN3A) causes MN3A to turn on, and EN2 low (e.g., ground potential) causes MN3A to turn off. Level shifter 200 is enabled if EN2 is asserted high, and otherwise disabled.

[0013] ​The gate of MP1 is connected to int2, and the gate of MP2 is connected to int1. The gates of MP3 and MN1 are connected together and receive IN_HV1. Inverter 202 inverts IN_HV1 to drive the gates of MP4 and MN2, which are also connected together. Inverters 204 and 206, connected in series, are connected to int2, and the output of inverter 206 provides the output signal OUT_HV2 from level shifter 200.

[0014] When IN_HV1 is high, OUT_HV2 is also high, and vice versa. However, when high, IN_HV1 is at a different voltage than OUT_HV2. The voltage level of OUT_HV2 can be higher or lower than the voltage level of IN_HV1. VDDHV2 is the power supply voltage for level shifter 200 and indicates the voltage level of OUT_HV2. When IN_HV1 is logic high, MN1 turns on, and MN2 and MP3 turn off. With MN1 on, in1 is pulled low to ground. When the voltage on int1 drives the gate of MP2, the VGS of MP2 is high enough to turn on MP2. With MP2 on, the source voltage of MP4 rises, causing MP4 to turn on. Thus, int2 is pulled high to VDDHV2, and OUT_HV2 is also pulled high to VDDHV2. Conversely, when IN_HV1 is logic low, MN2 turns on. With MN2 on, int2 is pulled low to ground, and thus OUT_HV2 is also low. When the voltage on int2 drives the gate of MP1, the VGS of MP1 is high enough to turn on MP1. With MP1 on, MP3 is also on, and int1 is pulled high, which in turn turns off MP2.

[0015] Figure 2 MP3 and MP4 in the example of FIG. 1 are used to isolate the input NMOS transistors MN1 and MN2 from the cross-coupled PMOS transistors MP1 and MP2. When IN_HV1 is 0, MN1 is off, and MP1 and MP3 are on. When IN_HV1 transitions from low to high, MN1 turns on, and MP3 turns off. In this way, MN1 only needs to sink enough current to discharge the drain of MP3. With MP3 additionally off, no current flows from MP1 through MP3. In contrast to level shifter 100 of FIG. 1, MP3 and MP4 reduce or completely eliminate the drive conflict between MN1 and MP1 and between MN2 and MP2. Figure 1 In contrast to level shifter 100 of FIG. 1, MP3 and MP4 reduce or completely eliminate the drive conflict between MN1 and MP1 and between MN2 and MP2.

[0016] Instead of having MN3 and MN4 in FIG. 1 as enable transistors, in FIG. 2 the feature has been implemented with a single-tail transistor MN3A connected between the sources of MN1, MN2 and ground node 115. Using single-tail transistor MN3A (as opposed to MN3 and MN4 in FIG. 1) reduces the number of transistors in the level shifter 200. Figure 1 In FIG. 1, MN3 and MN4 are used as enable transistors. In FIG. 2, the feature has been implemented with a single-tail transistor MN3A connected between the sources of MN1, MN2 and ground node 115. Using single-tail transistor MN3A (as opposed to MN3 and MN4 in FIG. 1) reduces the number of transistors in the level shifter 200. Figure 2 In FIG. 1, MN3 and MN4 are used as enable transistors. In FIG. 2, the feature has been implemented with a single-tail transistor MN3A connected between the sources of MN1, MN2 and ground node 115. Using single-tail transistor MN3A (as opposed to MN3 and MN4 in FIG. 1) reduces the number of transistors in the level shifter 200. Figure 1The two transistors MN3 and MN4 in the circuit provide area benefits, as well as improved performance from common-mode noise, because the level shifter 200 is perfectly differential.

[0017] exist Figure 2 In this example, when MN2 is on (when IN_HV1 transitions from high to low), MP4 is off. At that time, MP4 does not actively pull the intermediate node int4 low. This is addressed by connecting the input to inverter 204 to intermediate node int2 instead of intermediate node int4. However, if intermediate node int2 is used instead of intermediate node int4, the rising transition of OUT_HV2 will be slower.

[0018] Figure 3 An example of a level shifter 300 is shown, comprising NMOS transistors MN1, MN2, MN3A, MN5, and MN6, PMOS transistors MP1, MP2, MP3, and MP4, and inverters 302, 304, and 306. The sources of MP1 and MP2 are connected to a power supply voltage node 110 (VDDHV2). The drain of MP1 is connected to the source of MP3 at intermediate node int3, and the drain of MP2 is connected to the source of MP4 at intermediate node int4. The drain of MP3 is connected to the drain of MN1 at intermediate node int1, and the drain of MP4 is connected to the drain of MN2 at intermediate node int2. The sources of MN1 and MN2 are connected to the drain of MN3A. The source of MN3 is connected to ground node 115, and an enable signal EN2 is provided to the gate of MN3A to enable operation of the level shifter 300. As described above, a high EN2 causes MN3A to turn on, and a low EN2 causes MN3A to turn off. Level shifter 300 is enabled when EN2 is set to high, otherwise it is disabled.

[0019] Intermediate node int4 is connected to the input of inverter 304, and the output of inverter 304 is connected to the input of inverter 306. The output of inverter 306 provides the output signal OUT_HV2 from level shifter 300.

[0020] and Figure 2 The situation is the same. Figure 3 In this example, MP3 and MP4 are used to isolate the input NMOS transistors MN1 and MN2 from the cross-coupled PMOS transistors MP1 and MP2. When IN_HV1 is 0, MN1 is off, and MP1 and MP3 are on. When IN_HV1 transitions from low to high, MN1 is on and MP3 is off. Thus, MN1 only needs to draw enough current to discharge the drain of MP3. When MP3 is also off, no current flows from MP1 through MP3. Figure 1In contrast to the level shifter 100, MP3 and MP4 reduce or completely eliminate drive conflicts between MN1 and MP1 and between MN2 and MP2.

[0021] The drain of MN5 is connected to the drain of MP1, and at int3 it is connected to the source of MP3. The source of MN5 is connected to the source of MN1. The drain of MN6 is connected to the drain of MP2, and at int4 it is connected to the source of MP4. The source of MN6 is connected to the source of MN2. (As mentioned above...) Figure 2 The explanation is that when IN_HV1 transitions from high to low, thus turning off MP4, the intermediate node int4 is not actively pulled low. This is achieved by connecting the cascaded inverters 204 and 206 to the intermediate node int2 instead of the intermediate node int4. Figure 2 This issue is addressed in the instance level shifter 200, but results in a lower transition rate for OUT_HV2 when making low-to-high transitions. Figure 3 MN5 and MN6 in the diagram address this issue. When MN2 is on and MP4 is off, MN6 is on. Thus, the charge on intermediate node int4 discharges to ground through MN6, rapidly pulling the voltage on intermediate node int4 low. The same action occurs when MN1 is on and MP3 is off (MN5 is also on, rapidly discharging intermediate node int3). As a result of this rapid discharge of intermediate node int4, the voltage at the source of MP4 is rapidly pulled low, which in turn causes MP4 to have a shorter high-to-low transition during IN_HV1 compared to its low-to-high transition. Figure 2 In the case of the instance, the switch is turned off earlier. Similarly, if MN5 is turned on during the low-to-high transition of IN_HV1, MP3 is turned off earlier during that transition than during the high-to-low transition of MN5. Figure 2 In some cases, the shutdown occurs even earlier. Therefore, adding MN5 and MN6 has a dual advantage. First, it provides discharge paths to int4 and int3. Second, it improves isolation for MN1 and MP1, and for MN2 and MP2.

[0022] Figure 4An example of a level shifter 400 is shown, including NMOS transistors MN1, MN2, and MN3A, PMOS transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, and MP8, and inverters 402, 404, and 406. The sources of MP1 and MP2 are connected to a supply voltage node 110 (VDDHV2). The drain of MP1 is connected to the source of MP3, and the drain of MP2 is connected to the source of MP4. The drain of MP3 is connected to the drain of MN1 at an intermediate node int1, and the drain of MP4 is connected to the drain of MN2 at an intermediate node int2. The sources of MN1 and MN2 are connected to the drain of MN3A. The source of MN3 is connected to a ground node 115, and an enable signal EN2 is provided to the gate of MN3A to enable operation of level shifter 400. As described above, EN2 high causes MN3A to turn on, and EN2 low causes MN3A to turn off. Level shifter 400 is enabled if EN2 is established as high, otherwise disabled.

[0023] Intermediate node int2 is connected to the input of inverter 404, and the output of inverter 404 is connected to the input of inverter 406 at an intermediate node int5. The output of inverter 406 provides an output signal OUT_HV2 from level shifter 400. The gate of MP5 is connected to intermediate node int5. The gate of MP6 is connected to intermediate node int2. The gate of MP7 is connected to the output node (OUT_HV2) of level shifter 400. The gate of MP8 is connected to intermediate node int1.

[0024] As with Figure 2 , in the example of Figure 3 MP3 and MP4 are used to isolate the input NMOS transistors MN1 and MN2 from the cross-coupled PMOS transistors MP1 and MP2. When IN_HV1 is 0, MN1 is off, and MP1 and MP3 are on. Upon a transition of IN_HV1 from low to high, MN1 turns on and MP3 turns off. In this way, MN1 only needs to sink enough current to discharge the drain of MP3. Without MP3 additionally off, no current flows from MP1 through MP3. As with Figure 1 , in contrast to level shifter 100 of

[0025] MP7 and MP8 form a pull-up stack of transistors that is operable to quickly pull int2 (and thus OUT_HV2) from ground to VDDHV2. In this regard, MP7 and MP8 contribute to the pull-up functionality of MP2 and MP4. Similarly, MP5 and MP6 also form a pull-up stack of transistors that is operable to quickly pull intl from ground to VDDHV2. In this regard, MP5 and MP6 contribute to the pull-up functionality of MP1 and MP3. The operation of MP7 and MP8 when IN_HV1 transitions from low to high will now be described. The same or similar explanation applies to MP5 and MP6 when IN_HV1 transitions from high to low.

[0026] When IN_HV1 is low, MN2, MP3, and MP1 are on. With MN2 on, int2 is low, and through inverters 404 and 406, OUT_HV2 is also low. Because OUT_HV2 is used as the gate voltage to MP7, MP7 is on. However, MP8 is off because the intermediate node intl is high through MP1 and MP3, both of which are on.

[0027] During the transition of IN_HV1 from low to high, as soon as IN_HV1 reaches the threshold voltage of MN1, MN1 turns on, pulling the intermediate node intl low. With intl low, both MP2 and MP8 are on. MP4 is also on. At this point, the intermediate node int2 begins to charge through two stacks of transistors. One stack of transistors includes MP2 and MP4. The other stack of transistors includes MP7 and MP8. Thus, MP7 and MP8 contribute to quickly increasing the voltage on the intermediate node int2 (and thus OUT_HV2) from ground toward VDDHV2.

[0028] As OUT_HV2 begins to increase, as soon as OUT_HV2 reaches one transistor threshold voltage from VDDHV2, the VGS of MP7 drops below its threshold voltage and MP7 turns off, effectively disabling the stack of transistors of MP7 / MP8. Thus, the rising transition of OUT_HV2 is improved (i.e., its slew rate is increased) due to the action of MP7 and MP8 during a portion of the transition phase of IN_HV1. The same explanation applies to MP5 and MP6 when IN_HV1 transitions from high to low.

[0029] In this description, the term "couple" or "couples" means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection can be through a direct connection, or through an indirect connection via other devices and connections. The detail "based at least in part on" means "based, at least in part, on." Thus, if X is based on Y, X can be a function of Y and any number of other factors.

[0030] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: a first transistor having a first control input and first and second current terminals; a second transistor having a second control input and third and fourth current terminals; a third transistor having a third control input and fifth and sixth current terminals, the third control input coupled to the third current terminal, and the fifth current terminal coupled to a supply voltage node; a fourth transistor having a fourth control input and seventh and eighth current terminals, the fourth control input coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node; and a fifth transistor having a fifth control input and ninth and tenth current terminals, the fifth control input coupled to the first control input, and the tenth current terminal coupled to the second current terminal.

2. The circuit of claim 1, further comprising a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the sixth control input coupled to the second control input, and the twelfth current terminal coupled to the fourth current terminal.

3. The circuit of claim 2, further comprising a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the second and fourth current terminals.

4. The circuit of claim 1, further comprising a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the eleventh current terminal coupled to the second and fourth current terminals.

5. The circuit of claim 1, further comprising a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the eleventh current terminal coupled to the sixth current terminal, and the twelfth current terminal coupled to the first current terminal.

6. The circuit of claim 5, further comprising a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the eighth current terminal, and the fourteenth current terminal coupled to the third current terminal.

7. The circuit of claim 6, wherein the first and second transistors comprise n-type metal oxide semiconductor field effect transistors, and the sixth and seventh transistors comprise p-type metal oxide semiconductor field effect transistors.

8. The circuit of claim 1, further comprising: a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the sixth control input coupled to the second control input, and the twelfth current terminal coupled to the fourth current terminal; a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the sixth current terminal, and the fourteenth current terminal coupled to the first current terminal; and a eighth transistor having an eighth control input and fifteenth and sixteenth current terminals, the fifteenth current terminal coupled to the second and fourth current terminals. ​ an eighth transistor having an eighth control input and a fifteenth and a sixteenth current terminal, the fifteenth current terminal coupled to the eighth current terminal, and the sixteenth current terminal coupled to the third current terminal.

9. A circuit comprising: a first transistor having a first control input and a first and a second current terminal; a second transistor having a second control input and a third and a fourth current terminal; a third transistor having a third control input and a fifth and a sixth current terminal, the third control input coupled to the third current terminal, and the fifth current terminal coupled to a supply voltage node; a fourth transistor having a fourth control input and a seventh and an eighth current terminal, the fourth control input coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node; and a fifth transistor having a fifth control input and a ninth and a tenth current terminal, the fifth control input coupled to an output node of the circuit; a sixth transistor having a sixth control input and an eleventh and a twelfth current terminal, the sixth control input coupled to the first current terminal, the eleventh current terminal coupled to the tenth current terminal, and the twelfth current terminal coupled to the third current terminal; an inverter having an input and an output, the input coupled to the twelfth current terminal; and a seventh transistor having a seventh control input and a thirteenth and a fourteenth current terminal, the seventh control input coupled to the output of the inverter.

10. The circuit of claim 9, further comprising: an eighth transistor having an eighth control input and a fifteenth and a sixteenth current terminal, the eighth control input coupled to the third current terminal, the fifteenth current terminal coupled to the fourteenth current terminal, and the sixteenth current terminal coupled to the first current terminal.

11. The circuit of claim 10, further comprising a ninth transistor having a ninth control input and a seventeenth and an eighteenth current terminal, the seventeenth current terminal coupled to the second and fourth current terminals.

12. The circuit of claim 9, further comprising an eighth transistor having an eighth control input and a fifteenth and a sixteenth current terminal, the fifteenth current terminal coupled to the sixth current terminal, and the sixteenth current terminal coupled to the first current terminal.

13. The circuit of claim 12, further comprising a ninth transistor having a ninth control input and a seventeenth and an eighteenth current terminal, the seventeenth current terminal coupled to the eighth current terminal, and the eighteenth current terminal coupled to the third current terminal.

14. The circuit of claim 13, wherein the first and second transistors comprise n-type metal oxide semiconductor field effect transistors, and the eighth and ninth transistors comprise p-type metal oxide semiconductor field effect transistors.

15. A circuit comprising: a first transistor having a first control input and first and second current terminals; a second transistor having a second control input and third and fourth current terminals; a third transistor having a third control input and fifth and sixth current terminals, the third control input coupled to the third current terminal, and the fifth current terminal coupled to a supply voltage node; a fourth transistor having a fourth control input and seventh and eighth current terminals, the fourth control input coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node; and a fifth transistor having a fifth control input and ninth and tenth current terminals, the ninth current terminal coupled to the first and second current terminals.

16. The circuit of claim 15, further comprising a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the eleventh current terminal coupled to the sixth current terminal, and the twelfth current terminal coupled to the first current terminal.

17. The circuit of claim 16, further comprising a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the thirteenth current terminal coupled to the eighth current terminal, and the fourteenth current terminal coupled to the third current terminal.

18. The circuit of claim 15, further comprising: a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the sixth control input coupled to the first control input, the eleventh current terminal coupled to the sixth current terminal, and the twelfth current terminal coupled to the second current terminal; and a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the seventh control input coupled to the second control input, the thirteenth current terminal coupled to the fourth current terminal, and the fourteenth current terminal coupled to the fourth current terminal.

19. The circuit of claim 15, further comprising: a sixth transistor having a sixth control input and eleventh and twelfth current terminals, the sixth control input coupled to an output node of the circuit; and a seventh transistor having a seventh control input and thirteenth and fourteenth current terminals, the seventh control input coupled to the first current terminal, the thirteenth current terminal coupled to the twelfth current terminal, and the fourteenth current terminal coupled to the third current terminal; an eighth transistor having an eighth control input and fifteenth and sixteenth current terminals, the eighth control input configured to receive a control signal that is a logical inverse of a signal on an output node of the circuit; and a ninth transistor having a ninth control input and seventeenth and eighteenth current terminals, the ninth control input coupled to the third current terminal, the seventeenth current terminal coupled to the sixteenth current terminal, and the eighteenth current terminal coupled to the first current terminal. ​

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