A method of cutting a package substrate unit

Abstract

The application discloses a method for cutting package substrate units, comprising the following steps: preparing a temporary carrier plate; forming a first circuit layer and a copper column layer on at least one side of the temporary carrier plate and a dielectric layer covering the first circuit layer and the copper column layer, and thinning the dielectric layer to expose the copper column layer, wherein the copper column layer comprises a sacrificial copper column and a conductive copper column, the sacrificial copper column is located on a cutting path and penetrates the dielectric layer in the height direction, and the conductive copper column is located on the first circuit layer; forming a second circuit layer on the upper surface of the dielectric layer, and the first circuit layer and the second circuit layer are conductively connected through the conductive copper column; removing the temporary carrier plate; performing etching protection treatment on the surface of the first circuit layer; mounting a device on the second circuit layer; applying a protective layer on the upper surface of the dielectric layer to protect the second circuit layer, the copper column layer and the device; and etching the sacrificial copper column.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of packaging substrate cutting, in particular to a method for cutting packaging substrate units. BACKGROUND

[0002] With the increasing functions and smaller size of electronic products, the packaging substrate is required to be thinner and thinner, and the number of packaged devices is also increasing. Currently, for the cutting of ultra-thin packaging substrate or ultra-thin packaging unit, diamond blade cutting or laser cutting is generally used to cut and separate along the preset cutting path.

[0003] The current cutting method for ultra-thin packaging substrate or ultra-thin packaging unit usually encounters the following technical problems: 1. When cutting the packaging substrate directly, the thin substrate is prone to cracking during cutting due to its thin thickness, resulting in poor cutting accuracy and affecting the packaging yield; 2. When cutting the thin packaging body after plastic packaging of the ultra-thin packaging substrate, it is easy to exceed the operation limit of the cutting machine due to excessive warping or excessive warping stress of the packaging body, increasing the operation difficulty of the cutting machine, and the cutting process is prone to deviation, damaging the product and causing blade deformation; 3. The special cutting machine table needs to be used when cutting the special-shaped substrate unit in the prior art, which makes it difficult to adapt to the production line and significantly increases the production cost. SUMMARY

[0004] Embodiments of the present application relate to a method for cutting packaging substrate units to solve the above technical problems. The present application makes a sacrificial copper column on the cutting path during the manufacturing process of the packaging substrate, so that the unit separation can be achieved by etching the copper column, or the cutting path is pre-cut, and the cutting path after etching the sacrificial copper column is exposed. It can achieve unit separation by simply mechanical separation. Thus, the present application can obtain a single packaging unit with any shape and smooth cutting surface; can avoid the dielectric layer peeling caused by stress during the cutting process in the traditional cutting process, improve the packaging yield; no cutting machine table is needed, eliminating the failure caused by the cutting machine table, especially suitable for the cutting demand of special-shaped substrate units, significantly reducing the production cost.

[0005] The first aspect of the present application relates to a method for cutting packaging substrate units, comprising the following steps:

[0006] (a) preparing a temporary carrier plate;

[0007] (b) forming a first circuit layer and a copper pillar layer on at least one side of the temporary carrier and a dielectric layer covering the first circuit layer and the copper pillar layer, and thinning the dielectric layer to expose the copper pillar layer, wherein the copper pillar layer comprises a sacrificial copper pillar and a through copper pillar, the sacrificial copper pillar is on a scribe lane and penetrates the dielectric layer in a height direction, and the through copper pillar is on the first circuit layer;

[0008] (c) forming a second circuit layer on an upper surface of the dielectric layer, the first circuit layer and the second circuit layer are connected through the through copper pillar;

[0009] (d) removing the temporary carrier;

[0010] (e) performing an etch protection treatment on a surface of the first circuit layer;

[0011] (f) mounting a device on the second circuit layer;

[0012] (g) applying a protective layer on an upper surface of the dielectric layer to protect the second circuit layer, the copper pillar layer and the device;

[0013] (h) etching the sacrificial copper pillar.

[0014] In some embodiments, the copper pillar layer comprises at least one through copper pillar and at least one sacrificial copper pillar.

[0015] In some embodiments, top ends of the sacrificial copper pillar and the through copper pillar are flush with an upper surface of the dielectric layer, respectively.

[0016] In some embodiments, step (b) comprises:

[0017] (b1) applying a first photoresist layer on at least one side of the temporary carrier, exposing and developing to form a first feature pattern;

[0018] (b2) depositing copper in the first feature pattern to form a first circuit layer;

[0019] (b3) applying a second photoresist layer on the first circuit layer, exposing and developing to form a second feature pattern;

[0020] (b4) depositing copper in the second feature pattern to form a copper pillar layer, wherein the copper pillar layer comprises a sacrificial copper pillar and a through copper pillar, the sacrificial copper pillar is on a scribe lane and penetrates the dielectric layer in a height direction, and the through copper pillar is on the first circuit layer;

[0021] (b5) removing the first photoresist layer and the second photoresist layer;

[0022] (b6) applying a dielectric layer on the temporary carrier plate, and thinning the dielectric layer to expose the top ends of the sacrificial copper pillars and the through copper pillars.

[0023] In some embodiments, step (e) comprises tin plating the surface of the first circuit layer.

[0024] In some embodiments, the protective layer in step (g) comprises a tape.

[0025] In some embodiments, further comprising step (i) removing the protective layer.

[0026] In some embodiments, the top ends of the through copper pillars are flush with the upper surface of the dielectric layer, and the top ends of the sacrificial copper pillars are higher than the upper surface of the dielectric layer.

[0027] In some embodiments, the top ends of the sacrificial copper pillars are 50-200um higher than the upper surface of the dielectric layer.

[0028] In some embodiments, step (b) further comprises:

[0029] (b1 / ) applying a first photoresist layer on at least one side of the temporary carrier plate, and exposing and developing to form a first feature pattern;

[0030] (b2 / ) depositing copper in the first feature pattern to form a first circuit layer;

[0031] (b3 / ) applying a second photoresist layer on the first circuit layer, and exposing and developing to form a second feature pattern;

[0032] (b4 / ) depositing copper in the second feature pattern to form a copper pillar layer, wherein the copper pillar layer comprises through copper pillars on the first circuit layer and sacrificial copper pillars on the scribe lanes, and the top ends of the sacrificial copper pillars are higher than the top ends of the through copper pillars;

[0033] (b5 / ) removing the first photoresist layer and the second photoresist layer;

[0034] (b6 / ) applying a dielectric layer on the temporary carrier plate, and thinning the dielectric layer to expose the top ends of the sacrificial copper pillars and the through copper pillars, wherein the top ends of the through copper pillars are flush with the upper surface of the dielectric layer, and the top ends of the sacrificial copper pillars are higher than the upper surface of the dielectric layer.

[0035] In some embodiments, the protective layer in step (g) is a plastic encapsulation layer.

[0036] In some embodiments, the upper surface of the plastic encapsulation layer is 20-50 um higher than the top end of the sacrificial copper pillars.

[0037] In some embodiments, step (h) further comprises thinning the plastic encapsulation layer to expose the top end of the sacrificial copper pillars, and etching the sacrificial copper pillars.

[0038] In some embodiments, the temporary carrier board comprises a copper clad board with at least one side covered with a double layer of copper foil, wherein the copper clad board comprises a core layer, a first copper layer on the surface of the core layer, and a second copper layer on the first copper layer, and wherein the first copper layer and the second copper layer are attached together by physical pressing. Preferably, the core layer comprises a prepreg, the thickness of the first copper layer is 18 um, and the thickness of the second copper layer is 3 um.

[0039] In some embodiments, step (d) comprises removing the temporary carrier board by physically separating the first copper layer and the second copper layer, and etching the second copper layer.

[0040] In some embodiments, further comprising forming an etching barrier layer on at least one side of the temporary carrier board before step (b). Preferably, the etching barrier layer comprises nickel, titanium, or a combination thereof; more preferably, the etching barrier layer is selected from nickel.

[0041] In some embodiments, the device is selected from an active device, a passive device, or a combination thereof.

[0042] A second aspect of the present application provides a method of singulating a package substrate unit, comprising the following steps:

[0043] (a) preparing a temporary carrier board;

[0044] (b) forming a first circuit layer on at least one side of the temporary carrier board, forming a first copper pillar layer on the first circuit layer, applying a first dielectric layer to cover the first circuit layer and the first copper pillar layer, thinning the first dielectric layer to expose the first copper pillar layer, wherein the first copper pillar layer comprises first sacrificial copper pillars and first conductive copper pillars, the first sacrificial copper pillars are located in first singulation lanes, and the second singulation lanes of the first dielectric layer are pre-singulated;

[0045] (c) forming a second circuit layer on the upper surface of the first dielectric layer, the first circuit layer and the second circuit layer are conductively connected through the first copper pillar layer;

[0046] (d) removing the temporary carrier board;

[0047] (e) forming a third copper pillar layer and a second copper pillar layer on the first wiring layer and the second wiring layer, respectively, wherein the second copper pillar layer comprises a second sacrificial copper pillar and a second conductive copper pillar, the third copper pillar layer comprises a third sacrificial copper pillar and a third conductive copper pillar, the second sacrificial copper pillar and the third sacrificial copper pillar are located on the first cutting lane and the second cutting lane;

[0048] (f) applying a second dielectric layer and a third dielectric layer on the upper and lower surfaces of the first dielectric layer, respectively, thinning the second dielectric layer and the third dielectric layer to expose the second copper pillar layer and the third copper pillar layer, respectively;

[0049] (g) forming a third wiring layer and a fourth wiring layer on the second dielectric layer and the third dielectric layer, respectively, the second wiring layer and the third wiring layer are conductively connected through the second conductive copper pillar, the first wiring layer and the fourth wiring layer are conductively connected through the third conductive copper pillar;

[0050] (h) mounting a device on the third wiring layer, etching-protecting the surface of the fourth wiring layer, and applying a protective layer on the second dielectric layer to protect the third wiring layer and the device;

[0051] (i) etching the first sacrificial copper pillar, the second sacrificial copper pillar and the third sacrificial copper pillar to expose the second cutting lane after pre-cutting treatment.

[0052] In some embodiments, the diameters of the second sacrificial copper pillar and the third sacrificial copper pillar are greater than or equal to the diameter of the first sacrificial copper pillar, respectively, to completely cover the first sacrificial copper pillar.

[0053] In some embodiments, the etching-protecting treatment of the surface of the fourth wiring layer in step (h) comprises a tin plating treatment.

[0054] In some embodiments, the protective layer applied on the second dielectric layer in step (h) comprises a plastic encapsulation layer. BRIEF DESCRIPTION OF DRAWINGS

[0055] For a better understanding of the present application and to show how the same can be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings.

[0056] With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present application only and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the application. In this regard, no attempt is made to show structural details of the application in more detail than is necessary for a fundamental understanding of the application; the description taken with the drawings making apparent to those skilled in the art the several forms in which the application can be embodied. In the drawings:

[0057] Figures 1(a) to 1(n) FIG. 1 (a) shows a cross-sectional schematic view of an intermediate structure of a method of singulating a packaged substrate unit according to an embodiment of the present application;

[0058] Figure 2(a)~2(i) FIG. 1 (a) shows a cross-sectional schematic view of an intermediate structure of a method of singulating a packaged substrate unit according to an embodiment of the present application;

[0059] Figure 3 FIG. 1 (d) and FIG. 1 (1) show a top view of the sacrificial copper pillars.

[0060] Figure 4 FIG. 2 (g) shows a top view of the sacrificial copper pillars.

[0061] Figure 5 FIG. 3 shows a top schematic view of various shaped substrate units singulated by embodiments of the present application. DETAILED DESCRIPTION

[0062] With reference to Figures 1(a) to 1(n) FIG. 1 (a) shows a cross-sectional schematic view of an intermediate structure of a method of singulating a packaged substrate unit according to an embodiment of the present application;

[0063] The method comprises the following steps: preparing a temporary carrier plate - step (a), as shown in FIG. 1(a). The temporary carrier plate comprises a core layer 1011a, which can be a prepreg. The core layer 1011a is outwardly sequentially provided with a first copper layer 1011b on a surface of the core layer 1011a and a second copper layer 1011c on a surface of the first copper layer 1011b. The first copper layer 1011b and the second copper layer 1011c are physically pressed together to form a copper foil. The first copper layer 1011b and the second copper layer 1011c can be physically separated, so as to facilitate removal of the temporary carrier plate in a subsequent process. The thickness of the first copper layer 1011b and the second copper layer 1011c can be adjusted according to actual needs. Preferably, the thickness of the first copper layer 1011b is 18 μm, and the thickness of the second copper layer 1011c is 3 μm. Generally, an etching barrier layer 1012 can be simultaneously applied to both sides of the temporary carrier plate. In the present embodiment, a single unit on one side of the temporary carrier plate is demonstrated in subsequent processes, but it is not limited to that the subsequent operation can only be performed on one side of the temporary carrier plate. In the process of removing the temporary carrier plate, the etching barrier layer 1012 can protect the circuit layer and the copper pillar layer of the substrate when etching the second copper foil layer 1011b after separating the plate, so as to avoid excessive etching. The etching barrier layer 1012 can comprise nickel, titanium or a combination thereof, for example, a nickel layer with a thickness of 8-15 μm. The thickness of the etching barrier layer 1012 can be adjusted according to actual needs. Preferably, the thickness of the etching barrier layer 1012 is 3-10 μm.

[0064] After step (a), a first photoresist layer is applied on the etching barrier layer 1012, and a first feature pattern is formed by exposure and development, and copper is deposited in the first feature pattern to form a first circuit layer 1013, a second photoresist layer is applied on the first circuit layer 1013, and a second feature pattern is formed by exposure and development, and copper is deposited in the second feature pattern to form a copper pillar layer, and the first photoresist layer and the second photoresist layer are removed; wherein the copper pillar layer includes the end-flush sacrificial copper pillars 1022 and the conductive copper pillars 1021, the sacrificial copper pillars 1022 are located in the scribe lanes, and the conductive copper pillars 1021 are formed on the first circuit layer 1013—step (b), as shown in FIG. 1(b). Generally, the first photoresist layer and the second photoresist layer can be applied by means of film pasting or coating, and the first photoresist layer and the second photoresist layer can be removed by means of film stripping, and the thickness of the first photoresist layer and the second photoresist layer can be adjusted as needed. The copper can be deposited by means of electroplating deposition, chemical deposition or magnetron sputtering deposition; the height of the sacrificial copper pillars 1022 and the conductive copper pillars 1021 can be adjusted as needed; the sacrificial copper pillars 1022 are distributed along the scribe lanes and coincide with the scribe lanes in the longitudinal direction, and the scribe lanes are shown by the dashed lines in the figure. The copper pillar layer includes at least one conductive copper pillar 1021 and at least one sacrificial copper pillar 1022; preferably, the copper pillar layer includes multiple conductive copper pillars 1021 as IO channels, and the cross-sectional dimensions of the conductive copper pillars 1021 can be the same or different; the conductive copper pillars 1021 are uniform in size, which is advantageous for heat dissipation and stable signal transmission of the embedded package structure.

[0065] Then, a dielectric layer 101 is applied on the temporary carrier plate, and the dielectric layer 101 is thinned to expose the ends of the sacrificial copper pillars 1022 and the conductive copper pillars 1021, a third photoresist layer is applied on the upper surface of the dielectric layer 101, and a third feature pattern is formed by exposure and development, and copper is deposited in the third feature pattern to form a second circuit layer 1014, and the third photoresist layer is removed; the first circuit layer 1013 and the second circuit layer 1014 are connected by the conductive copper pillars 1021—step (c), as shown in FIG. 1(c). Generally, the dielectric layer 101 can be thinned as a whole by means of plate grinding or plasma etching to expose the ends of the sacrificial copper pillars 1022 and the conductive copper pillars 1021; the dielectric layer 101 can also be thinned locally by means of laser or drilling to expose the ends of the sacrificial copper pillars 1022 and the conductive copper pillars 1021; preferably, the dielectric layer 101 is thinned as a whole by means of plate grinding or plasma etching, and the ends of the sacrificial copper pillars 1022 and the conductive copper pillars 1021 are flush with the dielectric layer 101, respectively. The dielectric layer can include organic dielectric materials, inorganic dielectric materials or combinations thereof, for example, the dielectric layer can include polyimide, epoxy resin, bismaleimide triazine resin, ceramic material, glass fiber or combinations thereof.

[0066] It should be noted that when the circuit layer is prepared, a metal seed layer can be first formed before preparation to make the connection between the circuit layer and the temporary carrier plate or the dielectric layer more reliable. The metal seed layer can be formed by electroless plating or sputtering, and can include titanium, copper, titanium tungsten alloy or a combination thereof, and the thickness of the metal seed layer ranges from 1 to 3 μm; preferably, titanium and copper are sputtered to form the metal seed layer.

[0067] Next, a photoresist layer is applied on the upper surface of the dielectric layer 101 and exposed and cured to separate the first copper layer 1011b and the second copper layer 1011c, the second copper layer 1011c is etched, the etching barrier layer 1012 is etched, and the photoresist layer is removed—step (d), as shown in FIG. 1(d). Generally, the photoresist layer is applied to protect the copper pillar layer and the second circuit layer 1014 when the temporary carrier plate is removed; the photoresist layer can be applied by pasting or coating, and removed by film stripping. The etching barrier layer 1012 can be etched by a specific chemical solution, for example, etching the etching barrier layer 1012 by using a nickel etching chemical solution.

[0068] Then, the surface of the first circuit layer 1013 is subjected to etching protection treatment, for example, tin plating, to form a tin disc 1061 on the surface of the first circuit layer 1013—step (e), as shown in FIG. 1(e).

[0069] Next, the first device 1015 and the second device 1016 are pasted on the second circuit layer 1014, and a protective layer 103 is applied on the upper surface of the dielectric layer 101 so that the protective layer 103 covers the second circuit layer 1014, the conductive copper pillar 1021, the first device 1015 and the second device 1016—step (f), as shown in FIG. 1(f). Generally, the device can be an active device, a passive device, or a combination of active and passive devices; preferably, the first device 1015 is an active device, and the second device 1016 is a passive device. Generally, the protective layer 108 can include a tape.

[0070] Then, the sacrificial copper pillar 1022 is etched, and the protective layer 108 is removed—step (g), as shown in FIG. 1(g).

[0071] Finally, mechanical separation is performed along the cutting path to obtain the packaging unit 100a—step (h), as shown in FIG. 1(h). After the sacrificial copper pillar 1022 is etched, the cutting process of the cutting path is completed, and a single packaging unit 100a is obtained, which is regular and smooth in shape, and can avoid the peeling of the dielectric layer caused by stress during the cutting process in the traditional cutting process.

[0072] In one variation, the receiving step (a) is followed by applying a first photoresist layer on the etching barrier layer 1012, exposing and developing to form a first feature pattern, depositing copper in the first feature pattern to form a first circuit layer 1013, applying a second photoresist layer on the first circuit layer 1013, exposing and developing to form a second feature pattern, depositing copper in the second feature pattern to form a copper pillar layer, and removing the first and second photoresist layers; wherein the copper pillar layer includes a conductive copper pillar 1021 and a sacrificial copper pillar 1022 located in the scribe lane, the conductive copper pillar 1021 is on the first circuit layer 1013, and the end of the sacrificial copper pillar 1022 is higher than the end of the conductive copper pillar 1021—step (i), as shown in FIG. 1(i). Typically, the distance by which the end of the sacrificial copper pillar 1022 is higher than the end of the conductive copper pillar 1021 can be adjusted according to actual needs, for example, the end of the sacrificial copper pillar 1022 can be 50-200 um higher than the end of the conductive copper pillar 1021.

[0073] Next, a dielectric layer 101 is applied on the temporary carrier plate, and the dielectric layer 101 is thinned to expose the ends of the sacrificial copper pillar 1022 and the conductive copper pillar 1021, a third photoresist layer is applied on the upper surface of the dielectric layer 101, exposed and developed to form a third feature pattern, copper is deposited in the third feature pattern to form a second circuit layer 1014, and the third photoresist layer is removed; the first circuit layer 1013 and the second circuit layer 1014 are connected by the conductive copper pillar 1021, the end of the conductive copper pillar 1021 is flush with the dielectric layer 101, and the end of the sacrificial copper pillar 1022 is higher than the dielectric layer 101—step (j), as shown in FIG. 1(j). Typically, the distance by which the end of the sacrificial copper pillar 1022 is higher than the upper surface of the dielectric layer 101 is equivalent to the distance by which the end of the sacrificial copper pillar 1022 is higher than the end of the conductive copper pillar 1021, for example, the end of the sacrificial copper pillar 1022 can be 50-200 um higher than the upper surface of the dielectric layer 101.

[0074] Then, a photoresist layer is applied on the upper surface of the dielectric layer 101 and exposed and cured, the first and second copper layers 1011b and 1011c are separated, the second copper layer 1011c and the etching barrier layer 1012 are etched, and the photoresist layer is removed—step (k), as shown in FIG. 1(k). Typically, the photoresist layer covers the part of the sacrificial copper pillar 1022 that is higher than the dielectric layer 101, the second circuit layer 1014, and the dielectric layer 101, to protect the copper pillar layer and the second circuit layer 1014 when the temporary carrier plate is removed, and the photoresist layer can be applied by pasting or coating.

[0075] Next, the surface of the first circuit layer 1013 is etched and protected, for example, tin plating is performed to form a tin disc 1061 on the surface of the first circuit layer 1013—step (l), as shown in FIG. 1(l).

[0076] The top view of the sacrificial copper pillar 1022 in this embodiment is as shown in FIG. 2. Figure 3 As shown, the sacrificial copper pillars 1022 can be arranged in various patterns.

[0077] Then, the first device 1015 and the second device 1016 are attached on the second circuit layer 1014, and a molding layer 104 is applied on the upper surface of the dielectric layer 101, so that the molding layer 104 covers the second circuit layer 1014, the copper pillar layer, the first device 1015 and the second device 1016—step (m), as shown in FIG. 1(m). Generally, the thickness of the molding layer 104 can be adjusted as needed, for example, the upper surface of the molding layer 104 can be set to be 20-50 um higher than the end of the sacrificial copper pillar 1022. The device can be an active device, a passive device, or a combination of active and passive devices; preferably, the first device 1015 is an active device, and the second device 1016 is a passive device.

[0078] Finally, the molding layer 104 is thinned to expose the end of the sacrificial copper pillar 1022, the sacrificial copper pillar 1022 is etched, and mechanical separation is performed in the cutting area to obtain a packaging unit 100b—step (n), as shown in FIG. 1(n). After etching the sacrificial copper pillar 1022, the cutting process of the cutting path is completed, and a single packaging unit 100b can be obtained, which has a regular and smooth shape, and can avoid the peeling of the dielectric layer caused by stress during the cutting process in the traditional cutting process.

[0079] Referring to Figure 2(a)~2(i) FIG. 2 shows a cross-sectional schematic diagram of an intermediate structure of each step of a method for cutting a packaging substrate unit according to another embodiment of the present application.

[0080] The method includes the following steps: preparing a temporary carrier plate—step (a), as shown in FIG. 2(a). The temporary carrier plate includes a core layer 2011a, which can be a prepreg. The core layer 2011a has a first copper layer 2011b on the surface of the core layer 2011a and a second copper layer 2011c on the surface of the first copper layer 2011b. The first copper layer 2011b and the second copper layer 2011c are physically pressed together and can be physically separated for subsequent removal of the temporary carrier plate. Generally, an etching barrier layer 2012 can be applied on both sides of the temporary carrier plate. In this embodiment, the subsequent operation is demonstrated on a single unit on one side of the temporary carrier plate, but it is not limited to only one side of the temporary carrier plate. In the subsequent process of removing the temporary carrier plate, the etching barrier layer 2012 can protect the circuit layer and the copper pillar layer of the substrate during etching of the second copper foil layer 2011b after the plate is separated, thereby avoiding over-etching. The etching barrier layer 2012 can include nickel, titanium or a combination thereof.

[0081] Then, a first photoresist layer is applied on the etching barrier layer 2012, a first feature pattern is formed by exposure and development, copper is deposited in the first feature pattern to form a first circuit layer 2013, a second photoresist layer is applied on the first circuit layer 2013, a second feature pattern is formed by exposure and development, copper is deposited in the second feature pattern to form a first copper pillar layer, and the first photoresist layer and the second photoresist layer are removed; wherein the first copper pillar layer comprises a first sacrificial copper pillar 2022 and a first conductive copper pillar 2021, and the first sacrificial copper pillar 2022 is located in the first cutting path—step (b), as shown in FIG. 2(b). Generally, the height of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021 can be adjusted as needed; the ends of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021 can be flush or have a height difference; preferably, the ends of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021 are flush. The first sacrificial copper pillar 2022 is distributed along the first cutting path 501, and the first sacrificial copper pillar 2022 coincides with the first cutting path 501 in the longitudinal direction, as shown by the dashed line in the figure. The first copper pillar layer comprises at least one first conductive copper pillar 2021 and at least one first sacrificial copper pillar 2022; preferably, the first copper pillar layer comprises a plurality of first conductive copper pillars 2021 as IO channels, which can have the same or different cross-sectional dimensions; the first conductive copper pillar 2021 has uniform upper and lower dimensions, which is more advantageous for heat dissipation and stable signal transmission of the embedded packaging structure.

[0082] Then, a first dielectric layer 201 is applied on the temporary carrier plate, and the dielectric layer 201 is thinned to expose the ends of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021, a third photoresist layer is applied on the upper surface of the first dielectric layer 201, a third feature pattern is formed by exposure and development, copper is deposited in the third feature pattern to form a second circuit layer 2014, and the third photoresist layer is removed; the first circuit layer 2013 and the second circuit layer 2014 are connected by the first conductive copper pillar 2021 or the first sacrificial copper pillar 2022—step (c), as shown in FIG. 2(c). Generally, the ends of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021 can be flush with or protrude from the first dielectric layer 201, and can be adjusted according to actual needs; preferably, the ends of the first sacrificial copper pillar 2022 and the first conductive copper pillar 2021 are flush with the first dielectric layer 201.

[0083] Then, a photoresist layer is applied on the upper surface of the first dielectric layer 201 and exposed and cured, the first copper layer 2011b and the second copper layer 2011c are separated, the second copper layer 2011c and the etching barrier layer 2012 are etched, and the photoresist layer is removed—step (d), as shown in FIG. 2(d). Generally, the photoresist layer can protect the first copper pillar layer and the second circuit layer 2014 when the temporary carrier plate is removed.

[0084] Then, the fourth photoresist layer and the fifth photoresist layer are respectively applied on the first circuit layer 2013 and the second circuit layer 2014, and the fourth feature pattern and the fifth feature pattern are formed by exposure and development, and the third copper pillar layer is formed by depositing copper in the fourth feature pattern, and the second copper pillar layer is formed by depositing copper in the fifth feature pattern, the second copper pillar layer includes the second through copper pillar 3021 and the second sacrificial copper pillar 3022, the third copper pillar layer includes the third through copper pillar 4021 and the third sacrificial copper pillar 4022, and the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 are respectively located in the first cutting channel and the second cutting channel—step (e), as shown in FIG. 2 (e). Generally, the height of the second sacrificial copper pillar 3022 and the second through copper pillar 3021 can be adjusted as needed, and the ends of the second sacrificial copper pillar 3022 and the second through copper pillar 3021 can be flush or have a height difference. The height of the third through copper pillar 4021 and the third sacrificial copper pillar 4022 can be adjusted as needed, and the ends of the third through copper pillar 4021 and the third sacrificial copper pillar 4022 can be flush or have a height difference.

[0085] The second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 are located on the first cutting channel 501 and the second cutting channel 502, and the first cutting channel 501 and the second cutting channel 502 are shown by the dashed lines in the figure. The second sacrificial copper pillar 3022, the first sacrificial copper pillar 2022 and the third sacrificial copper pillar 4022 located on the first cutting channel 501 are longitudinally communicated in sequence, and the diameters of the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 can be respectively greater than or equal to the diameter of the first sacrificial copper pillar 2022 to completely cover the first sacrificial copper pillar 2022.

[0086] Then, the second dielectric layer 301 and the third dielectric layer 401 are respectively applied on the second copper pillar layer and the third copper pillar layer, and the second dielectric layer 301 and the third dielectric layer 401 are thinned to respectively expose the ends of the second copper pillar layer and the third copper pillar layer—step (f), as shown in FIG. 2 (f). Generally, the ends of the second copper pillar layer can be flush with or higher than the second dielectric layer 301; the ends of the third copper pillar layer can be flush with or higher than the third dielectric layer 401; preferably, the ends of the second copper pillar layer are flush with the second dielectric layer 301, and the ends of the third copper pillar layer are flush with the third dielectric layer 401.

[0087] Then, a sixth photoresist layer and a seventh photoresist layer are applied on the second dielectric layer 301 and the third dielectric layer 401 respectively, and a sixth feature pattern and a seventh feature pattern are formed by exposure and development, and copper is deposited in the sixth feature pattern to form a third line layer 3014, and copper is deposited in the seventh feature pattern to form a fourth line layer 4014, the second line layer 1014 and the third line layer 3014 are connected by a second conductive copper pillar 3021, and the first line layer 1013 and the fourth line layer 4014 are connected by a third conductive copper pillar 4021—step (g), as shown in FIG. 2(g).

[0088] The top view of the first sacrificial copper pillar 2022, the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 in the embodiment is shown in FIG. 2(f). Figure 4 When the substrate is in different orientations, the second sacrificial copper pillar 3022 in the top view can also be the third sacrificial copper pillar 4022. The first sacrificial copper pillar 2022, the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 can be arranged in various patterns. FIG. 2(h) shows the cutting channels exposed when the first sacrificial copper pillar 2022, the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 are etched.

[0089] Then, the surface of the fourth line layer 4014 is subjected to a tin plating process to form a tin disc 4061 on the surface of the fourth line layer 4014, the first device 3031 and the second device 3032 are attached on the third line layer 3014, and a plastic encapsulation layer 304 is applied on the upper surface of the second dielectric layer 301, and the plastic encapsulation layer 304 covers the first device 3031, the second device 3032 and the third line layer 3014—step (h), as shown in FIG. 2(i). Generally, the device can be an active device, a passive device or a combination of active and passive devices; preferably, the first device 3031 is an active device, and the second device 3032 is a passive device. The upper surface of the plastic encapsulation layer 304 can be higher than the end of the device, or flush with the end of the device, and preferably, the upper surface of the plastic encapsulation layer 304 is higher than the end of the device.

[0090] Then, the first sacrificial copper pillar 2022, the second sacrificial copper pillar 3022, the third sacrificial copper pillar 4022, the first line layer connected with the third sacrificial copper pillar and the second line layer connected with the second sacrificial copper pillar are etched—step (i). After the first sacrificial copper pillar 2022, the second sacrificial copper pillar 3022 and the third sacrificial copper pillar 4022 are etched, the cutting process of the first cutting channel and the second cutting channel is completed, and a single substrate unit can be further obtained by simple mechanical separation, and the substrate unit can have any shape and smooth cutting surface, which can avoid the peeling of the dielectric layer caused by the stress generated in the cutting process in the traditional cutting process, significantly improve the yield, and eliminate the failure caused by the cutting machine, and is particularly suitable for the cutting demand of special-shaped substrate units.

[0091] Figure 5 The method for cutting the package substrate unit of the present application shows the top view schematic diagram of the various irregular package substrate units cut by the method. The method for cutting the package substrate unit of the present application can be used in the cutting groove process of any shape substrate unit greater than two layers, and can also be used in the cutting of irregular substrate units, meeting the cutting demand of irregular substrate units, without the need to increase the cutting machine for special cutting, being able to perfectly adapt to the current existing technology production line process, and significantly reducing the production cost.

[0092] Those skilled in the art will realize that the present application is not limited to the particular implementation and examples described and illustrated herein. The scope of the present application is defined by the appended claims, including the combination and sub-combinations of the various features described above, and variations and modifications as would be apparent to those skilled in the art upon reading the foregoing description.

[0093] In the claims, the term "comprise" and variations thereof such as "comprising" and "comprises" do not exclude the presence of other elements or additional steps.

Claims

1. A method for cutting a packaging substrate unit, comprising the following steps: (a) Prepare a temporary support plate; (b) A first circuit layer and a copper pillar layer and a dielectric layer covering the first circuit layer and the copper pillar layer are formed on at least one side of the temporary support plate, and the dielectric layer is thinned to expose the copper pillar layer, wherein the copper pillar layer includes sacrificial copper pillars and conductive copper pillars, the sacrificial copper pillars being located on the cut track and penetrating the dielectric layer in the height direction, and the conductive copper pillars being located on the first circuit layer; (c) A second circuit layer is formed on the upper surface of the dielectric layer, and the first circuit layer and the second circuit layer are connected by the conductive copper pillar; (d) Remove the temporary support plate; (e) Perform an etching protection treatment on the surface of the first circuit layer; (f) Mounting the device on the second circuit layer; (g) Apply a protective layer to the upper surface of the dielectric layer to protect the second circuit layer, the copper pillar layer and the device; (h) Etching the sacrificial copper pillar; (i) Mechanical separation is performed along the cutting path to obtain the packaging unit.

2. The method according to claim 1, wherein the top ends of the sacrificial copper pillar and the conductive copper pillar are respectively flush with the upper surface of the dielectric layer.

3. The method according to claim 1, wherein step (b) comprises: (b1) A first photoresist layer is applied to at least one side of the temporary support plate, and the plate is exposed and developed to form a first feature pattern; (b2) Deposit copper in the first feature pattern to form a first circuit layer; (b3) A second photoresist layer is applied to the first circuit layer, and the second feature pattern is formed by exposure and development; (b4) Copper is deposited in the second feature pattern to form a copper pillar layer, wherein the copper pillar layer includes sacrificial copper pillars with flush tops and conductive copper pillars, the sacrificial copper pillars being located on the dicing track and penetrating the dielectric layer along the height direction, and the conductive copper pillars being located on the first circuit layer; (b5) Remove the first photoresist layer and the second photoresist layer; (b6) Apply a dielectric layer to the temporary support plate and thin the dielectric layer to expose the top of the sacrificial copper pillar and the conductive copper pillar.

4. The method of claim 1, wherein step (e) includes tinning the surface of the first circuit layer.

5. The method of claim 1, wherein the protective layer in step (g) comprises tape.

6. The method of claim 1, step (h) further includes removing the protective layer.

7. The method according to claim 1, wherein the top end of the conductive copper pillar is flush with the upper surface of the dielectric layer, and the top end of the sacrificial copper pillar is higher than the upper surface of the dielectric layer.

8. The method according to claim 7, wherein the top of the sacrificial copper pillar extends 50-200 μm above the upper surface of the dielectric layer.

9. The method of claim 7, wherein step (b) further comprises: (b1) / A first photoresist layer is applied to at least one side of the temporary support plate, and the plate is exposed and developed to form a first feature pattern. (b2) / Copper is deposited in the first feature pattern to form a first circuit layer; (b3) / A second photoresist layer is applied to the first circuit layer, and then exposed and developed to form a second feature pattern; (b4) / In the second feature pattern, copper is deposited to form a copper pillar layer, wherein the copper pillar layer includes a conductive copper pillar located on the first circuit layer and a sacrificial copper pillar located on the dicing track, the top of the sacrificial copper pillar being higher than the top of the conductive copper pillar. (b5) / Remove the first photoresist layer and the second photoresist layer; (b6) / A dielectric layer is applied to the temporary support plate and the dielectric layer is thinned to expose the tops of the sacrificial copper pillar and the conductive copper pillar, wherein the tops of the conductive copper pillar are flush with the upper surface of the dielectric layer and the tops of the sacrificial copper pillar are higher than the upper surface of the dielectric layer.

10. The method according to claim 7, wherein the protective layer in step (g) is a molding compound.

11. The method of claim 10, wherein the upper surface of the molding layer extends 20-50 μm above the top of the sacrificial copper pillar.

12. The method of claim 10, wherein step (h) further comprises: The molding layer is thinned to expose the top of the sacrificial copper pillar, and the sacrificial copper pillar is etched.

13. A method for cutting a packaging substrate unit, comprising the following steps: (a) Prepare a temporary support plate; (b) A first circuit layer is formed on at least one side of the temporary support plate, a first copper pillar layer is formed on the first circuit layer, a first dielectric layer is applied to cover the first circuit layer and the first copper pillar layer, the first dielectric layer is thinned to expose the first copper pillar layer, wherein the first copper pillar layer includes a first sacrificial copper pillar and a first conductive copper pillar, the first sacrificial copper pillar is located in a first cleaving channel, and a second cleaving channel of the first dielectric layer is pre-cut. (c) A second circuit layer is formed on the upper surface of the first dielectric layer, and the first circuit layer and the second circuit layer are connected through the first copper pillar layer; (d) Remove the temporary support plate; (e) A third copper pillar layer and a second copper pillar layer are formed on the first circuit layer and the second circuit layer, respectively, wherein the second copper pillar layer includes a second sacrificial copper pillar and a second conductive copper pillar, and the third copper pillar layer includes a third sacrificial copper pillar and a third conductive copper pillar, wherein the second sacrificial copper pillar and the third sacrificial copper pillar are located on the first cut track and the second cut track; (f) Apply a second dielectric layer and a third dielectric layer to the upper and lower surfaces of the first dielectric layer, respectively, and thin the second dielectric layer and the third dielectric layer to expose the second copper pillar layer and the third copper pillar layer, respectively; (g) A third circuit layer and a fourth circuit layer are formed on the second dielectric layer and the third dielectric layer, respectively. The second circuit layer and the third circuit layer are connected by the second conductive copper pillar, and the first circuit layer and the fourth circuit layer are connected by the third conductive copper pillar. (h) Attach the device on the third circuit layer, perform an etching protection treatment on the surface of the fourth circuit layer, and apply a protective layer on the second dielectric layer to protect the third circuit layer and the device; (i) Etch the first sacrificial copper pillar, the second sacrificial copper pillar and the third sacrificial copper pillar to expose the second cut path after pre-cutting, and complete the cutting process of the first cut path and the second cut path to obtain a single substrate unit through simple mechanical separation.

14. The method of claim 13, wherein the diameters of the second sacrificial copper pillar and the third sacrificial copper pillar are respectively greater than or equal to the diameter of the first sacrificial copper pillar, so as to completely cover the first sacrificial copper pillar.

15. The method of claim 13, wherein the etching protection treatment of the surface of the fourth circuit layer in step (h) includes tinning.

16. The method of claim 13, wherein the protective layer applied on the second dielectric layer in step (h) comprises a molding compound.

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