Side contact pads of a high-speed memory card

Abstract

A memory card includes a memory card body having a size configured to accommodate at least one integrated circuit die package. In some embodiments, the memory card body includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card further includes contact pads disposed on at least one of the plurality of side surfaces. The contact pads include a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] In various embodiments, the present disclosure relates to storing data at an integrated circuit, and more particularly to integrated circuit packages and related structures. Background Art

[0002] The term "die" in the field of integrated circuits refers to a small piece of semiconductor material on which a circuit is fabricated. Typically, dies are fabricated as part of a single wafer that includes multiple individual dies, where fabrication techniques (e.g., deposition, removal, patterning, etc.) are used to form the components and features of each die. Each die is connected to a package that allows the packaged die or "chip" to be connected to a circuit board or other suitable device. Non-volatile storage devices such as universal serial bus (USB) flash drives or removable memory cards implement integrated circuits and have improved the portability of data and software applications. However, as the package size of storage devices shrinks, the space for contact pads also shrinks. Summary of the Invention

[0003] A device for a memory card is presented, the device including a memory card body sized to accommodate at least one integrated circuit die package. In a particular embodiment, the memory card body includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The memory card further includes contact pads disposed on at least one of the plurality of side surfaces. The contact pads include a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

[0004] A system for a memory card body is presented, the memory card body having a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The system further includes an integrated circuit die package disposed within the memory card body. The integrated circuit die package includes a plurality of contact pads disposed on at least one of the plurality of side surfaces, and wherein the contact pads include alternating layers of conductive material and insulating material. The integrated circuit die package further includes: a memory stack including a plurality of integrated circuit dies; and a controller configured to transfer data to and receive data from the plurality of integrated circuit dies.

[0005] Other devices for removable memories are proposed. In one embodiment, the device includes a member for accommodating at least one integrated circuit die package, wherein the member for accommodating includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface. The other device further includes a member for electrically communicating with a computing device, wherein the member for electrical communication is disposed on at least one of the plurality of side surfaces. In a particular embodiment, the member for electrical communication further includes a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer.

[0006] Methods are also proposed. In one embodiment, the method includes providing a memory card body. In certain embodiments, the method further includes providing at least one contact pad located on a side surface of the memory card body. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] A more specific description will now be made with reference to the specific embodiments shown in the accompanying drawings. It is to be understood that these drawings only depict certain embodiments of the present disclosure and should not be considered as limiting its scope. By using the drawings, the present disclosure will be described and explained with additional features and details, wherein:

[0008] Figure 1 is a perspective view showing a memory card (e.g., a data storage device) according to an embodiment of the present disclosure;

[0009] Figure 2 is a schematic block diagram showing a cross-sectional view of a memory card according to an embodiment of the present disclosure;

[0010] Figure 3 is a schematic block diagram showing a cross-sectional view of a memory card according to an embodiment of the present disclosure;

[0011] Figure 4 is a schematic block diagram showing a partial cross-sectional view of a manufacturing process for creating an integrated circuit die package with side contact pads according to an embodiment of the present disclosure;

[0012] Figure 5 is a schematic block diagram showing the process steps of a multi-layer block according to an embodiment of the present disclosure;

[0013] Figure 6 is a schematic block diagram of an embodiment of a computing system for implementing the above-described memory card 100 with side contact pads according to an embodiment of the present disclosure; and

[0014] Figure 7 is a flowchart showing an embodiment of a method for forming a data storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure may be implemented as an apparatus, system, or method. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, or an embodiment combining software and hardware aspects, which may generally be referred to herein as "circuitry", "module", "apparatus", or "system".

[0016] Many of the functional units described in this specification have been labeled as modules to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit including a custom VLSI circuit or a gate array, such as a logic chip, die, transistor, or other off-the-shelf semiconductor of discrete components. A module may also be implemented in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, etc.

[0017] A module may also be implemented at least partially in software for execution by various types of processors. The identified executable code modules may include, for example, one or more physical or logical blocks of computer instructions, which may be organized, for example, as objects, procedures, or functions. However, the executable files of the identified modules need not be physically located together, but may include different instructions stored in different locations, which, when logically combined, include the module and implement the stated purpose of the module.

[0018] As used herein, a component includes a tangible, physical, non-transitory device. For example, a component may be implemented as: a hardware logic circuit including a custom VLSI circuit, a gate array, or other integrated circuit; an off-the-shelf semiconductor such as a logic chip, die, transistor, or other discrete device; and / or other mechanical or electrical devices. A component may also be implemented in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, etc. A component may include one or more silicon integrated circuit devices (e.g., chips, dies, die flats, packages) or other discrete electrical devices that communicate electrically with one or more other components via electrical lines of a printed circuit board (PCB). In certain embodiments, each module described herein may alternatively be implemented by or as a component.

[0019] The circuits used herein include a group of one or more electrical and / or electronic components that provide one or more current paths. In some embodiments, the circuit may include a return path for current such that the circuit is a closed loop. However, in another embodiment, a group of components that do not include a return path for current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is grounded (as a return path for current). In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a group of integrated circuits, a group of non-integrated electrical and / or electronic components with or without integrated circuit devices, etc. In one embodiment, a circuit may include: a custom VLSI circuit, a gate array, a logic circuit, or other integrated circuits; off-the-shelf semiconductors such as logic chips, die, transistors, or other discrete devices; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit (e.g., as firmware, a netlist, etc.) in a programmable hardware device such as a field programmable gate array, a programmable array logic, a programmable logic device, etc. A circuit may include one or more silicon integrated circuit devices (e.g., chips, die, die flats, packages) or other discrete electrical devices that are in electrical communication with one or more other components via wires of a printed circuit board (PCB). In some embodiments, each module described herein may be implemented or realized as a circuit.

[0020] Throughout the specification, references to "one embodiment", "an embodiment", or similar language mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment", "in an embodiment", and similar language throughout the specification may, but do not necessarily, all refer to the same embodiment, but rather refer to "one or more but not all embodiments" unless expressly stated otherwise. Unless expressly stated otherwise, the terms "comprises", "comprising", "has", and their variants mean "including but not limited to". Unless expressly stated otherwise, a list of recited items does not imply that any or all of the items are mutually exclusive and / or mutually inclusive. Unless otherwise expressly indicated, the terms "a", "an", and "the" also refer to "one or more".

[0021] Note that, in some alternative embodiments, the functions indicated in the boxes may not occur in the order indicated in the figures. For example, depending on the functions involved, two boxes shown consecutively may actually be performed substantially simultaneously, or sometimes the boxes may be performed in the reverse order. Other steps and methods may be envisioned that are equivalent in function, logic, or effect to one or more boxes or portions thereof of the illustrated figures. Although various arrow types and line types may be employed in the flowcharts and / or block diagrams, it should be understood that they do not limit the scope of the corresponding embodiments. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between the recited steps of the depicted embodiment.

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The foregoing summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, other aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each drawing may refer to elements in the previous drawings. Like numerals in the drawings may refer to like elements, including alternative embodiments of like elements.

[0023] Figure 1 FIG. 1 is a perspective view showing a memory card 100 (e.g., a data storage device) according to an embodiment of the present disclosure. As will be discussed in more detail below, the memory card 100 includes a memory card body (“body”) 102 that has been disposed within an integrated circuit die (ICD) substrate. The ICD substrate is configured to support a plurality of stacked integrated circuit dies. As used herein, an integrated circuit die includes one or more fabricated circuits and / or other electrical components (e.g., a monolithic integrated circuit, etc.). For example, an integrated circuit die may include a semiconductor device (e.g., silicon, gallium arsenide, etc.) having one or more gates, transistors, capacitors, resistors, diodes, power supplies, amplifiers, traces, vias, other electrical connections, electrical contacts, and / or other integrated electrical components. Integrated circuit dies may be fabricated using lithographic and / or chemical processes, where one or more layers of semiconductor, metal, or other conductors, insulators, etc. are deposited on and / or removed from a semiconductor substrate to form the circuits.

[0024] In one embodiment, a plurality of chips, die planes, dies, and / or other integrated circuit dies may be stacked or otherwise combined into a plurality of integrated circuit die arrangements. For example, a plurality of integrated circuit dies may be stacked and laterally offset relative to adjacent integrated circuit dies (see Figure 3 and Figure 4), to provide space for electrical connection. In some embodiments, multiple integrated circuit dies may be directly or indirectly coupled to the same ICD substrate or chip carrier and may communicate with each other through the ICD substrate and / or the chip carrier. Multiple integrated circuit dies may be disposed within the same body 102 (e.g., for protection, mechanical support, etc.), and the body may be formed of resin, plastic, or other polymers, ceramics, and / or other rigid materials that house and / or encapsulate the integrated circuit dies. To communicate with the integrated circuit dies, one or more electrical traces, pins, or contact pads 104 extend from the integrated circuit dies through the body 102 to the outer surface of the body 102 to support electrical communication leaving the body 102.

[0025] Although the depicted memory card 100 is an example of a nano Secure Digital (SD) card, it should be understood that the embodiments described and illustrated herein may be applied to other memory cards 100. Examples of other memory cards 100 include, but are not limited to, Secure Digital cards, miniSD TM cards (a trademark of SD-3C LLC, Wilmington, Delaware), MultiMediaCard TM cards (a trademark of JEDEC Solid State Technology Association, Arlington, Virginia), cards (a trademark of JEDEC Solid State Technology Association, Arlington, Virginia), SD Express, SD and SIM card combinations for phones, etc.

[0026] The size of the body 102 is determined to be insertable into a memory card reader 106. The card reader 106 is operatively coupled to a host computing device (see Figure 6 ). Examples of the card reader 106 include, but are not limited to, a memory card housing that slidably receives the memory card 100, a tray into which the memory card 100 is inserted, etc. As is well known, the card reader 106 includes electrical contacts for interfacing with the contact pads 104 to facilitate data transfer (e.g., reading and writing) between the host computing device and the memory card 100.

[0027] In some embodiments, the body 102 includes a first surface (e.g., top surface 108) that is spaced apart from a second surface (e.g., bottom surface 110). One or more side surfaces (collectively referred to as side surfaces 112 and individually referred to as first side surface 112a, second side surface 112b... nth side surface 112n) couple the top surface 108 to the bottom surface 110 and enclose the region between the top surface 108 and the bottom surface 110. Generally, a memory storage card includes contact pads 104 disposed on the top surface 108 or the bottom surface 110. Initially, the storage card has sufficient surface area to support two or more contact pads 104 thereon. However, over time, generally, the size of the storage card is reduced, and the area on which the contact pads 104 are disposed is decreased. Additionally, as the read / write speed increases, the need for additional high-speed contact pads also increases. Advantageously, embodiments of the present disclosure provide contact pads 114 disposed on the side surfaces 112 of the body 102.

[0028] In certain embodiments, one or more side contact pads 114 (collectively referred to as side contact pads 114 and individually referred to as first side contact pad 114a, second side contact pad 114b, etc.) may be positioned on the side surfaces 112 (e.g., see first side surface 112a or second side surface 112b). The side contact pads are configured to electrically couple the storage card 100 to a storage card reader 106. In some embodiments, a single side contact pad 114 is positioned on the side surface 112 (e.g., see third side surface 112c or fourth side surface 112d). In certain embodiments, the transmit / receive (TX / RX) pairs of side contact pads 114a, 114b are located on the same side surface (see, e.g., side surface 112a). In some embodiments, the TX / RX pairs of side contact pads 114 are disposed opposite to each other. For example, the transmit side contact pad 114a is positioned opposite to its receive side contact pad 114e. Advantageously, due to the available additional contact pads, the side contact pads 114 enable high-speed communication. A fifth side contact pad 114c and a sixth side contact pad 114f are also disclosed.

[0029] Figure 2 is a schematic block diagram showing a cross-sectional view of a storage card 100 according to an embodiment of the present disclosure. As described above, the storage card 100 is formed with one or more side contact pads 114 extending outward from the side surfaces 112 of the body 102. In certain embodiments, each side contact pad 114 includes a first conductive layer 202, a second conductive layer 204, and an insulating layer 206 (configured to insulate the first conductive layer 202 from the second conductive layer 204) or a dielectric layer, and the insulating layer 206 or the dielectric layer is disposed between the first conductive layer 202 and the second conductive layer 204.

[0030] In some embodiments, the first conductive layer 202 faces outward and is accessible from the exterior of the body 102. In other words, the side contact pads 114 extend from the interior region 208 of the body 102 to the region 210 outside the body 102. In some embodiments, the first conductive layer 202 and the second conductive layer 204 are formed of copper layers disposed on a non-conductive insulating layer 206. It is contemplated that any conductive material can be implemented as the first conductive layer 202 or the second conductive layer 204.

[0031] In some embodiments, the second conductive layer 204 is electrically coupled to ground or a ground plane. The second conductive layer 204 advantageously improves impedance control by allowing a return path for adjacent signals. The second conductive layer 204 also addresses EMI issues because the second conductive layer 204 acts as a ground shield, addressing the antenna effect of the side contact pads in a single-layer case and enabling high-speed data communication.

[0032] In some embodiments, the insulating layer 206 can surround the second conductive layer 204 on three sides, as shown. In other embodiments, the insulating layer 206 contacts a single side or a portion of a single side of the second conductive layer 204. Similarly, the insulating layer 206 can surround the first conductive layer on three sides.

[0033] Figure 3 is a schematic block diagram showing a cross-sectional view of a memory card 100 according to an embodiment of the present disclosure. In the depicted embodiment, the memory card 100 includes a plurality of side contact pads 114, each side contact pad 114 having at least an insulating layer and a conductive layer electrically coupled to a ground plane (see Figure 2 ). In some embodiments, the side contact pads 114 or pins are electrically coupled to a high-speed memory controller disposed within the body 102, which controls access to an integrated circuit die (e.g., a memory module, a memory package, etc.) described in more detail below with reference to Figure 2 .

[0034] In some embodiments, the side contact pad 114a is a ground (GND) pin. The body 102 can include a plurality of side contact pads 114a on each side of the body 102. High-speed data pins can be assigned to the side contact pads 114b, 114c, 114g, and 114f. In some embodiments, the transmit / receive (TX / RX) pair 302 includes a TX side contact pad 114b and an RX side contact pad 114g disposed opposite each other, as Figure 3As shown. In some embodiments, the TX / RX pair 302 includes side contact pads that are not disposed opposite each other. In some embodiments, a "data transmission channel" is formed by two TX / RX pairs 302 (e.g., differential pairs, etc.). Thus, the depicted embodiment shows a single data transmission channel, however, it is contemplated that any reasonable number of side contact pads 114 can be implemented to form any reasonable number of TX / RX pairs 302 (e.g., multiple differential pairs, multiple channels, etc.), and subsequently any reasonable number of data transmission channels. Power (PWR) 114h, clock (REFCLK) 114d, 114e, etc. can be assigned to other side contact pads.

[0035] Figure 4 is a schematic block diagram of a partial cross-sectional view showing a manufacturing process for creating an integrated circuit die package having side contact pads in accordance with an embodiment of the present disclosure. Generally, integrated circuit dies are mass-produced on a single wafer of a substrate material such as electronic-grade silicon. In certain embodiments, side contact pads 114 can be formed during the manufacturing process such that multi-layer blocks 402 are formed between adjacent memory stacks 404 and then cut through the multi-layer blocks 402 to form the side contact pads 114. Once cut, the newly separated integrated circuit die packages 406 can be placed within the body 102 of the memory card 100.

[0036] As described above, the body 102 of the memory card 100 can be configured to accommodate one or more memory stacks made of integrated circuit dies 409. For clarity, only a single integrated circuit die 409 is identified in Figure 4 , however, it should be understood that each offset layer in the memory stack 411 can be a separate integrated circuit die 409. In certain embodiments, each integrated circuit die 409 is electrically connected to the ICD substrate 408 via, for example, bonding wires 410, and the bonding wires 410 are electrically coupled to the controller 412 via electrical contacts (e.g., solder balls, pins, ports, traces, pillars, etc.). Although described as a single controller 412, in the example of a combined memory card / SIM card, the controller 412 can include a SIM controller and a memory controller. In some embodiments, the electrical contacts can be electrically and / or mechanically coupled using solder, wires, ports, clamps, clips, etc.

[0037] In some embodiments, the ICD substrate 408 may provide electrical connections (e.g., metal traces, metallized vias, conductive layers, and / or other conductive paths) between the top and bottom contact pads 104 and the side contact pads 114. For example, the traces, vias, etc. may include redistribution layers that generate electrical signals from one or more electrical contacts. One or more integrated circuit dies 409 may include electrical interconnections between different integrated circuit dies 409, such as the depicted bond wire 410 interconnections, such that one integrated circuit die 409 may communicate independently of the ICD substrate 408 and / or send data to one or more other integrated circuit dies 409 attached via the ICD substrate 408.

[0038] In some embodiments, the multi-layer block 402 is disposed on the ICD substrate 408 between adjacent memory stacks 411. The multi-layer block is formed of alternating layers of conductive and insulating materials. In the depicted embodiment, the multi-layer block 402 includes a first conductive layer 414, a first insulating layer 416, a second conductive layer 418, a second insulating layer 420, and a third conductive layer 422. In some embodiments, during the manufacturing process (identified by arrow 424), the integrated circuit die package 406 is separated, such that the multi-layer block becomes the side contact pads 114 with a first conductive layer 202, a second conductive layer 204, and an insulating layer 206. In other embodiments, the side contact pads 114 may be formed separately.

[0039] The integrated circuit die package 406 may include an encapsulation material for protecting the components described above Figure 4 The encapsulation material may include a resin, plastic, or other polymer, ceramic, and / or other rigid material that houses and / or encapsulates the integrated circuit die 409 and has one or more electrical traces, pins, contacts, etc. that extend from the integrated circuit die 409 (e.g., through the integrated circuit die 409 and / or the ICD substrate 408) through the integrated circuit die package 406 or other housing for external electrical communication outside of the package.

[0040] In one embodiment, multiple chips, die planes, dies, and / or other integrated circuit dies 409 may be stacked or otherwise combined in an arrangement of multiple integrated circuit dies 409 within an encapsulation material. For example, multiple integrated circuit dies 409 may be stacked and laterally offset relative to each other to provide space for electrical connections. In some embodiments, multiple integrated circuit dies 409 may be directly or indirectly coupled to the same ICD substrate 408 or chip carrier and may communicate with each other through the ICD substrate 408 and / or a controller 412. Multiple integrated circuit dies 409 may be disposed within the same integrated circuit die package 406 and / or housing (e.g., for protection, mechanical support, etc.), such as resin, plastic, or other polymers, ceramics, and / or other rigid materials that house and / or encapsulate the integrated circuit dies 409, having one or more electrical traces, pins, contacts, etc. that extend through the package from the integrated circuit dies 409.

[0041] Figure 5 is a schematic block diagram showing process steps of a multi-layer block 500 according to an embodiment of the present disclosure. In certain embodiments, the multi-layer block 402 may be formed by providing five alternating layers of conductive material 502 and insulating material 504. Arrow 506 graphically depicts the process step of joining the alternating layers of conductive material 502 and insulating material 504 together. Examples of suitable processes for joining the layers include, but are not limited to, lamination.

[0042] Arrow 508 graphically depicts the process step of splicing or cutting the multi-layer block into multiple smaller multi-layer blocks that can be positioned on the ICD substrate 408 and then cutting or splicing as described above Figure 4 into side contact pads 114. Dashed line 510 depicts the step of splicing the smaller multi-layer blocks to the side contact pads 114.

[0043] Figure 6 is a schematic block diagram of one embodiment of a computing system 600 for implementing the above-described memory card 100 having side contact pads 114 according to an embodiment of the present disclosure. Although the memory device 602 of the computing system 600 is used herein as an example of a system for the memory card 100, in other embodiments, multiple integrated circuit dies 409 may include one or more network interface controller (NIC) integrated circuit dies 409, one or more graphics processing unit (GPU) integrated circuit dies 409, one or more central processing unit (CPU) integrated circuit dies 409, and / or one or more other types of integrated circuit dies 409 that transmit and / or receive data.

[0044] In some embodiments, the memory device 602 of the computing device 610 may include a processor 611, volatile memory 612, and a communication interface 613. The processor 611 may include one or more central processing units, one or more general-purpose processors, one or more dedicated processors, one or more virtual processors (e.g., the computing device 610 may be a virtual machine running within a host), one or more processor cores, etc. The communication interface 613 may include one or more network interfaces configured to communicatively couple the computing device 610 and / or the device 626 to a communication network 615, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, etc.

[0045] In various embodiments, the memory device 620 may be disposed at one or more different locations relative to the computing device 610. In one embodiment, the memory device 620 includes one or more volatile and / or non-volatile storage elements 623 (e.g., stacked integrated circuit dies 409), such as semiconductor chips, dies, packages, or other integrated circuit devices disposed on one or more printed circuit boards, storage enclosures, and / or other mechanical and / or electrical support structures. For example, the memory device 620 may include one or more direct inline memory module (DIMM) cards, one or more expansion cards and / or daughter cards, memory cards, universal serial bus (USB) drives, solid state drive (SSD) or other hard drive devices, and / or may have other forms of memory and / or storage. The memory device 620 may be integrated with and / or mounted on the motherboard of the computing device 610, mounted in a port and / or slot of the computing device 610, mounted on a different computing device 610 and / or a dedicated storage device on the network 615, communicatively coupled to the computing device 610 via an external bus (e.g., an external hard drive), etc.

[0046] In one embodiment, the memory device 620 may be disposed on the memory bus of the processor 611 (e.g., on the same memory bus as the volatile memory 612, on a different memory bus from the volatile memory 612, instead of the volatile memory 612, etc.). In another embodiment, the memory device 620 may be disposed on the peripheral bus of the computing device 610, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, etc. In another embodiment, the memory device 620 may be disposed on the data network 615, such as Ethernet, Infiniband network, SCSI RDMA over network 615, Storage Area Network (SAN), Local Area Network (LAN), Wide Area Network (WAN), such as the Internet, another wired and / or wireless network 615, etc.

[0047] One or more integrated circuit dies 409 may include electrical interconnections between the integrated circuit dies 409 (e.g., one or more local buses, back channels, subnets, internal networks, internal buses, bond wires, circuit traces, etc.), such that one integrated circuit die 409 (e.g., an active integrated circuit) can send data to one or more other integrated circuit dies 409, and the integrated circuit dies 409 can send data in parallel (e.g., send it to the device controller 626, the processor 611, the computer-readable storage medium 614 via the data network 615, the bus 625, etc.).

[0048] According to various embodiments, the device controller 626 may manage one or more storage devices 620, memory elements (e.g., integrated circuit dies 409) and / or other integrated circuit devices. The (multiple) memory devices 620 may include recording, memory and / or storage devices, such as solid-state storage devices and / or semiconductor storage devices arranged and / or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of the memory (e.g., any number of physical storage media on the memory device 620). Memory units may include, but are not limited to, pages, memory partitions, blocks, sectors, a collection or group of physical storage locations (e.g., logical pages, logical blocks), etc.

[0049] The communication interface 613 may include one or more network interfaces configured to communicatively couple the computing device 610 and / or the device controller 626 to the network 615 and / or one or more remote ends, network-accessible storage clients 616. The storage clients 616 may include local storage clients 616 operating on the computing device 610 and / or remote storage clients 616 accessible via the network 615 and / or the communication interface 613. The device controller 626 is part of and / or communicatively coupled with one or more memory devices 620. Although Figure 6 a single memory device 620 is depicted, the present disclosure is not limited thereto and may be adapted to incorporate any number of memory devices 620.

[0050] The memory device 620 may include one or more integrated circuit dies 409 of volatile and / or non-volatile memory media 622, which may include but are not limited to: volatile memory such as SRAM and / or DRAM; non-volatile memory such as ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM or C-RAM), NAND flash (e.g., 2D NAND flash, 3D NAND flash), NOR flash, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, sub-10 nanometer process memory based on silicon oxide, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS), programmable metallization cell (PMC), conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disks, magnetic tapes) and / or optical storage media; or other memory and / or storage media. In certain embodiments, one or more integrated circuit dies 409 of the memory media 622 include storage class memory (SCM).

[0051] Although the memory medium 622 is referred to herein as a "memory medium", in various embodiments, the memory medium 622 can more generally include one or more volatile and / or non-volatile recording media capable of recording data, which can be referred to as memory media, storage media, and the like. Additionally, in various embodiments, the memory device 620 can include a recording device, a memory device, a storage device, and the like. Similarly, in various embodiments, the storage element 623 can include a recording element, a memory element, a storage element, and the like. In other embodiments, the storage element 623 can include different types of integrated circuit devices (e.g., ASIC, CPU, communication device, graphics device, system-on-chip, programmable logic device, etc.), and the storage element 623 is used only as an example as a type of integrated circuit device (e.g., integrated circuit die, chip, die plane, package, etc.), and other types of integrated circuit devices can be expected within the scope of the present disclosure.

[0052] The memory medium 622 can include one or more memory elements 623, which can include but are not limited to: chips, packages, dies, die planes, and the like. The device controller 626 can be configured to manage data operations on the memory medium 622 and can include one or more processors, programmable processors (e.g., FPGA), ASICs, microcontrollers, and the like. In some embodiments, the device controller 626 is configured to store data on and / or read data from the memory medium 622 to transfer data to / from the memory device 620, and so on. In certain embodiments, the memory medium 622 is a memory card 100, which communicates with the computing device 610 via a card reader 106 (see Figure 1 ) coupled to the computing device 610.

[0053] The device controller 626 can be communicatively coupled to the memory medium 622 and / or other integrated circuit dies 409 via a bus 627. The bus 625 can include an I / O bus for communicating data to / from the integrated circuits. The bus 627 can further include a control bus for transmitting addressing and other command and control information to the integrated circuit die 409. In some embodiments, the bus 627 can communicatively couple the integrated circuit die 409 in parallel to the device controller 626. This parallel access can allow the integrated circuits to be managed as a group (e.g., in embodiments where the integrated circuit die 409 includes memory elements to form a logical memory element 629, etc.). The logical memory element 629 can be divided into corresponding logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks). The logical memory units can be formed by logically combining the physical memory units of each integrated circuit die 409.

[0054] Figure 7FIG. 0 is a flowchart illustrating one embodiment of a method 700 for forming a data storage device according to an embodiment of the present invention. As used herein, a manufacturer (e.g., an assembly plant) includes a factory that obtains wafers having a plurality of integrated circuit dies and packages the dies into integrated circuit devices such as solid state storage devices.

[0055] Method 700 begins and the manufacturer provides 702 a memory card body 102. The memory card body may have a top surface and a bottom surface spaced from the top surface. Side surfaces 112 couple the top surface 108 to the bottom surface 110 and together form a region within the body 102 to receive an integrated circuit device package.

[0056] Method 700 also includes providing 704 at least one side contact pad 114 disposed on a side surface of the memory card body 102. In certain embodiments, the manufacturer creates a substrate having a plurality of memory stacks 404 with a plurality of multi-layer blocks 402 disposed between the memory stacks. The manufacturer then cuts or slices the substrate to form individual integrated circuit device packages. In certain embodiments, the manufacturer cuts through the multi-layer blocks 402 to form the side contact pads 114.

[0057] In various embodiments, a member for receiving at least one integrated circuit die package may include a memory card body having a top surface, a bottom surface, and side surfaces, etc. The body may be formed of two halves joined together to form the body. Other embodiments may include similar or equivalent members for receiving at least one integrated circuit die package.

[0058] In various embodiments, a member for communicating electrically with a computing device may include contact pads formed on a side surface of the member for receiving, etc. The contact pads may include a first conductive layer, a second conductive layer, and an insulating layer disposed between the first conductive layer and the second conductive layer. Other embodiments may include similar or equivalent members for communicating through a side surface of the member for receiving, including pins, traces, contacts, etc.

[0059] Without departing from the spirit or essential characteristics of the present disclosure, the present disclosure may be embodied in other specific forms. The described embodiments are to be considered in all respects only as illustrative and not restrictive. Thus, the scope of the present disclosure is defined by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Claims

1. A device, comprising: a memory card body sized to accommodate at least one integrated circuit die package, the memory card body including a first surface spaced from a second surface and a plurality of side surfaces connecting the first surface to the second surface; and contact pads disposed on at least one of the plurality of side surfaces, the contact pads including: a first conductive layer, wherein the first conductive layer is disposed on an outer surface of at least one side surface of the memory card body and configured to be electrically coupled to a memory card reader; a second conductive layer, the second conductive layer being disposed within the memory card body and electrically coupled to ground, and wherein the second conductive layer is insulated from the first conductive layer; and an insulating layer disposed between the first conductive layer and the second conductive layer.

2. The device according to claim 1, wherein the contact pads include a first contact pad, and at least one of the plurality of side surfaces includes a first side surface, and the device further includes a second contact pad disposed on the first side surface.

3. The device according to claim 2, further comprising: a third contact pad disposed on a second side surface positioned opposite the first side surface; and a fourth contact pad disposed on the second side surface.

4. The device according to claim 3, wherein, the third contact pad is configured to transfer data to a memory card reader.

5. The device according to claim 3, wherein, the fourth contact pad is configured to receive data from a memory card reader.

6. The device according to claim 3, further includes a fifth contact pad disposed on a third side surface.

7. The device according to claim 6, further includes a sixth contact pad disposed on a fourth side surface positioned opposite the third side surface.

8. A system, comprising: a memory card body including a first surface spaced from a second surface and a plurality of side surfaces connecting the first surface to the second surface; and an integrated circuit die package disposed within the memory card body, the integrated circuit die package including: a plurality of contact pads disposed on at least one of the plurality of side surfaces, the contact pads including alternating layers of a conductive material and an insulating material, wherein a first layer of the alternating layers is insulated from a second conductive layer of the alternating layers, and wherein the second conductive layer is electrically coupled to ground; a memory stack including a plurality of integrated circuit dies; and a controller configured to transfer data to and receive data from the plurality of integrated circuit dies.

9. The system according to claim 8, wherein the first layer of the alternating layers is disposed on an outer surface of at least one side surface of the memory card body and configured to be electrically coupled to a memory card reader.

10. The system according to claim 9, further includes a third layer of the alternating layers, wherein the third layer is disposed within the memory card body and configured to insulate the first layer from the second layer of the alternating layers.

11. The system according to claim 10, wherein, the second layer is disposed within the memory card body.

12. The system according to claim 8 further includes a first contact pad and a second contact pad among the plurality of contact pads disposed on a first side surface of the plurality of side surfaces.

13. The system according to claim 12 further includes a third contact pad and a fourth contact pad among the plurality of contact pads disposed on a second side surface of the plurality of side surfaces.

14. The system according to claim 13, wherein, the third contact pad is configured to transmit data to a memory card reader.

15. The system according to claim 13, wherein, the fourth contact pad is configured to receive data from a memory card reader.

16. The system according to claim 13 further includes a fifth contact pad among the plurality of contact pads disposed on a third side surface of the plurality of side surfaces.

17. The system according to claim 16 further includes a sixth contact pad among the plurality of contact pads disposed on a fourth side surface of the plurality of side surfaces, the fourth side surface being positioned opposite to the third side surface.

18. An apparatus, comprising: a member for accommodating at least one integrated circuit die package, wherein the member for accommodating includes a first surface spaced apart from a second surface and a plurality of side surfaces connecting the first surface to the second surface; and a member for electrically communicating with a computing device, wherein the member for electrical communication is disposed on at least one of the plurality of side surfaces, and the member for electrical communication includes: a first conductive layer, wherein the first conductive layer is disposed on an outer surface of one of the plurality of side surfaces and is configured to be electrically coupled to a memory card reader; a second conductive layer, the second conductive layer being disposed within the member for accommodating and electrically coupled to ground, and wherein the second conductive layer is insulated from the first conductive layer; and an insulating layer disposed between the first conductive layer and the second conductive layer.

Images