Successive approximation analog-to-digital conversion circuit and method of operation thereof

Abstract

A successive approximation analog-to-digital conversion circuit and a method of operating the same are disclosed. The successive approximation analog-to-digital conversion circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The plurality of latch circuits are coupled to the comparator circuit and are serially connected to each other. The plurality of latch circuits are sequentially triggered to store comparator outputs of the comparator circuit in response to a plurality of trigger signals, respectively, and to generate a digital signal accordingly. A first latch circuit and a second latch circuit of the plurality of latch circuits are triggered in response to a first trigger signal and a second trigger signal of the plurality of trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal based on the comparator output stored in the first latch circuit. The successive approximation analog-to-digital conversion circuit is capable of providing more time margin for a settling time of a digital-to-analog converter.

Description

TECHNICAL FIELD

[0001] The present application relates to signal conversion, and more particularly to a successive approximation analog-to-digital conversion circuit including a plurality of latch circuits connected in series with each other to implement a successive approximation algorithm, and a method of operating the successive approximation analog-to-digital conversion circuit. BACKGROUND

[0002] Successive-approximation-register analog-to-digital converters (SAR ADCs) are popular due to their low power consumption, simple structure, and small form factor. The basic operation principle of a SAR ADC is to use a series of comparison operations to implement a binary search algorithm to determine each bit of a digital signal converted from an analog signal. The number of bit cycles required to convert the analog signal can be determined according to the resolution of the SAR ADC. To increase the sampling rate, different types of SAR ADCs have been proposed, such as multi-bit / step SAR ADCs, time-interleaved SAR ADCs, asynchronous SAR ADCs, and SAR ADCs using non-binary search algorithms. For example, an asynchronous SAR ADC can provide an internally generated clock to increase the sampling rate. SUMMARY

[0003] Embodiments of the present application disclose a successive approximation analog-to-digital conversion circuit including a plurality of latch circuits connected in series with each other to implement a successive approximation algorithm, and a method of operating the successive approximation analog-to-digital conversion circuit.

[0004] Certain embodiments of the present disclosure disclose a successive approximation analog-to-digital conversion circuit. The successive approximation analog-to-digital conversion circuit includes a comparator circuit and a plurality of latch circuits. The comparator circuit is configured to compare an analog signal with a plurality of reference levels. The plurality of latch circuits are coupled to the comparator circuit and are serially connected to each other. The plurality of latch circuits are sequentially triggered to store comparator outputs of the comparator circuit in response to a plurality of trigger signals, respectively, and to generate a digital signal in accordance therewith. A first latch circuit and a second latch circuit of the plurality of latch circuits are triggered in response to a first trigger signal and a second trigger signal of the plurality of trigger signals, respectively. The first latch circuit is configured to generate the second trigger signal in accordance with the comparator output stored in the first latch circuit.

[0005] Certain embodiments of the present disclosure disclose a successive approximation analog-to-digital conversion circuit. The successive approximation analog-to-digital conversion circuit includes a comparator circuit, N latch stages, and (N-1) delay stages. N is an integer greater than 1. The comparator circuit is configured to compare an analog signal with a plurality of reference levels in N comparison periods, respectively. The N latch stages are coupled to the comparator circuit and are configured to store comparator outputs of the comparator circuit generated in the N comparison periods as N data signals, respectively, and to generate a digital signal in accordance therewith. Each latch stage is configured to output a first valid signal indicating whether the data signal stored in the latch stage is valid. Each delay stage is coupled to two consecutive latch stages of the N latch stages and is configured to delay the first valid signal output from one of the two consecutive latch stages to generate a trigger signal and to trigger the other of the two consecutive latch stages in accordance with the trigger signal.

[0006] Certain embodiments of the present disclosure disclose a method of operating a successive approximation analog-to-digital conversion circuit. The method includes comparing an analog signal with a plurality of reference levels in a plurality of consecutive comparison periods using a comparator circuit of the successive approximation analog-to-digital conversion circuit, wherein the plurality of comparison periods includes a first comparison period and a second comparison period; enabling a first latch circuit to store a comparator output of the comparator circuit generated in the first comparison period and to generate a trigger signal in accordance therewith; enabling a second latch circuit to store the comparator output generated in the second comparison period in accordance with the trigger signal; and generating at least a portion of a digital signal in accordance with the comparator output stored in the first latch circuit and the comparator output stored in the second latch circuit.

[0007] By the successive approximation control scheme disclosed in the present application, a latch circuit can trigger a next latch circuit according to a data signal latched therein. The aforementioned next latch circuit can be triggered before a comparator output to be stored is valid. Therefore, the successive approximation control scheme disclosed in the present application can provide more time margin for a settling time of a digital-to-analog converter. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a functional block diagram of an exemplary successive approximation analog-to-digital conversion circuit according to certain embodiments of the present application.

[0009] Figure 2 is a flowchart of an exemplary method of operating a successive approximation analog-to-digital conversion circuit according to certain embodiments of the present application.

[0010] Figure 3 is a schematic diagram of an embodiment of a control circuit according to certain embodiments of the present application. Figure 1

[0011] Figure 4 is a schematic diagram of an embodiment of a control circuit according to certain embodiments of the present application. Figure 3

[0012] Figure 5 is a schematic diagram of another embodiment of a control circuit according to certain embodiments of the present application. Figure 1

[0013] Figure 6 is a schematic diagram of an embodiment of a latch element according to certain embodiments of the present application. Figure 5

[0014] Figures 7A to 7C is a schematic diagram of a self-latching operation of a latch stage according to certain embodiments of the present application. Figure 3

[0015] Figure 8 is a schematic diagram of an embodiment of a latch element according to certain embodiments of the present application. Figures 7A to 7C

[0016] Figures 9A to 9C is a schematic diagram of a self-latching operation of a latch stage according to certain embodiments of the present application. Figure 8

[0017] Figure 10 is a flowchart of a method of operating a successive approximation analog-to-digital conversion circuit according to certain embodiments of the present application. DETAILED DESCRIPTION

[0018] ​​​​​​​The following disclosure discloses various implementations or examples that can be used to implement different features of the present disclosure. The specific examples of parameter values, components, and configurations described below are used to simplify the present disclosure. When possible, these descriptions are merely illustrative, and are not intended to limit the present disclosure. For example, the present disclosure can repeatedly use component symbols and / or numbers in the embodiments. Such repeated use is based on the purpose of simplicity and clarity, and does not in itself represent a relationship between the different embodiments and / or configurations discussed.

[0019] In addition, it can be understood that if an element is described as being "connected to" or "coupled to" another element, it can be directly connected or coupled to, or there can be other intervening elements between them.

[0020] When the comparator output generated in the current comparison cycle reaches a valid logic state, a successive approximation register (SAR) analog-to-digital conversion circuit (SAR ADC circuit, hereinafter referred to as "SAR ADC circuit") can wait for a time delay to provide sufficient time for the digital-to-analog converter (DAC) to settle down. After the time delay, the SAR ADC circuit triggers the next comparison cycle. However, the high-speed successive approximation analog-to-digital conversion structure can provide less time margin for the digital-to-analog converter (DAC) settling time, resulting in insufficient time for the digital-to-analog converter to settle down, causing conversion errors.

[0021] This application discloses exemplary SAR ADC circuits, each of which includes multiple latch circuits connected in series to implement a successive-approximate algorithm. These latch circuits can be part of the SAR control logic of the SAR ADC circuit. For example, an exemplary N-bit SAR ADC circuit can utilize N latch circuits connected in series to control a digital-to-analog conversion operation. These N latch circuits are sequentially triggered to generate N bits corresponding to a digital signal. One latch circuit generates a trigger signal based on a comparator output stored therein, and another latch circuit following the first latch circuit is triggered in response to the trigger signal generated by the first latch circuit. In some embodiments, at least one latch circuit can be triggered before the comparator output stored therein becomes valid. Therefore, when a valid logic state is reached, the comparator output can be immediately stored in the corresponding latch circuit. The time delay caused by the successive-approximate control logic can thus be reduced. The N-bit SAR ADC circuit allows sufficient time for the digital-to-analog converter to stabilize. Further explanation follows.

[0022] Figure 1 This is a block diagram of an exemplary SAR ADC circuit according to certain embodiments of this application. The SAR ADC circuit 100 is used to convert an analog signal A... IN Converted into a digital signal D OUT It can be an N-bit digital code. The SAR ADC circuit 100 can sample the analog signal A during one sampling phase of a conversion cycle. IN And a conversion phase following the sampling phase in the conversion period, converting analog signal A... IN Converted to digital signal D OUT Before the conversion result of the SAR ADC circuit 100 converges to a digital word, the analog signal A... IN The signal level can be compared with different quantization levels during the conversion phase.

[0023] The SAR ADC circuit 100 includes (but is not limited to) a digital-to-analog converter 110, a comparator circuit 120, and a control circuit 130. The digital-to-analog converter 110 can control the analog signal A... IN A digital signal DS and at least one reference signal V REF To provide analog signal V DACIn this embodiment, the digital-to-analog converter 110 can be implemented using a capacitive digital-to-analog converter, which itself provides a sample and hold function. Analog signal A IN This can be implemented as multiple voltage signals VIP and VIN, where the difference between the multiple voltage signals VIP and VIN can represent the analog signal A. IN The digital-to-analog converter 110 can process the analog signal A according to a control signal CKS. IN A sample-and-hold operation is performed, where the control signal CKS is used to control the analog signal A. IN The sampling operation. For example, at least one sampling switch of the digital-to-analog converter 110 ( Figure 1 (Not shown) can be selectively turned on according to the control signal CKS. The at least one sampling switch can be turned on during the sampling phase and turned off during the conversion phase. Furthermore, the digital-to-analog converter 110 can output multiple voltage signals VXP and VXN, wherein the difference between the multiple voltage signals VXP and VXN can represent the analog signal V. DAC The signal level difference (i.e., analog signal V) between multiple voltage signals VXP and VXN. DAC The signal level can change in response to the digital signal DS. At least one reference signal V REF It may include at least one of the power supply voltage, ground voltage, and common-mode voltage.

[0024] Comparator circuit 120 is coupled to digital-to-analog converter 110 to convert analog signal A IN The voltage signal VXP is compared with N reference levels. In this embodiment, the comparator circuit 120 is used to compare the voltage signal VXP with the voltage signal VXN, thereby comparing the analog signal A with N reference levels. IN The voltage signal VXP is compared with the N reference levels. For example, the comparator circuit 120 can compare the voltage signal VXP and the voltage signal VXN multiple times in multiple comparison cycles. The signal level difference between multiple voltage signals VXP and VXN in one comparison cycle is different from the signal level difference between multiple voltage signals VXP and VXN in another comparison cycle. By comparing the voltage signal VXP and the voltage signal VXN in different comparison cycles, the comparator circuit 120 can compare the analog signal A. IN It compares with different reference levels. Furthermore, the comparator circuit 120 can generate a comparator output C in each comparison cycle. OUT The comparator outputs C. OUT It can indicate the signal level difference between multiple voltage signals VIP and VIN (i.e., analog signal A). IN The signal level is greater than or less than one of the N reference levels. The comparator output C OUT It can be implemented as multiple voltage signals VOP and VON.

[0025] The control circuit 130 is coupled to the digital-to-analog converter 110 and the comparator circuit 120 for generating the digital signal D OUT based on the comparator output C OUT and the digital signal DS. The control circuit 130 further generates an enable signal EN_D for selectively enabling the comparator circuit 120. Each time the comparator circuit 120 is enabled, a comparison cycle is started. When the comparator circuit 120 is disabled, the comparator output C OUT may be reset.

[0026] The control circuit 130 includes, but is not limited to, a plurality of latch circuits 140.1-140.N and an enable circuit 150. The plurality of latch circuits 140.1-140.N are coupled to the comparator circuit 120 and are serially connected to each other. The plurality of latch circuits 140.1-140.N are sequentially triggered in response to a plurality of trigger signals TG[N-l]-TG[0] respectively, to store the comparator output C OUT and to generate the digital signal D OUT based thereon. For example, the plurality of latch circuits 140.1-140.N can store the comparator output C OUT as N data signals D[N-l]-D[0] and generate the digital signal D OUT based on the N data signals D[N-l]-D[0].

[0027] In addition, a latch circuit can generate a trigger signal based on the comparator output C OUT stored therein, which is used to trigger a next latch circuit located after the latch circuit. For example, the latch circuit 140.1 can be triggered first to store the comparator output C OUT and to generate a most significant bit (MSB) of the digital signal D OUT based thereon. The latch circuit 140.1 can generate a trigger signal TG[N-2] based on the comparator output C OUT stored therein (i.e. the data signal D[N-l]). Next, the latch circuit 140.2 can be triggered in response to the trigger signal TG[N-2] to store the comparator output C OUT .

[0028] In this embodiment, the comparator circuit 120 can compare the analog signal A N with N reference levels in N consecutive comparison cycles CC1-CC IN respectively. The plurality of latch circuits 140.1-140.N can store the comparator outputs C N generated in the N comparison cycles CC1-CC OUTAt least one of the plurality of latch circuits 140.1-140.N can be triggered in a comparison cycle in which the comparator output C OUT becomes valid (or before the comparator output becomes valid). When the valid logic state is reached, the comparator output C OUT may be considered valid.

[0029] For example, the latch circuit 140.1 can be triggered in response to a trigger signal TG[N-l] before the comparator output C OUT is generated or becomes valid. When the signal level difference between the plurality of voltage signals VOP and VON reaches a threshold level, it indicates that the comparator output C OUT is a valid output. Notably, once the comparator output C OUT is valid, the latch circuit 140.1 can latch the comparator output C OUT without (or with little) delay. The control circuit 130 can reserve more time for the digital-to-analog converter 110 to settle. In some embodiments, the trigger signal TG[N-l] can be implemented using the control signal CKS. When the control signal CKS indicates that the sampling operation of the analog signal A IN is ongoing or has not ended, the latch circuit 140.1 is not triggered. When the control signal CKS indicates that the sampling operation of the analog signal A IN has ended, the latch circuit 140.1 is triggered.

[0030] Similarly, the latch circuit 140.2 can be triggered in response to a trigger signal TG[N-2] before the comparator output C OUT is generated or becomes valid. In some embodiments, the latch circuit 140.2 can be triggered before the comparator circuit 120 enters a comparison cycle in which the comparator output C OUT that the latch circuit 140.2 desires to store is generated. Notably, when the latch circuit 140.2 is triggered to store the comparator output C OUT in response to the trigger signal TG[N-2], the latch circuit 140.1 can be uncoupled from the comparator output C OUT such that the data signal D[N-l] stored therein is not disturbed by the following comparison operation. Similarly, when the latch circuit 140.N is triggered to store the comparator output C OUT in response to the trigger signal TG[0], the plurality of latch circuits 140.1-140.(N-l) can be uncoupled from the comparator output C OUT .

[0031] The enable circuit 150 is coupled to the comparator circuit 120 to at least trigger the plurality of latch circuits 140.1-140.N by detecting the comparator output COUT The comparator circuit 120 can be selectively enabled based on the enable signal EN_D. For example, the enable circuit 150 can detect whether the signal level difference between multiple voltage signals VOP and VON reaches a threshold level to generate an active signal VD. When the signal level difference between multiple voltage signals VOP and VON reaches the threshold level, the active signal VD can indicate the comparator output C. OUT Effective. Enable circuit 150 generates an enable signal EN_D to disable comparator circuit 120, thereby resetting the comparator output C. OUT The comparator circuit 120 is ready to enter the next comparison cycle.

[0032] In some embodiments, the enable circuit 150 may generate an enable signal EN_D based on the control signal CKS. For example, when the control signal CKS indicates analog signal A... IN When the sampling operation is in progress, the enable circuit 150 can generate an enable signal EN_D to disable the comparator circuit 120, thereby resetting the comparator output C. OUT In some embodiments, the enable circuit 150 may generate an enable signal EN_D based on a valid signal CKO[0], wherein the valid signal CKO[0] indicates whether the data signal D[0] stored / latched in the latch circuit 140.N is valid. The latch circuit 140.N can be used to generate the digital signal D. OUT The least significant bit (LSB). For example, when the valid signal CKO[0] indicates that the data signal D[0] is valid, the enable circuit 150 can generate an enable signal EN_D to disable the comparator circuit 120, thereby resetting the comparator output C. OUT .

[0033] Figure 2 This is a flowchart illustrating an exemplary method of operating a SAR ADC circuit according to certain embodiments of this application. Method 200 can be applied to... Figure 1 The SAR ADC circuit 100 shown provides a greater time margin for the settling time of the digital-to-analog converter. For ease of explanation, method 200 is described below in conjunction with SAR ADC circuit 100. It is worth noting that method 200 can be applied to other SAR ADC circuits without departing from the scope of this application. Furthermore, in some embodiments, method 200 may include other operations. In some embodiments, the operation of method 200 may be performed in a different order, and / or in other implementations.

[0034] In operation 202, an analog signal is compared with N different reference levels in N consecutive comparison cycles to generate a comparator output in each comparison cycle. For example, comparator circuit 1420 is configured to compare the analog signal A IN with a reference level in comparison cycle CC1 by comparing voltage signal VXP with voltage signal VXN, and to compare the analog signal A IN with another reference level in comparison cycle CC2 by comparing voltage signal VXP with voltage signal VXN. The signal level difference between voltage signals VXP and VXN in comparison cycle CC1 is different from the signal level difference between voltage signals VXP and VXN in comparison cycle CC2. The comparator output C OUT is available or ready for use when reaching a valid logic state.

[0035] In operation 204, the comparator output is reset. For example, when latch circuit 140.1 stores the comparator output C OUT generated in comparison cycle CC1 as data signal D[N-1], comparator circuit 120 is configured to reset the comparator output C OUT according to an enable signal EN_D. When the comparator output C OUT is reset, voltage signals VOP and VON can be at the same or substantially the same signal level.

[0036] In operations 206.1-206.N, N latch circuits of the SAR ADC circuit are sequentially triggered to store the comparator outputs generated in the N consecutive comparison cycles, respectively. In operation 206.1, latch circuit 140.1 is configured to store the comparator output C OUT generated in comparison cycle CC1 and available. Latch circuit 140.1 is further configured to generate data signal D[N-1] based on the stored comparator output C OUT . In operation 206.2, latch circuit 140.2 is triggered to store the comparator output C OUT generated in comparison cycle CC2 and ready for use based on at least data signal D[N-1] stored in latch circuit 140.1. For example, when data signal D[N-1] is valid, latch circuit 140.1 is configured to generate a trigger signal TG[N-2] to trigger latch circuit 140.2. For another example, when data signal D[N-1] is valid and the comparator output C OUTWhen reset or rendered unavailable, latch circuit 140.1 can generate a trigger signal TG[N-2] to trigger latch circuit 140.2. Similarly, in operation 206.N, latch circuit 140.N is triggered at least according to the data signal D[1] latched in latch circuit 140.(N-1), thereby storing the comparator output C. OUT It originates from the comparison period CC N It is available.

[0037] The N latch circuits connected in series allow one latch circuit to trigger the next latch circuit based on the data signal latched therein. This next latch circuit can be triggered before the comparator output to be stored becomes valid. For example, latch circuit 140.2 can be triggered by latch circuit 140.1 during comparison cycle CC1. Therefore, when it becomes a valid output, the comparator output C generated in comparison cycle CC2... OUT It can be immediately stored in the latch circuit 140.2. The successive approximation control scheme disclosed in this application can provide more time margin for the stabilization time of the digital-to-analog converter.

[0038] Figure 1 The circuit structures shown are for illustrative purposes and are not intended to limit the scope of this application. For example, Figure 1 The digital-to-analog converter 110 shown can be implemented using a sample-and-hold circuit and a digital-to-analog converter that are set up separately from each other. Figure 1 The comparator circuit 120 shown compares the output of the sample-and-hold circuit with the output of the digital-to-analog converter to generate a comparator output C. OUT Any modifications and design variations that occur within the scope of this application, provided that the successive approximation control logic circuit includes multiple latch circuits connected in series, and one latch circuit triggers the next latch circuit based on the latched data, are within the scope of this application.

[0039] To facilitate understanding of the content of this application, certain embodiments are provided below to illustrate the successive approximation control scheme disclosed in this application. Those skilled in the art should understand that... Figure 1 Other embodiments of the structure of the control circuit 130 shown are all within the scope of this application.

[0040] Figure 3 According to certain embodiments of this application Figure 1 A schematic diagram of an embodiment of the control circuit 130 is shown. In this embodiment, the control circuit 330 may be implemented as a 4-bit SAR ADC circuit (e.g., Figure 1The SAR ADC circuit 100 shown is at least a portion of a successive approximation control logic circuit with N equal to 4. The control circuit 330 includes a plurality of latch circuits 340.1-340.4 and an enable circuit 350. The plurality of latch circuits 340.1-340.4 can be implemented as Figure 1 The plurality of latch circuits 140.1-140.N shown is an implementation of the plurality of latch circuits 140.1-140.N. The enable circuit 350 can be implemented as Figure 1 The enable circuit 150 shown is an implementation of the enable circuit 150.

[0041] Each latch circuit of the plurality of latch circuits 340.1-340.3 can be implemented with a latch stage and a delay stage connected in series with each other, while the latch circuit 340.4 can be implemented with a latch stage. The plurality of latch stages 342.1-342.4 can be triggered in response to the plurality of trigger signals TG[3]-TG[0], respectively, to store the comparator outputs C OUT generated in the plurality of comparison cycles CC1-CC4, respectively. OUT In addition, the plurality of latch stages 342.1-342.4 can generate digital signals D OUT from the comparator outputs C OUT stored in the latch stages in response to the comparator outputs C

[0042] For example, the plurality of latch stages 342.1-342.4 can include a data latch and a signal detector, one of the plurality of data latches 344.1-344.4 and one of the plurality of signal detectors 346.1-346.4. For the latch stage 342.1, the data latch 344.1 is configured to store the comparator output C OUT obtained in the comparison cycle CC1 when triggered by the trigger signal CKI[3] to generate the digital signal D[3]. In this implementation, the trigger signal CKI[3] can be an inverted version of the trigger signal TG[3]. The trigger signal TG[3] can be implemented using a control signal CKS, which can be used to control Figure 1 the sampling operation of the analog signal A IN .

[0043] The signal detector 346.1 is coupled to the data latch 344.1 to detect the digital signal D[3] to generate the valid signal CKO[3]. The valid signal CKO[3] can indicate whether the digital signal D[3] (i.e., the comparator output C OUTwhether the data signal D[3] is valid. When the difference between the plurality of voltage signals VP[3] and VN[3] reaches the threshold level, the valid signal CKO[3] can indicate that the data signal D[3] is valid. When the difference between the plurality of voltage signals VP[3] and VN[3] is less than the threshold level, the valid signal CKO[3] can indicate that the data signal D[3] is not valid. In this embodiment, the signal detector 346.1 can be implemented using a NAND gate that receives the plurality of voltage signals VP[3] and VN[3] to generate the valid signal CKO[3]. However, this is not intended to limit the scope of the present application. The signal detector 346.1 can be implemented using other detection circuits that are capable of detecting whether the data signal D[3] is valid.

[0044] Similarly, the data latches 344.2 / 344.3 / 344.4 can be triggered by the trigger signals CKI[2] / CKI[l] / CKI[O], which can be the inverted signals of the trigger signals TG[2] / TG[l] / TG[O]. When triggered by the trigger signals CKI[2] / CKI[l] / CKI[O], the data latches 344.2 / 344.3 / 344.4 can store the comparator outputs C OUT The signal detectors 346.2 / 346.3 / 346.4 can detect the data signals D[2] / D[l] / D[O] to generate valid signals CKO[2] / CKO[l] / CKO[O], which can indicate whether the data signals D[2] / D[l] / D[O] are valid.

[0045] Each of the plurality of delay stages 348.1-348.3 is coupled between two consecutive ones of the plurality of latch stages 342.1-342.4. Each delay stage is configured to delay a valid signal output from one of the two consecutive latch stages to generate a trigger signal, and to trigger the other one of the two consecutive latch stages according to the trigger signal. For example, delay stage 348.1 is coupled between consecutive latch stages 342.1 and 342.2, and is configured to delay a valid signal CKO[3] output from latch stage 342.1 to generate a trigger signal TG[2], and to trigger latch stage 342.2 according to the trigger signal TG[2]. Similarly, delay stage 348.2 is configured to delay a valid signal CKO[2] output from latch stage 342.2 to generate a trigger signal TG[1], and to trigger latch stage 342.3 according to the trigger signal TG[1]. Delay stage 348.3 is configured to delay a valid signal CKO[1] output from latch stage 342.3 to generate a trigger signal TG[0], and to trigger latch stage 342.4 according to the trigger signal TG[0].

[0046] In this embodiment, latch circuit 340.1 is configured to pass the trigger signal TG[2] to latch circuit 340.2 according to the valid signal VD. When the valid signal VD indicates that the comparator output C OUT The trigger signal TG[2] is not passed to latch circuit 340.2 when the valid signal VD indicates that the comparator output C OUT The trigger signal TG[2] is passed to latch circuit 340.2 when the valid signal VD indicates that the comparator output C OUT is triggered immediately after being reset in the previous comparison cycle. Similarly, latch circuit 340.3 / 340.4 is triggered immediately after being reset in the previous comparison cycle. OUT is triggered immediately after being reset in the previous comparison cycle.

[0047] For example, but not limited to, each of the plurality of delay stages 348.1-348.3 can be implemented using a flip-flop, which is triggered in response to the valid signal VD. The valid signal VD can indicate whether the comparator output C OUT is valid. The valid signal VD can indicate whether the comparator output C OUTWhen invalid (or becomes invalid output), the flip-flop can output a trigger signal TG[2] / TG[1] / TG[0] according to the valid signal VD. In this embodiment, the flip-flop can be triggered by a falling edge of the valid signal VD. The data input end D of the flip-flop is coupled to the valid signal CKO[3] / CKO[2] / CKO[1]. The inverted data output end Qb of the flip-flop is used to output the trigger signal TG[2] / TG[1] / TG[0]. In addition, the flip-flop can be reset when Figure 1 the analog signal A IN is sampled by the comparator circuit 120. For example, the reset input end R of the flip-flop can be coupled to the control signal CKS.

[0048] The enable circuit 350 includes (but is not limited to) a signal detector 352 and a signal generator 354. The signal detector 352 is used to detect the comparator output C OUT to generate the valid signal VD, which can indicate whether the comparator output C OUT is valid. For example (but the present application is not limited to this), the signal detector 352 can be implemented by using a NAND gate, wherein the NAND gate is used to generate the valid signal VD according to the voltage signals VOP and VON.

[0049] The signal generator 354 is coupled to the signal detector 352, the latch circuit 340.4 and the comparator circuit 120, and is used to generate the enable signal EN_D according to the valid signal VD, the valid signal CKO[0] and the control signal CKS. In addition, the signal generator 354 can selectively enable the comparator circuit 120 according to the enable signal EN_D.

[0050] In this embodiment, when the valid signal VD indicates that the comparator output C OUT is invalid, the valid signal CKO[0] indicates that the data signal D[0] latched in the latch circuit 340.4 is invalid, and the control signal CKS indicates that Figure 1 the sampling operation of the analog signal A IN is completed, the signal generator 354 can enable the comparator circuit 120 according to the enable signal EN_D. When the valid signal VD indicates that the comparator output C OUT is valid, the signal generator 354 can disable the comparator circuit 120, so that the comparator output C OUT can be reset. When the valid signal CKO[0] indicates that the data signal D[0] latched in the latch circuit 340.4 is valid, the signal generator 354 can disable the comparator circuit 120, so that the comparator output C OUT can be reset. When the control signal CKS indicates that Figure 1 the sampling operation of the analog signal A INthe sampling operation of the analog signal A OUT may be reset. For example (but the present application is not limited thereto), the signal generator 354 can be implemented as including an NOR gate 356 and a delay element 358. The NOR gate 356 is used to generate an enable signal EN according to the valid signal VD, the valid signal CKO[0] and the control signal CKS. The delay element 358 is used to delay the enable signal EN to generate the enable signal EN D.

[0051] Figure 4 is according to certain embodiments of the present application Figure 3 the signal waveform diagram involved in the operation of the control circuit 330. Please refer to Figure 3 together with Figure 4 At a time point tO, the enable signal EN D transitions to a high signal level. For example, a sampling phase ends and a transition phase starts, so that Figure 1 the analog signal A IN is sampled. The control signal CKS can transition from a high signal level to a low signal level. Since the control signal CKS, the valid signal CKO[0] and the valid signal VD are all at a low signal level, the NOR gate 356 can output the enable signal EN at a high signal level to the delay element 358.

[0052] After a time delay TD caused by the delay element 358 (i.e. at a time point tl), the delay element 358 can generate the enable signal EN D at a high signal level. The comparator circuit 120 can be enabled by the enable signal EN D to enter a comparison period CC1. The comparator output C OUT is valid before the control signal CKS has transitioned to the low signal level, the latch stage 342.1 can thus be triggered.

[0053] At a time point t2, the signal level difference between the plurality of voltage signals VOP and VON reaches a threshold level. The signal detector 352 can thus generate the valid signal VD at a high signal level. The enable signal EN outputted by the NOR gate 356 can transition to a low signal level. Moreover, since the latch stage 342.1 has been triggered, the data latch 344.1 can immediately store the comparator output C OUT reaching the valid logic state, and the signal detector 346.1 can generate the valid signal CKO[3] at a high signal level at the time point t2v. The latch circuit 340.1 can generate the most significant bit of the digital signal D OUT shown in FIG. 10B according to the data signal D[3] stored therein. Figure 1

[0054] ​After a time delay TD (i.e., time point t3), the enable signal EN_D will switch to a low signal level in response to the enable signal EN. The comparator circuit 120 can reset the comparator output C according to the enable signal EN_D. OUT This allows multiple voltage signals VOP and VON to be at the same signal level. The active signal VD is switched to a low signal level, and the enable signal EN_D is switched to a high signal level. In addition, the delay stage 348.1 (i.e., the flip-flop) can be triggered by the active signal VD to output the trigger signal TG[2]. The latch stage 342.2 can be triggered by the trigger signal CKI[2], where the trigger signal CKI[2] is the inverted signal of the trigger signal TG[2]. After a time delay TD (i.e., time point t4), the enable signal EN_D can be switched to a high signal level. The comparator circuit 120 can enter the comparison cycle CC2.

[0055] Since latch stage 342.2 can be triggered in response to the valid signal CKO[3] and valid signal VD output by the previous latch stage 342.1, the successive approximation control logic circuit implemented based on multiple latch circuits 340.1-340.4 can be called a two-path successive approximation control logic circuit. As those skilled in the art will understand the above information regarding... Figures 1 to 4 Following the paragraph description, it should be clear how the control circuit 330 operates during the multiple comparison cycles CC2-CC4; therefore, a similar description will not be repeated here.

[0056] It is worth noting that, due to the comparator output C generated during the comparison period CC1 OUT The comparator output can be immediately stored in latch circuit 340.1 when it becomes a valid comparator output. Therefore, the time allowed for the digital-to-analog converter to stabilize is approximately twice the time delay TD. Compared to successive approximation control logic circuits that enable the storage operation of the comparator output only when it becomes valid, the successive approximation control logic circuit disclosed in this application provides more time margin for the stabilization time of the digital-to-analog converter.

[0057] Figure 5 According to certain embodiments of this application Figure 1 The diagram shows another embodiment of the control circuit 130. Apart from the plurality of latch circuits 540.1-540.4, the circuit structure of the control circuit 530 can be the same as... Figure 3 The control circuit 330 shown has the same / similar circuit structure.

[0058] The latch circuit 540.1 includes a latch stage 542.1 and a delay stage 548.1 connected in series. The latch stage 542.1 includes... Figure 3The data latch 344.1 is shown in conjunction with the signal detector 346.1. The trigger signal CKI[3] for triggering the data latch 344.1 can be implemented using a control signal CKSb, which is the inverted signal of the control signal CKS. The delay stage 548.1 can be implemented using a delay element 549.1, which is used to delay the valid signal CKO[3] to generate the trigger signal CKI[2].

[0059] The latch circuit 540.2 includes a latch stage 542.2 and a delay stage 548.1 coupled in series with each other. The latch stage 542.2 includes Figure 3 The data latch 344.2 is shown in conjunction with the signal detector 346.2. The trigger signal CKI[2] for triggering the data latch 344.2 is output from the delay stage 548.1. The delay stage 548.2 can be implemented using a delay element 549.2, which is used to delay the valid signal CKO[2] to generate the trigger signal CKI[l]. Similarly, the latch circuit 540.3 includes a latch stage 542.3 and a delay stage 548.3 coupled in series with each other. The trigger signal CKI[l] for triggering the data latch 344.3 is output from the delay stage 548.2. The delay stage 548.2 can be implemented using a delay element 549.3, which is used to delay the valid signal CKO[l] to generate the trigger signal CKI[O]. Furthermore, the latch circuit 540.4 is implemented using a latch stage 542.4, which includes Figure 3 The data latch 344.4 is shown in conjunction with the signal detector 346.4. The trigger signal CKI[O] for triggering the data latch 344.4 is output from the delay stage 548.3.

[0060] Figure 6 The signal waveforms involved in the operation of the control circuit 530 are shown in FIG. 13. Please refer to Figure 5 The signal waveforms involved in the operation of the control circuit 530 are shown in FIG. 13. Please refer to Figure 5 Referring to Figure 6 At time point tO, the enable signal EN_D is converted to the high signal level. After a time delay TD caused by the delay element 358 (i.e. time point t1'), the enable signal EN_D can be converted to the high signal level. The comparator circuit 120 can enter the comparison period CC1. The comparator output C OUT Before the valid signal CKO[3] is valid, the latch stage 542.1 can thus be triggered since the control signal CKS has been converted to the low signal level.

[0061] At time point t2', the signal level difference between the plurality of voltage signals VOP and VON reaches a threshold level. Since the latch stage 542.1 has been triggered, the data latch 344.1 can immediately store the comparator output C OUT reaches the threshold level. Since the latch stage 542.1 has been triggered, the data latch 344.1 can immediately store the comparator output C

[0062] In addition, the enable signal EN can transition to a low signal level when the signal level difference between the plurality of voltage signals VOP and VON reaches the threshold level. After a time delay TD (i.e., time point t3'), the enable signal EN D can respond to the transition of the enable signal EN to the low signal level. The comparator circuit 120 can reset the comparator output C OUT so that the plurality of voltage signals VOP and VON can be at the same signal level. The enable signal EN can transition to a high signal level. After a time delay TD (i.e., time point t4'), the enable signal EN D can transition to the high signal level. The comparator circuit 120 can enter the comparison cycle CC2.

[0063] Since the latch stage 542.2 can be triggered in response to the valid signal CKO[3] outputted by the previous latch stage 542.1, the successive approximation control logic circuit implemented based on the plurality of latch circuits 540.1-540.4 can be referred to as a single-path successive approximation control logic circuit. Since those skilled in the art should understand the operation of the control circuit 530 in the plurality of comparison cycles CC2-CC4 after reading the above description of the paragraph Figures 1 to 6 , similar descriptions will not be repeated here.

[0064] In some embodiments, a latch stage can perform a self-latching operation such that the comparator output stored in a previous comparison cycle is not disturbed by the comparator output generated in a current comparison cycle. For example, when another latch stage located after the latch stage is triggered in response to a trigger signal to store the comparator output generated in the current comparison cycle, the latch stage can be uncoupled from the comparator output generated in the current comparison cycle.

[0065] Figures 7A to 7CAccording to certain embodiments of this application Figure 3 The diagram shows the self-latch operation of latch stage 342.1. Please refer to [link / reference] first. Figure 7A The data latch 344.1 of latch stage 342.1 may include a latch element 744 and a switching circuit 746. The latch element 744 includes multiple input terminals T. IP With T IN and multiple output terminals T OP With T ON Input terminal T IP Coupled to the output terminal T OP and input terminal T IN Coupled to the output terminal T ON The latch element 744 can operate in different modes according to the valid signal CKO[3] output from the signal detector 346.1. For example, the latch element 744 can operate in a bypass mode, in which the data latching function of the latch element 744 can be disabled. As another example, the latch element 744 can operate in a latching mode, in which the data latching function of the latch element 744 can be enabled.

[0066] Switching circuit 746 is used to selectively switch the comparator output C based on the valid signal CKO[3]. OUT Coupled to latching element 744. In this embodiment, switching circuit 746 includes multiple switches SWP and SWN. Switch SWP is selectively coupled to voltage signal VOP and input terminal T. IP Between. Switch SWN is selectively coupled to the voltage signal VON and the input terminal T. IN between.

[0067] During operation, the comparator output C is set during a reset period. OUT Reset, wherein the reset period can be (but is not limited to) from Figure 4 The time interval from time point t0 to time point t1 is shown. Multiple voltage signals VOP and VON are reset to high signal levels. Multiple switches SWP and SWN are turned on according to the valid signal CKO[3]. Latch element 744 can operate in the bypass mode. Therefore, input T IP The voltage signal VLP and the output terminal T OP The voltage signal VP[3] is set to high signal level. Input terminal T IN The voltage signal VLN and the output terminal T ON The voltage signal VN[3] is set to a high signal level. The data signal D[3] is in an invalid state. In addition, during a sampling period (such as Figure 4At the beginning of the period from time t1 to time t2 (as shown), multiple voltage signals VOP, VON, VLP, VLN, VP[3] and VN[3] are all at high signal levels.

[0068] Next, please refer to Figure 7B When the signal level of the voltage signal VON transitions to a low signal level (such as...) Figure 4 (As shown at time point t2), the comparator output C OUT This becomes a valid comparator output. Multiple voltage signals VLN and VN[3] will be converted to low signal levels. See also... Figure 7C When the voltage signal VN[3] transitions to a low signal level (such as... Figure 4 At the indicated time point t2v), the valid signal CKO[3] can be switched to a high signal level to disconnect switches SWP and SWN. Latch element 744 can operate in the latch mode. Since both switches SWP and SWN are disconnected, latch stage 342.1 can be decoupled from the comparator output C generated in the next comparison cycle. OUT .

[0069] Figure 8 According to certain embodiments of this application Figures 7A to 7C The diagram illustrates an embodiment of the latch element 744. In this embodiment, the latch element 744 includes a pair of cross-coupled inverters and multiple switches SWP1, SWN1, SWP2, and SWN2. The pair of cross-coupled inverters includes inverters 846 and 848, used to store the comparator output C. OUT To generate data signal D[3]. The input terminal of inverter 846 is used as input terminal T. IP And the output terminal of inverter 846 is used as output terminal T. ON The input terminal of the inverter 848 is used as input terminal T. IN And the output terminal of inverter 848 is used as output terminal T. OP .

[0070] Switch SWP1 according to Figure 3 The trigger signal CKI[3] shown is selectively coupled to a reference voltage VDD and the input terminal T. IP Between. Switch SWN1 is selectively coupled to the reference voltage VDD and the input terminal T according to the trigger signal CKI[3]. IN Between. Switch SWP2 is selectively coupled to the power supply terminal T of inverter 846 according to the valid signal CKO[3]. SP Between a reference voltage VSS and a switch SWN2, the switch SWN2 is selectively coupled to the power supply terminal T of the inverter 848 based on the valid signal CKO[3]. SNwith respect to a reference voltage VSS.

[0071] Figures 9A to 9C is a schematic diagram of a self-latching operation of the latch stage 342.1 according to certain embodiments of the present disclosure. First, refer to Figure 8 , the switch SWP1 and the switch SWN1 are both turned on according to the trigger signal CKI[3] during a reset period (such as a period of time before the time point t0 shown in Figure 9A ). The switch SWP2 and the switch SWN2 are both turned off, and the switch SWP and the switch SWN are both turned on. The latch element 744 is operable in the bypass mode. Figure 4

[0072] Refer to Figure 9B , the switch SWP1 and the switch SWN1 are both turned off according to the trigger signal CKI[3] during a sampling period. Since the data signal D[3] is invalid at the beginning of the sampling period (such as the time point t1 to the time point t2 shown in Figure 4 ), the switch SWP2 and the switch SWN2 are both turned off according to the valid signal CKO[3]. In addition, the switch SWP and the switch SWN are both turned on according to the valid signal CKO[3].

[0073] Refer to Figure 9C , when the data signal D[3] is valid (becomes a valid data signal) (such as the time point t2v shown in Figure 4 ), the valid signal CKO[3] can be converted to a high signal level. The latch element 744 is operable in the latching mode. The switch SWP2 and the switch SWN2 are both turned on to latch the data signal D[3]. The switch SWP and the switch SWN are both turned off to decouple the voltage signals VOP and VON from the latch element 744. The latch stage 342.1 is decoupled from the comparator output C OUT .

[0074] It is noted that the above-described structure and operation shown in Figures 7A to 9C can be used to implement at least one of the latch stages 342.2-342.4 shown in Figure 3 and the latch stages 542.1-542.4 shown in Figure 5 without departing from the scope of the present disclosure. In addition, the circuit structure shown in Figure 8 is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0075] Figure 10 is a flowchart of a method of operating a SAR ADC circuit according to certain embodiments of the present disclosure. For illustrative purposes, the method 1000 is described below in conjunction with the control circuit 330 shown in Figure 3 . It should be appreciated by those skilled in the art that the method 1000 can be applied to the control circuit 430 shown in Figure 1 ​The control circuit 130 shown Figure 5 The control circuit 530 shown, without departing from the scope of the present application. Moreover, in certain embodiments, the method 1000 can include other operations. In certain embodiments, the operations of the method 1000 can be performed in a different order, and / or using other implementations.

[0076] At operation 1002, a comparator circuit of the SAR ADC circuit is utilized to compare an analog signal to a plurality of reference levels in a plurality of successive comparison cycles. The plurality of comparison cycles includes a first comparison cycle and a second comparison cycle. The comparator circuit 120 is utilized to compare the analog signal A IN to the plurality of reference levels in the plurality of comparison cycles CC1-CC4, respectively.

[0077] At operation 1004, a first latch circuit is enabled to store a comparator output of the comparator circuit generated in the first comparison cycle and to generate a trigger signal therefrom. For example, the latch circuit 340.1 is enabled to store the comparator output C OUT generated in the comparison cycle CC1 and to generate the trigger signal TG[2] therefrom.

[0078] At operation 1006, a second latch circuit is enabled to store the comparator output generated in the second comparison cycle based on the trigger signal. For example, the latch circuit 340.2 is enabled to store the comparator output C OUT generated in the comparison cycle CC2 based on the trigger signal TG[2].

[0079] At operation 1008, at least a portion of a digital signal is generated based on the comparator output stored by the first latch circuit and the comparator output stored by the second latch circuit. For example, a portion of the digital signal D OUT is generated based on the comparator output C OUT generated in the comparison cycle CC1 and the comparator output C OUT generated in the comparison cycle CC2.

[0080] In certain embodiments, the first latch circuit can be enabled prior to the comparator output generated in the first comparison cycle being valid. For example, the latch circuit 340.1 can be enabled prior to the start of the comparison cycle CC1. Since one of ordinary skill in the art, after reading the above description of the paragraph Figures 1 to 9C regarding the method 1000, will be able to understand the details of the operations of the method 1000, further explanation is not provided herein.

[0081] By the successive approximation control scheme disclosed herein, a latch circuit can trigger a next latch circuit according to a data signal latched therein. The aforementioned next latch circuit can be triggered before a comparator output to be stored becomes valid (i.e., a valid comparator output). Thus, the successive approximation control scheme disclosed herein can provide more time margin for the settling time of a digital-to-analog converter.

[0082] The word "substantially" is used herein to describe and account for many changes in a quantity that can occur in a given instance. When used in conjunction with an event or circumstance, the word "substantially" can cover instances where the event or circumstance occurs exactly or instances where the event or circumstance occurs within a reasonable tolerance range. For example, when the word "substantially" is used in conjunction with a given value or range, it generally can mean ±10%, ±5%, ±1%, or ±0.5% of the given value or range. In the present disclosure, a numerical range is indicated from one endpoint to another, or between two endpoints. Unless otherwise indicated, the numerical ranges described herein are inclusive of the endpoints. Further, when referring to a plurality of values or characteristics being "substantially" the same, it can encompass instances where the values are each within ±10%, ±5%, ±1%, or ±0.5% of the average of the values.

[0083] The above description is intended to enable those skilled in the art to present more fully the nature of the application. It will be apparent, however, to those skilled in the art that they can readily apply the teachings of the present disclosure as applicable to other functions, structures, and applications without departing from the spirit and scope of the present disclosure. Those skilled in the art will appreciate that they can readily apply the teachings of the present disclosure as applicable to other functions, structures, and applications without departing from the spirit and scope of the present disclosure. Accordingly, the application is not to be limited by the above description, but is to be given full scope to the claims below.

Claims

1. A successive approximation analog-to-digital conversion circuit, characterized by comprising: comparator circuit for comparing the analog signal with a plurality of reference levels; and a plurality of latch circuits coupled to the comparator circuit and in series with each other, the plurality of latch circuits being sequentially triggered to store comparator outputs of the comparator circuit in response to a plurality of trigger signals and to generate digital signals based on the comparator outputs, wherein a first latch circuit and a second latch circuit of the plurality of latch circuits are triggered in response to a first trigger signal and a second trigger signal of the plurality of trigger signals, respectively; the first latch circuit being configured to generate the second trigger signal based on the comparator output stored in the first latch circuit, wherein the comparator circuit is configured to compare the analog signal with the plurality of reference levels in a plurality of comparison periods, respectively; and the plurality of latch circuits are configured to store the comparator outputs generated in the plurality of comparison periods, respectively; at least one of the plurality of latch circuits is triggered before the comparator output generated in a corresponding comparison period is valid. The first latch circuit is not coupled to the comparator output when the second latch circuit is triggered to store the comparator output in response to the second trigger signal.

2. The successive approximation analog-to-digital conversion circuit of claim 1, wherein, The first latch circuit comprises:

3. The successive approximation analog-to-digital conversion circuit of claim 1, wherein, a data latch configured to store the comparator output to generate a data signal when triggered in response to the first trigger signal; a signal detector coupled to the data latch and configured to detect the data signal to generate a first valid signal indicating whether the data signal is valid; and a delay element coupled to the signal detector and configured to delay the first valid signal to generate the second trigger signal. The comparator output comprises a first voltage signal and a second voltage signal; and the data latch comprises:

4. The successive approximation analog-to-digital conversion circuit of claim 3, wherein, a pair of cross-coupled inverters configured to store the comparator output to generate the data signal, the pair of cross-coupled inverters comprising a first inverter and a second inverter, an input of the first inverter being coupled to an output of the second inverter, and an input of the second inverter being coupled to an input of the first inverter; a first switch selectively coupled between the first voltage signal and the input of the first inverter based on the first valid signal; a second switch selectively coupled between the second voltage signal and the input of the second inverter based on the first valid signal; a third switch selectively coupled between a first reference voltage and the input of the first inverter based on the first trigger signal; a fourth switch selectively coupled between the first reference voltage and the input of the second inverter based on the first trigger signal; a fifth switch selectively coupled between a supply terminal of the first inverter and a second reference voltage based on the first valid signal; and a sixth switch selectively coupled between a supply terminal of the second inverter and the second reference voltage based on the first valid signal. ​ 5. The successive approximation analog-to-digital conversion circuit of claim 4, wherein, When the third switch and the fourth switch are both turned on, the fifth switch and the sixth switch are both turned off, and the first switch and the second switch are both turned off; when the third switch, the fourth switch, the fifth switch and the sixth switch are all turned off, the first switch and the second switch are both turned on; when the third switch and the fourth switch are both turned off, and the fifth switch and the sixth switch are both turned on, the first switch and the second switch are both turned off.

6. The successive approximation analog-to-digital conversion circuit of claim 3, wherein, The data signal includes a first voltage signal and a second voltage signal; the signal detector is a NAND gate, and the NAND gate is used to receive the first voltage signal and the second voltage signal to generate the first valid signal.

7. The successive approximation analog-to-digital conversion circuit of claim 3, wherein, The delay element is a flip-flop triggered in response to a second valid signal, the second valid signal indicating whether the comparator output is valid; when the second valid signal indicates that the comparator output is invalid, the flip-flop is used to output the second trigger signal according to the first valid signal.

8. The successive approximation analog-to-digital conversion circuit of claim 7, wherein, The flip-flop is reset when the analog signal is sampled by the comparator circuit.

9. The successive approximation analog-to-digital conversion circuit of claim 1, wherein, The second latch circuit is used to generate the least significant bit of the digital signal according to the comparator output; the second latch circuit includes: a data latch, used to store the comparator output to generate a data signal when triggered in response to the second trigger signal; and a signal detector, coupled to the data latch, used to detect the data signal to generate a valid signal, the valid signal indicating whether the data signal is valid; wherein when the valid signal indicates that the data signal is valid, the comparator circuit is used to reset the comparator output according to the valid signal.

10. The successive approximation analog-to-digital conversion circuit of claim 9, wherein, The data signal includes a first voltage signal and a second voltage signal; the signal detector is a NAND gate, and the NAND gate is used to receive the first voltage signal and the second voltage signal to generate the valid signal.

11. The successive approximation analog-to-digital conversion circuit of claim 1, wherein, The first latch circuit is used to generate the most significant bit of the digital signal according to the comparator output; the first trigger signal is a control signal for controlling the sampling operation of the analog signal; when the control signal indicates that the sampling operation of the analog signal is in progress, the first latch circuit is not triggered; when the control signal indicates that the sampling operation of the analog signal is complete, the first latch circuit is triggered.

12. The successive approximation analog-to-digital conversion circuit of claim 1, wherein, Further comprising: a signal detector, coupled to the comparator circuit and the first latch circuit, used to detect the comparator output to generate a valid signal, the valid signal indicating whether the comparator output is valid; wherein the first latch circuit is used to transmit the second trigger signal to the second latch circuit according to the valid signal; when the valid signal indicates that the comparator output is valid, the second trigger signal is not transmitted to the second latch circuit; when the valid signal indicates that the comparator output is invalid, the second trigger signal is transmitted to the second latch circuit.

13. A successive approximation analog-to-digital conversion circuit, characterized by comprising: comprising: a comparator circuit to compare the analog signal to a plurality of reference levels in a plurality of comparison periods, N being an integer greater than 1; N latch stages coupled to the comparator circuit to store a comparator output of the comparator circuit generated in the plurality of comparison periods as N data signals, and to generate a digital signal from the N data signals, wherein each latch stage is to output a first valid signal indicating whether the data signal stored in the latch stage is valid; and (N-1) delay stages, wherein each delay stage is coupled to two consecutive latch stages of the N latch stages to delay the first valid signal output from one of the two consecutive latch stages to generate a trigger signal, and to trigger the other of the two consecutive latch stages according to the trigger signal.

14. The successive approximation analog-to-digital conversion circuit of claim 13, wherein, At least one of the N latch stages is triggered before the data signal generated in the corresponding comparison period is valid.

15. The successive approximation analog-to-digital conversion circuit of claim 13, wherein, The one of the two consecutive latch stages is not coupled to the comparator output when the other of the two consecutive latch stages is triggered in response to the trigger signal.

16. The successive approximation analog-to-digital conversion circuit of claim 13, wherein, The latch stage comprises: a data latch to store the comparator output to generate the data signal, the data signal comprising a first voltage signal and a second voltage signal; and a signal detector coupled to the data latch to detect whether a signal level difference between the first voltage signal and the second voltage signal reaches a threshold level to generate the first valid signal, wherein the first valid signal indicates that the data signal stored in the latch stage is valid when the signal level difference between the first voltage signal and the second voltage signal reaches the threshold level.

17. The successive approximation analog-to-digital conversion circuit of claim 13, wherein, The delay stage is a flip-flop triggered in response to a second valid signal indicating whether the comparator output is valid; when the second valid signal indicates that the comparator output is invalid, the flip-flop is to output the trigger signal according to the first valid signal.

18. A method of operating a successive approximation analog-to-digital conversion circuit, characterized by, comprises: a comparator circuit to compare an analog signal to a plurality of reference levels in a plurality of successive comparison periods, wherein the plurality of successive comparison periods comprises a first comparison period and a second comparison period; a first latch circuit enabled to store a comparator output of the comparator circuit generated in the first comparison period, and to generate a trigger signal from the comparator output; a second latch circuit enabled to store the comparator output generated in the second comparison period according to the trigger signal; and a digital signal generated from at least a portion of the comparator output stored by the first latch circuit and the comparator output stored by the second latch circuit, wherein the first latch circuit is enabled before the comparator output generated in the first comparison period is valid. ​

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