Address-based filtering for load / store speculation

Abstract

Address-based filtering for load / store speculation includes maintaining a filter table including table entries associated with address ranges, in response to receiving an order check trigger transaction, querying the filter table using a target address of the order check trigger transaction to determine whether an instruction dependent on the order check trigger transaction has previously generated a physical address, and in response to determining that the filter table lacks an indication that the instruction dependent on the order check trigger transaction has previously generated a physical address, bypassing a lookup operation in an order violating memory fabric for determining whether the instruction dependent on the order check trigger transaction is currently in progress.

Description

[0001] Statement regarding federally sponsored research or development

[0002] This disclosure was made with government support under the PathForward project (basic contract number DE-AC52-07NA27344, subcontract number B620717) awarded by the DOE to the Lawrence Livermore National Security Agency. The government retains certain rights in this disclosure. Background Technology

[0003] Computer processors employing data speculation typically allow load and store instructions within load memory locations to be performed out of program order. This data speculation requires checking memory dependencies for order violations to prevent such violations. These checks may require a full physical address comparison between a load or store and a subset of a store or load in progress. For some memory coherence models, the checks may also require comparing the full physical address of an externally probed memory with the physical address of a load in progress. Preventing order violations often involves using content-addressable memory (CAM) architectures. Attached Figure Description

[0004] Figure 1 A block diagram of an exemplary system for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is illustrated.

[0005] Figure 2 A block diagram of an exemplary system for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is illustrated.

[0006] Figure 3 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented.

[0007] Figure 4 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented.

[0008] Figure 5 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented.

[0009] Figure 6 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented.

[0010] Figure 7A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented.

[0011] Figure 8 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation, according to an embodiment of the present disclosure, is presented. Detailed Implementation

[0012] Using content-addressable memory (CAM) architectures and lookup operations to prevent order violations is costly in terms of power consumption. Therefore, by reducing the number of CAM lookups in the load memory unit (LSU), the overall power consumption of the LSU is reduced. Embodiments of this disclosure use a filtering mechanism to bypass memory operations such as CAM lookups for some incoming instructions. This filtering mechanism operates by maintaining a table of entries corresponding to the addresses or address ranges of previously received store or load instructions. If an incoming store instruction, load instruction, or cache probe includes a target address within a range not targeted by a previously received instruction, the incoming store instruction, load instruction, or cache probe does not require a CAM lookup and is forwarded toward completion. In some embodiments, this filtering mechanism is utilized at many different stages in the LSU pipeline.

[0013] Figure 1 This is a block diagram of a non-limiting exemplary computing system (152) for address-based filtering of load / store speculation according to some implementation schemes. Figure 1 The computing system (152) includes at least one computer processor (156) or 'CPU' and random access memory (168) ('RAM'), which is connected to the processor (156) and other components of the computing system (152) via a high-speed memory bus (166) and a bus adapter (158).

[0014] The operating system (154) is stored in RAM (168). Operating systems used in computers for address-based filtering of load / store speculation include UNIX. TM Linux TM Microsoft Windows TM AIX TM And other operating systems that those skilled in the art would think of. Figure 1 The operating system (154) in the example is shown in RAM (168), but many components of such software are also typically stored in non-volatile memory, such as, for example, on a data storage device (170) (such as a disk drive).

[0015] Figure 1The computing system (152) includes a disk drive adapter (172) coupled to the processor (156) and other components of the computing system (152) via an expansion bus (160) and a bus adapter (158). The disk drive adapter (172) connects a non-volatile data storage device in the form of a data storage device (170) to the computing system (152). In some embodiments, the disk drive adapter includes an Integrated Drive Electronics ('IDE') adapter, a Small Computer System Interface ('SCSI') adapter, and other disk drive adapters that will be apparent to those skilled in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disc drive, an electrically erasable programmable read-only memory (so-called 'EEPROM' or 'flash' memory), a RAM drive, etc., as will be apparent to those skilled in the art.

[0016] Figure 1 An exemplary computing system (152) includes one or more input / output ('I / O') adapters (178). The I / O adapters implement user-oriented input / output through software drivers and computer hardware, for example, for controlling output to display devices such as computer displays and user input from user input devices (181) such as keyboards and mice. Figure 1 An exemplary computing system (152) includes a video adapter (209), which is an example of an I / O adapter specifically designed for graphics output to a display device (180) (such as a display screen or computer monitor). The video adapter (209) is connected to the processor (156) via a high-speed video bus (164), a bus adapter (158), and a front-side bus (162), which is also a high-speed bus.

[0017] Figure 1 An exemplary computing system (152) includes a communication adapter (167) for data communication with other computers and for data communication with a data communication network. In some embodiments, such data communication is performed continuously via an RS-232 connection, via an external bus such as a Universal Serial Bus ('USB'), via a data communication network such as an IP data communication network, and in other ways as those skilled in the art will conceive. The communication adapter implements the hardware level of data communication, through which one computer sends data communication to another computer directly or via a data communication network. In some embodiments, examples of communication adapters include modems for wired dial-up communication, Ethernet (IEEE 802.3) adapters for wired data communication, and 802.11 adapters for wireless data communication.

[0018] Figure 2This is a block diagram of a non-limiting exemplary processor (156) for address-based filtering for load / store speculation, according to some implementation schemes. Figure 2 As shown, the exemplary processor (156) includes a load memory unit (LSU) (200), an address generation unit (202), control logic (204), a filter table shift trigger (206), a violation sort memory structure filter table (208), and a violation sort memory structure (210). Figure 2 The depiction of the LSU (200) includes elements representing different specific structures within the LSU (200). Specifically, in some embodiments, a filter table shift trigger (206) and a violation order memory structure (210) are applied to many different elements along the LSU (200) pipeline, as described below.

[0019] The LSU (200) is part of the processor (156) that executes load and store instructions. When load and store operations are allowed to proceed outside of program order, the LSU (200) is responsible for checking memory dependencies and violations of ordering. The control logic (204) of the LSU (200) performs the functions of the LSU (200), including executing load and store instructions to complete the operation. For illustrative purposes, Figure 2 The control logic (204) is depicted as a separate element within the LSU (200). In reality, the control logic (204) is a collection of behaviors within and between other elements on the LSU (200). The address generation unit (202) calculates the physical addresses for load instructions and store instructions and provides the physical addresses to the LSU (200) as an initial step in executing load instructions or store instructions.

[0020] The filter table shift trigger (206) is a data structure used by the control logic (204) to trigger shifts in the filter table (208). The control logic (204) monitors the filter table shift trigger (206) for specific conditions under which it initiates shifts in the filter table (208). The shifts in the filter table are performed to maintain equality with the memory locations targeted by the load and store instructions. In some implementations, the filter table shift trigger (206) is a queue for sequential allocation and deallocation, such as the storage queue (STQ) or load trace queue (LTQ) of the LSU (200). In some implementations, the shifts are triggered by the reuse of a specific pre-programmed time slot in the queue. In some implementations, the specific time slot is pre-programmed using Basic Input / Output System (BIOS) settings.

[0021] Violation-order memory structures (210) are memory structures such as CAM structures whose operations are part of memory dependencies and violation-order checks in control logic. Examples of violation-order memory structures (210) include stores to Load Forwarding (STLF) CAMs, Out-of-Order Buffer (OOB) CAMs, and Load Sequence Queues (LOQ) CAMs. Because lookup operations in these violation-order memory structures are expensive in terms of power usage, embodiments of this disclosure include a filter table (208) to reduce the number of lookup operations by tracking the residency of loads and stores in progress within a predefined range of physical addresses within the filter table (208) without any full or partial address comparisons.

[0022] The STLF CAM is a memory structure used by the LSU (200) to verify that a load to be executed has the same target address as an older memory that has not yet been executed. When the execution of a load is scheduled by the Load Memory Queue (LSQ), the control logic (204) compares all entries in the STLF CAM with the target address of the load to determine if there are any previous older memories that have the same target address as the load. The OOB CAM performs a similar function to the STLF CAM, but detects memory order violations between store instructions and load instructions that were missed when the LSQ first scheduled the load to memory. This is possible because not all previous older memories may have generated their physical addresses by the time the load is executed. As long as all older memories are assumed to have generated their physical addresses and dependencies are checked, the completed load remains in the OOB. Similarly, the LOQ CAM detects memory order violations between load instructions (from the same or different threads) by monitoring cache events. Cache events include cache probes (such as L1 data cache probes) and cache evictions (such as L1 data cache evictions).

[0023] The violation-order memory structure filter table (208) is a mechanism for filtering out certain order-check triggering transactions (e.g., load instructions, store instructions, and cache events) from the violation-order memory structure (210), for which there is a violation of ordering, including dependency violations. The filter table (208) includes entries representing the target address (i.e., physical address or logical address) or target address range of the order-check triggering transaction. For example, in some embodiments, the filter table includes 2... N N entries, where N is a subset of the bits in the target address of the transaction that triggered the sort check. In some implementations, a filter table (208) is implemented for each or any violation of the sort memory structure (210) in LSU (200).

[0024] In some implementations, the violation of the sorted memory structure filter table (208) is implemented as two or more separate filter tables. In some implementations, each filter table is dedicated to a different set of target address ranges. In some implementations, the control logic (204) makes an initial determination about which filter table to query based on a portion of the target address.

[0025] Figure 3 A flowchart illustrating a non-limiting exemplary method for address-based filtering for load / store speculation, according to some embodiments, is provided, including maintaining (302) a filter table comprising table entries associated with address ranges. In some embodiments, maintaining (302) the filter table comprising table entries associated with address ranges is performed by control logic (204) placing indications in the filter table for potential order violations. In some embodiments, maintaining (302) the filter table comprising table entries associated with address ranges is performed by control logic (204) shifting table entries based on conditions of filter table shift triggers.

[0026] Figure 3 The method further includes: in response to receiving a sort check trigger transaction (320), querying (304) a filter table (208) using the target address of the sort check trigger transaction (320) to determine whether an instruction dependent on the sort check trigger transaction (320) has previously generated a physical address. In some embodiments, receiving the sort check trigger transaction (320) is performed by the control logic (204) detecting that the address generation unit has provided a physical address for the sort check trigger transaction (320) (e.g., a load instruction, a store instruction, a cache event). In some embodiments, the control logic (204) receives a physical address from the address generation unit and extracts a subset of the physical address to use as a key to enter the filter table (208). Alternatively, in some embodiments, the control logic (204) uses a portion of a logical address as a key to enter the filter table (208).

[0027] In some implementations, the target address of the sort check triggering transaction (320) is used to query (304) the filter table (208) to determine whether the physical address of the instruction dependent on the sort check triggering transaction (320) has been previously generated. This is performed by the control logic (204) generating a query entry identifier using a portion of the target address (i.e., a physical address or a logical address) and accessing the entry identified by the entry identifier. For example, in some implementations, the entry identifier is generated from the physical address using [M:M+N-1], where M is the starting address of the memory window and N is a subset of the physical address bits used for the filter table (208).

[0028] Figure 3 The method further includes: in response to determining that the filter table (208) lacks an indication that an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address, bypassing (306) a lookup operation in the sorted memory structure used to determine whether an instruction dependent on the sort check triggering transaction (320) is currently in progress. "In progress" refers to an instruction that has been completed but not yet decommissioned. In some implementations, determining that the filter table (208) lacks an indication that an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address is performed by the control logic (204) accessing an entry in the filter table and determining that the entry's content is zero. Because there is no indication of a previous instruction dependent on the sort check triggering transaction (320), the control logic (204) guarantees that no previously dependent instruction is currently in progress (i.e., any in-progress instruction in the pipeline has not yet loaded data from or stored data at the target physical address).

[0029] In some implementations, bypassing (306) a lookup operation in the violation of the sorting memory structure to determine whether an instruction dependent on the sort check triggering transaction (320) is currently in progress is performed by the following: the control logic (204) operates as if the lookup operation in the violation of the sorting memory structure has been performed, and a response has been returned indicating that no instruction dependent on the sort check triggering transaction (320) is currently in progress (i.e., any in-progress instruction in the pipeline has not yet loaded data from or stored data at the target physical address).

[0030] The aforementioned functionality improves computer system operation by maintaining a filter table for incoming sorting checks that trigger transactions (e.g., load instructions, store instructions, cache events), thus avoiding expensive lookup operations in the memory architecture. In some cases, this filter table access can be used to identify missing dependency instructions. Furthermore, it makes the execution of applications that perform numerous load / store micro-operations within the processor core more power-efficient by reducing dynamic power consumption without performance degradation.

[0031] To further explain, Figure 4A flowchart illustrating another exemplary method for address-based filtering for load / store speculation according to an implementation scheme is provided, comprising: maintaining (302) a filtering table including table entries associated with address ranges; in response to receiving a sort check triggering transaction (320), querying (304) the filtering table (208) using the target address of the sort check triggering transaction (320) to determine whether an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address; and in response to determining that the filtering table (208) lacks an indication that an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address, bypassing (306) a lookup operation in the sorted memory structure for determining whether an instruction dependent on the sort check triggering transaction (320) is currently in progress.

[0032] However, Figure 4 Methods and Figure 3 The difference in methods lies in Figure 4 The method further includes: in response to determining that the filter table (208) includes an indication that the instruction dependent on the sort check triggering transaction (320) has previously generated a physical address, performing (402) a lookup operation in the violation of the sort memory structure (210) for determining whether the instruction dependent on the sort check triggering transaction (320) is currently in progress.

[0033] In some implementations, determining the filter table (208) includes an indication that an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address. This is done by the control logic (204) accessing entries in the filter table and determining that an entry is not zero (i.e., an entry has been marked to indicate that a previously dependent instruction is potentially in progress (i.e., any in-progress instruction has not yet loaded data from or stored data to the target physical address)). If each entry represents an address range, the marking of an entry does not necessarily indicate a violation of sorting. Instead, the marking indicates that a dependent instruction has generated a physical address for the same range. Because there is an indication of a previous instruction potentially dependent on the sort check triggering transaction (320), the control logic (204) does not guarantee that no previously dependent instruction is currently in progress (i.e., any in-progress instruction has not yet loaded data from or stored data to the target physical address). In this case, a considerably more expensive lookup operation is performed in the violation of sorting memory structure (210) to determine whether an instruction dependent on the sort check triggering transaction (320) is currently in progress.

[0034] To further explain, Figure 5A flowchart illustrating another exemplary method for address-based filtering for load / store speculation according to an implementation scheme is provided, comprising: maintaining (302) a filtering table including table entries associated with address ranges; in response to receiving a sort check triggering transaction (320), querying (304) the filtering table (208) using the target address of the sort check triggering transaction (320) to determine whether an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address; and in response to determining that the filtering table (208) lacks an indication that an instruction dependent on the sort check triggering transaction (320) has previously generated a physical address, bypassing (306) a lookup operation in the sorted memory structure for determining whether an instruction dependent on the sort check triggering transaction (320) is currently in progress.

[0035] However, Figure 5 Methods and Figure 3 The difference in the method is that: maintaining (302) a filter table including table entries associated with address ranges includes detecting (502) that a dependent instruction has generated a physical address; indicating (504) that the dependent instruction has generated a physical address in an entry of a filter table (208) associated with the target address of the dependent instruction; and shifting (506) a table entry in the filter table (208) in response to detecting that a particular time slot has been reused in a queue that is deallocated in program order.

[0036] In some implementations, detecting (502) that a dependent instruction has generated a physical address is performed by the address generation unit (202) notifying the control logic (204) that a physical address for a specific type of dependent instruction (e.g., a load instruction or a store instruction) has been generated. In some implementations, the control logic (204) receives a physical address for the instruction, a logical address for the instruction, or a portion of either.

[0037] In some implementations, the dependent instruction generates a physical address by marking the target address in an entry of a filter table (208) associated with the target address of the dependent instruction (504). This is done by the control logic (204) marking the entry in the filter table (208) with respect to the target address. In some implementations, the control logic (204) marks the entry in a manner that uses minimal power. For example, in some implementations, the control logic (204) writes the value "0x03" to indicate a non-zero entry.

[0038] In some implementations, detecting that a specific time slot has been reused in a queue that is being deallocated in program order is performed by the control logic (204) monitoring the filter table shift trigger (206) for a condition to shift the filter table (208). In some implementations, the condition is the reuse of a specified time slot in the queue. In some implementations, shifting (506) of table entries in the filter table (208) in response to detecting that a specific time slot has been reused in a queue that is being deallocated in program order is performed by the control logic (204) advancing each table entry by one unit to ensure that when an entry is zero, there is no in-process load / store with the same physical address bits as the address index. In some implementations, the queue that is being deallocated in program order is either a store queue or a load trace queue, depending on the violation of the sorted memory structure for which the filtering is performed. Alternatively, in some implementations, the filter table shift trigger (206) detects the reuse of a pre-selected reorder buffer ID in the instruction window.

[0039] To further explain, Figure 6 , Figure 7 and Figure 8 The illustration shows Figure 3 , Figure 4 and Figure 5 A flowchart illustrating the context of the methods described in [the document]. Specifically, Figure 6 , Figure 7 and Figure 8 Flowcharts are provided to illustrate examples of storage in the context of Load Forwarding (STLF) CAM, Out-of-Order Buffer (OOB) CAM, and Load Order Queue (LOQ) CAM. Figure 6 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation is presented within the context of an implementation based on STLFCAM. (As shown in...) Figure 3 , Figure 4 and Figure 5 In the combination, Figure 6 This includes maintaining (302) a filter table that includes table entries associated with address ranges, which includes detecting (502) that a dependent (store) instruction has generated a physical address, indicating (504) that a dependent (store) instruction has generated a physical address in an entry in the filter table (208A) associated with the target address of the dependent (store) instruction, and shifting (506) a table entry in the filter table (208A) in response to detecting that a specific time slot has been reused in a queue that is deallocated in program order. Figure 6It also includes, in response to receiving a sort check trigger transaction (load instruction) (320), using the target address lookup (304) of the sort check trigger transaction (load instruction) (320) to query the filter table (208A) to determine whether the (store) instruction dependent on the sort check trigger transaction (load instruction) (320) has previously generated a physical address; in response to determining that the filter table (208A) lacks an indication that the (store) instruction dependent on the sort check trigger transaction (load instruction) (320) has previously generated a physical address, bypassing (306) a lookup operation in the sorted memory structure for determining whether the (store) instruction dependent on the sort check trigger transaction (load instruction) (320) is currently in progress; and in response to determining that the filter table (208A) includes an indication that the (store) instruction dependent on the sort check trigger transaction (load instruction) (320) has previously generated a physical address, performing (402) a lookup operation in the sorted memory structure (210A) for determining whether the (store) instruction dependent on the sort check trigger transaction (load instruction) (320) is currently in progress.

[0040] exist Figure 6 In the exemplary method, the detection (502) of the dependent instruction having generated a physical address is achieved by the control logic (204) detecting that the storage instruction has been executed by generating a physical address by the address generation unit (202A). Each time the control logic (204) is notified that the address generation unit (202A) has generated a physical address for the storage instruction, the filter table (208A) of the STLF CAM (210A) is updated. Specifically, in Figure 6 In the exemplary method, the entry in the filter table (208A) associated with the target address of the dependent instruction indicates (504) that the dependent instruction generates a physical address by performing the following: the control logic (204) uses a subset of the bits of the target address of the stored instruction (i.e., a portion of the physical or logical address) as the identifier of the entry in the filter table (208A) of the STLF CAM (210A). This entry, representing a range of target addresses, is marked with 0x03. This action indicates the presence of an in-process stored instruction for an address within the indicated entry range.

[0041] exist Figure 6 In the exemplary method, shifting (506) a table entry in the filter table (208A) in response to detecting that a specific time slot has been reused in a queue that is programmatically deallocated is performed by control logic (204) detecting that a pre-programmed time slot in the storage queue (206A) has been reused. If a partial or complete pipeline flush occurs, the table is not modified. Because the storage queue is allocated and deallocated programmatically, it operates in a manner similar to a first-in, first-out queue, thus eliminating the need to flush the table.

[0042] exist Figure 6 In the exemplary method, the receiving sorting check trigger transaction (320) detects through control logic (204) that a load instruction has been executed by generating a physical address from the address generation unit (202A). Each time the control logic (204) is notified that the address generation unit (202A) has generated a physical address for the load instruction, the filter table (208A) of the STLF CAM (210A) is queried. Figure 6 In the exemplary method, the target address query (304) of the sort check triggering transaction (320) is used to query the filter table (208A) to determine whether the instruction that depends on the sort check triggering transaction (320) has previously generated a physical address. This is performed by the control logic (204) using the target address of the load instruction to query the filter table (208A) to determine whether the in-process storage instruction has previously generated a physical address in the same range as the target address of the load instruction.

[0043] exist Figure 6 In the exemplary method, if it is determined that the filter table (208A) lacks an indication that the instruction that triggers the transaction (320) based on the sort check has previously generated a physical address, the control logic (204) accesses the STLF CAM filter table (208A) using a portion of the target address of the load instruction and reads a zero entry (e.g., "0x0") to execute. Therefore, the control logic (204) determines that an associated entry in the filter table (208A) lacks an indication that the in-process store instruction for the same target address range has previously generated a physical address by the address generation unit (202A).

[0044] exist Figure 6 In the exemplary method, bypassing (306) the lookup operation in the sorted memory structure for determining whether an instruction that depends on the sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) bypasses the lookup operation in the STLF CAM (210A) for determining whether a storage instruction is currently in progress (i.e., whether data is stored in the target physical address by an in-progress storage instruction).

[0045] exist Figure 6In the exemplary method, determining that the filter table (208A) includes an indication that the physical address of the instruction that triggers the transaction (320) based on the sort check has been previously generated, is performed by the control logic (204) accessing the STLF CAM filter table (208A) using a portion of the target address of the load instruction and reading out non-zero entries. Therefore, the control logic (204) determines that associated entries in the filter table (208A) include an indication that the physical address of an in-process store instruction targeting the same target address range has been previously generated by the address generation unit (202A).

[0046] exist Figure 6 In the exemplary method, the execution (402) of a lookup operation in the violation of the sorted memory structure (210A) to determine whether an instruction dependent on the sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) performs a CAM lookup operation on the STLF CAM (210A) to determine whether a load instruction is subject to a dependency on an in-progress store instruction.

[0047] Figure 7 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation is presented within the context of an implementation based on OOB CAM. (See also...) Figure 3 , Figure 4 and Figure 5 In the combination, Figure 7 This includes maintaining (302) a filter table containing table entries associated with address ranges, which includes detecting (502) that a dependent (load) instruction has generated a physical address, indicating (504) that a dependent (load) instruction has generated a physical address in an entry of the filter table (208B) associated with the target address of the dependent (load) instruction, and shifting (506) a table entry in the filter table (208B) in response to detecting that a specific time slot has been reused in a queue that is deallocated in program order. Figure 7It also includes, in response to receiving a sort check trigger transaction (store instruction) (320), using the target address of the sort check trigger transaction (store instruction) (320) to query (304) a filter table (208B) to determine whether a (load) instruction dependent on the sort check trigger transaction (store instruction) (320) has previously generated a physical address; in response to determining that the filter table (208B) lacks an indication that a (load) instruction dependent on the sort check trigger transaction (store instruction) (320) has previously generated a physical address, bypassing (306) a lookup operation in the sorted memory structure for determining whether a (load) instruction dependent on the sort check trigger transaction (store instruction) (320) is currently in progress; and in response to determining that the filter table (208B) includes an indication that a (load) instruction dependent on the sort check trigger transaction (store instruction) (320) has previously generated a physical address, performing (402) a lookup operation in the sorted memory structure (210B) for determining whether a (load) instruction dependent on the sort check trigger transaction (store instruction) (320) is currently in progress.

[0048] exist Figure 7 In the exemplary method, the detection (502) of the dependent instruction having generated a physical address is achieved by the control logic (204) detecting that the load instruction has been executed by generating a physical address by the address generation unit (202B). Each time the control logic (204) is notified that the address generation unit (202B) has generated a physical address for the load instruction, the filter table (208B) of the OOB CAM (210B) is updated. Specifically, in Figure 7 In the exemplary method, the control logic (204) indicates (504) that the dependent instruction generates a physical address by executing the following in an entry of a filter table (208B) associated with the target address of the dependent instruction: the control logic (204) uses a subset of the bits of the target address of the load instruction (i.e., a portion of the physical or logical address) as the identifier of the entry in the filter table (208B) of OOBCAM (210B). This entry, representing a range of target addresses, is marked with 0x03. This action indicates the presence of an in-process load instruction for an address within the indicated entry range.

[0049] exist Figure 7In the exemplary method, shifting (506) a table entry in the filter table (208B) in response to detecting that a specific time slot has been reused in a queue that is deallocated in program order is performed by control logic (204) detecting that a pre-programmed time slot in the load trace queue (206B) has been reused. The load trace queue (206B) is a bit vector indexed by load IDs and is allocated during dispatch (in program order) and deallocated during decommissioning (again in program order). The load trace queue (206B) sets a bit when the corresponding load ID has been reserved by an in-progress load. The load trace queue (206B) is managed as a first-in, first-out queue and is cleared from the load trace queue (206B) upon pipeline cleanup by the load ID of the erroneous load or the load ID of the oldest load closest to the erroneous instruction or the micro-operation that triggered the pipeline cleanup.

[0050] exist Figure 7 In the exemplary method, the receiving sorting check trigger transaction (320) detects through control logic (204) that a storage instruction has been executed by generating a physical address from the address generation unit (202B). Each time the control logic (204) is notified that the address generation unit (202B) has generated a physical address for the storage instruction, the filter table (208B) of the OOB CAM (210B) is queried. Figure 7 In the exemplary method, the target address query (304) of the sort check triggering transaction (320) is used to query the filter table (208B) to determine whether the instruction that depends on the sort check triggering transaction (320) has previously generated a physical address. This is performed by the control logic (204) using the target address of the stored instruction to query the filter table (208B) to determine whether the load instruction has previously generated a physical address in the same range as the target address of the stored instruction.

[0051] exist Figure 7 In the exemplary method, if it is determined that the filter table (208B) lacks an indication that the instruction relying on the sort check to trigger the transaction (320) has previously generated a physical address, the control logic (204) accesses the OOB CAM filter table (208B) using a portion of the target address of the stored instruction and reads out a zero entry to execute. Therefore, the control logic (204) determines that the associated entry in the filter table (208B) lacks an indication that the load instruction for the same target address range has previously generated a physical address by the address generation unit (202B).

[0052] exist Figure 7In the exemplary method, bypassing (306) the lookup operation in the sorted memory structure for determining whether an instruction that depends on the sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) bypasses the lookup operation in the OOB CAM (210B) for determining whether a load instruction is currently in progress (i.e., whether data is loaded from the targeted physical address by an in-progress load).

[0053] exist Figure 7 In the exemplary method, determining that the filter table (208B) includes an indication that the physical address of the instruction that triggers the transaction (320) based on the sorting check has been previously generated, is performed by the control logic (204) accessing the OOB CAM filter table (208B) using a portion of the target address of the stored instruction and reading out non-zero entries. Therefore, the control logic (204) determines that associated entries in the filter table (208B) include an indication that the physical address of a load instruction targeting the same target address range has been previously generated by the address generation unit (202B).

[0054] exist Figure 7 In the exemplary method, the execution (402) of a lookup operation in the violation memory structure (210B) for determining whether an instruction dependent on a sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) performing a CAM lookup operation on the OOB CAM (210B) for determining whether a storage instruction has suffered a violation of sorting.

[0055] Figure 8 A flowchart illustrating an exemplary method for address-based filtering for load / store speculation is presented within the context of an implementation based on LOQ CAM. (See also...) Figure 3 , Figure 4 and Figure 5 In the combination, Figure 8 This includes maintaining (302) a filter table containing table entries associated with address ranges, which includes detecting (502) that a dependent (first load) instruction has generated a physical address, indicating (504) that a dependent (first load) instruction has generated a physical address in an entry in the filter table (208C) associated with the target address of the dependent (first load) instruction, and shifting (506) a table entry in the filter table (208C) in response to detecting that a specific time slot has been reused in a queue that is deallocated in program order. Figure 8It also includes, in response to receiving a sort check triggering transaction (second load instruction) (320), using the target address lookup (304) of the sort check triggering transaction (second load instruction) (320) to query a filter table (208C) to determine whether a (first load) instruction dependent on the sort check triggering transaction (second load instruction) (320) has previously generated a physical address; and in response to determining that the filter table (208C) lacks an indication that a (first load) instruction dependent on the sort check triggering transaction (second load instruction) (320) has previously generated a physical address, bypassing (306) a sort violation. A lookup operation in the memory structure for determining whether the (first load) instruction dependent on the sort check triggering transaction (second load instruction) (320) is currently in progress; and in response to determining that the filter table (208C) includes an indication that the (first load) instruction dependent on the sort check triggering transaction (second load instruction) (320) has previously generated a physical address, (402) a lookup operation in the memory structure (210C) for determining whether the (first load) instruction dependent on the sort check triggering transaction (second load instruction) (320) is currently in progress is executed.

[0056] exist Figure 8 In the exemplary method, the detection (502) of the dependent instruction having generated a physical address is achieved by the control logic (204) detecting that the load instruction has been executed by generating a physical address by the address generation unit (202C). Each time the control logic (204) is notified that the address generation unit (202C) has generated a physical address for the load instruction, the filter table (208C) of the LOQ CAM (210C) is updated. Specifically, in Figure 8 In the exemplary method, the control logic (204) indicates (504) that the dependent instruction generates a physical address by executing the following in an entry of a filter table (208C) associated with the target address of the dependent instruction: the control logic (204) uses a subset of the bits of the target address of the load instruction (i.e., a portion of the physical or logical address) as the identifier of the entry in the filter table (208C) of LOQCAM (210C). This entry, representing a range of target addresses, is marked with 0x03. This action indicates the presence of an in-process load instruction for an address within the indicated entry range.

[0057] exist Figure 8 In the exemplary method, shifting (506) a table entry in the filter table (208C) in response to detecting that a specific time slot has been reused in a queue that is programmatically deallocated is performed by control logic (204) detecting that a pre-programmed time slot in the load trace queue (206C) has been reused. In some embodiments, the load trace queue (206C) is used as a filter table shift trigger in both OOB CAM and LOQ CAM backgrounds.

[0058] exist Figure 8 In the exemplary method, the receiving sort check trigger transaction (320) is executed upon the control logic (204) detecting that a cache probe or cache eviction has occurred. Each time the control logic (204) is notified that a cache probe or cache eviction has occurred, the filter table (208C) of the LOQ CAM (210C) is queried. Figure 8 In the exemplary method, the target address lookup (304) of the sort check triggering transaction (320) is used to query the filter table (208C) to determine whether the physical address of the instruction that depends on the sort check triggering transaction (320) has been previously generated. This is performed by the control logic (204) using the target address of the cache probe or cache eviction victim to query the filter table (208C) to determine whether the load instruction has been previously generated in the same range as the target address of the cache probe or cache eviction victim.

[0059] exist Figure 8 In the exemplary method, if it is determined that the filter table (208C) lacks an indication that the instruction relying on the sort check to trigger the transaction (320) has previously generated a physical address, the control logic (204) accesses the LOQ CAM filter table (208C) using a portion of the target address probed by the cache and reads out a zero entry to execute. Therefore, the control logic (204) determines that the associated entry in the filter table (208B) lacks an indication that the load instruction for the same target address range has previously generated a physical address by the address generation unit (202C).

[0060] exist Figure 8 In the exemplary method, bypassing (306) the lookup operation in the sorted memory structure for determining whether an instruction that depends on the sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) bypasses the lookup operation in the LOQ CAM (210C) for determining whether a load instruction is currently in progress (i.e., whether data is loaded from the targeted physical address by an in-progress load).

[0061] exist Figure 8 In the exemplary method, the filter table (208C) is determined to include an indication that the instruction that triggers the transaction (320) based on the sort check has previously generated a physical address. The control logic (204) accesses the LOQ CAM filter table (208C) using a portion of the target address probed by the cache and reads non-zero entries to execute. Therefore, the control logic (204) determines that associated entries in the filter table (208C) include an indication that a load instruction targeting the same target address range has previously generated a physical address by the address generation unit (202C).

[0062] exist Figure 8 In the exemplary method, the execution (402) of a lookup operation in the violation memory structure (210C) for determining whether an instruction dependent on a sort check triggering transaction (320) is currently in progress is performed by the following: control logic (204) performing a CAM lookup operation on the LOQ CAM (210C) for determining whether a cache probe or cache eviction victim has suffered a memory violation.

[0063] Based on the above explanation, the reader will recognize the benefits of address-based filtering based on load / store speculation according to the implementation scheme, including:

[0064] ● The operation of the computing system is improved by maintaining a filter table for incoming sorting checks that trigger transactions (such as load instructions, store instructions, cache probes, cache evictions). In some cases, the power efficiency of the computing system can be improved by using cheaper filter table access to identify missing dependent instructions.

[0065] ● By reducing dynamic power consumption without performance degradation, the operation of the computing system is improved, thereby increasing the power efficiency of loading / storing micro-operations in the processor core.

[0066] Exemplary embodiments are described primarily within the context of a full-featured computer system for performing address-based filtering for load / store speculation. Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0067] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this respect, each box in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions indicated in the boxes may not occur in the order shown in the figures. For example, two boxes shown consecutively may actually be executed substantially simultaneously, or sometimes they may be executed in reverse order, depending on the functions involved. It should also be noted that each box in the block diagrams and / or flowcharts, and combinations of boxes in the block diagrams and / or flowcharts, may be implemented by a system based on dedicated hardware that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0068] The above describes a method for address-based filtering for load / store speculation, comprising: maintaining a filtering table including table entries associated with address ranges; in response to receiving a sort check triggering transaction, querying the filtering table using the target address of the sort check triggering transaction to determine whether an instruction dependent on the sort check triggering transaction has previously generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent on the sort check triggering transaction has previously generated a physical address, bypassing a lookup operation in the sorted memory structure for determining whether the instruction dependent on the sort check triggering transaction is currently in progress.

[0069] The method may include: in response to determining that the filter table includes an indication that the instruction dependent on the sort check triggering transaction has previously generated a physical address, performing a lookup operation in the violation sort memory structure for determining whether the instruction dependent on the sort check triggering transaction is currently in progress.

[0070] The above also describes a load memory unit for the processor, a processor, and a device having address-based filtering for load / store speculation. The load memory unit includes a filtering table comprising table entries associated with address ranges, and control logic for the load memory unit maintains the filtering table; in response to receiving a sort check triggering transaction, the filtering table is queried using the target address of the sort check triggering transaction to determine whether an instruction dependent on the sort check triggering transaction has previously generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent on the sort check triggering transaction has previously generated a physical address, a lookup operation in the violation sort memory structure for determining whether the instruction dependent on the sort check triggering transaction is currently in progress is bypassed.

[0071] The control logic, in response to determining that the filter table includes an indication that the instruction dependent on the sort check triggering transaction has previously generated a physical address, executes a lookup operation in the violation sort memory structure to determine whether the instruction dependent on the sort check triggering transaction is currently in progress.

[0072] Maintaining the filter table, which includes table entries for address ranges, may include: detecting that a dependent instruction has generated a physical address; and indicating in the filter table entry associated with the target address of the dependent instruction that the dependent instruction generated the physical address. Maintaining the filter table, which includes table entries associated with address ranges, may further include: shifting the table entry in the filter table in response to detecting that a specific time slot has been reused in a queue for program-ordered deallocation. The queue for program-ordered deallocation may be a storage queue or a load trace queue. Maintaining the filter table, which includes table entries associated with address ranges, may further include: shifting the table entry in the filter table in response to detecting the reuse of a pre-selected reorder buffer ID. The filter table may include multiple separate tables.

[0073] The sorting check triggering transaction can be a load instruction. Therefore, receiving the sorting check triggering transaction can include detecting that the load instruction has generated a physical address; querying the filter table using the target address of the sorting check triggering transaction to determine whether an instruction dependent on the sorting check triggering transaction has previously generated a physical address can include querying the filter table using the target address of the load instruction to determine whether a storage instruction has previously generated a physical address; determining that the filter table lacks an indication, i.e., an indication that the instruction dependent on the sorting check triggering transaction has previously generated a physical address, can include determining that the filter table lacks an indication that the storage instruction has previously generated a physical address; and bypassing a lookup operation in the violation-of-sorting memory structure for determining whether the instruction dependent on the sorting check triggering transaction is currently in progress can include bypassing a lookup operation in the load-forward memory structure for determining whether the storage is currently in progress.

[0074] The sorting check triggering transaction can be a storage instruction. Therefore, receiving the sorting check triggering transaction can include detecting that the storage instruction has generated a physical address; querying the filter table using the target address of the sorting check triggering transaction to determine whether an instruction dependent on the sorting check triggering transaction has previously generated a physical address can include querying the filter table using the target address of the storage instruction to determine whether a load instruction has previously generated a physical address; determining that the filter table lacks an indication, i.e., an indication that the instruction dependent on the sorting check triggering transaction has previously generated a physical address, can include determining that the filter table lacks an indication that the load instruction has previously generated a physical address; and bypassing the lookup operation in the violation-ordered memory structure for determining whether the instruction dependent on the sorting check triggering transaction is currently in progress can include bypassing the lookup operation in the unordered buffer memory structure for determining whether the load is currently in progress.

[0075] The reader will understand that the steps described herein can be performed in various ways and do not require a specific order. It will be further understood from the foregoing description that modifications and changes can be made in various embodiments of this disclosure. The descriptions in this specification are for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is limited only by the language of the appended claims.

Claims

1. A load memory unit for a processor having address-based filtering for load / store speculation, the load memory unit comprising: A filter table, comprising table entries associated with address ranges, The control logic for the loading storage unit is configured as follows: Maintain the filter table; In response to receiving a sort check triggered transaction, the filter table is queried using the target address of the sort check triggered transaction to determine whether a physical address has been previously generated for instructions dependent on the sort check triggered transaction; and In response to determining that the filter table lacks an indication that the instruction dependent on the sort check triggering transaction has previously generated a physical address, a lookup operation in the sort memory structure for determining whether the instruction dependent on the sort check triggering transaction is currently in progress is bypassed.

2. The loading storage unit as claimed in claim 1, wherein the control logic is further configured to: In response to determining that the filter table includes an indication that the instruction depending on the sort check triggering transaction has previously generated a physical address, a lookup operation in the violation sort memory structure for determining whether the instruction depending on the sort check triggering transaction is currently in progress is performed.

3. The loading storage unit as described in claim 1, wherein the control logic is further configured to: The detection dependency instruction has generated a physical address; and The entry in the filter table associated with the target address of the dependent instruction indicates that the dependent instruction generated the physical address.

4. The loading storage unit as claimed in claim 1, wherein the control logic is further configured to: In response to the detection that a specific time slot has been reused in a queue that is being deallocated in a procedural order, the table entry in the filter table is shifted.

5. The load storage unit of claim 4, wherein the queue that is deallocated in program order is selected from a group consisting of a storage queue and a load tracking queue.

6. The loading storage unit as claimed in claim 1, wherein the control logic is further configured to: In response to the detection of reuse of the preselected reorder buffer ID, the table entry in the filter table is shifted.

7. The loading storage unit as claimed in claim 1, wherein the filtering table comprises a plurality of separate tables.

8. The loading storage unit as claimed in claim 1, wherein: The sorting check triggers a load instruction. Receiving the sort check triggered transaction includes detecting that the load instruction has generated a physical address. The filter table is queried using the target address of the sort check-triggered transaction to determine whether the physical address of the instruction dependent on the sort check-triggered transaction has been previously generated, including querying the filter table using the target address of the load instruction to determine whether the physical address of the store instruction has been previously generated. Determining that the filter table lacks an indication, namely an indication that the instruction that triggered the transaction based on the sorting check has previously generated a physical address, includes determining that the filter table lacks an indication that the storage instruction has previously generated a physical address, and Bypassing the lookup operation in the violation ordering memory structure for determining whether the instruction that triggers the transaction depending on the ordering check is currently in progress includes bypassing the lookup operation in the load forwarding memory structure for determining whether the storage is currently in progress.

9. The loading storage unit as claimed in claim 1, wherein: The sorting check triggers a storage instruction. Receiving the sorting check-triggered transaction includes detecting that the storage instruction has generated a physical address. The filter table is queried using the target address of the sort check-triggered transaction to determine whether the physical address of the instruction dependent on the sort check-triggered transaction has been previously generated, including querying the filter table using the target address of the stored instruction to determine whether the physical address of the load instruction has been previously generated. Determining that the filter table lacks an indication, namely an indication that the instruction that triggered the transaction based on the sorting check had previously generated a physical address, includes determining that the filter table lacks an indication that the load instruction had previously generated a physical address, and Bypassing the lookup operation in a violation-ordered memory structure for determining whether an instruction that triggers a transaction dependent on the order check is currently in progress includes bypassing the lookup operation in an unordered buffer memory structure for determining whether a load is currently in progress.

10. The loading storage unit as claimed in claim 1, wherein: The sorting check triggering transaction is a cache event, which includes cache probing or cache eviction. Receiving the sorting check-triggered transaction includes detecting that the cache event has generated a physical address. The target address of the transaction triggered by the sort check is used to query the filter table to determine whether the physical address of the instruction dependent on the transaction triggered by the sort check has been previously generated. This includes querying the filter table using the target address of the cache event to determine whether the physical address of the load instruction has been previously generated. Determining that the filter table lacks an indication, namely an indication that the instruction that triggered the transaction based on the sorting check had previously generated a physical address, includes determining that the filter table lacks an indication that the load instruction had previously generated a physical address, and Bypassing the lookup operation in the violation ordering memory structure for determining whether the instruction that triggers the transaction depending on the ordering check is currently in progress includes bypassing the lookup operation in the load ordering queue memory structure for determining whether the load is currently in progress.

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