Method for doping silicon

Abstract

A method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on the surface of the substrate. At least one dopant layer is deposited on the silicon oxide diffusion barrier layer. A cap layer is deposited on the at least one dopant layer to form a stack of a substrate, a silicon oxide diffusion barrier layer, at least one dopant layer and a cap layer. The stack is annealed. The cap layer, at least one dopant layer and the silicon oxide diffusion barrier layer are removed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Patent Application No. 62 / 822,423, filed on March 22, 2019, which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to the formation of semiconductor devices. More particularly, the present disclosure relates to the formation of semiconductor devices having doped silicon regions. Background Art

[0004] In the formation of semiconductor devices, a substrate (e.g., a silicon substrate) may be doped with dopants. Sometimes a uniform doping profile is used. Other times a non-uniform doping profile is used. Summary of the invention

[0005] In order to achieve the aforementioned and the purposes of the present disclosure, a method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on a surface of the substrate. At least one dopant layer is deposited on the silicon oxide diffusion barrier layer. A cap layer is deposited on the at least one dopant layer to form a stack of a substrate, a silicon oxide diffusion barrier layer, at least one dopant layer, and a cap layer. The stack is annealed. The cap layer, at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description of the present disclosure and in conjunction with the following figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the accompanying figures and in which like reference numerals indicate similar elements and in which:

[0008] Figure 1 is a flow chart of an implementation scheme;

[0009] Figures 2A-2F is a schematic cross-sectional view of a stack processed according to one embodiment;

[0010] Figure 3A is a schematic cross-sectional top view of a processing chamber that may be used in one embodiment.

[0011] Figure 3B yes Figure 3A A cross-sectional schematic side view of the embodiment shown.

[0012] Figure 3C yes Figure 3B Magnified view of area 3C.

[0013] Figure 4is a flow chart of a more detailed view of the atomic layer deposition process.

[0014] Figure 5 is a schematic diagram of a computer system that may be used to implement an embodiment. DETAILED DESCRIPTION

[0015] The present disclosure will now be described in detail with reference to several preferred embodiments shown in the accompanying drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be implemented without some or all of these specific details. In other cases, well-known process steps and / or structures are not described in detail to avoid making the present disclosure unclear unnecessarily.

[0016] Borosilicate glass (BSG) film deposition uses a nano-laminated stack of boron oxide (B2O3) and silicon oxide (SiO2) with a capping oxide on top to prevent external diffusion. During the deposition of boron oxide and SiO2, an uncontrolled interface oxide is formed due to the interaction of the oxidizing plasma with the silicon substrate. This usually results in a thinner interface oxide thickness at the edge of the silicon substrate, resulting in higher boron diffusion.

[0017] To enhance understanding of the implementation plan, Figure 1 is a flow chart of one embodiment. A substrate is provided (step 104). Figure 2A 2 is a schematic cross-sectional view of a substrate 200 in one embodiment. The substrate 200 may be polysilicon formed on other layers.

[0018] A silicon oxide diffusion barrier layer is formed on the surface of the substrate 200. In this embodiment, an atomic layer deposition (ALD) process is used to deposit the silicon oxide deposition layer. Figure 3A is a schematic cross-sectional top view of a processing chamber 300 having four processing stations that may be used in an atomic layer deposition process. Figure 3B for Figure 3AA schematic side view of a process chamber 300 is shown in cross section. The process chamber 300 has a chamber wall 304. Four process stations are located within the chamber wall 304. Each process station contains a pedestal 312, which acts as a substrate support to support a wafer 308, a showerhead 316 (for providing gas to the wafer 308 located below the showerhead 316), and a manifold 320, which connects the showerhead 316 to a gas source 322. In this embodiment, the gas source 322 includes a first gas source 328, a second gas source 332, and a primary purge gas source 336. A secondary purge gas outlet 324 is in fluid communication with the secondary purge gas source 326. In this embodiment, the secondary purge gas outlet 324 is in the shape of a cylindrical collar surrounding the manifold 320. The cylindrical collar has a plurality of holes that enable the secondary purge gas to flow outwardly in a radial direction over the top of the showerhead 316. A carrier ring 310 surrounds the wafer 308. A portion of the carrier ring 310 is below the wafer 308. The carrier ring 310 may be a dielectric ceramic material, such as alumina. The carrier ring 310 may be used to move the wafer 308 into and out of the processing chamber 300 and between various chambers. The controller 335 is controllably connected to the gas source 322, the secondary purge gas source 326, the radio frequency (RF) power system 340, and the vacuum system 344. An example of such a chamber is manufactured by Lam Research Corporation of Fremont, CA. Oxide system. The substrate 200 is formed on the wafer 308 in a stacked manner.

[0019] Figure 4 Flow chart of an atomic layer deposition process for forming a silicon oxide diffusion barrier. A flow of a secondary purge gas is provided (step 404). In this example, the secondary purge gas is oxygen (O2). Oxygen is at least one component gas of the secondary purge gas. The secondary purge gas 348 flows from the secondary purge gas outlet 324 over the top of the showerhead 316 to form a secondary purge gas curtain 352 around the outer edge of the showerhead 316.

[0020] Simultaneously with the flow of the secondary purge gas (step 404), an atomic layer deposition process (step 408) is provided, which deposits an ALD layer. The atomic layer deposition process (step 408) includes multiple cycles, wherein each cycle includes providing a first reactant gas (step 412), purging the first reactant gas (step 414), providing a second reactant gas (step 416), and purging the second reactant gas (step 418). An example of a recipe for an atomic layer deposition process (step 408) provides a first reactant gas, such as 400 sccm of aminosilane (step 412). A silicon-containing precursor layer is deposited. After 0.4 seconds, the flow of the first reactant gas through the nozzle 316 is stopped. The first purge gas flows to the station through the nozzle 316 (step 414). In this example, the first purge gas is argon (Ar). The flow of the first purge gas is stopped. The second reactant gas flows into the processing chamber through the nozzle 316 (step 416). In this example, the second reactant gas is oxygen-free and contains an inert gas, such as 13000 sccm of Ar. The second reactant gas is converted to a plasma. In this example, 100 to 500 watts of RF power is provided at a frequency of 13.56 (megahertz) MHz. The plasma from the second reactant gas and the secondary purge gas convert the deposited silicon-containing precursor layer into silicon oxide, which is part of the ALD layer. After 0.25 seconds, the flow of the second reactant gas into the processing chamber is stopped. The purge gas is flowed into the processing chamber to purge the second reactant gas (step 418). The flow of the second purge gas is stopped. The cycle is then repeated starting from the step of flowing the precursor gas into the processing chamber. The cycle is repeated until the silicon oxide diffusion barrier is completed.

[0021] Figure 2B is a schematic cross-sectional view of substrate 200 after deposition of silicon oxide diffusion barrier layer 204. It was unexpectedly discovered that by providing oxygen in the flow of the secondary purge gas instead of through a showerhead, a silicon oxide diffusion barrier layer 204 is formed that is thicker around the outer edges of substrate 200 than over the center of substrate 200.

[0022] Next, at least one dopant layer is deposited on the silicon oxide diffusion barrier layer 204 (step 112 ). In this example, five dopant layers are formed on the silicon oxide diffusion barrier layer 204 . Figure 2C2 is a schematic cross-sectional view of substrate 200 after five dopant layers are formed on silicon oxide diffusion barrier layer 204. In this example, the five dopant layers are first boron-containing layer 208, second boron-containing layer 212, third boron-containing layer 216, fourth boron-containing layer 220, and fifth boron-containing layer 224. In this embodiment, first boron-containing layer 208, second boron-containing layer 212, third boron-containing layer 216, fourth boron-containing layer 220, and fifth boron-containing layer 224 are all boron oxide layers. The shading indicates the presence of boron. First boron-containing layer 208, second boron-containing layer 212, third boron-containing layer 216, fourth boron-containing layer 220, and fifth boron-containing layer 224 may be deposited by ALD processing.

[0023] Such ALD treatment may flow the first dopant reactant gas containing trimethyl borate (TMB). The first dopant reactant gas is formed into plasma to deposit a boron-containing precursor layer. After the first dopant reactant gas is swept, the second dopant reactant gas containing oxygen is flowed. The second dopant reactant gas is formed into plasma to form a boron oxide layer from a boron-containing precursor layer. The process repeats multiple cycles. In other embodiments, the first boron-containing layer 208, the second boron-containing layer 212, the third boron-containing layer 216, the fourth boron-containing layer 220 and the fifth boron-containing layer 224 can be formed by plasma enhanced atomic layer deposition (PEALD) processing, plasma enhanced chemical vapor deposition (PECVD) processing or chemical vapor deposition (CVD) processing. In other embodiments, other similar processes can be used to deposit the first boron-containing layer 208, the second boron-containing layer 212, the third boron-containing layer 216, the fourth boron-containing layer 220 and the fifth boron-containing layer 224.

[0024] A capping layer is deposited over the dopant layer (step 116). In this embodiment, the capping layer is deposited by at least one of a PEALD process, an ALD process, a PECVD process, or a CVD process. In this embodiment, the capping layer is a silicon oxide capping layer. In other embodiments, other similar processes may be used to deposit the capping layer. Figure 2D is a schematic cross-sectional view of substrate 200 after capping layer 228 has been deposited to form stack 232. Ideally, capping layer 228 is dense enough to limit out-diffusion of dopants from stack 232.

[0025] The stack 232 is annealed (step 120). In this example, the annealing process is performed in situ or by heating in a different furnace. The stack 232 is heated to a temperature exceeding 700° C. in a nitrogen (N2) or Ar atmosphere. The annealing process transfers dopants from the first boron-containing layer 208, the second boron-containing layer 212, the third boron-containing layer 216, the fourth boron-containing layer 220, and the fifth boron-containing layer 224 to the substrate 200 via the silicon oxide diffusion barrier layer 204. Figure 2E2 is a schematic cross-sectional view of the stack 232 after annealing. The shading indicates that the substrate 200 is doped with boron, and also indicates the depletion of boron in the first boron-containing layer 208 , the second boron-containing layer 212 , the third boron-containing layer 216 , the fourth boron-containing layer 220 , and the fifth boron-containing layer 224 .

[0026] The capping layer 228, the first boron-containing layer 208, the second boron-containing layer 212, the third boron-containing layer 216, the fourth boron-containing layer 220, the fifth boron-containing layer 224, and the silicon oxide diffusion barrier layer 204 are removed from the stack 232 (step 124). Wet etching using hydrofluoric acid (HF) may be used to remove the capping layer 228, the first boron-containing layer 208, the second boron-containing layer 212, the third boron-containing layer 216, the fourth boron-containing layer 220, the fifth boron-containing layer 224, and the silicon oxide diffusion barrier layer 204 from the stack 232. Figure 2F is a schematic cross-sectional view of stack 232 after removal of cap layer 228, first boron containing layer 208, second boron containing layer 212, third boron containing layer 216, fourth boron containing layer 220, fifth boron containing layer 224, and silicon oxide diffusion barrier layer 204. Doped substrate 200 remains. In this embodiment, doped substrate 200 is BSG.

[0027] By having a separate step (step 104) of forming the silicon oxide diffusion barrier layer 204, the thickness of the silicon oxide diffusion barrier layer 204 can be controlled. The controlled thickness of the silicon oxide diffusion barrier layer 204 provides control over the concentration profile of the dopant of the substrate 200. This embodiment provides more uniform doping of the underlying silicon devices across the wafer. The goal is to match the performance of each device in each die on the wafer.

[0028] Figure 3C yes Figure 3B 3C is shown. The first gap 364 is the distance between the wafer 308 and the carrier ring 310. The second gap 368 is the distance between the carrier ring 310 and the pedestal 312. The O-ring 360 is between the pedestal 312 and the wafer 308. If the first gap 364 is increased to enhance the plasma at the edge of the wafer 308, the enhanced plasma results in a lower thickness of the silicon oxide diffusion barrier layer 204 around the edge of the wafer 308 due to densification. In this embodiment, the first gap 364 is reduced, so the thickness of the silicon oxide diffusion barrier layer 204 around the edge of the substrate 308 is increased.

[0029] In other embodiments, the operation of depositing at least one dopant layer on the silicon oxide diffusion barrier layer 204 (step 112) deposits a first phosphorus-containing layer of phosphorus oxide (P2O5). The first phosphorus-containing layer can be deposited by an ALD process or the process described for boron oxide deposition. Other embodiments may deposit an arsenic-containing layer to provide an arsenic dopant. In other embodiments, the second dopant reactant gas contains an inert gas and oxygen. In some embodiments, a region of the substrate 200 on the wafer may be doped with boron, and another region of the substrate 200 may be doped with another dopant, such as phosphorus or arsenic. In different embodiments, the substrate 200 may be silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN). The substrate 200 may be a wafer or a layer deposited on a wafer.

[0030] In other embodiments, a thicker layer of silicon-containing precursor layer is deposited near the center of the substrate than a layer of silicon-containing precursor layer deposited near the edge of the substrate. In such embodiments, the deposited silicon oxide diffusion barrier layer 204 is thicker near the center of the substrate 200 than at the edge of the substrate 200.

[0031] In another embodiment, the silicon oxide diffusion barrier layer 204 may be formed by heating the substrate 200 (step 108). The substrate 200 is heated non-uniformly so that the thickness of the silicon oxide diffusion barrier layer 204 is non-uniform. For example, the edge around the substrate 200 is heated to a higher temperature than the center of the substrate 200. Therefore, the silicon oxide diffusion barrier layer 204 is thicker at the edge of the substrate 200 than the center of the substrate 200. In this example, silicon oxide is formed from the top surface of the substrate 200 instead of depositing silicon oxide on the substrate 200. Non-uniform heating of the substrate 200 can be provided by providing non-uniform heating throughout the pedestal 312. Oxygen is provided during the heating of silicon to form silicon oxide. In several embodiments, the substrate 200 is heated to a temperature in the range of 200°C to 900°C to form the silicon oxide diffusion barrier layer 204. More specifically, the substrate 200 is heated to a temperature in the range of 200°C to 650°C to form the silicon oxide diffusion barrier layer 204. Even more specifically, the substrate 200 is heated to a temperature in a range of 200° C. to 400° C. to form the silicon oxide diffusion barrier layer 204 .

[0032] In various embodiments, the substrate support in the form of a pedestal has multiple heating zones. In one embodiment, the substrate support has more than 20 independently controlled heating zones. The independently controlled heating zones are used to independently heat different parts of the substrate to different temperatures. These zones can be annular or rectangular or other different shapes and combinations of different shapes. In various embodiments, in order to correct other non-uniformities, the independently controlled heating zones can be set to provide a non-uniform temperature distribution throughout the substrate to produce a silicon oxide diffusion barrier layer 204 with a more uniform thickness. The other non-uniformity can be a non-uniform gas flow. The more uniform silicon oxide diffusion barrier layer 204 can be used to provide a more uniform doping concentration throughout the substrate 200. In other embodiments, the non-uniform temperature distribution provides an adjusted silicon oxide diffusion barrier layer 204, which has a non-uniform thickness. The substrate 200 is heated non-uniformly so that a thicker silicon oxide diffusion barrier layer 204 is formed on a higher temperature area of ​​the substrate 200. In several embodiments, the non-uniform thickness of the silicon oxide diffusion barrier layer 204 can be used to provide a more uniform concentration of doping of the substrate 200. In other embodiments, the non-uniform thickness of the silicon oxide diffusion barrier layer 204 can be used to provide a tuned non-uniform concentration doping of the substrate 200. The non-uniform thickness of the silicon oxide diffusion barrier layer 204 can be used to control the uniformity of the doping concentration.

[0033] In an exemplary embodiment, the secondary purge gas may include O2, N2, Ar, carbon monoxide (CO), carbon dioxide (CO2), ozone (O3), or helium (He). In other exemplary embodiments, the secondary purge gas may be a mixture of O2 and N2 having a molecular number flow ratio in the range of 3:1 to 1:3. In other exemplary embodiments, the secondary purge gas may be a mixture of O2 and Ar or He having a molecular number flow ratio in the range of 3:1 to 1:3. Other gases (which are inert to the ALD process and are not ignited by the plasma during the ALD process) may be used in other embodiments. Because the secondary purge gas is not ignited by the ALD process and is inert, the secondary purge gas provides isolation between adjacent stations to avoid crosstalk.

[0034] Figure 5335 is a high-level block diagram showing a computer system 500 suitable for implementing a controller 335 used in the embodiments. Computer systems can have many physical forms ranging from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. Computer system 500 includes one or more processors 502, and may also include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., a random access memory (RAM)), a storage device 508 (e.g., a hard drive), a removable storage device 510 (e.g., an optical drive), a user interface device 512 (e.g., a keyboard, a touch screen, a keypad, a mouse or other pointing device, etc.) and a communication interface 514 (e.g., a wireless network interface). The communication interface 514 allows software and data to be transmitted between the computer system 500 and external devices via a link. The system may also include a communication infrastructure 516 (e.g., a communication bus, a cross-connect bar, or a network) connected to the above-mentioned devices / modules.

[0035] The information transmitted via the communication interface 514 may be in the form of a signal, such as an electronic signal, an electromagnetic signal, an optical signal, or other signal that can be received by the communication interface 514 via a communication link, which carries the signal and can be implemented using a wire or cable, an optical fiber, a telephone line, a cellular phone link, a radio frequency link, and / or other communication channels. Using such a communication interface, it is contemplated that the one or more processors 502 may receive information from a network during the execution of the above-described method steps, or may output information to a network. In addition, the method embodiments may be executed solely on a processor, or may be executed in conjunction with a remote processor that shares a portion of the processing over a network such as the Internet.

[0036] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering transient subject matter such as carrier waves or signals. Examples of computer code include machine code (such as produced by a compiler) and files containing higher-level code executed by a computer using an interpreter. The computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a series of instructions that can be executed by a processor.

[0037] Although the present invention has been described according to several preferred embodiments, there are changes, modifications, permutations and various alternative equivalents that fall within the scope of the present invention. It should also be noted that there are many alternatives to the methods and devices of the present disclosure. Therefore, the following appended claims are intended to be interpreted as including all such changes, modifications, permutations and various alternative equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. A method for doping a substrate, comprising: forming a silicon oxide diffusion barrier layer on the surface of the substrate, wherein the silicon oxide diffusion barrier layer has a non-uniform thickness to control the uniformity of the doping concentration of the substrate; depositing at least one dopant layer on the silicon oxide diffusion barrier layer; depositing a capping layer on the at least one dopant layer to form a stack of the substrate, the silicon oxide diffusion barrier layer, the at least one dopant layer, and the capping layer; annealing the stack; as well as The cap layer, the at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.

2. The method of claim 1, wherein the substrate has an outer edge and a center, and wherein the silicon oxide diffusion barrier layer is thicker on the outer edge of the substrate than on the center of the substrate. 3 . The method of claim 2 , wherein forming the silicon oxide diffusion barrier layer comprises heating the substrate, wherein the outer edge of the substrate is heated to a temperature higher than a temperature of a center of the substrate. 4 . The method of claim 1 , wherein forming the silicon oxide diffusion barrier layer comprises providing an atomic layer deposition process.

5. The method of claim 4, wherein the atomic layer deposition process comprises a plurality of cycles, wherein each cycle comprises: flowing a first reactant gas comprising a silicon-containing precursor; depositing a silicon-containing precursor layer; stopping the flow of the first reactant gas; flowing a second reactant gas; providing RF power to convert the second reactant gas into a plasma; converting the silicon-containing precursor layer into silicon oxide; and The flow of the second reactant gas is stopped.

6. The method of claim 5, wherein the substrate is located below a showerhead in a processing chamber, wherein flowing the second reactant gas is flowing the second reactant gas from the showerhead, the method further comprising flowing an oxygen-containing secondary purge gas from outside the showerhead in the processing chamber to form a curtain around an outer edge of the showerhead, wherein the second reactant gas is oxygen-free.

7. The method of claim 5, wherein the substrate is located below a showerhead in a processing chamber, wherein flowing the second reactant gas is flowing the second reactant gas from the showerhead, the method further comprising flowing an oxygen-containing secondary purge gas from outside the showerhead in the processing chamber to form a curtain around an outer edge of the showerhead, wherein the second reactant gas comprises an inert gas and oxygen.

8. The method according to claim 5, wherein: More silicon-containing precursor is deposited near the center of the substrate compared to the outer edges of the substrate.

9. The method of claim 1, wherein the dopant layer comprises a dopant that is at least one of boron, phosphorus, and arsenic.

10. The method of claim 1, wherein the substrate is composed of at least one of Si, SiC, GaAs, or GaN.

11. The method of claim 1 , wherein the substrate is supported above a substrate support, wherein forming the silicon oxide diffusion barrier layer comprises: non-uniformly heating the substrate support to produce a higher temperature region of the substrate support so as to non-uniformly heat the substrate to produce a higher temperature region of the substrate, wherein the silicon oxide diffusion barrier layer is formed to be thicker above the higher temperature region of the substrate.

12. A method for doping a substrate, comprising: forming a silicon oxide diffusion barrier layer on a surface of the substrate, wherein the silicon oxide diffusion barrier layer is thicker on an outer edge of the substrate than on a center of the substrate; depositing at least one dopant layer on the silicon oxide diffusion barrier layer; depositing a capping layer on the at least one dopant layer to form a stack of the substrate, the silicon oxide diffusion barrier layer, the at least one dopant layer, and the capping layer; annealing the stack; as well as The cap layer, the at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.

13. The method of claim 12, wherein forming the silicon oxide diffusion barrier layer comprises heating the substrate, wherein the outer edge of the substrate is heated to a temperature higher than a temperature of a center of the substrate.

14. The method of claim 12, wherein forming the silicon oxide diffusion barrier layer comprises providing an atomic layer deposition process.

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