Peak detector

Abstract

A circuit includes a peak detector (220), a diode (D0), a dynamic clamp circuit (210), and an offset correction circuit (250). The peak detector (220) generates a voltage on a peak detector output that is proportional to a minimum voltage on a peak detector input. The anode of the diode (D0) is coupled to the peak detector input. The dynamic clamp circuit (210) is coupled to the peak detector input and is configured to clamp the voltage on the peak detector input in response to a voltage on the anode of the diode being greater than the minimum voltage on the peak detector input. The offset correction circuit (250) is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from the amplitude of the peak detector output.

Description

Background Art

[0001] Some systems include a laser diode driven by a laser driver integrated circuit (IC). The laser driver IC includes a current source. The laser diode is coupled between a supply voltage and an output terminal of the laser driver IC. When activated, the current source causes current to flow from the supply voltage, through the laser diode, and through the current source to ground. When turned on, a voltage drop is generated across the laser diode, and the voltage at the output terminal of the laser driver IC is equal to the supply voltage minus the voltage drop across the laser diode.

[0002] Parasitic inductance is typically present between the laser diode and the output terminals of the laser driver IC. Parasitic inductance is a combination of the IC bond wire inductance and trace inductance of the printed circuit board on which the laser driver IC is mounted. Thus, the current path is from the supply voltage, through the laser diode, through the parasitic capacitance, and through the IC's current source to ground.

[0003] The laser diode is pulsed on and off, and during each on pulse, the current from the current source of the IC is ramped up relatively quickly. As the current through the parasitic inductor ramps up during each cycle, the voltage generated across the parasitic inductor is proportional to the product of the conversion rate of the added current and the value of the inductance of the parasitic inductor. In addition to the voltage drop across the laser diode, there is an additional voltage drop between the laser diode and the output terminal of the laser driver IC to which the laser diode is connected due to the parasitic inductance. Thus, during the current ramp-up period, the output voltage of the laser diode IC (i.e., the voltage coupled to the output terminal of the laser diode) drops to a level equal to the supply voltage minus both the laser diode voltage drop and the parasitic inductor voltage. The duration of the period during which the output voltage drops due to the inductor voltage drop (in addition to the laser diode voltage drop) is relatively short, but unfortunately, during this period the current source within the laser driver IC may saturate. The result of such saturation may be detrimental to system performance. Summary of the invention

[0004] In one example, a circuit includes a peak detector, a diode, a dynamic clamp circuit, and an offset correction circuit. The peak detector generates a voltage on a peak detector output that is proportional to a minimum voltage on a peak detector input. An anode of the diode is coupled to the peak detector input. The dynamic clamp circuit is coupled to the peak detector input and is configured to clamp the voltage on the peak detector input in response to a voltage on the anode of the diode being greater than the minimum voltage on the input of the peak detector. The offset correction circuit is coupled to the peak detector output and is configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a detailed description of various embodiments, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A system is described that includes a laser driver integrated circuit (IC) that drives a laser diode, wherein the laser driver IC includes a minimum peak detector.

[0007] Figure 2 exhibit Figure 1 An example implementation of a minimum peak detector.

[0008] Figure 3 An example waveform illustrating the voltage within a minimum peak detector.

[0009] Figure 4 Another example of a waveform of the voltage within the minimum peak detector is illustrated.

[0010] Figure 5 and 6 Shows an example waveform within the minimum peak detector when the laser diode is repeatedly turned on and off.

[0011] Figure 7 and 8 Example waveforms of a minimum peak detector showing a dynamic clamp circuit with the peak detector enabled and disabled.

[0012] Fig. 9 The diagram illustrates the progression of the minimum peak value of the input voltage of the minimum peak detector over time when the laser diode is repeatedly turned on and off.

[0013] Fig.10 Show the relative relationship between the output signal of the minimum peak detector and its input voltage.

[0014] Fig.11 The example minimum peak detectors disclosed herein are shown to be relatively temperature independent. DETAILED DESCRIPTION

[0015] Figure 1 The system 100 is shown in which a laser driver integrated circuit (IC) 120 is connected to an external laser diode 110. The laser driver IC 120 and the laser diode 110 are mounted on a printed circuit board (PCB) 119. Although Figure 1 Examples of include laser diodes, but other examples include light sources other than laser diodes. Figure 1In an example implementation of , the anode of the laser diode 110 is connected to a positive power supply node (VDD). Ignoring the inductor L0 for simplicity, the cathode of the laser diode 110 is coupled to an output node (also referred to as a terminal or pin) 121 of the laser driver IC 120. The voltage on the output node 121 is labeled VOUT. The laser driver IC 120 includes a current source 122 and a minimum peak detector circuit 130, as well as possible other components. An input signal (VIN) is provided to the current source 122 to cause the current source 122 to generate a current. In one example, VIN includes a control signal to turn the current source 122 on and off. When the current source 122 is activated, the IOUT current flows from VDD through the laser diode 110 and the current source 122 to ground.

[0016] Inductor L0 is shown between the laser driver IC 120 output node 121 and the laser diode 110. As explained above, inductor L0 represents a parasitic inductance, which is a combination of bond wire inductance (e.g., bond wire between the output node 121 and the PCB 119 on which the laser diode IC 120 is mounted) and PCB trace inductance. When the current source 122 is activated, the current IOUT of the laser driver IC 120 ramps up from its 0 amps to its steady state level over a period of time (e.g., 230ps). During the IOUT rise time, the voltage developed across the inductor L0 is equal to L0*d(IOUT) / dt, where L0 is the inductance value of the inductor L0, and d(IOUT) / dt is the time derivative of IOUT. As IOUT increases, the voltage (VOUT) on the output node 121 of the laser driver is therefore VDD minus both the voltage drop across the laser diode 110 and the voltage developed across the inductor L0. Figure 1 The waveform 150 in FIG. 1 shows the time course of VOUT. Due to the voltage across the laser diode 110 and the inductor L0, VOUT drops to a minimum level (VOUTmin) at 152. Tpeak is the amount of time that IOUT increases, and therefore the voltage developed across the inductor L0. After IOUT reaches its steady state level and therefore stops changing with time, the voltage drop across the inductor L0 becomes 0V, and VOUT increases to its steady state level (VOUTst) 154, which is VDD minus the voltage drop across the laser diode 110.

[0017] The laser diode 110 is turned on by the laser driver IC 120 for a period of time (Ton) and then turned off for a period of time Toff. During Toff, no IOUT current flows and VOUT is equal to VOUTmax (156). VOUTmax 156 is approximately equal to VDD. The laser driver IC 120 repeatedly pulses the laser diode 110 on and off with a predetermined period. Waveform 160 shows VIN as a periodic waveform, high during Ton and then low during Toff. When VIN is high, the current source 122 is activated to source current through the laser diode 110, and then when VIN is low, the laser diode is turned off.

[0018] VOUTmin (the minimum voltage of VOUT that occurs when IOUT ramps up to turn on the laser diode 110) may be low enough to saturate the current source 122. Saturation of the current source 122 may be detrimental to system performance, such as causing latching problems in the bipolar junction transistors within the current source 122, causing relatively large amounts of current to flow from the power supply to the current source 122, causing the off time of the current source 122 to increase, etc. The minimum peak detector circuit 130 monitors the voltage VOUT on the output node 121 and, in response, generates an output signal VPEAK including a voltage level equal to VOUTmin. That is, although VOUT is only briefly at VOUTmin during each cycle of the laser diode 110, VPEAK (after a short settling time) persists at a relatively constant voltage level (equal to VOUTmin). Therefore, VPEAK indicates the lowest level to which VOUT drops during the portion Tpeak of each cycle. The minimum peak detector circuit 130 allows the system to adjust the magnitude of the laser diode supply voltage (VDD) and / or the IOUT current to prevent saturation of the current source 122.

[0019] Figure 2 An example implementation of a minimum peak detector circuit 130 is shown. In this example, the minimum peak detector circuit 130 includes a dynamic clamp circuit 210, a main peak detector circuit 220, a charging current circuit 230, a base current cancellation circuit 240, an offset correction circuit 250, and a latching diode D0. Other components may also be included. The cathode of diode D0 is coupled to the output node 121 and thus receives VOUT. The main peak detector circuit 220 generates a signal shown as VPEAK_LS, which is a voltage on node 213 that is proportional to VOUTmin, but is offset above VOUTmin due to the voltage drop across diode D0 and another voltage offset described below. The offset correction circuit 250 corrects these offsets and produces a resulting VPEAK signal.

[0020] Figure 2The example circuit implementation of FIG. 1 shows multiple transistors of various types—npn bipolar junction transistors (BJTs), pnp BJTs, n-type metal oxide semiconductor field effect transistors (NMOS), and p-type metal oxide semiconductor field effect transistors (PMOS). Other implementations may include different circuit architectures, and for Figure 2 A different type of transistor for one or more of the transistors shown in .

[0021] Dynamic clamp circuit 210 includes current source devices ISRC4, ISRC5, ISRC6, and ISRC7, resistor R2, capacitor C1, diode D1, pnp transistors QP1, QP2, and QP3, npn transistor QN2, and PMOS transistors MP0, MP1, and MP2. A voltage supply (VSUP) is provided to the emitter of QP1, the collector of QN2, and ISRC5 and ISRC7. The collector of QP1 is connected to its base and R2. The other terminal of R2 is connected to the source of MP1 at node 217, whose voltage is designated as VCLmax. The gates of MP0 and MP1 are connected together and to the drain of MP1. ISRC4 is connected between the drain of MP1 and ground.

[0022] The base of QN2 is connected to the sources of MP0 and MP2 and to ISRC5 at a node whose voltage is designated as VCL1. The emitters of QN2 and QP2 are connected together. The bases of QP2 and QP3 are connected together and to the collector of QP2, ISRC6, and C1. ISRC6, C1, and the collector of QP3 are connected to ground. The anode of D1 is connected to ISRC7, and the cathode of D1 is connected to the emitter of QP3. The anode of D1 is also connected to D0 at node 215 whose voltage is VOUT_LS.

[0023] The main peak detector circuit 220 includes pnp transistors QP4 and QP5, npn transistors QN1, QN0, resistors R0 and R1. The base of QP4 is connected to node 215 and thus to the anodes of diodes D0 and D1. The collector of QP4 is connected to the collector and base of QN1. The emitter of QN1 is connected to ground as is the emitter of QN0. The bases of QN1 and QN0 are connected together. Resistors R0 and R1 are connected together and to C0 and ISRC3 at node 221 whose voltage is designated as VED. R1 is connected to the emitter of QP4. R0 is connected to the emitter of QP5. The collector of QP5 is connected to ground. VSUP is provided to C0, ISRC3 and Cpk as shown.

[0024] The charging current circuit 230 includes current sources ISRC0 and ISRC1. The current from ISRC0 is designated as ICH_OTC. The ISRC1 current source is a proportional to absolute temperature (PTAT) current source device whose current varies proportionally with temperature (current increases with increasing temperature, and current decreases with decreasing temperature). ISRC0 and ISRC1 are connected together as shown. Some of the ICH_OTC current from ISRC0 is provided as ICH_PTAT (proportional to absolute temperature) by ISRC1. The rest of ICH_OTC (ICH_OTC-ICH_PTAT) is shown as ICH. The effect of temperature on the minimum peak detector 130 is described below.

[0025] Current sources ISRC0 and ISRC1 are connected to the collector of QN0 at node 231 whose voltage is designated as VPEAK_LS. Node 231 (VPEAK_LS) is connected to base current cancellation circuit 240. Base current cancellation circuit 240 in this example includes current source ISRC2, NMOS transistors MN0 and MN1, and pnp transistor QP0. MN0 and MN1 are configured as current sources and are connected to the base of QP0. The emitter of QP0 is connected to current source ISRC2.

[0026] Node 231 (VPEAK_LS) is also coupled to offset correction circuit 250. Offset correction circuit 250 includes an operational amplifier (OP0), a diode D2, current sources ISRC8, ISRC9, and ISRC10, a capacitor Clp, and a resistor Roff. The output of OP0 is connected to anode D2. The cathode of D2 provides the output signal VPEAK and is also connected to ISRC10. Roff includes a feedback resistor connected between the output of OP0 and the negative input of OP0. Capacitor Clp is connected in parallel with Roff. VPEAK_LS is provided to the positive input of OP0. ISRC9 is connected to Roff, Clp, and the negative input of OP0.

[0027] The minimum peak detector circuit 130 detects the minimum or negative peak value in VOUT during each cycle. The term "negative peak" refers to the lowest voltage level (VOUTmin) of VOUT during each cycle. However, VOUTmin is not a negative voltage relative to ground. The minimum peak detector circuit 130 handles several design drivers. For example, when the laser diode 110 is turned on, VOUT may experience large amplitude swings (due to the voltage generated across the parasitic capacitance L0) as IOUT ramps up. For example, VOUT may swing from 10V or more down to ground (e.g., 500mV) in 230ps. Further, due to the fast rise time of IOUT and / or the large total inductance L0, there may be a large delta (e.g., more than 7V) between VOUTmin and VOUTst. The minimum peak detector circuit 130 should accurately generate VPEAK for input pulses at VIN (Ton) of a few nanoseconds or less, and generate pulse widths of negative peaks (Tpeak) on the order of hundreds of picoseconds. These latter timing values ​​typically require transistors manufactured according to high speed processes, which is generally synonymous with lower breakdown voltages of active devices. The minimum peak detector circuit 130 should also operate over a Toff range of from 20ns to 200ns. Further, the detection performed by the minimum peak detector circuit 130 should have low temperature variation, assuming no difference in system response when temperature varies. The minimum VOUT peak to be detected can be in the range of 300mV to 2.3V, with a maximum available power supply of 4.8V. Still further, the total current consumption should be less than 500uA. The disclosed minimum peak detector circuit 130 meets one or more of these design criteria.

[0028] The voltage at the anode of diode D0 is VOUT_LS. Given the large voltage swing at VOUT (e.g., 6.5V and possibly larger), diode D0 acts as a blocking diode to allow the VOUT voltage to only be one diode voltage drop below VOUT during each negative transition of VOUT. The dynamic clamp circuit 210 limits the upper limit of VOUT_LS to a predetermined level (e.g., 2.88V), while the minimum voltage on VOUT_LS is approximately 0.85V (one diode voltage drop) higher than VOUTmin. For example, in an example where VOUTmin is 0.56V, VOUT_LS will be 1.41V (0.56V+0.85V). As will be explained below, the voltage VCLmax on node 217 of the dynamic clamp circuit 210 represents the maximum voltage of VOUT_LS. Figure 4(described further below) illustrates a case where the VOUT range drops from 8.8 V to 2.36 V, and therefore VOUT_min is 2.36 V. In this case, the maximum voltage at VOUT_LS is equal to 3.57 V, which is the same as the VCLmax voltage on node 217. Therefore, VCLmax sets (clamps) the maximum voltage of VOUT_LS.

[0029] The following discussion includes Figure 2 The operation of the example dynamic clamp circuit 210 is also shown in FIG. Figure 3 , which shows VOUT and VOUT_LS during a portion of the cycle in which the laser diode 110 is on. When the laser diode 110 is off (as is the case at 302) and before any negative peak appears on VOUT, the following operating conditions exist in the dynamic clamp circuit 210. The voltage VOUT at 302 is equal to VOUTmax, which is Figure 3 When the laser diode 110 is turned off (312), the voltage VOUT_LS is equal to VCLmax and is indicated by the voltage drop across the loop formed by the device transistors MP1, MP0, QN2, QP2, and QP3 and the diode D1. In this example, the loop formed by the transistors MP1, MP0, QN2, QP2, and QP3 and the diode D1 limits the high voltage of VOUT_LS to 2.88V.

[0030] Current source ISRC7 sinks current through D1 and QP3 to ground. For quantities where VSUP is 4.8V, at a temperature of 27 degrees Celsius, VOUT_LS equals 3.57V. If VOUT equals 7V, then diode D0 is reverse biased 7V minus 3.57V, which equals 3.43V. In this implementation, diodes D0 and D1 are implemented as base-collector junctions of NPN transistors (e.g., an NPN transistor with its base connected to its collector) having a reverse bias breakdown voltage greater than, for example, 10V. By solving Kirchhoff's voltage law (KVL), it can be shown that the main peak detector circuit 220 will set the voltage VPEAK_LS on the node 231 as follows: VPEAK_LS = VOUT_LS - VT*ln[(Ibs0-ICH) / ICH], where ICH = ISRC0-ISRC1 (described below), Ibs0 is the current value of ISRC3, Ibs0 is substantially greater than ICH, and VT = KT / q, T is the temperature of the pn junction, K is the Boltzmann constant, and q is the magnitude of the electron charge.

[0031] In one example, at 27 degrees Celsius, Ibs0 is approximately equal to 100*ICH, and VPEAK_LS = VOUT_LS - 0.12 V, which is equal to 3.57 V - 0.12 V = 3.45 V. Transistor MP2 is turned off because the voltage on its source (VCL1) is the same as the voltage of VCLmax, which is equal to 3.57 V in one example, and the gate voltage of MP2 is VPEAK_LS, which is 3.45 V. Thus, the gate-to-source voltage of MP2 is lower than its threshold voltage, and therefore MP2 is turned off.

[0032] The collector current of QP4 is equal to the collector current of QN1. QN1 and QN0 form a current mirror. In one example, the current mirror ratio of the current mirror QN1 / QN0 is 1:1, and the collector current through QN0 is also equal to the collector current of QP4 and QN1. The charging current ICH flows through QN0, and therefore the collector currents of QN0, QN1, and QP4 are equal to ICH. At node 221, the current Ibs0 from ISRC3 is divided between the branch including R1 and QP4 and the branch including R0 and QP5. Therefore, some of the Ibs0 current flows through R1 / QP4, and the rest flows through R0 / QP5. The collector current of QP5 is equal to Ibs0 minus ICH. The magnitude of Ibs0 is much larger than ICH, which means that most of the current of ISRC3 flows through QP5, and only ICH flows through QP4. The base current of QP5 is provided via the base current cancellation circuit 240.

[0033] Figure 3 and 4 Show where VOUTmax is 7V ( Figure 3 ) and 8.8V( Figure 4 ). Figure 3 In the case of VOUTmin, VOUT drops to 565mV, while in Figure 4 In the example, VOUT at VOUTmin drops to 2.36V. When VOUT drops to its minimum value, VOUT_LS also tracks downward, but due to the voltage drop across D0, VOUT_LS remains approximately one diode drop above VOUTmin. Figure 3 The minimum value of VOUT_LS is 1.41V, and Figure 4 , the minimum value of VOUT_LS is 3.16 V. The main peak detector circuit 220 generates VPEAK_LS as an indication of the negative peak of VOUT, and the offset correction circuit 250 (described below) corrects the offset between VPEAK_LS and VOUTmin.

[0034] Figure 5shows what happens during the first pulse on VOUT when diode D0 is first turned on and VOUTmin is less than VCLmax minus the voltage drop across D0. Figure 5 During the first few pulses of VOUT (about 230 ps in the example), there is a large pump current through QP4, which is mirrored by QN1 / QN0 to capacitor Cpk. Cpk acts as a sampling capacitor. The current into sampling capacitor Cpk is I_DISCH and causes VPEAK_LS to drop rapidly during Tpeak. During this short pulse, the current in QP4 has two components: a) a DC current component provided by ISRC3, which is quite small (e.g., about 40 uA) for power reasons; and b) a transient component determined by C0, R1, the emitter area of ​​QP4, and the initial voltage at VED (node ​​221). During the first few pulses of VOUT, the transient component dominates the I_DISCH current and gradually becomes smaller as VPEAK_LS approaches the minimum value (510) of VOUT_LS.

[0035] When VOUTmin is close to ground, resistor R1 limits the current in QP4 during the first pulse. After the minimum peak detector circuit 130 reaches a steady state (VPEAK_LS has reached its lowest value),

[0036] ICH*(Ton+Toff)=I_DISCH*Tpeak. (1)

[0037] That is, I_DISCH integrated over the period (Ton+Toff) of the signal (during Tpeak) will be equal to the constant pull-up current ICH. Under this steady-state condition, VOUT_LS during Tpeak drops by about 250mV (27 degrees Celsius), below the VPEAK_LS value of equation (1) to remain correct.

[0038] Figure 6 A plurality of events 610 are shown where the laser diode 110 is turned on, each time VOUT drops (due to the inductor L0) to about 557 mv (VOUTmin). Each time the laser diode 110 is turned on, VOUT_LS also drops. VOUT_LS drops to a level about one diode voltage drop above VOUTmin. Over the course of events 610 where the laser diode 110 is repeatedly turned on, VPEAK_LS also begins to drop downward, as shown at 630. VPEAK_LS flattens out at about 250 mV above the lowest level 640 of VPEAK_LS. The 250 mV excursion is due to maintaining enough voltage across the capacitor Cpk to be able to charge and discharge the capacitor. Figure 6Also shown is the progression of I_DISCH each time the laser diode 110 is turned on. Initially, I_DISCH is equal to 8.66 mA (as shown at 660), but drops to 10 μamps at 665.

[0039] Figure 7 A comparison of several signals is shown when the dynamic clamp circuit 210 is included and used and when it is not used. The upper waveform 710 shows an example of VOUT when the laser diode 110 is repeatedly turned on and off. In this example, VOUTmin is 256.2mV. Figure 7 The lower waveforms of show the base-to-emitter voltage (Vbe) of QP4 in the case where the dynamic clamp circuit 210 is enabled (waveform 720) and the dynamic clamp circuit is disabled (waveform 730). In both cases, the first peak on VOUT results in a maximum Vbe of approximately -1.23V, which does not damage QP4. When the dynamic clamp circuit 210 is disabled, Vbe reaches a steady-state voltage of -1.45V, which may damage QP4. When the dynamic clamp circuit is enabled, Vbe reaches a steady-state voltage of approximately -577mV, which is not enough to damage QP4. The Vbe of QP4 is the difference between VOUT_LS (the base of QP4) and the voltage on the emitter of QP4.

[0040] Figure 8 Waveform 805 is shown for VOUT_LS with dynamic clamp 210 enabled as the laser diode is repeatedly turned on and off. Waveform 810 shows VOUT_LS with dynamic clamp 210 disabled. When dynamic clamp 210 is enabled, the maximum VOUT_LS voltage goes down, as shown in this example, to approximately 2.65V, thereby reducing the Vbe of QP4. With dynamic clamp 210 disabled, VOUT_LS remains at node 217 ( Figure 2 ), which is 3.56 V in this example. When the dynamic clamp circuit 210 is enabled, the maximum voltage at VOUT_LS is adjusted downward by 0.91 V (3.56 V to 2.65 V), thereby preventing degradation of QP4.

[0041] Figure 8The bottom portion of 8000 shows VPEAK_LS for two scenarios (dynamic clamp 210 enabled and disabled). Waveform 820 shows an example of VPEAK_LS with the dynamic clamp disabled, and waveform 830 indicates an example of VPEAK_LS with the dynamic clamp enabled. VPEAK_LS is slightly lower (about 30 mV in this example) because the drop in VOUT_LS is less when the dynamic clamp is enabled (2.65 V to 1.12 V) than when the dynamic clamp is enabled (3.56 V to 1.12 V). The smaller the voltage swing, the wider the pulse, and therefore less overdrive is required at the input of QP4 / QP5 to generate the same integrated I_DISCH current.

[0042] Return to reference Figure 2 , the offset correction circuit 250 compensates for both offsets. The voltage drop across D0 is compensated by D2, which has the same current density as D0 when D0 is on. The approximately 250mV offset of VPEAK_LS greater than VOUT_LS is compensated in the feedback of the operational amplifier OP0 using Roff, ISRC8, and ISRC9. In addition, capacitor Clp is connected in parallel with Roff to create a low pass filter to filter out small glitches on VPEAK_LS created during the pulse.

[0043] Fig. 9 Example waveforms of VOUT, VOUT_LS, VPEAK_LS, and VPEAK are shown as the loop acquires VOUTmin, which in this example is 796mV. As shown, after the loop stabilizes, VPEAK stabilizes at a level equal to VOUTmin. In this example, the loop takes approximately 25 cycles (approximately 1μs) to stabilize to produce an accurate level for VPEAK.

[0044] Fig.10 Shows an example relationship between VPEAK and VOUTmin, with VOUTmin ranging from 50mV to 2.75V. Shows the set value of VPEAK (set after 1.4μs). Fig.10 The graph of 230 shows satisfactory linearity of VOUTmin in the range of about 0.3 V to 2.3 V. Due to the headroom loss at the VOUT_LS node 231, there is some compression of VPEAK for VOUTmin greater than 2.3 V. If a larger supply voltage VSUP is used, the compression problem can be improved.

[0045] refer to Figure 2, current ICH has a complementary to absolute temperature (CTAT) characteristic that helps the main peak detector circuit 220 maintain approximately the same minimum VOUT peak detection as the temperature varies over a range of, for example, -20 degrees Celsius to 105 degrees Celsius. Current ICH is the current from ISRC0 minus the current from current source ISRC1. The current from ISRC0 is ICH_0TC and is a fine-tuning current that is independent of temperature. The current from ISRC2 is proportional to the absolute temperature (PTAT) current. The subtraction of the two results in the CTAT characteristic of ICH. The reason for the relatively constant level of VPEAK over temperature is that as temperature increases, QP4 slows down (e.g., lower bandwidth) and conducts less pump current during Tpeak for the same VOUT_LS-VPEAK_LS voltage. If ICH had a PTAT characteristic, as temperature increases, the peak detector loop would cause VPEAK_LS to increase, causing it to have more overdrive during Tpeak to compensate for ICH. By reducing ICH with increasing temperature (CTAT), the peak detector loop can maintain approximately the same VPEAK voltage.

[0046] Fig.11 VPEAK at different VOUTmin values ​​and different temperatures are illustrated. For example, plot 1102 shows VPEAK for VOUTmin of 0.25V over a temperature range of -20 degrees Celsius to 110 degrees Celsius. Example plot 1112 shows VPEAK for VOUTmin of 1.15V across the same temperature range. For a range of VOUTmin of 250mV to 2.3V, the worst percentage change is at VOUTmin = 250mV, where VPEAK changes by 19mV, less than 8%, for a detected VOUTmin peak of 250mV.

[0047] The transistor comprises a control input and a current terminal. In the case of a bipolar junction transistor, the control input is the base, and the current terminals are the emitter and the collector. In the case of a metal oxide semiconductor field effect transistor, the control input is the gate, and the current terminals are the source and the drain.

[0048] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that enable a functional relationship consistent with the description of the present disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A, then device A is coupled to device B through the intermediate component C.

[0049] Modifications are possible in the embodiments described, and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: a peak detector circuit comprising a peak detector input and a peak detector output, the peak detector configured to generate a voltage on the peak detector output that is proportional to the lowest voltage on the peak detector input; a diode comprising a cathode and an anode, the anode coupled to the peak detector input; a dynamic clamp circuit coupled to the peak detector input, the dynamic clamp circuit configured to clamp the voltage on the peak detector input in response to the voltage on the anode of the diode being greater than the minimum voltage on the input of the peak detector; and An offset correction circuit is coupled to the peak detector output, the offset correction circuit being configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

2. The circuit of claim 1 , wherein the peak detector circuit comprises: Capacitors; a first transistor having a first control input coupled to the capacitor; a second transistor having a second control input coupled to an anode of the diode; and A third transistor is coupled to the first control input and the capacitor.

3. The circuit of claim 2, wherein the peak detector circuit further comprises a current source, a first resistor coupled between the current source and the first transistor, and a second resistor coupled between the current source and the second transistor.

4. The circuit of claim 1, wherein the diode comprises a bipolar junction transistor.

5. The circuit of claim 1 , wherein the dynamic clamp circuit comprises: a PNP transistor having a base, a source, and an emitter, with the base coupled to the source; a resistor coupled to the source of the PNP transistor; and A first current source is coupled between the resistor and a ground node.

6. The circuit of claim 5, wherein the diode is a first diode, and wherein the dynamic clamp circuit further comprises: a second current source coupled to the anode of the diode; a second transistor; and A second diode is coupled between the second current source and the second transistor.

7. The circuit according to claim 5, further comprising: a second current source; and A second transistor is coupled between the second transistor and the ground node, the second transistor having a control input coupled to an output of the peak detector.

8. The circuit of claim 1 , wherein the diode is a first diode, and the offset correction circuit comprises: A second diode comprising a cathode and an anode; and an operational amplifier including an input coupled to the peak detector output, the operational amplifier including an output coupled to the anode of the second diode, and the output of the offset correction circuit is taken from the cathode of the second diode.

9. The circuit of claim 1, further comprising a current cancellation circuit comprising: a first transistor coupled to an output of the peak detector; a current source; and A second transistor is coupled between the current source and a ground node, the second transistor being coupled to the first transistor.

10. The circuit of claim 1 , further comprising a charging current circuit comprising a first current source and a second current source, the first current source being coupled to the peak detector output, the second current source being coupled to the first current source, and the first current source comprising a proportional to absolute temperature (PTAT) current source.

11. A circuit comprising: A diode having an anode and a cathode; a first transistor having a first control input coupled to the anode of the diode; a first current source; a first resistor coupled between the first current source and the first transistor; a second transistor having a second control input; a second resistor coupled between the first current source and the second transistor; a capacitor coupled between a power supply node and the second control input; a second current source coupled between the power supply node and the second control input; and A third transistor is coupled between the second control input and a ground node.

12. The circuit of claim 11, further comprising a dynamic clamp circuit configured to clamp a voltage on the anode of the diode.

13. The circuit of claim 12, wherein the dynamic clamp circuit comprises: a fourth transistor having a control input, a first current terminal, and a second current terminal, and the control input of the fourth transistor is coupled to the second current terminal of the fourth transistor; a third resistor coupled to the second current terminal of the fourth transistor; and A third current source is coupled between the third resistor and the ground node.

14. The circuit of claim 13, wherein the diode is a first diode, and wherein the dynamic clamp circuit further comprises: a fourth current source coupled to the anode of the first diode; a fifth transistor; and A second diode is coupled between the fourth current source and the fifth transistor.

15. The circuit of claim 11, further comprising a third current source coupled to the first current source, the third current source comprising a proportional to absolute temperature (PTAT) current source.

16. The circuit of claim 11, further comprising an offset correction circuit coupled to the second control input, the offset correction circuit configured to generate an output signal whose amplitude is offset from a voltage on the second control input.

17. A system comprising: Laser diodes; and A laser driver coupled to the laser diode, the laser driver comprising: a peak detector circuit comprising a peak detector input and a peak detector output, the peak detector configured to generate a voltage on the peak detector output that is proportional to the lowest voltage on the peak detector input; a diode comprising a cathode and an anode, the anode coupled to the peak detector input; a dynamic clamp circuit coupled to the peak detector input, the dynamic clamp circuit configured to clamp the voltage on the peak detector input in response to the voltage on the anode of the diode being greater than the minimum voltage on the input of the peak detector; and An offset correction circuit is coupled to the peak detector output, the offset correction circuit being configured to generate an output signal whose amplitude is offset from an amplitude of the peak detector output.

18. The system of claim 17, wherein the peak detector circuit comprises: Capacitors; a first transistor having a first control input coupled to the capacitor; a second transistor having a second control input coupled to an anode of the diode; a third transistor coupled to the first control input and the capacitor; Current source; a first resistor coupled between the current source and the first transistor; and A second resistor is coupled between the current source and the second transistor.

19. The system of claim 17, wherein the dynamic clamp circuit comprises: a first transistor having a base, a source and an emitter, with the base coupled to the source; a resistor coupled to the source of the first transistor; a first current source coupled between the resistor and a ground node; a second current source coupled to the anode of the diode; a second transistor; and A second diode is coupled between the second current source and the second transistor.

20. The system of claim 17, further comprising a charging current circuit comprising a first current source and a second current source, the first current source being coupled to the peak detector output, the second current source being coupled to the first current source, and the first current source comprising a proportional to absolute temperature (PTAT) current source.

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