Automatic correction system and method for integrated circuit timing design

Abstract

The present invention relates to the field of semiconductor chip technology, and in particular to an automatic correction system and method for integrated circuit timing design. The present invention classifies the default port full name and margin in the data module into the port maximum load default module and the port signal conversion time default module, sends the port signal conversion time default port default information to the data path port signal conversion time default module or the clock path port signal conversion time default module, and the traversal correction module traverses the port default module respectively and converts the default information. The default information is corrected by adding a driver module and inserting a buffer module, and then output to the correction result module. The present invention can quickly repair the maximum load and port signal conversion time defaults, and provide detailed data, physical location and other information for accurate repair, accelerate the convergence of logic constraints, reduce manual operations, and improve the accuracy and efficiency of digital physical design.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to an automatic correction system and method for integrated circuit timing design. Background Art

[0002] Digital physical design accounts for a large proportion of the entire chip design, and the digital physical design process is complex and has long links.

[0003] As the scale of chips increases, the requirements for digital physical design are also increasing. Usually, in digital physical design, ECO (Engineer Changing Order) needs to be performed to iterate and fix problems in the design. Among them, the maximum load of the port and the port signal conversion time are important goals of logic convergence. Violations of the maximum load of the port and the port signal conversion time will cause inaccurate timing at this level, affecting the accuracy of the setup time and hold time, and thus making the circuit unable to work properly.

[0004] The usual method to solve this type of default is to manually repair it according to the report. When faced with a large number of defaults, manual repair is inefficient and designers are prone to misoperation, which increases the difficulty of repair.

[0005] Current EDA software such as ICC2 (IC Compiler 2) and FC (Fusion Compiler) cannot completely solve the port maximum load and port signal conversion time violation problems during the digital physical design phase, and lacks support for ECO. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention discloses an automatic correction system and method for integrated circuit timing design, which is used to accurately and quickly repair port maximum load and port signal conversion time violations, thereby reducing manual operations of designers, accelerating logic convergence, and improving the efficiency and accuracy of physical design.

[0007] The present invention is achieved through the following technical solutions:

[0008] In a first aspect, the present invention provides an automatic correction system for integrated circuit timing design, comprising:

[0009] A data input module is used to provide the full name of the port maximum load or port signal conversion time default port and the margin parameter of the default port, and to perform default classification repair by selecting a default module type;

[0010] A traversal correction module is used to accurately obtain the actual information of the port-related drive, interconnection line, load and physical position input by the data input module, and display the actual information in real time;

[0011] A correction module, used for selecting, according to the actual information obtained by the traversal correction module, to perform enlargement drive repair by regular matching or to insert a buffer repair at a specified position by calling an EDA tool repair command;

[0012] The correction result module is used to output the default data corrected by the correction module in detail.

[0013] Furthermore, when the data input module performs default classification and repair by selecting the default module type, when the port signal conversion time default module is selected, the port signal conversion time default ports in the data input module are divided into two types of ports: ports on the datapath and ports on the clock path, and are imported into the data path port signal conversion time default module and the clock path port signal conversion time default module respectively, and then enter the traversal correction module.

[0014] Furthermore, when the data input module performs default classification repair by selecting the default module type, when the port maximum load default module is selected, the port maximum load default port and margin in the data input module are processed and imported into this module and then enter the traversal correction module.

[0015] Furthermore, the correction module selects the best solution according to the accurate real-time data information displayed by the traversal correction module, and when the increase drive module is selected for repair, the drive is increased through regular matching.

[0016] Furthermore, the correction module selects the best solution according to the accurate real-time data information displayed by the traversal correction module, and when the insert buffer module is selected for repair, the EDA tool repair command is called to insert the buffer at the specified position for repair.

[0017] In a second aspect, the present invention provides an automatic correction method for integrated circuit timing design, the method using the automatic correction system for integrated circuit timing design described in the first aspect, comprising the following steps:

[0018] S1 classifies the default port full name and margin in the data module into the port maximum load default module and the port signal conversion time default module;

[0019] S2 sends the port signal conversion time violation information to a datapath port signal conversion time violation module or a clock path port signal conversion time violation module according to the data or clock violation type;

[0020] S3 traverses the violation information in the port maximum load violation module, the data path port signal conversion time violation module, and the clockpath port signal conversion time violation module;

[0021] S4 outputs the default information to the correction result module after adding a driver module and inserting a buffer module.

[0022] Furthermore, the method traverses the default ports to accurately obtain the actual information of the port-related drivers, interconnection lines, loads, physical locations, etc. and displays it in real time.

[0023] Furthermore, the method uses an additional driver module to perform regular matching on the output information of the traversal correction module to increase the driver repair or uses an insert buffer module to call an EDA tool repair command to insert a buffer at a specified position for repair.

[0024] Furthermore, the method traverses the default ports in the port maximum load default module, the data path port signal conversion time default module or the clock path port signal conversion time default module respectively, captures the information related to the pin drive, interconnection line, load, etc. and outputs it.

[0025] Furthermore, the method uses TCL to process the logic part and uses TK to graphically interact with the interface.

[0026] The beneficial effects of the present invention are:

[0027] The present invention is based on the initial setting of EDA software and is combined with EDA software to accurately and quickly repair port maximum load and port signal conversion time violations. Only two parameters, the default port and the margin, need to be provided, and repairs can be performed in batches, which greatly improves the repair efficiency, reduces manual operations, and improves the repair reliability. At the same time, it saves chip design time and makes the chip more competitive. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a schematic diagram of the automatic correction system used in the timing design of integrated circuits according to the present invention;

[0030] Figure 2 It is a graphical interface diagram of a module of an embodiment of the present invention;

[0031] Figure 3 is the full name of the default port and the margin diagram before repair in the embodiment of the present invention;

[0032] Figure 4 It is a highlighted diagram of the EDA software of an embodiment of the present invention;

[0033] Figure 5 This is a diagram showing information displayed in a dialog box of an EDA software according to an embodiment of the present invention;

[0034] Figure 6 It is the full name and margin of the default port after repair in the embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Example 1

[0037] Reference Figure 1 As shown, this embodiment provides an automatic correction system for integrated circuit timing design, including:

[0038] A data input module is used to provide the full name of the port maximum load or port signal conversion time default port and the margin parameter of the default port, and to perform default classification repair by selecting a default module type;

[0039] A traversal correction module is used to accurately obtain the actual information of the port-related drive, interconnection line, load and physical position input by the data input module, and display the actual information in real time;

[0040] A correction module, used for selecting, according to the actual information obtained by the traversal correction module, to perform enlargement drive repair by regular matching or to insert a buffer repair at a specified position by calling an EDA tool repair command;

[0041] The correction result module is used to output the default data corrected by the correction module in detail.

[0042] In this embodiment, first, the data input module provides two parameters: the full name of the default port for port maximum load or port signal conversion time, and the margin of the default port. Then, the default module is selected through the graphical button.

[0043] In this embodiment, when the port signal conversion time module is selected, the ports are divided into two types: ports on the data path and ports on the clock path, and then enter the traversal correction module; when the port maximum load default module is selected, the port maximum load default port and margin in the data input module are processed and imported into this module.

[0044] Next, the embodiment executes the traversal correction module to accurately obtain the actual information of the pin-related drive, interconnection line, and load. According to the accurate real-time data information displayed by the traversal correction module, the optimal solution is selected.

[0045] When the add driver module is selected for repair, the driver is increased by regular matching. When the insert buffer module is selected for repair, the EDA tool repair command is called to insert the buffer at the specified position for repair.

[0046] The logic processing part of this embodiment is written in TCL language to realize its functions, and the graphical interactive interface is written in TK.

[0047] This embodiment solves the problem of port maximum load or port signal conversion time default. Only two parameters, the default port and the margin, need to be provided, and repairs can be performed in batches, which greatly improves the repair efficiency, reduces manual operations, and improves the repair reliability.

[0048] Example 2

[0049] At the implementation level, this embodiment provides a specific implementation of a Linux system. First, start the FC tool in the Linux system working directory and read the repair program source file in the FC dialog box. At this time, the repair module graphical interactive interface is displayed, such as Figure 2 shown.

[0050] Put the full name of the port signal conversion time violation in the example and the corresponding margin into the show_drv / trans.tcl file in the current working directory.

[0051] like Figure 3 First, click the split trans button in the graphical interface to enter the port signal conversion time violation module to classify the ports with port signal conversion time violation, then click the ck_trans button to enter the clock path port signal conversion time violation module or click the data_trans button to enter the data path port signal conversion time violation module, and then enter the traversal correction module to repair it.

[0052] This embodiment takes the pin scrypt_top / salsa_mem_wrapper_1 / COM_OPT_COM_OPT_ctmTdsLR_1_473769 / A1 as an example to illustrate the repair method.

[0053] In this embodiment, after clicking the split trans button on the graphical interface to enter the port signal conversion time violation module, the pin is divided into a data path type port. Then we click the data_trans button to enter the data path port signal conversion time violation module, and then we click the Next button to enter the traversal correction module.

[0054] In this embodiment, when traversing to this pin, FC displays the physical information of the driver (red highlight), interconnection line (yellow highlight), and load (green highlight) associated with the default port, and the software dialog box displays the driver size, load number, interconnection line, and margin, such as Figure 4 , Figure 5 shown.

[0055] In this embodiment, according to the information displayed in the FC dialog box and the FC highlight display, it is found that the cause of the default is that the interconnection line is too long, and the buffer insertion module is selected to repair it, and the buffer insertion point is selected as follows: Figure 5 As shown, select any standard cell near the interconnect line, and then click the add_buf_user button to repair it.

[0056] In this embodiment, the report of the port whose port signal conversion time is in violation after repair is as follows: Figure 6 As shown, the default pin scrypt_top / salsa_mem_wrapper_1 / COM_OPT_COM_OPT_ctmTdsLR_1_473769 / A1 has been successfully fixed.

[0057] Example 3

[0058] This embodiment provides an automatic correction method for integrated circuit timing design, comprising the following steps:

[0059] S1 classifies the default port full name and margin in the data module into the port maximum load default module and the port signal conversion time default module;

[0060] S2 sends the port signal conversion time violation information to a datapath port signal conversion time violation module or a clock path port signal conversion time violation module according to the data or clock violation type;

[0061] S3 traverses the violation information in the port maximum load violation module, the data path port signal conversion time violation module, and the clockpath port signal conversion time violation module;

[0062] S4 outputs the default information to the correction result module after adding a driver module and inserting a buffer module.

[0063] This embodiment traverses the default port to accurately obtain the actual information of the port related driver, interconnection line, load, physical location, etc. and display it in real time. This embodiment uses TCL to process the logic part and uses TK graphical interactive interface.

[0064] In this embodiment, the output information of the traversal correction module is repaired by increasing the drive module for regular matching or by inserting a buffer module to call the EDA tool repair command to insert a buffer at a specified position for repair.

[0065] This embodiment traverses the default ports in the port maximum load default module, the data path port signal conversion time default module or the clock path port signal conversion time default module respectively, captures the information related to the pin drive, interconnection line, load, etc. and outputs it.

[0066] In summary, the present invention is based on the initial setting of the EDA software and is combined with the EDA software to accurately and quickly repair the port maximum load and port signal conversion time violations. Only two parameters, the default port and the margin, need to be provided, and repairs can be performed in batches, which greatly improves the repair efficiency, reduces manual operations, and improves the repair reliability. At the same time, it saves chip design time and makes the chip more competitive.

[0067] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An automatic correction system for integrated circuit timing design, characterized in that: include: A data input module is used to provide the full name of the port maximum load or port signal conversion time default port and the margin parameter of the default port, and to perform default classification repair by selecting a default module type; A traversal correction module is used to accurately obtain the actual information of the port-related drive, interconnection line, load and physical position input by the data input module, and display the actual information in real time; A correction module, used for selecting, according to the actual information obtained by the traversal correction module, to perform enlargement drive repair by regular matching or to insert a buffer repair at a specified position by calling an EDA tool repair command; A correction result module, used for outputting the default data corrected by the correction module in detail; When the data input module selects the default module type to perform default classification repair, when the port signal conversion time default module is selected, the port signal conversion time default ports in the data input module are divided into two types of ports, namely, ports on the data path and ports on the clock path, and are respectively imported into the data path port signal conversion time default module and the clock path port signal conversion time default module, and then enter the traversal correction module; When the data input module performs default classification repair by selecting the default module type, when the port maximum load default module is selected, the port maximum load default port and margin in the data input module are processed and imported into the port maximum load default module and then enter the traversal correction module.

2. The automatic correction system for integrated circuit timing design according to claim 1, characterized in that: The correction module selects the best solution according to the accurate real-time data information displayed by the traversal correction module. When the drive increase module is selected for repair, the drive is increased through regular matching.

3. The automatic correction system for integrated circuit timing design according to claim 2, characterized in that: The correction module selects the best solution according to the accurate real-time data information displayed by the traversal correction module. When the insert buffer module is selected for repair, the EDA tool repair command is called to insert the buffer at the specified position for repair.

4. An automatic correction method for integrated circuit timing design, the method using the automatic correction system for integrated circuit timing design as claimed in any one of claims 1 to 3, characterized in that: The method comprises the following steps: S1 classifies the default port full name and margin in the data input module into the port maximum load default module and the port signal conversion time default module; S2 sends the port signal conversion time violation information to the data path port signal conversion time violation module or the clock path port signal conversion time violation module according to the data or clock violation type; S3 traverses the violation information in the port maximum load violation module, the data path port signal conversion time violation module, and the clock path port signal conversion time violation module; S4 outputs the default information to the correction result module after adding a driver module and inserting a buffer module.

5. The automatic correction method for integrated circuit timing design according to claim 4, characterized in that: The method traverses the default ports to accurately obtain the actual information of port-related drivers, interconnection lines, loads, and physical locations and displays them in real time.

6. The automatic correction method for integrated circuit timing design according to claim 4, characterized in that: The method uses an adding driving module to perform regular matching on the output information of the traversal correction module to increase the driving repair or uses an inserting buffer module to call an EDA tool repair command to insert a buffer at a specified position for repair.

7. The automatic correction method for integrated circuit timing design according to claim 4, characterized in that: The method traverses the default ports in the port maximum load default module, the data path port signal conversion time default module or the clockpath port signal conversion time default module respectively, captures the pin-related drive, interconnection line, and load information and outputs them.

8. The automatic correction method for integrated circuit timing design according to claim 4, characterized in that: The method adopts TCL to process the logic part and uses TK to graphically interact with the interface.

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