Error correction code circuit having a one-to-one relationship with input / output pads, and related devices and methods

Abstract

The present invention discloses an error correction code circuit having a one-to-one relationship with an input / output pad, and related devices and methods. A device includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared master input / output (MIO) lines. The single set of shared MIO lines is shared by the plurality of memory banks. The device further includes a single ECC control circuit configured to generate corrected read data in response to the read data received by the ECC control circuit input. The device additionally includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

Description

[0001] Priority Claim

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 912,214, filed on June 25, 2020, entitled "ERROR CORRECTION CODE CIRCUITS HAVING ONE-TO-ONE RELATIONSHIPS WITH INPUT / OUTPUT PADS AND RELATED APPARATUSES AND METHODS". Technical Field

[0003] This application generally relates to error correction code (ECC) control circuits, and more particularly, to ECC control circuits in memory devices. Background Art

[0004] In the design of memory devices, there has been a constant pressure to reduce the power consumed when operating the memory device and to reduce the amount of semiconductor chip area (commonly referred to as "real estate") occupied by the circuitry of the memory device. Although the error correction code (ECC) capability in memory devices improves the operational reliability of the memory device, the circuitry used to provide the ECC capability occupies a non-negligible chip area and consumes a non-negligible amount of power during operation. Summary of the Invention

[0005] In some embodiments, an apparatus includes an error correction code (ECC) control circuit input, a single ECC control circuit, and an ECC control circuit output. The ECC control circuit input is configured to receive read data from a plurality of memory banks of a memory cell array via a single shared set of master input / output (MIO) lines. The single shared set of MIO lines is shared by the plurality of memory banks. The single ECC control circuit is configured to generate corrected read data in response to the read data received by the ECC control circuit input. The ECC control circuit output is configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

[0006] In some embodiments, a device includes a plurality of memory banks, a single set of input / output (I / O) pads, data I / O circuitry, a global data bus, and a single error correction code (ECC) control circuit. The plurality of memory banks are configured to store data thereon. The single set of I / O pads is shared by the plurality of memory banks. The data I / O circuitry is electrically connected to the single set of I / O pads. The global data bus is operatively coupled to the data I / O circuitry. The single ECC control circuit is electrically connected between the plurality of memory banks and the data I / O circuitry. The ECC control circuit has a one-to-one relationship with the single set of I / O pads. The single ECC control circuit is configured to receive read data read from the plurality of memory banks. The single ECC control circuit is further configured to provide corrected read data to the global data bus in response to the read data.

[0007] In some embodiments, a method of operating an error correction code (ECC) control circuit having a one-to-one relationship with an input / output pad shared by a plurality of memory banks of a memory cell array includes generating a parity signal in response to read data received from the memory cell array. The read data corresponds to a read command. The method further includes decoding the parity signal to generate a decoded signal, and generating corrected read data in response to the decoded signal and the read data. The method additionally includes driving the corrected read data onto the global data bus a predetermined amount of time after the read command and before a read latency time period expires. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Although the present disclosure is summarized with claims that specifically recite and clearly claim particular embodiments, various features and advantages of embodiments within the scope of the present disclosure may be more readily determined from the following description when read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a semiconductor device in accordance with some embodiments;

[0010] Figure 2 is a block diagram of a memory device in accordance with some embodiments;

[0011] Figure 3 is in accordance with some embodiments Figure 1 and Figure 2 a block diagram of an ECC control circuit;

[0012] Figure 4 is a signal timing diagram of example signals observable in an ECC control circuit that can be in Figure 3 an ECC control circuit;

[0013] Figure 5 is in an ECC control circuit that can be in Figure 3 an ECC control circuit andFigure 4 The signal timing diagram of an example signal having a longer period compared to the clock signal;

[0014] Figure 6 is a flowchart illustrating a method of operating an ECC control circuit according to some embodiments;

[0015] Figure 7 is a block diagram of a computing system according to some embodiments; and

[0016] Figure 8 is a block diagram of a circuit system that can be used to implement various functions, operations, actions, processes, and / or methods disclosed herein in some embodiments. Detailed Description

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific examples in which the embodiments of the disclosure may be practiced. The embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the disclosure. However, other embodiments may be utilized and structural, material, and process changes may be made without departing from the scope of the disclosure.

[0018] The illustrations presented herein are not meant to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations for describing embodiments of the disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar reference numerals to facilitate the reader; however, the similarity of the reference numerals does not necessarily mean that the size, composition, configuration, or any other property of the structure or component is the same.

[0019] The following description may include examples to help enable those of skill in the art to practice the disclosed embodiments. The use of the terms "exemplary," "for example," and "such as" means that the related description is explanatory, and although the scope of the disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the disclosure to the specified components, steps, features, functions, etc.

[0020] It will be readily understood that the components of the embodiments, as generally described herein and illustrated in the figures, can be arranged and designed in a wide variety of different configurations. Accordingly, the following description of the various embodiments is not intended to limit the scope of the disclosure, but is merely representative of the various embodiments. Although aspects of the embodiments may be presented in the drawings, unless otherwise specifically stated, the drawings are not necessarily drawn to scale.

[0021] In addition, unless otherwise specified herein, the specific embodiments shown and described are merely examples and should not be construed as the only ways to implement the present disclosure. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring the present disclosure with unnecessary details. Instead, unless otherwise specified herein, the specific embodiments shown and described are merely exemplary and should not be construed as the only ways to implement the present disclosure. Additionally, the block definitions and the partitioning of logic between various blocks are exemplary of the specific embodiments. Those skilled in the art will readily appreciate that the present disclosure may be practiced with many other partitioning solutions. To a large extent, details regarding timing considerations and the like have been omitted, where such details are unnecessary for obtaining a full understanding of the present disclosure and are within the capabilities of those skilled in the relevant art.

[0022] Those of ordinary skill in the art will understand that any of a variety of different techniques and methodologies may be used to represent information and signals. Some of the figures may illustrate a signal as a single signal for purposes of presentation and description clarity. Those of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented on any number of data signals including a single data signal.

[0023] Embodiments may be described in terms of processes depicted as flowcharts, flow diagrams, structural diagrams, or block diagrams. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in another order, in parallel, or substantially simultaneously. In addition, the order of the acts may be rearranged. A process may correspond to a method, a thread, a function, a program, a subroutine, a subprogram, other structures, or a combination thereof. In addition, the methods disclosed herein may be implemented in hardware, software, or a combination of both. If implemented in software, functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, where communication media includes any medium that facilitates transfer of a computer program from one place to another.

[0024] Any reference to an element herein using terms such as “first,” “second,” etc. does not limit the number or order of those elements, unless such limitations are expressly stated. In fact, these names may be used herein as a convenient way to distinguish between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be employed herein or that the first element must precede the second element in a particular manner. Additionally, unless otherwise stated, a group of elements may include one or more elements.

[0025] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes that a person of ordinary skill in the art would understand that the given parameter, property, or condition is met within a small degree of variation, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition may be met at least 90.0%, at least 95.0%, or even at least 99.0%.

[0026] In a memory device (e.g., a low-power double data rate (LPDDR) memory device), all memory banks on a memory chip may share a set of input / output (DQ) pads. One way to handle ECC capabilities in such memory chips is to provide each memory bank on the memory chip with its own error correction code digital sense amplifier (ECCDSA) block. In this way, read data can be driven from the ECCDSA block of the memory bank to the global data bus of the memory chip before entering the DQ first-in-first-out (FIFO) buffer of the DQ pads. The timing of providing the corrected read data from the ECCDSA block to the global data bus can be determined based on the error correction code (ECC) parity generation delay in these memory chips. After ECC parity generation and data correction, the read data can be driven onto the data bus. In these memory devices, the timing of driving the corrected read data onto the global data bus can be determined using logic for an ECC read replica. The ECC read replica emulates the ECC syndrome tree path (e.g., using "exclusive OR" (XOR) gates) and a delay trimming option for adjusting the timing. Due to the multiple logic gates in the replica path, the current consumption during operation and the chip space occupied by the logic gates are not negligible. In addition, the DQ FIFO can also occupy a non-negligible chip area, consume current, and complicate the design and operation of the memory device.

[0027] Embodiments disclosed herein eliminate the reliance on the DQ FIFO and ECC read replica logic by employing a one-to-one relationship between a single ECC control circuit shared by each memory bank of a memory cell array and a single set of input / output (DQ) pads shared by each memory bank of the memory cell array. Thus, the circuit system according to embodiments disclosed herein occupies less chip area and consumes less power compared to a circuit system that includes a DQ FIFO and ECC read replica logic.

[0028] In some embodiments, a device includes an ECC control circuit input, a single ECC control circuit, and an ECC control circuit output. The ECC control circuit input is configured to receive read data from a plurality of memory banks of a memory cell array via a single shared set of master input / output (MIO) lines. The single shared set of MIO lines is shared by the plurality of memory banks. The single ECC control circuit is configured to generate corrected read data in response to the read data received at the ECC control circuit input. The ECC control circuit output is configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

[0029] In some embodiments, a device includes a plurality of memory banks, a single set of I / O pads, data I / O circuitry, a global data bus, and a single ECC control circuit. The plurality of memory banks are configured to store data thereon. The single set of I / O pads is shared by the plurality of memory banks. The data I / O circuitry is electrically connected to the single set of I / O pads. The global data bus is operatively coupled to the data I / O circuitry. A single error correction code (ECC) control circuit is electrically connected between the plurality of memory banks and the data I / O circuitry. The ECC control circuit has a one-to-one relationship with the single set of I / O pads. The single ECC control circuit is configured to receive read data read from the plurality of memory banks and provide corrected read data to the single set of input / output pads in response to the read data.

[0030] In some embodiments, the ECC control circuit has a one-to-one relationship with an input / output pad shared by a plurality of memory banks of a memory cell array. In some embodiments, a method of operating an ECC control circuit includes generating a parity signal in response to read data received from a memory cell array. The read data corresponds to a read command. The method further includes decoding the parity signal to generate a decoded signal, and generating corrected read data in response to the decoded signal and the read data. The method additionally includes driving the corrected read data onto the global data bus a predetermined amount of time after the read command and before the expiration of a read latency time period.

[0031] In some embodiments, a device includes a digital sense amplifier (DSA) configured to receive read data from any one of a plurality of memory banks. The digital sense amplifier is configured such that the DSA can operate in response to the assertion of a DSA enable signal. The assertion of the DSA signal occurs a first predetermined number of clock cycles of a clock after a read command to retrieve read data from the plurality of memory banks. The device further includes a first latch configured to receive the read data and latch the read data in response to the DSA enable signal to provide latched read data. The device additionally includes a syndrome tree circuit configured to receive the latched read data and generate one or more parity bits in response to the latched read data. The device further includes a second latch configured to latch the one or more parity bits from the syndrome tree in response to the assertion of a latch signal. The assertion of the latch signal occurs a second predetermined number of clock cycles before a read latency time. The read latency time is a read latency time period after the read command. The second predetermined number of clock cycles is sufficient to provide the syndrome tree circuit with sufficient time to generate one or more parity bits. The device additionally includes a decoder configured to generate a decoder signal in response to the one or more latched parity bits; and a correction circuit configured to generate corrected read data in response to the latched read data and the decoder signal. The device additionally includes a global data bus (GBUS) driver configured to drive the corrected read data onto the GBUS in response to the assertion of a GBUS driver trigger signal, the GBUS driver trigger signal being configured to assert a third predetermined number of clock cycles before the read latency time. In some embodiments, the third predetermined number of clock cycles is two clock cycles. In some embodiments, the device is configured to operate according to a first operating mode in which a period clock is configured to cycle according to a first period and according to a second operating mode in which the period clock is configured to cycle according to a second period longer than the first period. In some embodiments, the third predetermined number of clock cycles is the same in the first operating mode as in the second operating mode. In some embodiments, the first predetermined number of clock cycles is smaller in the second operating mode than in the first operating mode. In some embodiments, the second predetermined number of clock cycles is larger in the second operating mode than in the first operating mode. In some embodiments, the second predetermined number of clock cycles is five (5) in the second operating mode and four (4) in the first operating mode.

[0032] Figure 1is a block diagram of a semiconductor device 100 according to some embodiments. By way of non-limiting example, the semiconductor device 100 according to an embodiment is a double data rate 4 (DDR4) type dynamic random access memory (DRAM) integrated on a single semiconductor chip and mounted on a substrate 140. The substrate 140 is a memory module substrate or a motherboard and is provided with a resistor RE. The resistor RE is connected to a calibration terminal ZQ of the semiconductor device 100, and its impedance is used as a reference impedance for a calibration circuit 134. In this embodiment, a ground voltage potential VSS is supplied to the resistor RE.

[0033] As Figure 1 shown, the semiconductor device 100 includes a memory cell array 114. The memory cell array 114 is divided into eight groups BANK0 to BANK7. Each of the groups BANK0 to BANK7 is provided with a plurality of word lines WL and a plurality of bit lines BLT, BLB, and memory cells MC are disposed at the intersections of these lines. By way of non-limiting example, the memory cell MC may be a DRAM cell having a cell transistor T and a memory cell capacitor C connected in series with the cell transistor T.

[0034] The selection of the word line WL is performed by a row decoder 112, and the selection of the bit line BL is performed by a column decoder 116. As Figure 1 shown, a row decoder 112 and a column decoder 116 are provided for each of BANK0 to BANK7.

[0035] The bit lines BLT, BLB are electrically connected to a sense amplifier SAMP. Read data read from the bit line BLT or the bit line BLB is amplified by the sense amplifier SAMP and then transmitted to an ECC control circuit 300 via complementary local data lines LIOT / LIOB, a switch circuit TG (transfer gate), and complementary main data lines MIOT / MIOB. A single shared ECC control circuit 300 is provided for all memory groups BANK0 to BANK7. Thus, there is a one-to-one relationship between the ECC control circuit 300 and the data terminal 120. In other words, the semiconductor device 100 includes a set of I / O pads (e.g., DQ pads) for the single ECC control circuit 300 at the data terminal 120, and all memory groups BANK0 to BANK7 of the memory cell array 114 share the single ECC control circuit 300. This one-to-one relationship enables simplification of the DQ output compared to semiconductor devices that use a separate ECC control circuit for each memory group of the memory cell array. For example, a first-in first-out (FIFO) buffer may not be required at the data input / output circuit 118 and the ECC copy logic because, as discussed in more detail below, the ECC control circuit 300 can manage the timing of providing the corrected read data to the global data bus GBUS.

[0036] When reading read data from the memory cell array 114, the ECC control circuit 300 generates parity. The write data output from the ECC control circuit 300 is transmitted to the sense amplifier SAMP via the complementary main data lines MIOT / MIOB, the switch circuit TG, and the complementary local data lines LIOT / LIOB, and is written in the memory cell MC connected to the bit line BLT or the bit line BLB. The write data is written in the memory cell array 114.

[0037] In addition, the semiconductor device 100 is provided with terminals as external terminals as follows: an address terminal 124, a command terminal 138, a clock terminal 126, a data terminal 120, a data mask terminal 122, a voltage terminal 128, a voltage terminal 130, and a calibration terminal ZQ.

[0038] The address terminal 124 is a terminal to which an address signal ADD and a bank address signal BADD are externally input. The address signal ADD input to the address terminal 124 is supplied to the address latch circuit 102 via the address input circuit 110 and is latched therein. The signals latched by the address latch circuit 102, the row address signal XADD, and the bank address signal BADD are supplied to the row decoder 112, while the column address signal YADD and the bank address signal BADD are supplied to the column decoder 116.

[0039] The row decoders corresponding to BANK0 to BANK7 in the row decoder 112 are selected based on the bank address signal BADD, and a predetermined word line WL is selected based on the row address signal XADD. The column decoders corresponding to BANK0 to BANK7 in the column decoder 116 are selected based on the bank address signal BADD, and a predetermined sense amplifier SAMP is selected based on the column address signal YADD.

[0040] The command terminal 138 is a terminal to which a command signal COM is externally input. The command signal COM input to the command terminal 138 is supplied to the command decoder 104 via the command input circuit 132. The command decoder 104 is a circuit that decodes the command signal COM and further generates various internal commands ICOM. The internal commands ICOM are supplied to the row decoder 112, the column decoder 116, and so on.

[0041] For example, if an active command and a read command are input as a command signal COM, and a row address XADD and a column address YADD are input synchronously therewith, read data is read from a memory cell MC specified by these row address XADD and column address YADD. The read data is input to the ECC control circuit 300, and if an error bit is included in the read data, the read data is corrected. The corrected read data DQ is supplied to the global data bus GBUS (e.g., a read / write bus (RWBS)), and is burst-output to the outside from the data terminal 120 via the data input / output circuit 118. Although not particularly limited, the embodiment is provided with eight terminals (DQ0 to DQ7) in the data terminal 120, and during a read operation, read data of 8 bits DQ is burst-output from each terminal of the data terminal 120. Therefore, read data of 64 bits DQ is output in one read operation.

[0042] On the other hand, if an active command and a write command are input as a command signal COM, and a row address XADD and a column address YADD are input synchronously therewith, and thereafter write data DQ is burst-input to the data terminal 120, then the write data DQ is supplied to the ECC control circuit 300 via the global data bus GBUS through the data input / output circuit 118. The write data is supplied to the memory cell array 114 and written to the memory cell MC specified by the row address XADD and the column address YADD. As described above, when eight terminals are provided in the data terminal 120 and the burst number is eight bits, write data of 64 bits DQ is input in one write operation.

[0043] During a write operation, a data mask signal DM may be input to the data mask terminal 122. If the data mask signal DM is input, the corresponding burst data of the write data DQ to be burst-input is masked.

[0044] An external clock signal CK, / CK is input to the clock terminal 126. The external clock signal CK and the external clock signal / CK are complementary signals to each other, and both of these external clock signals are supplied to the clock input circuit 108. The clock input circuit 108 generates an internal clock signal ICLK in response to the external clock signals CK, / CK. The internal clock signal ICLK is supplied to the internal clock generator 106, and in turn, a phase-controlled internal clock signal LCLK is generated. Although not particularly limited, a DLL circuit can be used as the internal clock generator 106. The phase-controlled internal clock signal LCLK is supplied to the data input / output circuit 118 and is used as a timing signal for determining the output timing of the read data DQ. It should be noted that the internal clock generator 106 is activated in response to a clock enable signal CKE which is one of the command signals COM.

[0045] The voltage terminals 128 are terminals to which voltage potentials VDD and VSS are supplied. The voltage potentials VDD and VSS supplied to the voltage terminals 128 are supplied to the internal voltage generator 136. The internal voltage generator 136 generates various internal voltage potentials VPP, VOD, VARY, VPERI, and a reference voltage potential ZQVREF based on the voltage potentials VDD and VSS. The internal voltage potential VPP is a voltage potential mainly used in the row decoder 112, the internal voltage potentials VOD and VARY are voltage potentials used in the sense amplifiers SAMP in the memory cell array 114, and the internal voltage potential VPERI is a voltage potential used in a plurality of other circuit blocks. On the other hand, the reference voltage potential ZQVREF is a reference voltage potential used in the calibration circuit 134.

[0046] The voltage terminals 130 are terminals to which voltage potentials VDDQ and VSSQ are supplied. The voltage potentials VDDQ and VSSQ supplied to the voltage terminals 130 are supplied to the data input / output circuit 118. The voltage potentials VDDQ and VSSQ are the same voltage potentials as the voltage potentials VDD and VSS supplied to the voltage terminals 128, respectively, but in order to prevent voltage noise caused by the data input / output circuit 118 from propagating to another circuit block, the voltage potentials VDDQ and VSSQ dedicated to the data input / output circuit 118 are used.

[0047] The calibration terminal ZQ is connected to the calibration circuit 134. When activated by the calibration signal ZQC, the calibration circuit 134 performs a calibration operation with reference to the impedance of the resistor RE and the reference potential ZQVREF. The impedance code ZQCODE obtained by the calibration operation is supplied to the data input / output circuit 118, and further specifies the impedance of an output buffer (not shown) included in the data input / output circuit 118.

[0048] Figure 2 is a block diagram of a memory device 200 according to some embodiments. The memory device 200 includes a plurality of memory cell arrays, each memory cell array being similar to the memory cell array 114 discussed in the reference Figure 1 discussed. The memory device 200 also includes a plurality of ECC circuits, each ECC circuit being similar to the Figure 1 ECC control circuit 300. The memory device 200 further includes multiple sets of data terminals, each data terminal being similar to the Figure 1The data terminal 120. Each memory cell array 114 is operatively coupled to the ECC control circuit 300 via a main input / output line (MIO line 202). Thus, all memory banks in each memory cell array 114 share a common set of MIO lines 202 that operatively couple the memory cell array 114 to its corresponding ECC control circuit 300. In some embodiments, each memory cell array 114 and its corresponding ECC MIO lines 202, ECC control circuit 300, global data bus GBUS 204, data input / output circuit 118, and data terminal 120 correspond to a separate memory chip.

[0049] Each ECC control circuit 300 is operatively coupled to its corresponding data input / output circuit 118 via the global data bus GBUS 204. Each ECC control circuit 300 is configured to receive read data 206 provided by the corresponding memory cell array 114 and to generate corrected read data 208 in response to the read data 206 received from the memory cell array 114. The ECC control circuit 300 is configured to provide the corrected read data 208 to its corresponding data terminal 120 via the global data bus GBUS 204.

[0050] The data input / output circuit 118 is operatively coupled to its corresponding data terminal 120. The data input / output circuit 118 is configured to receive the corrected read data 208 from the ECC control circuit 300 via the global data bus GBUS 204, serialize the corrected read data 208 to generate serialized read data 210, and provide the serialized read data 210 to the data terminal 120. The data terminal 120 includes I / O pads 212 (e.g., DQ pads).

[0051] There is a one-to-one relationship between each set of I / O pads 212 and its corresponding ECC control circuit 300. In other words, a single ECC control circuit 300 is operatively coupled to a single set of I / O pads 212 (via the global data bus GBUS 204 and the data input / output circuit 118). Thus, the data input / output circuit 118 does not include a FIFO buffer that is operatively coupled to multiple ECC control circuits, each corresponding to a single memory bank. Accordingly, the interface between the ECC control circuit 300 and the data terminal 120 is simpler compared to an interface that does not implement a one-to-one relationship between the ECC control circuit and the data terminal.

[0052] Figure 3 is according to some embodiments Figure 1 and Figure 2 block diagram of the ECC control circuit 300.Figure 3 The ECC control circuit 300 described in Figure 2 includes an ECC control circuit input 328 operatively coupled to the MIO line 202 of Figure 2 . The ECC control circuit 300 also includes an ECC control circuit output 330 operatively coupled to the global data bus GBUS 204 of Figure 1 and Figure 2 . The ECC control circuit 300 further includes a digital sense amplifier (DSA 302) operatively coupled to the ECC control circuit input 328, a latch 304 operatively coupled to the DSA 302, a syndrome tree circuit 306 operatively coupled to the latch 304, a latch 318 operatively coupled to the syndrome tree circuit 306, and a decoder 320 operatively coupled to the latch 318. The ECC control circuit 300 also includes a latch 324 operatively coupled to the latch 304, a correction circuit 322 operatively coupled to the latch 324, and a GBUS driver 326 operatively coupled between the correction circuit 322 and the ECC control circuit output 330. As previously discussed, the ECC control circuit 300 is configured to receive read data 206 at the ECC control circuit input 328 from the memory bank of the memory cell array 114 corresponding to the ECC control circuit 300 ( Figure 1 and Figure 2 ) and provide corrected read data 208 to the global data bus GBUS 204 at the ECC control circuit output 330.

[0053] The ECC control circuit input 328 of the ECC control circuit 300 is configured to receive read data 206 from the memory bank corresponding to the ECC control circuit 300 in the memory cell array 114 via the MIO line 202. The read data 206 is provided to the DSA 302, and the DSA 302 is enabled by a DSA enable signal CDAE provided to the ECC control circuit 300 by the memory cell array 114. By way of non-limiting example, the group logic of the memory cell array 114 can generate the DSA enable signal CDAE and provide the DSA enable signal CDAE to the ECC control circuit 300. In response to the assertion of the DSA enable signal CDAE (e.g., a transition from a first logic level not associated with triggering the DSA 302 to a second logic level associated with triggering the DSA 302), the DSA 302 is configured to amplify the read data 206 to produce amplified read data 308 and provide the amplified read data 308 to the latch 304.

[0054] Latch 304 is configured to latch the amplified read data 308 provided to the latch 304 by the DSA 302 in response to the DSA enable signal CDAE to generate the latched read data LDr 310. The latch 304 is configured to provide the amplified read data 308 to the syndrome tree circuit 306 and the latch 324. The syndrome tree circuit 306 is configured to receive the latched read data LDr 310 and generate one or more parity bits in response to the latched read data LDr 310, and provide the one or more parity bits in the ECC decode signal ECCDec 314 to the latch 318.

[0055] Latch 318 is configured to receive the ECC decode signal ECCDec 314 from the syndrome tree circuit 306, and latch one or more parity bits in the parity check signal zldcorf 316 in response to the latch signal CLDEF. The latch 318 is configured to provide the latched parity check signal zldcorf 316 to the decoder 320. The latch 324 is configured to latch the latched read data LDr 310 in response to the latch signal CLDEF to generate the latched read data LLDr 312. The latch 324 is configured to provide the latched read data LLDr 312 to the correction circuit 322. Since both the latch 318 and the latch 324 are triggered by the same latch signal CLDEF, the parity check signal zldcorf 316 is provided to the decoder 320 substantially at the same time as the LLDr 312 is provided to the correction circuit 322.

[0056] Decoder 320 is configured to receive the parity check signal zldcorf 316 and generate the decoded signal 332 in response to the parity check signal zldcorf316. The decoder 320 is configured to provide the decoded signal 332 to the correction circuit 322.

[0057] Correction circuit 322 is configured to receive the latched read data LLDr 312 from the latch 324 and the decoded signal 332 from the decoder 320. The correction circuit 322 is configured to determine whether there are one or more errors in the latched read data LLDr 312 in response to the decoded signal 332. In response to determining that there are one or more errors in the latched read data LLDr 312, the correction circuit 322 is configured to correct the latched read data LLDr 312 to generate the corrected read data CRD334. In response to determining that there are no errors in the latched read data LLDr 312, the correction circuit 322 is configured to pass the latched read data LLDr 312 as the corrected read data CRD 334. The correction circuit 322 is configured to provide the corrected read data CRD 334 to the GBUS driver 326.

[0058] The GBUS driver 326 is configured to receive the corrected read data CRD 334 from the correction circuit 322 and drive the corrected read data CRD 334 in response to the GBUS driver trigger signal CRlat to generate the corrected read data 208. The GBUS driver 326 is configured to provide the corrected read data 208 to the global data bus GBUS 204 through the ECC control circuit output 330.

[0059] Rather than relying on the ECC copy and the delay block to account for the computational delay added by the correction subtree circuit 306, the timing for the trigger latches 318, latch 324, and GBUS driver 326 can be determined from known system parameters such as the read latency (RL). It can be known how much time it takes from receiving the read command to delivering the read data 206 to the ECC control circuit 300. It can also be known how much time it takes for the correction subtree circuit 306 to generate the ECCDec 314. Therefore, the DSA enable signal CDAE and the latch signal CLDEF can be timed according to these known parameters.

[0060] Moreover, by way of non-limiting example, if it is known that the GBUS driver 326 takes less than two clock cycles but more than one clock cycle to drive the corrected read data 208 onto the global data bus GBUS 204, then the GBUS driver trigger signal CRlat can be set to trigger the GBUS driver 326 two clock cycles before the read latency time period (RL - 2) after triggering the read command that provides the read data 206 to the ECC control circuit 300. As another non-limiting example, if it is known that the GBUS driver 326 takes less than three clock cycles but more than two clock cycles to drive the corrected read data 208 onto the global data bus GBUS 204, then the GBUS driver trigger signal CRlat can be set to trigger the GBUS driver 326 three clock cycles before the read latency time period (RL - 3) after triggering the read command that provides the read data 206 to the ECC control circuit 300.

[0061] Since the ECC control circuit 300 does not include an ECC copy or a delay block for taking into account the calculation delay added by the syndrome tree circuit 306, the ECC control circuit 300 may have improved power consumption and chip space compared to an ECC control circuit that includes an ECC copy and / or a delay block for taking into account the calculation delay added by the syndrome tree circuit. For example, the ECC copy may include an epitaxial logic circuit system (e.g., an "exclusive OR" (XOR) gate), which occupies a relatively large amount of chip space and consumes a non-negligible amount of current. Thus, removing such a circuit system from the ECC control circuit 300 reduces the power consumption during operation and the chip space occupancy required to manufacture the ECC control circuit 300.

[0062] Figure 4 is an example signal timing diagram of signal 400 that can be observed in Figure 3 the ECC control circuit 300. Referring together to Figure 3 and Figure 4 , signal 400 includes a clock signal 422 (CK, which, without limitation, may be Figure 1 the internal clock ICK), a command 420 (CMD) including a first read command 416 and a second read command 418, read data 206 and read data 402 on the MIO line 202, a DSA enable signal CDAE, latched read data LDr 310 and LDr404, ECC decode signals ECCDec 314 and ECCDec 406, a latch signal CLDEF, parity signals zldcorf316 and zldcorf 408, a GBUS driver trigger signal CRlat, corrected read data 208 and corrected read data 410 on the global data bus GBUS 204, and serialized read data 210 and serialized read data 412 on the I / O pad 212 (DQ).

[0063] can (e.g., by the memory cell array 114 ( Figure 1 and Figure 2 ) receive the first read command 416. In some embodiments, a read command such as read command 416 may begin with the assertion of a column select (read CS) signal (e.g., received from the column decoder 116 by the memory cell array 114 ( Figure 1 ). Thus, read data 206 may be transferred to the LIOT / B line ( Figure 1 of the memory cell array 114 on the bit lines (e.g., Figure 1 ). The read data 206 is transferred to the MIOT / B line ( Figure 1 ) via a transfer gate TG ( Figure 1 , corresponding to Figure 4The MIO line 202), and thus, the memory cell array 114 can provide the read data 206 to the ECC control circuit 300 via the MIO line 202. The DSA enable signal CDAE can be asserted at a predetermined time period after the first read command 416 (i.e., from the read CS signal) (by transitioning from a low logic level to a high logic level in Figure 4 . The DSA enable signal CDAE can be an analog delay signal that tracks the data path triggered by the read CS signal corresponding to the first read command 416. The syndrome tree circuit 306 receives the latched read data LDr for parity generation and provides the ECC decode signal ECCDec 314 to the latch 318.

[0064] For the correct read data to be driven onto the global data bus GBUS 204 at RL-2, the ECCdec signal 314 is latched in response to CLDEF at a clock cycle after a delay time period sufficient to account for the delay through the syndrome tree circuit 306. According to RL - [(2 + n)*tCK], the latch signal CLDEF can be asserted at a number n of clock cycles before two clock cycles before the read latency time labeled RL. In other words, the latch signal CLDEF can be asserted at time RL - [(2 + n)*tCK], where n is an integer value and tCK depends on the frequency of the clock signal 422 (e.g., tCK can be the period of the clock signal 422). In Figure 4 the example, the latch signal CLDEF is asserted at four clock cycles before RL (RL - 2 - 2, corresponding to n = 2). Thus, the latch signal CLDEF is asserted at RL - 4 (transitioning from a high logic level to a low logic level in Figure 4 ), to provide the syndrome tree circuit 306 with sufficient time to generate the ECC decode signal ECCDec 314. In response, the parity signal zldcorf 316 is latched into the decoder 320, the decoder 320 receives the parity signal zldcorf 316, and the correction circuit 322 receives the latched read data LLDr 312 and the decoded signal 332. The parity signal zldcorf 316 is valid throughout the window until CRlat ends and the read data is driven onto the global data bus GBUS 204. The correction circuit 322 provides the CRD 334 to the GBUS driver 326.

[0065] For the read data to be correctly output to the DQ pad 212 at a time tDQSCK (RL + tDQSCK, where tDQSCK is the clock for the read DQS delay, which is an LPDDR4 JEDEC analog specified value of 1 to 4.5 nanoseconds) after the read latency RL, the GBUS driver 326 ( Figure 3) drives the global data bus GBUS 204 at RL-2. This allows the parallel-to-serial conversion of the global data bus GBUS 204 propagating and reading data to be completed. A predetermined number of clock cycles ( Figure 4 ) asserts (for example, in Figure 4 The GBUS driver trigger signal CRlat is changed from logic level low to logic level high in the process, which provides sufficient time for the GBUS driver 326 to drive the corrected read data 208 to the global data bus GBUS 204. The corrected read data 208 is provided to the data input / output circuit 118 ( Figure 1 and Figure 2 ), the data input / output circuit 118 performs parallel-to-serial conversion 414 on the corrected read data 208 to generate serialized read data 210, and the data input / output circuit 118 provides the serialized read data 210 to the I / O pad 212.

[0066] After the first read command 416, (eg, via the memory cell array 114 ( Figure 1 and Figure 2 ) receives the second read command 418, and thus, the memory cell array 114 may provide the read data 402 corresponding to the second read command 418 to the ECC control circuit 300 via the MIO line 202. The DSA enable signal CDAE may be asserted a predetermined time period after the second read command 418 (e.g., a predetermined time period after the read CS signal corresponding to the second read command 416). Thus, the latch 304 latches the latched read data LDr 404, and the correction subtree circuit 306 provides the ECC decoding signal ECCDec 406 to the latch 318.

[0067] The latch signal CLDEF is latched a predetermined time period before RLL (in Figure 4 , about four clock cycles before the RLL, or RLL-4) assertion (in Figure 4 406) to provide sufficient time for the correction subtree circuit 306 to generate the ECC decode signal ECCDec 406. In response, the parity signal zldcorf 408 is latched to the decoder 320, the decoder 320 receives zldcorf 408, and the correction circuit 322 receives the latched read data and the decoded signal associated with the second read command 418. The correction circuit 322 receives the CRD 334 ( Figure 3 ) is provided to the GBUS driver 326.

[0068] A predetermined number of clock cycles before the RLL ( Figure 4Two clock cycles in, or RLL-2) asserts the GBUS driver trigger signal CRlat (e.g., transitions from a low logic level to a high logic level in Figure 4 ), which provides sufficient time for the GBUS driver 326 to drive the corrected read data 410 onto the global data bus GBUS 204. The corrected read data 410 is provided to the data input / output circuit 118 ( Figure 1 and Figure 2 ), and the data input / output circuit 118 performs a parallel-to-serial conversion 414 on the corrected read data 410 to generate the serialized read data 412, and the data input / output circuit 118 provides the serialized read data 412 to the I / O pad 212.

[0069] Figure 5 is an example signal timing diagram of the clock signal 522 (CK) having a longer period compared to the clock signal 422 of Figure 3 that can be observed in the ECC control circuit 300 of Figure 4 . Referring together to Figure 3 and Figure 5 , the signal 500 includes the clock signal 522 (CK), the command 520 (CMD) including the first read command 516 and the second read command 518, the read data 206 and read data 502 on the MIO line 202, the DSA enable signal CDAE, the latched read data LDr 310 and LDr 504, the ECC decoding signals ECCDec 314 and ECCDec 506, the latch signal CLDEF, the parity signals zldcorf 316 and zldcorf508, the GBUS driver trigger signal CRlat, the corrected read data 208 and corrected read data 510 on the global data bus GBUS 204, and the serialized read data 210 and serialized read data 512 on the I / O pad 212 (DQ).

[0070] can (e.g., via the memory cell array 114 ( Figure 1 and Figure 2 )) receive the first read command 516, and thus, the memory cell array 114 can provide the read data 206 to the ECC control circuit 300 via the MIO line 202. The DSA enable signal CDAE can be asserted after a predetermined time period after the first read command 516 (e.g., after the read CS signal) (by transitioning from a low logic level to a high logic level in Figure 5 ). Thus, the latch 304 latches the latched read data LDr 310, and the syndrome tree circuit 306 provides the ECC decoding signal ECCDec 314 to the latch 318.

[0071] The latch signal CLDEF is asserted at RL - [(2 + n)*tCK] (transitions from a high logic level to a low logic level in Figure 5 ) at a predetermined time period before RL. Compared to Figure 4 , this corresponds to the n = 4 case (due to the higher frequency of the clock signal CK in Figure 4 ), and the latch signal CLDEF of Figure 5 can be asserted at RL - 5, which corresponds to the n = 3 case. This can provide sufficient time for the syndrome tree circuit 306 to generate the ECC decoding signal ECCDec 314. In response, the parity check signal zldcorf 316 is latched into the decoder 320, the decoder 320 receives the parity check signal zldcorf 316, and the correction circuit 322 receives the latched read data LLDr 312 and the decoded signal 332. The correction circuit 322 provides the CRD334 to the GBUS driver 326.

[0072] The GBUS driver trigger signal CRlat is asserted at a predetermined number of clock cycles before RL (two clock cycles in Figure 5 ) (e.g., transitions from a low logic level to a high logic level in Figure 5 ), which provides sufficient time for the GBUS driver 326 to drive the corrected read data 208 to the global data bus GBUS 204. The corrected read data 410 is provided to the data input / output circuit 118 ( Figure 1 and Figure 2 ), and the data input / output circuit 118 performs a parallel - to - serial conversion 514 on the corrected read data 208 to generate the serialized read data 210, and the data input / output circuit 118 provides the serialized read data 210 to the I / O pad 212.

[0073] After the first read command 516, a second read command 518 is received (e.g., from the column decoder 116 ( Figure 1 and Figure 2 )) by the memory cell array 114 ( Figure 1 ), and thus, the memory cell array 114 can provide the read data 502 corresponding to the second read command 518 to the ECC control circuit 300 via the MIO line 202. The DSA enable signal CDAE can be asserted at a predetermined time period after the second read command 418 (i.e., after the read CS signal). Thus, the latch 304 latches the latched read data LDr 504, and the syndrome tree circuit 306 provides the ECC decoding signal ECCDec506 to the latch 318.

[0074] The latch signal CLDEF is at a predetermined time period before RL (e.g., in Figure 5In five clock cycles prior to RL, or RL-5), assert (in Figure 5 a transition from a high logic level to a low logic level in) to provide sufficient time for the syndrome tree circuit 306 to generate the ECC decode signal ECCDec 506. In response, the parity signal zldcorf508 is latched into the decoder 320, the decoder 320 receives zldcorf 508, and the correction circuit 322 receives the latched read data and the decoded signal associated with the second read command 418. The correction circuit 322 provides the corrected read data CRD to the GBUS driver 326.

[0075] At a predetermined number of clock cycles prior to RLL ( Figure 5 two clock cycles in) assert the GBUS driver trigger signal CRlat (e.g., in Figure 5 a transition from a low logic level to a high logic level in), which provides sufficient time for the GBUS driver 326 to drive the corrected read data 510 onto the global data bus GBUS 204. The corrected read data 510 is provided to the data input / output circuit 118 ( Figure 1 and Figure 2 ), and the data input / output circuit 118 performs a parallel-to-serial conversion 514 on the corrected read data 510 to generate the serialized read data 512, and the data input / output circuit 118 provides the serialized read data 512 to the I / O pad 212.

[0076] In some embodiments, the ECC control circuit 300 is configured to operate according to a first operating mode in which the period clock CK is configured to cycle according to a first period (e.g., Figure 4 a relatively short tCK of) and according to a second operating mode in which the period clock is configured to cycle according to a second period longer than the first period (e.g., Figure 5 a relatively long tCK of). In some such embodiments, the GBUS trigger signal CRlat can be asserted at the same predetermined number of clock cycles prior to RL (e.g., two clock cycles prior to RL, or RL-2), regardless of the difference between the first period and the second period. However, the number of predetermined clock cycles from the read command to the DSA enable signal CDAE can be smaller in the second operating mode (longer tCk) than in the first operating mode (shorter tCK). Also, the latch signal CLDEF can be asserted at a larger predetermined number of clock cycles prior to RL compared to the first operating mode. By way of non-limiting example, compared to Figure 5 which can correspond to the second operating mode (longer period tCK) and in which the latch signal CLDEF is asserted at five clock cycles prior to RL (RL-5), in Figure 4In it, the latch signal CLDEF is asserted four clock cycles before RL (RL - 4).

[0077] Figure 6 is a flowchart illustrating a method 600 of operating an ECC control circuit. The ECC control circuit has a one - to - one relationship with input / output pads shared by multiple memory banks of a memory cell array. At operation 602, method 600 includes amplifying read data received from a memory cell array including multiple memory banks via a set of MIO lines shared by the multiple memory banks to generate amplified read data. The read data corresponds to a read command. In some embodiments, amplifying the read data includes using a digital sense amplifier (e.g., Figure 3 the DSA 302) to amplify the read data. In some embodiments, amplifying the read data includes providing the read data to a digital sense amplifier and asserting a DSA enable signal (e.g., Figure 3 the CDAE) to enable the digital sense amplifier.

[0078] At operation 604, method 600 includes latching the amplified read data to provide the latched read data to a syndrome tree circuit. In some embodiments, latching the amplified read data includes triggering a latch using the DSA enable signal. At operation 606, method 600 includes generating an ECC decoding signal by the syndrome tree circuit in response to the latched read data. In some embodiments, generating the ECC decoding signal includes generating one or more parity bits based on the latched read data.

[0079] At operation 608, method 600 includes latching the latched read data to provide the latched read data to a correction circuit. In some embodiments, latching the latched read data includes latching a signal to trigger a latch provided with the latched read data. In some embodiments, latching the latched read data includes latching the latched read data at a predetermined amount of time before a read latency time period expires. In some embodiments, the predetermined amount of time before the read latency time period expires is RL - [(2 + n)*tCK].

[0080] At operation 610, method 600 includes latching an ECC decoded signal to provide a parity signal. In some embodiments, latching the ECC decoded signal includes latching the ECC decoded signal by the same latching signal used to latch the latched read data in operation 608. At operation 612, method 600 includes decoding the parity signal to generate a decoded signal. For example, the latching signal used to latch the ECC decoded signal to provide the parity signal may be asserted at RL-[(2+n)*tCK]. In some embodiments, decoding the parity signal includes using a decoder to decode the parity signal. In some embodiments, decoding the parity signal to provide the parity signal includes providing the parity signal to indicate whether there is one or more errors in the latched read data.

[0081] At operation 614, method 600 includes generating corrected read data in response to the decoded signal and the latched read data. In some embodiments, generating the corrected read data includes providing the read data as the corrected read data in response to determining that the decoded signal does not indicate an error in the read data, and correcting the read data and providing the corrected read data in response to determining that the decoded signal indicates an error in the read data.

[0082] At operation 616, method 600 includes driving the corrected read data onto a global data bus in response to a trigger signal. The trigger signal is asserted at a predetermined amount of time (e.g., two clock cycles) after the read command and before the expiration of a read latency time period to trigger the driving of the corrected read data.

[0083] Figure 7 is a block diagram of a computing system 700 according to some embodiments. The computing system 700 includes one or more processors 704 operatively coupled to one or more memory devices 702, one or more non-volatile data storage devices 710, one or more input devices 706, and one or more output devices 708. In some embodiments, the computing system 700 includes a personal computer (PC), such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (e.g., a smart phone, a personal digital assistant (PDA), etc.), a network server, or other computer device.

[0084] In some embodiments, one or more processors 704 may include a central processing unit (CPU) or other processors configured to control the computing system 700. In some embodiments, one or more memory devices 702 include random access memory (RAM), such as volatile data storage devices (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, one or more non-volatile data storage devices 710 include hard disk drives, solid state drives, flash memory, erasable programmable read only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, one or more input devices 706 include a keyboard 712, a pointing device 714 (e.g., a mouse, a track pad, etc.), a microphone 716, a keypad 718, a scanner 720, a camera 722, other input devices, or any combination thereof. In some embodiments, output devices 708 include an electronic display 724, speakers 726, a printer 728, other output devices, or any combination thereof.

[0085] In some embodiments, one or more memory devices 702 include Figure 1 semiconductor device 100 of Figure 2 memory device 200 of and / or Figure 3 ECC control circuit 300 of. In some embodiments, one or more memory devices 702 are configured to generate Figure 4 signal 400 of and / or Figure 5 part or all of signal 500 of. In some embodiments, one or more memory devices 702 are configured to execute Figure 6 part or all of method 600 of.

[0086] Those of ordinary skill in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or any combination thereof. Figure 8 Non-limiting examples of implementing the functional elements disclosed herein are described. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to implement the functional elements.

[0087] Figure 8FIG. 0 is a block diagram of a circuit system 800 that may be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Circuit system 800 includes one or more processors 802 (sometimes referred to herein as "processor 802") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage device 804"). Storage device 804 includes machine-executable code 806 stored thereon and processor 802 includes logic circuitry 808. Machine-executable code 806 includes information describing functional elements that may be implemented (e.g., executed) by logic circuitry 808. Logic circuitry 808 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 806. Circuit system 800 should be regarded as specialized hardware configured to implement the functional elements disclosed herein when executing the functional elements described by machine-executable code 806. In some embodiments, processor 802 may be configured to execute the functional elements described by machine-executable code 806 sequentially, in parallel (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0088] When implemented by logic circuitry 808 of processor 802, machine-executable code 806 is configured to adapt processor 802 to perform the operations of the embodiments disclosed herein. For example, machine-executable code 806 may be configured to adapt processor 802 to execute at least a portion or all of Figure 6 method 600. As another example, machine-executable code 806 may be configured to adapt processor 802 to execute at least a portion or all of the operations discussed for Figure 1 , Figure 2 and Figure 3 ECC control circuit 300.

[0089] The processor 802 may include a general - purpose processor, a special - purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application - specific integrated circuit (ASIC), a field - programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general - purpose computer including a processor is considered a special - purpose computer, and the general - purpose computer is configured to execute functional elements corresponding to machine - executable code 806 (e.g., software code, firmware code, hardware description) related to embodiments of the present disclosure. It should be noted that a general - purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor 802 may include any conventional processor, controller, microcontroller, or state machine. The processor 802 may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0090] In some embodiments, the storage device 804 includes volatile data storage devices (e.g., random - access memory (RAM)), non - volatile data storage devices (e.g., flash memory, hard - disk drive, solid - state drive, erasable programmable read - only memory (EPROM), etc.). In some embodiments, the processor 802 and the storage device 804 may be implemented into a single device (e.g., a semiconductor device product, a system - on - chip (SOC), etc.). In some embodiments, the processor 802 and the storage device 804 may be implemented into separate devices.

[0091] In some embodiments, the machine - executable code 806 may include computer - readable instructions (e.g., software code, firmware code). By way of non - limiting examples, the computer - readable instructions may be stored by the storage device 804, directly accessed by the processor 802, and executed by the processor 802 using at least the logic circuitry 808. Also by way of non - limiting examples, the computer - readable instructions may be stored on the storage device 804, transferred to a memory device (not shown) for execution, and executed by the processor 802 using at least the logic circuitry 808. Thus, in some embodiments, the logic circuitry 808 includes electrically configurable logic circuitry 808.

[0092] In some embodiments, the machine-executable code 806 may describe hardware (e.g., circuitry) to be implemented in the logic circuitry 808 to perform functional elements. This hardware may be described at any of a variety of levels of abstraction from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) such as the IEEE standard hardware description language (HDL) may be used. By way of non-limiting example, Verilog may be used TM , SystemVerilog TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL TM ).

[0093] The HDL description may be converted as needed to a description at any of a number of other levels of abstraction. By way of non-limiting example, a high-level description may be converted to a logic-level description (e.g., Register Transfer Language (RTL)), gate-level (GL) description, layout-level description, or mask-level description. By way of non-limiting example, the micro-operations that the hardware logic circuitry of the logic circuitry 808 (e.g., non-limitingly, gates, flip-flops, registers) will perform may be described in RTL and then converted to a GL description by a synthesis tool, and the GL description may be converted to a layout-level description corresponding to the physical layout of an integrated circuit of programmable logic devices, discrete gates or transistor logic, discrete hardware components, or combinations thereof by a placement and routing tool. Thus, in some embodiments, the machine-executable code 806 may include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0094] In embodiments in which the machine-executable code 806 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 804) may be configured to implement the hardware description described by the machine-executable code 806. By way of non-limiting example, the processor 802 may include a programmable logic device (e.g., FPGA or PLC) and the logic circuitry 808 may be electrically controlled to implement the circuitry corresponding to the hardware description into the logic circuitry 808. Also by way of non-limiting example, the logic circuitry 808 may include hardwired logic fabricated by a manufacturing system (not shown, but including the storage device 804) according to the hardware description of the machine-executable code 806.

[0095] Regardless of whether the machine-executable code 806 includes computer-readable instructions or a hardware description, the logic circuitry 808 is adapted to perform the functional elements described by the machine-executable code 806 when implementing the functional elements of the machine-executable code 806. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0096] As used in this disclosure, the term "module" or "component" may refer to a particular hardware implementation configured to perform the actions of a module or component and / or a software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, etc.). In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or handlers executing on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), particular hardware implementations or combinations of software with particular hardware implementations are also possible and contemplated.

[0097] As used in this disclosure, the term "combination" referring to multiple elements may include any combination of all the elements or any of the various different sub-combinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to any of the following: A, B, C, or D; the combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0098] The terms used in this disclosure and especially in the appended claims (e.g., the body of the appended claims) are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", the term "includes" should be interpreted as "including but not limited to", etc.).

[0099] Moreover, if an intent is to use a specific number of introduced claim recitations, then such intent will be explicitly recited in the claim, and in the absence of such recitation, there is no such intent. For example, for purposes of aiding understanding, the appended claims may contain the use of introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that any particular claim that introduces a claim recitation by the indefinite article "a / an" is limited to an embodiment containing only one such recitation, even when the same claim contains an introductory phrase "one or more" or "at least one" and an indefinite article such as "a" (e.g., "a" should be interpreted to mean "at least one" or "one or more"); this also applies to the case of using a definite article to introduce a claim recitation.

[0100] In addition, even if a specific number of recited claims are recited explicitly, those skilled in the art will recognize that such recitation should be interpreted to mean at least that number (e.g., an explicit recitation of "two recitations" without further modifiers means at least two recitations or two or more recitations). Further, in those instances where a convention such as "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, generally, such constructions are intended to cover only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc.

[0101] In addition, it should be understood that any transitional phrase or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, is expected to cover the possibility of one of the terms, any one of the terms, or both terms. For example, the phrase "A or B" should be understood to cover the possibility of "A" or "B" or "A and B".

[0102] Although the present disclosure has been described with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, many additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the claimed invention and its legal equivalents. Additionally, features from one embodiment can be combined with features from another embodiment while still being covered within the scope of the present disclosure as contemplated by the inventors.

Claims

1. A memory device, comprising: An error correction code (ECC) control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared master input / output (MIO) lines, the single set of shared MIO lines being shared by the plurality of memory banks; A single ECC control circuit configured to generate corrected read data in response to the read data received at the ECC control circuit input; And An ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus, the single ECC control circuit including a global data bus driver configured to drive the corrected read data to the global data bus in response to a global data bus trigger signal, the global data bus trigger signal being asserted for a predetermined number of clock time periods before the expiration of a read latency time period after a read command corresponding to the corrected read data.

2. The memory device according to claim 1, further comprising a data input / output (I / O) circuit configured to receive the corrected read data from the global data bus and provide serialized read data in response to the corrected read data, wherein the data I / O circuit does not include a first-in-first-out (FIFO) buffer coupled to a plurality of ECC control circuits.

3. The memory device according to claim 2, further comprising a single set of I / O pads operatively coupled to the data I / O circuit, the single set of I / O pads being configured to provide the serialized read data, the single set of I / O pads having a one-to-one relationship with the single ECC control circuit.

4. The memory device according to claim 1, wherein the single ECC control circuit includes: A digital sense amplifier configured to receive the read data from the ECC control circuit input and generate amplified read data in response to a DSA enable signal received from the memory cell array; A first latch configured to latch the amplified read data in response to the DSA enable signal to provide latched read data; A syndrome tree configured to generate an ECC decoded signal including one or more parity bits in response to the latched read data; A second latch configured to latch the latched read data in response to a latch signal; A third latch configured to latch the ECC decoded signal in response to the latch signal to provide a parity check signal; A decoder configured to decode the parity check signal to generate a decoded signal; A correction circuit configured to generate the corrected read data in response to the latched read data and the decoded signal.

5. The memory device according to claim 1, wherein the predetermined number of clock time periods is two clock time periods.

6. A memory device, comprising: A plurality of memory banks configured to store data thereon; A single set of input / output I / O pads shared by the plurality of memory banks; A data I / O circuit electrically connected to the single set of I / O pads; A global data bus operatively coupled to the data I / O circuit; and A single error correction code ECC control circuit electrically connected between the plurality of memory banks and the data I / O circuit, the single ECC control circuit having a one-to-one relationship with the single set of I / O pads, the single ECC control circuit being configured to: Receive read data read from the plurality of memory banks; and Provide corrected read data to the global data bus in response to the read data; Wherein the single ECC control circuit includes a global data bus driver configured to provide the corrected read data to the data I / O circuit at a predetermined number of clock cycles before the expiration of a read latency time period after a read command corresponding to the corrected read data.

7. The memory device according to claim 6, wherein the single ECC control circuit includes a correction circuit configured to generate the corrected read data in response to the read data and a decoded signal corresponding to one or more decoded parity bits generated in response to the read data.

8. The memory device according to claim 7, wherein the correction circuit is configured to determine whether the read data includes an error in response to the decoded signal.

9. The memory device according to claim 8, wherein the correction circuit is further configured to provide the read data as the corrected read data in response to determining that the read data does not include an error.

10. The memory device according to claim 8, wherein the correction circuit is further configured to correct the read data and provide the corrected read data in response to determining that the read data includes an error.

11. The memory device according to claim 6, wherein the single ECC control circuit includes a syndrome tree circuit configured to generate one or more parity bits in response to the read data.

12. The memory device according to claim 11, wherein the single ECC control circuit does not include ECC copy logic configured to model the delay of the syndrome tree circuit.

13. A method of operating an error correction code ECC control circuit having a one-to-one relationship with an input / output pad shared by a plurality of memory banks of a memory cell array, the method comprising: Generating a parity check signal in response to receiving read data from the memory cell array, the read data corresponding to a read command; Decoding the parity check signal to generate a decoded signal; Generating corrected read data in response to the decoded signal and the read data; and Driving the corrected read data onto a global data bus at a predetermined amount of time before the expiration of a read latency time period after the read command.

14. The method according to claim 13, which further comprises: Amplify the read data received from the memory cell array to generate amplified read data; and Latch the amplified read data to provide latched read data, wherein generating the parity check signal in response to the read data and generating the corrected read data in response to the read data includes generating the parity check signal and generating the corrected read data in response to the latched read data.

15. The method according to claim 13, wherein generating the parity check signal includes: Applying the read data to a syndrome circuit to generate an ECC decoding signal; and Latching the ECC decoding signal to provide the parity check signal to a decoder.

16. The method according to claim 13, wherein driving the corrected read data onto the global data bus a predetermined amount of time before the expiration of the read latency time period includes driving the corrected read data onto the global data bus two clock cycles before the expiration of the read latency time period.

17. The method according to claim 13, wherein generating the corrected read data in response to the decoded signal and the read data includes: Providing the read data as the corrected read data in response to determining that the decoded signal does not indicate an error in the read data; and Correcting the read data and providing the corrected read data in response to determining that the decoded signal indicates an error in the read data.

18. The method according to claim 13, wherein driving the corrected read data onto the global data bus a predetermined amount of time before the expiration of the read latency time period includes providing the corrected read data to a global data bus driver and asserting a trigger signal provided to the global data bus a predetermined amount of time before the expiration of the read latency time period.

19. A memory device, comprising: A digital sense amplifier DSA configured to receive read data from any one of a plurality of memory banks, the DSA being configured to be enabled to operate in response to an assertion of a DSA enable signal, the assertion of the DSA enable signal occurring a first predetermined number of clock cycles after a read command to retrieve the read data from the plurality of memory banks; A first latch configured to receive the read data and latch the read data in response to the DSA enable signal to provide latched read data; A syndrome circuit configured to receive the latched read data and generate one or more parity bits in response to the latched read data; A second latch configured to latch the one or more parity bits from the syndrome tree circuit in response to an assertion of a latch signal, the assertion of the latch signal occurring a second predetermined number of clock cycles before a read latency time, the read latency time occurring during a read latency time period after the read command, the second predetermined number of clock cycles being sufficient to provide the syndrome tree circuit with sufficient time to generate the one or more parity bits; A decoder configured to generate a decoder signal in response to the one or more latched parity bits; A correction circuit configured to generate corrected read data in response to the latched read data and the decoder signal; and A global data bus driver configured to drive the corrected read data onto a global data bus in response to an assertion of a global data bus driver trigger signal, the global data bus driver trigger signal being configured to assert a third predetermined number of clock cycles before the read latency time.

20. The memory device of claim 19, wherein the third predetermined number of clock cycles is two clock cycles.

21. The memory device of claim 19, wherein the memory device is configured to operate according to a first operating mode during which the clock is configured to cycle according to a first period and according to a second operating mode during which the clock is configured to cycle according to a second period that is longer than the first period.

22. The memory device of claim 21, wherein the third predetermined number of clock cycles is the same during the first operating mode as during the second operating mode.

23. The memory device of claim 21, wherein the first predetermined number of clock cycles is smaller in the second operating mode than in the first operating mode.

24. The memory device of claim 21, wherein the second predetermined number of clock cycles is larger in the second operating mode than in the first operating mode.

25. The memory device of claim 21, wherein the second predetermined number of clock cycles is five in the second operating mode and four in the first operating mode.

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