A non-ion-implanted radiation-resistant power transistor and its manufacturing method

Abstract

An ion implantation-free anti-radiation power transistor and its manufacturing method belong to the technical field of transistors. By first forming a dense thin silicon oxide layer in the active region of the transistor, then forming a highly dense anti-radiation barrier layer on the thin silicon oxide layer, and then forming a low-density anti-radiation absorption layer on the anti-radiation barrier layer, the radiation is greatly attenuated, the influence of radiation on the underlying silicon oxide layer is greatly reduced, the electron-hole pairs generated by irradiation of the thin silicon oxide layer are quickly swept out of the oxide layer, and positively charged oxide trap charges cannot be formed at the oxide layer interface, greatly reducing the redistribution of impurity concentration in the silicon substrate, greatly improving the carrier lifetime and current gain, reducing the reverse leakage current and saturation voltage drop, and significantly improving the anti-radiation ability of the transistor. It solves the problem that a high-energy ion implantation process must be used to manufacture an anti-radiation power transistor and the cost is high. It is widely used in the anti-radiation fields of semiconductor transistors and semiconductor integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor transistors, and more particularly, to a non-ion-implanted radiation-resistant power transistor structure and a method for manufacturing the same. Background Art

[0002] The typical structure and production process of existing power transistors are as shown in Figure 1 , Figure 2 . After the irradiation test, the products produced by this design process have obvious decreases in current gain, increases in reverse leakage current, and increases in saturation voltage drop, and the radiation resistance of the products is poor. The reason is that for bipolar transistors, instantaneous radiation energy can generate electron-hole pairs in the silicon dioxide passivation layer of the chip. Since the mobility of electrons in silicon dioxide is large, the electrons in the electron-hole pairs will be swept out of the oxide layer within a few picoseconds, and the holes that are not recombined will make a step-by-step movement in the oxide layer in the form of localized states towards the interface. When the holes move near the interface, some of them will be trapped by the traps at the interface, forming positively charged oxide trap charges, causing redistribution of the impurity concentration in the silicon substrate, and reducing the carrier lifetime, thereby causing phenomena such as decreased current gain, increased reverse leakage current, increased saturation voltage drop, and significantly decreased radiation resistance of the transistor. This trend will be more obvious as the thickness of the oxide layer increases. Therefore, in order to ensure improving the radiation resistance of power transistors and having an ideal match between subsequent product processes, a more ideal method is to control the thermal oxidation thickness of the silicon wafer within the range of the oxide layer thickness . However, since the silicon wafer is thermally oxidized to form an oxide layer by a dry + wet + dry process, and the oxidation temperature is about 1150 °C, the oxide layer thickness is very thick when using the traditional high-temperature diffusion process to form the base region and the emitter region. Generally, it reaches

[0003] In the actual process, since the density of the oxide layer is lower than the theoretical value, in order to ensure that the oxide layer does not penetrate during phosphorus diffusion, the thickness of the base region oxide layer of the NPN transistor usually takes a value of or more to ensure that the emitter region does not penetrate during the high-temperature emitter region diffusion of the chip. The reason is that

[0004] The thickness calculation of the base region oxide layer of the NPN transistor is as follows:

[0005] The diffusion of impurity atoms in silicon dioxide also approximately follows the complementary error distribution. According to the complementary error distribution function, it can be obtained that:

[0006] The diffusion junction depth of impurities in silicon dioxide

[0007] For the NPN transistor:

[0008] Pre-diffusion of the emitter region: Assume the pre-diffusion temperature of the emitter region is 1080 °C and the time is 60 min = 3600 s. The diffusion coefficient in silicon dioxide at 1080 °C is The junction depth can be calculated as

[0009] Main diffusion of the emitter region: Assume the main diffusion temperature is 1050 °C and the time is 10 min + 60 min + 10 min + 120 min = 200 min = 12000 s. The diffusion coefficient in silicon dioxide at 1050 °C is The junction depth can be calculated as

[0010] The total phosphorus diffusion junction depth

[0011] If the oxide layer is artificially controlled within the range, the phenomenon of base region and emitter region punch-through will occur, and it is impossible to produce qualified power transistor parameters. Existing problems: 1) The thin oxide layer cannot effectively mask the diffusion movement of phosphorus atoms, resulting in phosphorus doping in the entire chip base region during the emitter region doping process, leading to parameter deterioration and even complete punch-through; 2) After depositing silicon nitride on the thin oxide layer, during the subsequent phosphorus pre-diffusion, due to the large difference in the expansion coefficients of silicon nitride and the oxide layer, all the passivation layers on the chip surface crack and the parameters are completely punched through. Therefore, it is not feasible to control the oxide layer within the range when using the traditional process to produce power transistor radiation-resistant products.

[0012] Considering that the base region oxide layer is processed by dry + wet + dry process and the compactness of the oxide layer is lower than the theoretical value, in order to ensure that there is no oxide layer punch-through during phosphorus diffusion, the thickness of the base region oxide layer for NPN transistors usually takes a value of or more to ensure that there is no emitter region punch-through phenomenon when the chip undergoes high-temperature emitter diffusion. Therefore, an ideal method to ensure the radiation resistance of power transistors is to control the thermal oxidation thickness of the silicon wafer within the oxide layer thickness range and use ion implantation process technology for base region and emitter region implantation to form the base and emitter, which is an effective method. However, the use and maintenance costs of ion implantation equipment are very high. According to the general design requirements of NPN transistors, the general implantation dose in the base region of the device is between 5e14 and 2e15 (the base region square is in ), and to ensure sufficient emitter efficiency in the emitter region, a larger doping concentration is required in the emitter region. Therefore, the implantation dose in the emitter region needs to reach about 3e16 or more (emitter region surface square: )。If a medium beam current ion implanter is used, the beam current is small, and long-term implantation will cause the scanning mechanism of the machine to overheat and lead to equipment failure. Therefore, the single-dose phosphorus implantation is limited to 5e14, and it takes about 1.5 minutes to scan once. If the dose implantation is above 3E16, the single-chip duration will exceed 90 minutes, which is too long for the process time and the equipment operation risk is relatively high. If a large beam current ion implanter is used, the equipment cost, material cost, usage cost and maintenance cost will increase significantly.

[0013] In view of this, the present invention is specifically proposed. Summary of the Invention

[0014] The object of the present invention is to solve the problem that in the prior art, it is necessary to adopt the medium beam current ion implantation process or the large beam current ion implantation process to manufacture an anti-radiation power transistor, and the cost remains high.

[0015] The technical concept adopted by the present invention is: cancel the medium beam current ion implantation process or the large beam current ion implantation process, and improve the process structure of the traditional power transistor (such as Figure 1 , Figure 2 shown), first form a dense thin silicon oxide layer in the active region of the transistor, then form a highly dense anti-radiation barrier layer on the thin silicon oxide layer, and then form a low-density anti-radiation absorption layer on the anti-radiation barrier layer, that is, adopt a double-layer anti-radiation structure of high density - low density (such as Figure 3 , Figure 4 shown), greatly attenuate the radiation, greatly reduce the influence of the underlying silicon dioxide layer by radiation, and at the same time adopt a thin silicon dioxide layer with as thin a thickness as possible, so that the electron-hole pairs generated by the radiation are quickly swept out of the oxide layer, and no positively charged oxide trap charges can be formed at the oxide layer interface, greatly reducing the redistribution of the impurity concentration in the silicon substrate, greatly improving the carrier lifetime and current gain, reducing the reverse leakage current and saturation voltage drop, and significantly improving the anti-radiation ability of the transistor.

[0016] For this reason, the present invention provides a non-ion implantation anti-radiation power transistor, as Figure 3 shown. It includes: N + silicon substrate 1, deep base region 2, light base region 3, emitter region 4, deep boron ring 5, thick silicon dioxide layer 6, thin silicon dioxide layer 7, emitter metal electrode 8, base metal electrode 9, anti-radiation barrier layer 10, anti-radiation absorption layer 11, backside metallization layer 12.

[0017] In the N +On the upper surface of a silicon substrate 1, a heavily doped base region 2 with a set thickness is epitaxially grown. In the middle region of the heavily doped base region 2, a lightly doped base region 3 with a set thickness is diffused at a high temperature. In the middle region of the lightly doped base region 3, an emitter region 4 with a set thickness is diffused at a high temperature. A heavily doped boron ring 5 surrounding the lightly doped base region 3 is formed around the periphery of the lightly doped base region 3. A base lead hole is provided in the middle region of the surface of the heavily doped boron ring 5. An emitter lead hole is provided in the middle region of the surface of the emitter region 4. A thick silicon dioxide layer 6 is provided on the surface of the peripheral region of the base lead hole. A thin silicon dioxide layer 7 is provided on the surface of the region between the base lead hole and the emitter lead hole. An emitter metal electrode 8 and a base metal electrode 9 are respectively provided on the emitter lead hole and the base lead hole, forming an emitter external lead bonding region and a base region external lead bonding region respectively. An anti-irradiation blocking layer 10 is provided on the thick silicon dioxide layer 6 and the thin silicon dioxide layer 7. An anti-irradiation absorption layer 11 is provided on the anti-irradiation blocking layer 10, N + A backside metallization layer 12 is provided on the bottom surface of the silicon substrate 1.

[0018] The doping of the heavily doped base region and the lightly doped base region is boron, and the doping of the emitter region is phosphorus; the heavily doped boron ring straddles the boundary line between the heavily doped base region and the lightly doped base region, and the depth of the heavily doped boron ring is greater than the thickness of the lightly doped base region.

[0019] The emitter metal electrode 8 is the emitter E of the power transistor, the base metal electrode 9 is the base B of the power transistor, and the backside metallization layer 12 is the collector C of the power transistor. When the power transistor is placed in an irradiation environment, a part of the irradiation is first absorbed by the low-density anti-irradiation absorption layer 11, and the irradiation that is not absorbed and penetrates the anti-irradiation absorption layer 11 is then reflected and blocked by the dense anti-irradiation blocking layer 10, thereby greatly reducing the influence of the irradiation on the thin silicon dioxide layer 7 in the active region of the power transistor and realizing the anti-irradiation function of the power transistor.

[0020] Furthermore, as Figure 5 shown, an anti-irradiation reinforcement layer 13 is provided on the upper surface of the anti-irradiation absorption layer 11, which first reflects and absorbs a large amount of irradiation, thereby further greatly improving the anti-irradiation ability of the power transistor.

[0021] The preparation method of the non-ion-implanted anti-irradiation power transistor is as Figure 4 shown. It includes the following steps:

[0022] (1) Oxidize the silicon wafer to grow a thick silicon dioxide layer with a thickness value of or more;

[0023] (2) Photolithograph the heavily doped base region;

[0024] (3) Diffuse the heavily doped boron;

[0025] (4) Photolithograph the lightly doped base region;

[0026] (5) Diffuse the lightly doped boron;

[0027] (6) Photolithography of the emitter region;

[0028] (7) Phosphorus diffusion in the emitter region;

[0029] (8) Photolithography of the active region;

[0030] (9) Grow a thin silicon dioxide layer with a thickness value

[0031] (10) Grow an anti - radiation barrier layer with a thickness value of

[0032] (11) Photolithography of the via hole;

[0033] (12) Grow a metal thin film;

[0034] (13) Photolithography of the metal lead;

[0035] (14) Alloying;

[0036] (15) Grow an anti - radiation absorption layer with a thickness value of

[0037] (16) Photolithography of the bonding region;

[0038] (17) Back - side thinning;

[0039] (18) Back - side metallization.

[0040] The beneficial effects of the present invention are as follows:

[0041] By analyzing the influence of each process method in the production of power transistors on the irradiation performance and product parameters of the transistors, after etching off the oxide layer with a thickness of or more generated on the active region during the production process of power transistors by photolithography, a thin oxide layer with a thickness value of and an anti - radiation barrier layer with thickness values of respectively and an anti - radiation absorption layer with a thickness value of are formed on the active region, which can inhibit the accumulation of charges in the passivation layer on the base region and the recombination current generated on the surface of the base region, reduce the current gain h FE degradation degree caused by radiation, and can also effectively control the generation of electron - hole pairs in the oxide layer, reduce the capture of positive charges by silicon dioxide, thereby reducing the oxide trap charges at the interface after transient radiation, and reducing the influence of radiation effects on the forward current gain, reverse leakage current and saturation voltage drop, greatly reducing the influence of irradiation on the performance of power transistors (bipolar transistors), and thus greatly improving the anti - radiation ability of power transistors.

[0042] The technical solution described in the present invention can be widely applied to the anti - radiation fields of semiconductor transistors and semiconductor integrated circuits. Description of the Drawings

[0043] Figure 1 It is a schematic diagram of the original transistor structure.

[0044] Figure 2 It is a schematic diagram of the preparation process of the original transistor.

[0045] Figure 3 It is a schematic diagram of the structure of the double-layer radiation-resistant transistor of the present invention.

[0046] Figure 4 It is a schematic diagram of the preparation process of the transistor of the present invention.

[0047] Figure 5 It is a schematic diagram of the structure of the triple-layer radiation-resistant transistor of the present invention.

[0048] In the drawings: 1 is N + silicon substrate, 2 is the thick base region, 3 is the light base region, 4 is the emitter region, 5 is the thick boron ring, 6 is the thick silicon dioxide, 7 is the thin silicon dioxide, 8 is the emitter metal electrode, 9 is the base metal electrode, 10 is the radiation-resistant barrier layer, 11 is the radiation-resistant absorption layer, 12 is the back metallization layer, and 13 is the radiation-resistant reinforcement layer. Detailed Embodiments

[0049] Combined with Figures 3 - 5 , the detailed embodiments of the present invention are as follows:

[0050] I. Radiation-resistant method of thin silicon dioxide layer + double-layer hetero silicon nitride (high-density silicon nitride + low-density silicon nitride)

[0051] First, a dense thin silicon dioxide layer is formed in the active region of the transistor, then a high-density silicon nitride barrier layer is formed on the thin silicon dioxide layer, and then a low-density silicon nitride absorption layer is formed on the silicon nitride barrier layer, that is, a double-layer silicon nitride structure of high density - low density is adopted to reduce the radiation to the minimum extent, so that the influence of the underlying silicon dioxide layer by radiation reaches the minimum extent. At the same time, a thin silicon dioxide layer with as thin a thickness as possible is adopted, so that the electron-hole pairs generated by radiation are quickly swept out of the oxide layer, and no positively charged oxide trap charges can be formed at the oxide layer interface, greatly reducing the redistribution of impurity concentration in the silicon substrate, greatly improving the carrier lifetime and current gain, reducing the reverse leakage current and saturation voltage drop, and significantly improving the radiation-resistant ability of the transistor.

[0052] Etch off the oxide layer with a thickness value of or more generated in the active region during the production process of the power transistor by photolithography, and then adopt a dry oxygen method of low-temperature oxidation (1000°C - 1050°C, time: 30 min) or deposit silicon dioxide in the active region to grow a thin oxide layer with a thickness value of and a thickness value of Silicon nitride at (650°C - 750°C, time: 30 min - 40 min), the surface of the E - B junction between the base region and the emitter region is A thin oxide layer. After the silicon nitride is fabricated, there is no high - temperature process, so there is no problem of thermal matching. The process adopts a double - layer heterostructure of LPCVD high - temperature (650°C - 750°C) and PECVD low - temperature (400°C) silicon nitride. By using the structure of thin oxide layer + double - layer heterostructure of silicon nitride, the generation of electron - hole pairs in the oxide layer can be effectively controlled, the capture of positive charges by silicon dioxide can be reduced, thereby reducing the oxide trap charges at the interface after transient radiation, and reducing the influence of radiation effects on the convection gain, reverse leakage current and saturation voltage drop, and improving the radiation resistance of the power transistor.

[0053] The specific implementation key points are as follows:

[0054] 1. Thick silicon oxide layer growth process

[0055] Adopt the oxidation process of dry oxygen + wet oxygen + dry oxygen. In a high - temperature furnace at about 1180°C, carry out the thermal oxidation on the silicon wafer in the time sequence of 10 min + 60 min + 10 min, and a thick silicon oxide layer with the thickness of can be obtained.

[0056] 2. Thin silicon oxide layer growth process

[0057] Adopt the dry - oxygen oxidation process. In a high - temperature furnace at 1000°C - 1050°C, carry out thermal oxidation on the surface of the active region of the silicon wafer for 35 min, and a thin silicon oxide layer with the thickness of can be obtained.

[0058] 3. High - density silicon nitride layer growth process

[0059] Adopt the high - temperature low - pressure chemical vapor deposition (LPCVD) process. In an LPCVD furnace at 650°C - 750°C, under low - pressure conditions, introduce SiH 2 Cl 2 +NH 3 mixed process gas for 30 min - 40 min, and a high - density silicon nitride (Si N 3 N 4 ) anti - radiation barrier layer with the thickness of can be obtained.

[0060] 4. Low - density silicon nitride layer growth process

[0061] Adopt the low - temperature plasma chemical vapor deposition (PECVD) process. In a PECVD furnace at 350°C - 400°C, under vacuum conditions, introduce SiH 4 +NH 3 mixed process gas for 3 min - 4 min, and a layer with the thickness of can be obtained Low-density silicon nitride (Si 3 N 4 ) anti-irradiation absorption layer.

[0062] 5. The metal electrode is an aluminum metal film electrode.

[0063] 6. The backside metallization electrode is a gold electrode or a multi-layer composite metal film electrode.

[0064] II. Anti-irradiation method of thin silicon oxide layer + double-layer hetero-silicon nitride (high-density silicon nitride + low-density silicon nitride) + polyimide, as Figure 5 shown.

[0065] On the surface of the low-density silicon nitride layer, a polyimide anti-irradiation reinforcement layer with a thickness is formed by spin coating, curing, and etching processes.

[0066] The polyimide is high-purity polyimide or a mixed polyimide added with irradiation absorption substances.

[0067] Finally, it should be noted that the above embodiments are merely examples given for clear illustration. The present invention includes but is not limited to the above embodiments, and it is not necessary and impossible to enumerate all implementation manners here. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. All implementation manners that meet the requirements of the present invention fall within the protection scope of the present invention.

Claims

1. A non-ion-implanted radiation-resistant power transistor, characterized in that, comprising: N + Silicon substrate, thick base region, thin base region, emitter region, thick boron ring, thick silicon dioxide layer, thin silicon dioxide layer, emitter metal electrode, base metal electrode, anti-irradiation barrier layer, anti-irradiation absorption layer, backside metallization layer; On the upper surface of the N+ silicon substrate, a thick base region with a set thickness is epitaxially grown. In the middle region of the thick base region, a light base region with a set thickness is formed by high-temperature diffusion. In the middle region of the light base region, an emitter region with a set thickness is formed by high-temperature diffusion. A thick boron ring surrounding the light base region is provided around the light base region. A base lead hole is provided in the middle region of the surface of the thick boron ring. An emitter lead hole is provided in the middle region of the surface of the emitter region. A thick silicon dioxide layer is provided on the surface of the peripheral region of the base lead hole. A thin silicon dioxide layer is provided on the surface of the region between the base lead hole and the emitter lead hole. An emitter metal electrode and a base metal electrode are respectively provided on the emitter lead hole and the base lead hole, forming an emitter external lead bonding region and a base external lead bonding region respectively. An anti-radiation blocking layer is provided on the thick silicon dioxide layer and the thin silicon dioxide layer. An anti-radiation absorption layer is provided on the anti-radiation blocking layer, N + A backside metallization layer is provided on the bottom surface of the silicon substrate; The thickness value of the thick silicon dioxide layer is above 7000 Å; The thickness value of the thin silicon dioxide layer is 1000 Å - 2000 Å; The thickness value of the radiation-resistant barrier layer is 2000 Å - 2500 Å; The thickness value of the radiation-resistant absorption layer is 4000 Å - 5000 Å.

2. A non-ion-implanted radiation-resistant power transistor according to claim 1, characterized in that, The doping of the thick base region and the light base region is boron, and the doping of the emitter region is phosphorus; the thick boron ring straddles the boundary line between the thick base region and the light base region, and the depth of the thick boron ring is greater than the thickness of the light base region.

3. A non-ion-implanted radiation-resistant power transistor according to claim 1, characterized in that, The emitter metal electrode and the base metal electrode are aluminum metal film electrodes; the back metallization layer is a gold electrode or a multi-layer composite metal film electrode.

4. A non-ion-implanted radiation-resistant power transistor according to claim 1, characterized in that, The thin silicon dioxide layer is a highly dense silicon dioxide layer with a thickness value of 1000 Å - 2000 Å; the radiation-resistant barrier layer is highly dense silicon nitride with a thickness of 2000 Å - 2500 Å; the radiation-resistant absorption layer is low-dense silicon nitride with a thickness of 4000 Å - 5000 Å.

5. A non-ion-implanted radiation-resistant power transistor according to claim 1, characterized in that, It further includes a radiation-resistant reinforcement layer, and the radiation-resistant reinforcement layer is located on the upper surface of the radiation-resistant absorption layer; the thickness of the radiation-resistant reinforcement layer is 8000 Å - 12000 Å; the radiation-resistant reinforcement layer is high-purity polyimide or a mixed polyimide added with radiation-absorbing substances.

6. A preparation method of a non-ion-implanted radiation-resistant power transistor according to claim 1, characterized in that, comprising the following steps: (1) Oxidize the silicon wafer to grow a thick silicon dioxide layer with a thickness value above 7000 Å; (2) Photolithograph the thick base region; (3) Diffuse thick boron; (4) Photolithograph the light base region; (5) Diffuse light boron; (6) Photolithograph the emitter region; (7) Diffuse phosphorus in the emitter region; (8) Photolithograph the active region; (9) Grow a thin silicon dioxide layer with a thickness value of 1000 Å - 2000 Å; (10) Grow a radiation-resistant barrier layer with a thickness value of 2000 Å - 2500 Å; (11) Photolithograph the lead holes; (12) Grow a metal thin film; (13) Photolithograph the metal leads; (14) Alloy; (15) Grow a radiation-resistant absorption layer with a thickness value of 4000 Å - 5000 Å; (16) Photolithograph the bonding region; (17) Thinning the back surface; (18) Back surface metallization.

7. A preparation method of a non-ion-implanted radiation-resistant power transistor according to claim 6, characterized in that, The growth process of the thick silicon dioxide layer is: Adopt a dry oxygen + wet oxygen + dry oxygen oxidation process, in a high-temperature furnace at about 1180 °C, in the time sequence of 10 min + 60 min + 10 min, perform thermal oxidation on the silicon wafer, and a thick silicon dioxide layer with an oxidation layer thickness of 7000 Å - 10000 Å can be obtained.

8. The manufacturing method of a non-ion-implanted radiation-hardened power transistor as claimed in claim 6, characterized in that, the growth process of the thin silicon dioxide layer is as follows: Adopt dry oxidation process, in a high-temperature furnace at 1000°C - 1050°C, perform thermal oxidation on the surface of the active region of the silicon wafer for 35 minutes, and a thin silicon dioxide layer with an oxide layer thickness of 1000 Å - 2000 Å can be obtained.

9. The manufacturing method of a non-ion-implanted radiation-hardened power transistor as claimed in claim 6, characterized in that, the radiation-hardened barrier layer is high-density silicon nitride, and the growth process of the high-density silicon nitride layer is: Using the low-pressure chemical vapor deposition (LPCVD) process at high temperature, in an LPCVD furnace at 650°C - 750°C, under low-pressure conditions, SiH 2 Cl 2 + NH 3 The mixed process gas is introduced for 30 min - 40 min to obtain a highly dense silicon nitride anti-irradiation barrier layer with a thickness of 2000 Å - 2500 Å.

10. The manufacturing method of a non-ion-implanted radiation-hardened power transistor as claimed in claim 6, characterized in that, the radiation-hardened absorption layer is low-density silicon nitride, and the growth process of the low-density silicon nitride layer is: Using the low-temperature plasma chemical vapor deposition PECVD process, in a PECVD furnace at 350°C - 400°C, under vacuum conditions, SiH 4 + NH 3 The mixed process gas is introduced for 3 min - 4 min to obtain a low-density silicon nitride anti-irradiation absorption layer with a thickness of 4000 Å - 5000 Å.

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