Semiconductor device

Abstract

A semiconductor device can include a first electrode; a second electrode; and a multilayer stack interposed between the first electrode and the second electrode and including a seed layer and a high-k dielectric layer, wherein the seed layer and the high-k dielectric layer can each have a rock-salt crystal structure, and wherein the high-k dielectric layer can exhibit a dielectric constant (k) of fifty (50) or higher.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0078253, filed on June 26, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Exemplary embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a multi-layer stack including a dielectric layer. BACKGROUND

[0004] Recently, semiconductor memory devices have been highly integrated, so that a semiconductor memory unit cell area is reduced and an operating voltage is lowered. Accordingly, a high-k material having a high capacitance and a low leakage current is required. However, since a dielectric constant (k) and a band gap of a dielectric material tend to be inversely proportional to each other, there is a limitation in actually applying a high-k material to a device. SUMMARY

[0005] Embodiments of the present disclosure are directed to a semiconductor device including a multi-layer stack including a high-k dielectric layer having a high dielectric constant.

[0006] According to one embodiment of the present disclosure, a semiconductor device can include a first electrode; a second electrode; and a multi-layer stack interposed between the first electrode and the second electrode and including a seed layer and a high-k dielectric layer, wherein the seed layer and the high-k dielectric layer each can have a rock-salt crystal structure, and wherein the high-k dielectric layer can exhibit a dielectric constant (k) of fifty (50) or more.

[0007] According to another embodiment of the present disclosure, a semiconductor device can include a first electrode; a second electrode; and a multi-layer stack interposed between the first electrode and the second electrode and including a seed layer and a high-k dielectric layer structure, wherein the high-k dielectric layer structure can include at least two high-k dielectric layers and at least one strain applying layer, and wherein the strain applying layer can be interposed between adjacent high-k dielectric layers. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A semiconductor device according to embodiments of the present disclosure is illustrated.

[0009] Figures 2 to 22 A semiconductor device according to other embodiments of the present disclosure is illustrated.

[0010] Figures 23A to 23C is a view illustrating a memory cell.

[0011] Figure 24 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the disclosure. DETAILED DESCRIPTION

[0012] Exemplary embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms, and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the present disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments of the present disclosure.

[0013] The drawings are not necessarily to scale and, in some instances, proportional dimensions have been exaggerated to illustrate features clearly. When a first layer is referred to as being "on" or "under" a second layer or a substrate, it not only refers to the case where the first layer is directly formed on the second layer or the substrate, but also refers to the case where a third layer is present between the first layer and the second layer or the substrate.

[0014] In the background of requiring a material having a high dielectric constant and a high energy band gap to scale down a device and improve characteristics, it has been reported that beryllium oxide (BeO) having a rock-salt crystal structure can have a high dielectric constant and a high energy band gap. However, BeO has a rock-salt crystal structure that is an unstable phase under ambient conditions, i.e., at room temperature and atmospheric pressure, and thus BeO having a rock-salt crystal structure can exhibit a high dielectric constant only under high pressure conditions of 100 gigapascal (GPa) or more. Thus, there is a practical problem in applying BeO having a rock-salt crystal structure to a device.

[0015] Recently, it has been reported that a stable beryllium-magnesium oxide (Be x Mg 1-x O) structure can be formed by doping magnesium oxide (MgO) into BeO. MgO has a stable rock-salt crystal structure under ambient conditions and has structural compatibility with BeO. However, since the k value of the doped MgO is as low as about 9.8, the dielectric constant of the Be x Mg 1-x O structure is about 15 to about 20. Thus, it is not possible to achieve a high k, i.e., a high dielectric constant of 50 or more.

[0016] According to embodiments of the present disclosure, a higher-k dielectric layer oriented to a rock-salt crystal structure can be formed by using a seed layer having a rock-salt crystal structure. Thus, a high-k dielectric layer having a dielectric constant of 50 or more, which is not possible with a single layer of Be x Mg 1-x O, can be implemented. Thus, it is possible to further scale down a memory device while securing sufficient operating characteristics.

[0017] As used herein, the term “ambient conditions” can mean room temperature and pressure conditions that are not artificially regulated, and can be used interchangeably with “room temperature and atmospheric pressure conditions.”

[0018] As used herein, the term “room temperature” can mean a natural temperature that is not artificially heated or cooled, and can include, for example, a temperature of about 15°C to about 35°C or a temperature of about 18°C to about 30°C.

[0019] As used herein, the term “atmospheric pressure” can mean a natural pressure that is not artificially pressurized or depressurized, and can include, for example, a pressure of about 0.5 atm to about 1.5 atm or a pressure of about 0.8 atm to about 1.2 atm.

[0020] As used herein, a “rock salt” structure can represent a crystal structure in which the coordination number of each atom is 6 and the cation-anion radius ratio can be in the range of about 0.414 to 0.732. Each cation is coordinated with 6 anions at the vertices of an octahedron, and similarly, each anion is coordinated with 6 cations at the vertices of an octahedron.

[0021] Figure 1 A semiconductor device 100 according to an embodiment of the disclosure is shown.

[0022] Reference is made to Figure 1 The semiconductor device 100 can be part of a memory. The semiconductor device 100 can be part of a volatile memory. The semiconductor device 100 can be part of a DRAM. The semiconductor device 100 can include a DRAM capacitor.

[0023] The semiconductor device 100 can include a first electrode 101, a second electrode 102, and a multi-layer stack between the first electrode 101 and the second electrode 102.

[0024] The first electrode 101 can include a metal-containing material. The first electrode 101 can include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The first electrode 101 can include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), niobium nitride (NbN), molybdenum nitride (MoN), or a combination thereof. According to another embodiment of the disclosure, the first electrode 101 can include a silicon-containing material. For example, the first electrode 101 can include silicon, germanium silicon, or a combination thereof. According to still another embodiment of the disclosure, the first electrode 101 can include a stack of a metal-containing material and a silicon-containing material. The first electrode 101 can be referred to as a ‘bottom electrode’ or a storage node.

[0025] The second electrode 102 can include a silicon-containing material, a germanium- containing material, a metal-containing material, or a combination thereof. The second electrode 102 can include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The second electrode 102 can include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO2), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. The second electrode 102 can include a "Si / SiGe stack" in which silicon is layered on top of silicon germanium. The second electrode 102 can include a "Ge / SiGe stack" in which germanium is layered on top of silicon germanium. The second electrode 102 can be formed by layering silicon germanium on top of a metal nitride. For example, the second electrode 102 can be formed by layering silicon germanium (SiGe) on top of titanium nitride (TiN). According to another embodiment of the disclosure, the second electrode 102 can include titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W), layered in that order. According to another embodiment of the disclosure, the second electrode 102 can include titanium nitride (TiN), silicon germanium (SiGe), and tungsten nitride (WN), layered in that order.

[0026] The multi-layer stack can include a seed layer 110 and a high-k dielectric layer 120. The seed layer 110 can include a first seed layer 111 and a second seed layer 112. The first seed layer 111, the second seed layer 112, and the high-k dielectric layer 120 can be layered in that order between the first electrode 101 and the second electrode 102.

[0027] The seed layer 110 can be formed between the first electrode 101 and the high-k dielectric layer 120. The seed layer 110 can have a rock salt crystal structure, such that the high-k dielectric layer 120 formed over the seed layer 110 is oriented in a rock salt crystal structure. The seed layer 110 can have a dielectric constant of about 15 to about 20. The seed layer 110 can enable the high-k dielectric layer 120 having a high dielectric constant of about 50 or more to grow on the seed layer 110.

[0028] The first seed layer 111 can include MgO having a rock salt crystal structure, and the second seed layer 112 can include BeO having a rock salt crystal structure. The first seed layer 111 and the second seed layer 112 can each have a dielectric constant of about 15 to about 20.

[0029] MgO has a rock salt crystal structure under ambient conditions and has the same number of ions as BeO. Therefore, MgO has structural compatibility with BeO. By forming the seed layer 110 to include a first seed layer 111 having a rock salt crystal structure and a second seed layer 112 having a rock salt crystal structure, the high-k dielectric layer 120 can be oriented to a rock salt crystal structure by subsequent epitaxial growth, and the rock salt crystal structure of the high-k dielectric layer 120 can be stabilized under ambient conditions (i.e., at room temperature and atmospheric pressure).

[0030] The first seed layer 111 and the second seed layer 112 have a similar lattice constant to the high-k dielectric layer 120, and thus the high-k dielectric layer 120 can be oriented to a rock salt crystal structure. Therefore, the high-k dielectric layer 120 can have a rock salt crystal structure that is a stable phase under ambient conditions (i.e., at room temperature and atmospheric pressure).

[0031] The high-k dielectric layer 120 can include a high-k material. The high-k material can have a high dielectric constant of about 50 or more. The high-k material can include BeO having a stable rock salt crystal structure under ambient conditions (i.e., at room temperature and atmospheric pressure). The high-k material can include BeO having a rock salt crystal structure and a high dielectric constant of about 50 or more.

[0032] According to the embodiments disclosed herein, by performing epitaxial growth of a high-k material using the first seed layer 111 and the second seed layer 112 having a similar lattice constant to the high-k dielectric layer 120, the high-k dielectric layer 120 having a high dielectric constant and oriented to a rock salt crystal structure can be formed over the second seed layer 112. In this way, by using the seed layer 110 having a rock salt crystal structure and a similar lattice constant to the high-k dielectric layer 120, BeO having a rock salt crystal structure that is a stable phase under ambient conditions (i.e., at room temperature and atmospheric pressure) can be formed. As a result, BeO having a rock salt crystal structure can be practically applied to devices.

[0033] In one embodiment, the high-k dielectric layer 120 can exhibit a high dielectric constant, for example, a high dielectric constant of about 50 or more. Such a high dielectric constant is a relatively high dielectric constant that cannot be implemented in a single layer of BeO. x Mg 1-x O. Therefore, according to the embodiments disclosed herein, further scaling and performance improvement of memory devices can be achieved.

[0034] Further, in the semiconductor device 100, the high-k dielectric layer 120 can need to have a certain thickness or more to exhibit sufficient characteristics including a high dielectric constant and a high band gap energy. However, during the epitaxial growth of BeO having a rock-salt crystal structure, the effect of applying strain decreases as the thickness increases and grows. Accordingly, the structure of BeO tends to become a wurtzite structure having a low dielectric constant, rather than a rock-salt crystal structure, making a thicker BeO layer disadvantageous for the stability of the rock-salt crystal structure. BeO having a wurtzite structure with a dielectric constant of about 7.2 or less is difficult to use as a high-k material having a dielectric constant of 50 or more.

[0035] Accordingly, in forming the high-k dielectric layer 120, it can be necessary to prevent the formation of a wurtzite structure having a low dielectric constant while ensuring a sufficient thickness, and to stabilize and maintain a rock-salt crystal structure having a high dielectric constant. To this end, a method of growing at least two high-k dielectric layers ex situ, and a method of inserting a strain applying layer between at least two high-k dielectric layers can be considered in order to overcome the decrease in the effect of applying strain due to the increase in the thickness of the high-k dielectric layer 120. Reference will be made to Figure 2 and Figures 4 to 8 for a detailed description thereof.

[0036] Figure 2 A semiconductor device according to another embodiment of the disclosure is illustrated. The constituent elements of the semiconductor device 200 can be the same as those of the semiconductor device 100 illustrated Figure 1 in the following description of the first electrode 101, the second electrode 102, the first seed layer 111, and the second seed layer 112, reference will be made to Figure 1 and the description thereof. The semiconductor device 200 can be a part of a memory. The semiconductor device 200 can be a part of a volatile memory. The semiconductor device 200 can be a part of a DRAM. The semiconductor device 200 can include a DRAM capacitor.

[0037] Reference will be made to Figure 2 , the semiconductor device 200 can include the first electrode 101, the second electrode 102, and a multi-layer stack layer interposed between the first electrode 101 and the second electrode 102.

[0038] The multi-layer stack layer can include the seed layer 110 and the high-k dielectric layer 220 disposed above the seed layer 110.

[0039] The high-k dielectric layer 220 can include a first high-k dielectric layer 221 and a second high-k dielectric layer 222.

[0040] Both the first high-k dielectric layer 221 and the second high-k dielectric layer 222 may include a high-k material. The high-k material may have a high dielectric constant of about 50 or higher. The high-k material may include BeO, which has a stable rock salt crystal structure under environmental conditions (i.e., at room temperature and atmospheric pressure). The high-k material may include BeO with a rock salt crystal structure and a high dielectric constant of about 50 or higher.

[0041] A first high-k dielectric layer 221 and a second high-k dielectric layer 222 can be formed using a seed layer 110 through multi-epitaxial growth. For example, the first high-k dielectric layer 221 and the second high-k dielectric layer 222 can be formed by forming the first high-k dielectric layer 221 on a second seed layer 112 and then forming the second high-k dielectric layer 222 on the first high-k dielectric layer 221. The first high-k dielectric layer 221 can be formed by performing epitaxial growth of a high-k material with a rock-salt crystal structure using a first seed layer 111 and a second seed layer 112 that have similar lattice constants to the first high-k dielectric layer 221 and the second high-k dielectric layer 222. The second high-k dielectric layer 222 can be formed by performing epitaxial growth of a high-k material with a rock-salt crystal structure using a first seed layer 111 and a second seed layer 112. The first seed layer 111 and the second seed layer 112 have lattice constants similar to those of the first high-k dielectric layer 221 and the second high-k dielectric layer 222.

[0042] and Figure 1 Compared to the semiconductor device 100 shown, the difference in semiconductor device 200 is that the high-k dielectric layer 220 includes a first high-k dielectric layer 221 and a second high-k dielectric layer 222 formed in two steps.

[0043] In this embodiment, a high-k dielectric layer 220, comprising a first high-k dielectric layer 221 and a second high-k dielectric layer 222, is formed through a two-step epitaxial growth process. This prevents the formation of a massive wurtzite structure with a low dielectric constant due to the reduced effect of applied strain as the overall growth thickness of the high-k dielectric layer 220 increases. Therefore, the high-k dielectric layer 220 can maintain the rock salt crystal structure as a stable phase under environmental conditions (i.e., at room temperature and atmospheric pressure). Therefore, compared with... Figure 1 Compared to the thickness of the monolayer high-k dielectric layer 120 in the semiconductor device 100 shown, the increased thickness of the high-k dielectric layer 220 ensures sufficient characteristics of the high-k dielectric layer 220. Simultaneously, it prevents instability in the rock salt crystal structure of the high-k dielectric layer 220 due to increased growth thickness, and allows for the stable formation of a high-k dielectric layer 220 with a high dielectric constant of 50 or higher and a rock salt crystal structure.

[0044] According to Figure 2 the embodiment shown, the semiconductor device 200 includes a first high-k dielectric layer 221 and a second high-k dielectric layer 222. According to another embodiment, a high-k dielectric layer including three or more layers may be formed.

[0045] Figure 3 A semiconductor device according to another embodiment of the present disclosure is shown. Except for the seed layer 210, Figure 3 the constituent elements of the semiconductor device 201 shown in Figure 1 may be the same as those of the semiconductor device 100 shown in Figure 1 and its description. Hereinafter, the description of the first electrode 101, the second electrode 102, and the high-k dielectric layer 120 will refer to

[0046] Reference Figure 3 , the semiconductor device 201 may include a first electrode 101, a second electrode 102, and a multi-layer stack interposed between the first electrode 101 and the second electrode 102. <00,00147>The multi-layer stack may include a seed layer 210 and a high-k dielectric layer 120 provided above the seed layer 210.

[0048] The seed layer 210 may include Be x Mg 1-x O (0 < x < 0.5) having a rock salt crystal structure. The seed layer 210 may have a dielectric constant of about 15 to about 20.

[0049] Be x Mg 1-x O having a rock salt crystal structure may be formed by doping MgO into BeO. MgO has a rock salt crystal structure under ambient conditions and has structural compatibility with BeO, and BeO and MgO have the same number of ions. Considering process conditions, etc., a method of doping MgO may be appropriately selected from methods known in the art. For example, BeO may be doped with MgO via atomic layer deposition (ALD) by co-deposition.

[0050] Different from BeO having a rock salt crystal structure that is in an unstable phase under ambient conditions, Be x Mg 1-x O having a rock salt crystal structure can maintain a stable state under ambient conditions (i.e., at room temperature and atmospheric pressure). Be x Mg1-x O can have a dielectric constant of about 15 to 20.

[0051] including BeO having a rock salt crystal structure x Mg 1-x The seed layer 210 of O has a similar lattice constant to the high-k dielectric layer 120, and thus, as a result, the high-k material, such as BeO, can be oriented to a rock salt crystal structure by epitaxial growth. Thus, the high-k dielectric layer 120 having a dielectric constant of 50 or more at ambient conditions (i.e., at room temperature and atmospheric pressure) can be stably formed.

[0052] Figure 4 A semiconductor device according to another embodiment of the disclosure is shown. The constituent elements of the semiconductor device 202 can be the same as those of the semiconductor device 201 shown in Figure 3 , except for the high-k dielectric layer 220. Hereinafter, the description regarding the first electrode 101, the second electrode 102, and the seed layer 210 will be made with reference to Figure 3 and the description thereof. The semiconductor device 202 can be part of a memory. The semiconductor device 202 can be part of a volatile memory. The semiconductor device 202 can be part of a DRAM. The semiconductor device 202 can include a DRAM capacitor.

[0053] Referring to Figure 4 , the semiconductor device 202 can include the first electrode 101, the second electrode 102, and a multilayer stack layer interposed between the first electrode 101 and the second electrode 102.

[0054] The multilayer stack layer can include the seed layer 210 and the high-k dielectric layer 220 disposed over the seed layer 210.

[0055] The high-k dielectric layer 220 can include a first high-k dielectric layer 221 and a second high-k dielectric layer 222.

[0056] The first high-k dielectric layer 221 and the second high-k dielectric layer 222 can each include a high-k material. The high-k material can have a high dielectric constant of about 50 or more. The high-k material can include BeO having a stable rock salt crystal structure at ambient conditions (i.e., at room temperature and atmospheric pressure). The high-k material can include BeO having a rock salt crystal structure and a high dielectric constant of about 50 or more.

[0057] The first high-k dielectric layer 221 and the second high-k dielectric layer 222 can be formed by non-in-situ multiple epitaxial growth using the seed layer 210. For example, the first high-k dielectric layer 221 and the second high-k dielectric layer 222 can be formed by forming the first high-k dielectric layer 221 over the seed layer 210 and then forming the second high-k dielectric layer 222 over the first high-k dielectric layer 221. The first high-k dielectric layer 221 can be formed by performing epitaxial growth of a high-k material oriented to a rock-salt crystal structure using the seed layer 210 having a similar lattice constant to the first high-k dielectric layer 221 and the second high-k dielectric layer 222. The second high-k dielectric layer 222 can be formed by performing epitaxial growth of a high-k material oriented to a rock-salt crystal structure using the seed layer 210 having a similar lattice constant to the first high-k dielectric layer 221 and the second high-k dielectric layer 222. With Figure 3 The semiconductor device 202 is different from the semiconductor device 201 shown in FIG. 1 in that the high-k dielectric layer 220 includes the first high-k dielectric layer 221 and the second high-k dielectric layer 222 formed in two steps.

[0058] In this embodiment, the high-k dielectric layer 220 including the first high-k dielectric layer 221 and the second high-k dielectric layer 222 is formed by two-step epitaxial growth, which can prevent formation of a bulk wurtzite structure having a low dielectric constant due to a decrease in the effect of applying strain as the total growth thickness of the high-k dielectric layer 220 increases. Accordingly, the high-k dielectric layer 220 can maintain a rock-salt crystal structure as a stable phase under ambient conditions (i.e., at room temperature and atmospheric pressure). Thus, the high-k dielectric layer 220 can have a high dielectric constant. Figure 3 Compared to the thickness of the high-k dielectric layer 120 composed of a single layer in the semiconductor device 201 shown in FIG. 1, a sufficient property of the high-k dielectric layer 220 can be ensured as the thickness of the high-k dielectric layer 220 increases.

[0059] According to Figure 4 The semiconductor device 202 includes the first high-k dielectric layer 221 and the second high-k dielectric layer 222 according to the embodiment shown in FIG. 2. According to another embodiment, a high-k dielectric layer including three or more layers can be formed.

[0060] Figure 2 The semiconductor device 200 shown in FIG. 1 and Figure 4 The semiconductor device 202 shown in FIG. 2 includes the high-k dielectric layer 220 including at least two layers (i.e., the high-k dielectric layers 221 and 222) formed by non-in-situ multiple epitaxial growth in order to increase the total thickness of the high-k dielectric layer 220. Alternatively, a strain applying layer can be included in order to overcome a decrease in the effect of applying strain due to an increase in the thickness of the high-k dielectric layer. This will be described in detail with reference to Figures 5 to 8 FIG. 3.

[0061] Figure 5 A semiconductor device according to another embodiment of the disclosure is illustrated. Constituent elements of the semiconductor device 300 can be the same as those of the semiconductor device 100 illustrated except for the high-k dielectric layer structure 320. Figure 1 Hereinafter, with respect to the description of the first electrode 101, the second electrode 102, the first seed layer 111, and the second seed layer 112, reference will be made to the description of the semiconductor device 100 illustrated in FIG. 1. Figure 1 The semiconductor device 300 can be a part of a memory. The semiconductor device 300 can be a part of a volatile memory. The semiconductor device 300 can be a part of a DRAM. The semiconductor device 300 can include a DRAM capacitor.

[0062] Referring to FIG. 3, Figure 5 The semiconductor device 300 can include the first electrode 101, the second electrode 102, and a multi-layer stack interposed between the first electrode 101 and the second electrode 102.

[0063] The multi-layer stack can include the seed layer 110 and the high-k dielectric layer structure 320 disposed above the seed layer 110. The seed layer 110 can include the first seed layer 111 and the second seed layer 112. The high-k dielectric layer structure 320 can include the first high-k dielectric layer 321, the strain-imparting layer 323, and the second high-k dielectric layer 322. The first high-k dielectric layer 321, the strain-imparting layer 323, and the second high-k dielectric layer 322 can be formed in the order between the seed layer 110 and the second electrode 102.

[0064] The first high-k dielectric layer 321 and the second high-k dielectric layer 322 can each include a high-k material. The high-k material can have a high dielectric constant of about 50 or more. The high-k material can include BeO having a stable rock-salt crystal structure under ambient conditions (i.e., at room temperature and atmospheric pressure). The high-k material can include BeO having a rock-salt crystal structure and a high dielectric constant of about 50 or more.

[0065] The strain-imparting layer 323 can be interposed between the first high-k dielectric layer 321 and the second high-k dielectric layer 322.

[0066] The strain-imparting layer 323 can impart a strain to the first high-k dielectric layer 321 and the second high-k dielectric layer 322 to compensate for a decrease in a strain-imparting effect due to an increase in a total thickness of the high-k dielectric layer structure 320. Accordingly, a problem that occurs when the rock-salt crystal structure of the high-k dielectric layer structure 320 becomes unstable can be overcome.

[0067] The strain-imparting layer 323 can include MgO, Be x Mg 1-xO(0 < x < 0.5) or combinations thereof.

[0068] In this way, through the strain application layer 323 between the first high-k dielectric layer 321 and the second high-k dielectric layer 322, the first high-k dielectric layer 321 and the second high-k dielectric layer 322 can maintain the rock salt crystal structure as a stable phase under ambient conditions (i.e., at room temperature and atmospheric pressure). Therefore, both the first high-k dielectric layer 321 and the second high-k dielectric layer 322 can exhibit a high dielectric constant. At the same time, the overall thickness of the high-k dielectric layer structure 320 can be increased, so that the high-k dielectric layer structure 320 exhibits the characteristics of a sufficient high-k dielectric layer structure 320.

[0069] According to Figure 5 the illustrated embodiment, the semiconductor device 300 includes a strain application layer 323. According to another embodiment, two or more strain application layers can be formed. This will be described in detail with reference to Figure 6 this.

[0070] Figure 6 shows a semiconductor device according to another embodiment of the present disclosure. Except for the high-k dielectric layer structure 320′, the constituent elements of the semiconductor device 302 can be the same as those of the semiconductor device 100 shown in Figure 1 this. In the following, the descriptions of the first electrode 101, the second electrode 102, the first seed layer 111, and the second seed layer 112 will refer to Figure 1 this and its description. The semiconductor device 302 can be part of a memory. The semiconductor device 302 can be part of a volatile memory. The semiconductor device 302 can be part of a DRAM. The semiconductor device 302 can include a DRAM capacitor.

[0071] Referring to Figure 6 this, the semiconductor device 302 can include a first electrode 101, a second electrode 102, and a multi-layer stack between the first electrode 101 and the second electrode 102.

[0072] The multi-layer stack can include a seed layer 110 and a high-k dielectric layer structure 320′ disposed above the seed layer 110. The seed layer 110 can include a first seed layer 111 and a second seed layer 112.

[0073] The high-k dielectric layer structure 320′ may include at least two strain-applying layers 323′, and each strain-applying layer 323′ may be disposed between adjacent high-k dielectric layers 321′. For example, the high-k dielectric layer structure 320′ may include a stack of high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′. In another example, the high-k dielectric layer structure 320′ may include a stack of high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′ / strain-applying layer 323′ / high-k dielectric layer 321′.

[0074] Each high-k dielectric layer 321′ may include a high-k material. The high-k material may have a high dielectric constant of about 50 or higher. The high-k material may include BeO with a stable rock salt crystal structure under ambient conditions (i.e., at room temperature and atmospheric pressure). The high-k material may include BeO with a rock salt crystal structure and a high dielectric constant of about 50 or higher.

[0075] The thickness of each high-k dielectric layer 321′ can be the same or different from each other.

[0076] A strain-applying layer 323' can be disposed between two adjacent high-k dielectric layers 321'. The strain-applying layer 323' can apply strain to the two adjacent high-k dielectric layers 321' to compensate for the reduced strain application effect caused by the increase in the overall thickness of the high-k dielectric layer structure 320. Therefore, it can overcome the problem that occurs when the rock salt crystal structure of the high-k dielectric layer 321' becomes unstable. The strain-applying layer 323' may include MgO, Be... x Mg 1-x O (0 < x < 0.5) or combinations thereof. Therefore, by providing a strain-applying layer 323' between two adjacent high-k dielectric layers 321', each high-k dielectric layer 321' can maintain the rock salt crystal structure as a stable phase under ambient conditions (i.e., at room temperature and atmospheric pressure). Thus, the high-k dielectric layer 321' can exhibit a high dielectric constant. Simultaneously, the overall thickness of the high-k dielectric layer structure 320 can be increased, thereby allowing the high-k dielectric layer structure 320 to exhibit sufficient characteristics of a high-k dielectric layer structure 320.

[0077] Furthermore, according to another embodiment of this disclosure, the high-k dielectric layer may further include an additional high-k dielectric layer comprising a common high-k material. This will be referred to... Figures 7 to 14 Provide a detailed description.

[0078] Figures 7 to 14 Semiconductor devices according to other embodiments of this disclosure are shown.

[0079] In addition to the additional high-k dielectric layer 430, Figures 7 to 14 The constituent elements of the semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 shown can be the same as those of the semiconductor devices 100, 200, 201, 202, 300, and 302, respectively. Figures 1 to 6 The constituent elements of the semiconductor devices 100, 200, 201, 202, 300, and 302 are described below. In the following description of the constituent elements other than the additional high-k dielectric layer 430, reference will be made to the descriptions of the semiconductor devices 100, 200, 201, 202, 300, and 302. Figures 1 to 6 The semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 can be part of a memory. The semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 can be part of a volatile memory. The semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 can be part of a DRAM. The semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 can include a DRAM capacitor.

[0080] Referring to Figures 7 to 14 , the semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 can further include the additional high-k dielectric layer 430.

[0081] The additional high-k dielectric layer 430 can be disposed between the high-k dielectric layer 120 and the second electrode 102 (see Figure 7 and Figure 9 ), or between the high-k dielectric layer 220 and the second electrode 102 (see Figure 8 and Figure 10 ), or between the high-k dielectric layer structure 320 and the second electrode 102 (see Figure 11 and Figure 12 ), or between the high-k dielectric layer structure 320' and the second electrode 102 (see Figure 13 and Figure 14 ).

[0082] The additional high-k dielectric layer 430 can include a common high-k material. The additional high-k dielectric layer 430 can include a high-k material having a high dielectric constant higher than that of silicon oxide (SiO2). For example, the additional high-k dielectric layer 430 can have a dielectric constant of about 4 to about 40.

[0083] The additional high-k dielectric layer 430 may include a material different from high-k dielectric layers 120 and 321', different from the first high-k dielectric layers 221 and 321, and different from the second high-k dielectric layers 222 and 322. The material included in the additional high-k dielectric layer 430 may have a dielectric constant lower than that of the high-k dielectric layers 120 and 321', lower than that of the first high-k dielectric layers 221 and 321, and lower than that of the second high-k dielectric layers 222 and 322.

[0084] In an exemplary embodiment, the additional high-k dielectric layer 430 may include zirconium oxide (ZrO2), hafnium oxide (HfO2), or hafnium zirconium oxide (HfO2). x Zr 1-x O2), aluminum oxide (Al2O3), or combinations thereof, wherein 0.3 < x < 1.0. The additional high-k dielectric layer 430 may comprise a single-layer or multi-layer structure.

[0085] For example, the additional high-k dielectric layer 430 can have a monolayer structure comprising zirconium oxide (ZrO2), hafnium oxide (HfO2), and hafnium zirconium oxide (HfO2). x Zr 1-x O2), aluminum oxide (Al2O3), or a combination thereof.

[0086] Alternatively, for example, the additional high-k dielectric layer 430 may comprise a multilayer structure comprising zirconium oxide (ZrO2), hafnium oxide (HfO2), and hafnium zirconium oxide (HfO2). x Zr 1-x O2), aluminum oxide (Al2O3), or a combination thereof.

[0087] Furthermore, according to other embodiments, the semiconductor device may also include an interface layer. This will be referenced. Figures 15 to 22 Provide a detailed description.

[0088] Figures 15 to 22 Semiconductor devices according to other embodiments of this disclosure are shown.

[0089] In addition to interface layer 440 Figures 15 to 22 The constituent elements of the semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 shown can be used with... Figures 7 to 14 The semiconductor devices 400, 401, 402, 403, 404, 405, 406, and 407 shown are identical in their constituent elements. In the following description of the constituent elements of semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415, excluding interface layer 440, will refer to... Figures 7 to 14 and its description and Figures 1 to 6and described. The semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 can be part of a memory. The semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 can be part of a volatile memory. The semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 can be part of a DRAM. The semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 can include a DRAM capacitor.

[0090] Referring to Figures 15 to 22 , the semiconductor devices 408, 409, 410, 411, 412, 413, 414, and 415 can also include an interface layer 440.

[0091] The interface layer 440 can be disposed between the second electrode 102 and the multi-layer stack.

[0092] The interface layer 440 can be used to suppress leakage current of a high-k dielectric layer, such as the high-k dielectric layer 430 or 120. The interface layer 440 can be used to protect the high-k dielectric layer when the second electrode 102 is formed. The interface layer 440 can include a material that is more easily reduced than the high-k dielectric layer when the second electrode 102 is formed. The interface layer 440 can be used to prevent reduction of the high-k dielectric layer. The interface layer 440 can be used as a leakage current barrier layer having a large activation work function (eWF) and a large conduction band offset (CBO). In addition, the interface layer 440 can not increase the equivalent oxide thickness T ox of the high-k dielectric layer. The interface layer 440 can be used as part of the second electrode 102.

[0093] The interface layer 440 can be a material having a relatively large electronegativity. For example, the interface layer 440 can have a larger Pauling electronegativity than the high-k dielectric layer. The interface layer 440 can include a material having a larger Pauling electronegativity (hereinafter, it is simply referred to as "electronegativity") than the high-k dielectric layers 120 and 321', the first high-k dielectric layers 221 and 321, the second high-k dielectric layers 222 and 322, and the additional high-k dielectric layer 430. When the electronegativity is large, it is hardly oxidized and is easily reduced. Thus, the interface layer 440 can lose oxygen instead of the high-k dielectric layer, and thus the interface layer 440 can prevent oxygen loss of the high-k dielectric layer.

[0094] The interface layer 440 can include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide, or a combination thereof.

[0095] Figures 23A to 23Cis a view showing the storage unit. Figure 23B is a cross-sectional view taken along Figure 23A line A-A' in Figure 23C is a cross-sectional view taken along Figure 23A line B-B' in

[0096] The storage unit 500 can include a cell transistor including a buried word line 508, a bit line 514, and a capacitor 600. The capacitor 600 can include a multi-layer stack, and the multi-layer stack can include one of the multi-layer stacks of the above-described embodiments of the present disclosure.

[0097] The storage unit 500 will be described in detail.

[0098] An isolation layer 503 and an active region 504 can be formed on a substrate 501. The plurality of active regions 504 can be defined by the isolation layer 503. The substrate 501 can be a material suitable for semiconductor processing. The substrate 501 can include a semiconductor substrate. The substrate 501 can be formed of a silicon-containing material. The substrate 501 can include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon-germanium, single-crystal silicon-germanium, polysilicon-germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The substrate 501 can also include other semiconductor materials such as germanium. The substrate 501 can include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 501 can include a silicon-on-insulator (SOI) substrate. The isolation layer 503 can be formed in the isolation trench 502 by a shallow trench isolation (STI) process.

[0099] A word line trench 506 can be formed in the substrate 501. The word line trench 506 can be referred to as a gate trench. A gate dielectric layer 507 can be formed on a surface of the word line trench 506. A buried word line 508 can be formed over the gate dielectric layer 507 to partially fill the word line trench 506. The buried word line 508 can be referred to as a buried gate electrode. A word line cap layer 509 can be formed over the buried word line 508. A top surface of the buried word line 508 can be located at a level lower than a surface of the substrate 501. The buried word line 508 can be a low-resistance metal material. The buried word line 508 can be a stack in which titanium nitride and tungsten are sequentially stacked. According to another embodiment of the present disclosure, the buried word line 508 can be formed of only titanium nitride (TiN).

[0100] The first impurity region 510 and the second impurity region 511 can be formed in the substrate 501. The first impurity region 510 and the second impurity region 511 can be spaced apart from each other by the word line trench 506. The first impurity region 510 and the second impurity region 511 can be referred to as a first source / drain region and a second source / drain region. The first impurity region 510 and the second impurity region 511 can include an N-type impurity such as arsenic (As) or phosphorus (P). Accordingly, the buried word line 508 and the first impurity region 510 and the second impurity region 511 can become a unit transistor. The unit transistor can improve a short channel effect by the buried word line 508.

[0101] The bit line contact plug 513 can be formed over the substrate 501. The bit line contact plug 513 can be coupled to the first impurity region 510. The bit line contact plug 513 can be located in the bit line contact hole 512. The bit line contact hole 512 can be formed in the hard mask layer 505. The hard mask layer 505 can be formed over the substrate 501. The bit line contact hole 512 can expose the first impurity region 510. A bottom surface of the bit line contact plug 513 can be lower than a top surface of the substrate 501. The bit line contact plug 513 can be formed of a polysilicon or a metal material. A portion of the bit line contact plug 513 can have a line width shorter than a diameter of the bit line contact hole 512. The bit line 514 can be formed over the bit line contact plug 513. The bit line hard mask 515 can be formed over the bit line 514. A stack structure of the bit line 514 and the bit line hard mask 515 can be referred to as a bit line structure BL. The bit line 514 can have a line shape extending in a direction crossing the buried word line 508. A portion of the bit line 514 can be coupled to the bit line contact plug 513. The bit line 514 can include a metal material. The bit line hard mask 515 can include a dielectric material.

[0102] The bit line spacer 516 can be formed on sidewalls of the bit line structure BL. A bottom of the bit line spacer 516 can extend to form on both sides of the bit line contact plug 513. The bit line spacer 516 can include silicon oxide, silicon nitride, or a combination thereof. According to another embodiment of the disclosure, the bit line spacer 516 can include an air gap. For example, it can be an NAN (nitride-air gap-nitride) structure in which an air gap is located between silicon nitride.

[0103] A storage node contact plug SNC can be formed between adjacent bit line structures BL. The storage node contact plug SNC can be formed in a storage node contact hole 518. The storage node contact plug SNC can be coupled to the second impurity region 511. The storage node contact plug SNC can include a lower plug 519 and an upper plug 521. The storage node contact plug SNC can also include an ohmic contact layer 520 between the lower plug 519 and the upper plug 521. The ohmic contact layer 520 can include a metal silicide. The upper plug 521 can include a metal material, and the lower plug 519 can include a silicon-containing material.

[0104] From a perspective of a direction parallel to the bit line structures BL, a plug isolation layer 517 can be formed between adjacent storage node contact plugs SNC. The plug isolation layer 517 can be formed between adjacent bit line structures BL and can provide the storage node contact hole 518 together with the hard mask layer 505.

[0105] The capacitor 600 can be coupled to the storage node contact plug SNC.

[0106] Figure 24 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the disclosure.

[0107] Reference Figure 24 The semiconductor device 700 can include a transistor. The semiconductor device 700 can include a semiconductor substrate 701, a gate dielectric layer 710, a gate electrode 720, a source region 740, and a drain region 750. The gate dielectric layer 710 can be formed over the semiconductor substrate 701, and the gate electrode 720 can be formed over the gate dielectric layer 710. The source region 740 and the drain region 750 can be formed in the semiconductor substrate 701.

[0108] The gate dielectric layer 710 can include one of the multi-layer stacks according to the above-described embodiments of the disclosure. In this embodiment, the gate dielectric layer 710 can be a multi-layer stack including a seed layer and a high-k dielectric layer. The seed layer and the high-k dielectric layer can have a rock-salt crystal structure, and the high-k dielectric layer can have a dielectric constant of 50 or more. Alternatively, for example, the gate dielectric layer 710 can be a multi-layer stack including a seed layer and a high-k dielectric layer structure. The high-k dielectric layer structure can include at least two high-k dielectric layers and at least one strain-imposing layer, and the strain-imposing layer can be disposed between adjacent high-k dielectric layers.

[0109] The gate electrode 720 can be a metal gate electrode including a metal-based material. The gate electrode 720 can include tungsten, aluminum, tungsten nitride, titanium nitride, titanium, or a combination thereof.

[0110] The source region 740 and the drain region 750 can include impurities of the same conductivity type. The source region 740 and the drain region 750 can include N-type impurities or P-type impurities. The N-type impurities can include phosphorus or arsenic, and the P-type impurities can include boron or indium.

[0111] According to another embodiment of the disclosure, a thin interface layer can also be formed between the gate dielectric layer 710 and the semiconductor substrate 701. Here, the thin interface layer can include silicon oxide or silicon oxynitride.

[0112] According to another embodiment of the disclosure, the gate dielectric layer 710 can be applied to a gate dielectric layer of a FinFET.

[0113] The multilayer stack according to the above-described embodiments of the disclosure can be applied to a metal-insulator-metal (MIM) capacitor. For example, the MIM capacitor can include a first metal electrode, a second metal electrode, and a multilayer stack formed between the first metal electrode and the second metal electrode. The multilayer stack of the MIM capacitor can include one of the multilayer stacks according to the above-described embodiments of the disclosure. For example, the multilayer stack can include a seed layer and a high-k dielectric layer. The seed layer and the high-k dielectric layer can have a rock-salt crystal structure, and the high-k dielectric layer can have a dielectric constant of 50 or more. Alternatively, for example, the multilayer stack can include a seed layer and a high-k dielectric layer structure. The high-k dielectric layer structure can include at least two high-k dielectric layers and at least one strain-imposing layer, and the strain-imposing layer can be disposed between adjacent high-k dielectric layers.

[0114] The multilayer stack according to the above-described embodiments of the disclosure can be applied to an embedded DRAM. For example, the embedded DRAM can include a logic circuit and an embedded DRAM, and a capacitor of the embedded DRAM can include a lower electrode, a multilayer stack, and an upper electrode. The multilayer stack of the capacitor of the embedded DRAM can include one of the multilayer stacks according to the above-described embodiments of the disclosure. For example, the multilayer stack can include a seed layer and a high-k dielectric layer. The seed layer and the high-k dielectric layer can have a rock-salt crystal structure, and the high-k dielectric layer can have a dielectric constant of 50 or more. Alternatively, for example, the multilayer stack can include a seed layer and a high-k dielectric layer structure. The high-k dielectric layer structure can include at least two high-k dielectric layers and at least one strain-imposing layer, and the strain-imposing layer can be disposed between adjacent high-k dielectric layers.

[0115] The multi-layer stack according to the above-described embodiments of the present disclosure can be applied to 3D NAND (three-dimensional NAND). For example, the 3D NAND can include a multi-layer stack including a columnar channel layer, a word line surrounding the columnar channel layer, and a tunneling dielectric layer between the columnar channel layer and the word line. At least the tunneling dielectric layer of the multi-layer stack of the 3D NAND can include a seed layer and a high-k dielectric layer. The seed layer and the high-k dielectric layer can have a rock-salt crystal structure, and the high-k dielectric layer can have a dielectric constant of 50 or more. Alternatively, for example, at least the tunneling dielectric layer of the multi-layer stack of the 3D NAND can include a seed layer and a high-k dielectric layer structure. The high-k dielectric layer structure can include at least two high-k dielectric layers and at least one strain-imparting layer, and the strain-imparting layer can be disposed between adjacent high-k dielectric layers.

[0116] While the application has been described with respect to the particular embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the application defined in the following claims.

Claims

1. A semiconductor device comprising: a first electrode; a second electrode; and a multilayer stack interposed between the first electrode and the second electrode and including a seed layer and a high-k dielectric layer, wherein the seed layer and the high-k dielectric layer each have a rock-salt crystal structure, and wherein the high-k dielectric layer exhibits a dielectric constant k of 50 or more, wherein the multilayer stack further includes an additional high-k dielectric layer disposed on the high-k dielectric layer, and wherein the additional high-k dielectric layer exhibits a lower dielectric constant k than the high-k dielectric layer. the seed layer includes a first seed layer and a second seed layer, wherein the first seed layer includes magnesium oxide MgO having a rock-salt crystal structure, and the second seed layer is disposed on the first seed layer and includes beryllium oxide BeO having a rock-salt crystal structure.

2. The semiconductor device of claim 1, wherein, the seed layer exhibits a dielectric constant k of 15 to 20.

3. The semiconductor device of claim 1, wherein, The seed layer comprises a beryllium-magnesium oxide Be x Mg 1-x O, wherein 0 < x < 0.

5.

4. The semiconductor device of claim 1, wherein, the high-k dielectric layer includes BeO having a rock-salt crystal structure that is stable at room temperature and atmospheric pressure.

5. The semiconductor device of claim 1, wherein, the high-k dielectric layer includes a single-layer structure or a multilayer structure including two or more layers, 6. The semiconductor device of claim 1, wherein, wherein, when the high-k dielectric layer includes a multilayer structure, each layer included in the multilayer structure includes BeO having a rock-salt crystal structure, and wherein a thickness of the high-k dielectric layer including the multilayer structure is greater than a thickness of the high-k dielectric layer including the single-layer structure. 7.The semiconductor device of claim 1, further comprising an interface layer disposed between the second electrode and the multilayer stack. 8.A semiconductor device comprising: a first electrode; a second electrode; and a multilayer stack interposed between the first electrode and the second electrode and including a seed layer and a high-k dielectric layer structure, wherein the high-k dielectric layer structure includes at least two high-k dielectric layers and at least one strain-imposing layer, wherein the multilayer stack further includes an additional high-k dielectric layer disposed on the high-k dielectric layer among the at least two high-k dielectric layers adjacent to the second electrode, wherein the additional high-k dielectric layer exhibits a lower dielectric constant k than the at least two high-k dielectric layers, and wherein the strain-imposing layer is interposed between adjacent high-k dielectric layers. the strain-imposing layer is configured to stabilize a rock-salt crystal structure of the at least two high-k dielectric layers by imposing a strain to the at least two high-k dielectric layers. the seed layer includes a first seed layer and a second seed layer, wherein the first seed layer includes magnesium oxide MgO having a rock-salt crystal structure, and the second seed layer is disposed on the first seed layer and includes beryllium oxide BeO having a rock-salt crystal structure.

9. The semiconductor device of claim 8, wherein, the seed layer exhibits a dielectric constant k of 15 to 20.

10. The semiconductor device of claim 8, wherein, The strain-imposing layer includes magnesium oxide MgO, beryllium-magnesium oxide Be x Mg 1-x O or a combination thereof, where 0 < x < 0.

5.

11. The semiconductor device of claim 8, wherein, each of the at least two high-k dielectric layers includes beryllium oxide BeO having a rock-salt crystal structure that is stable at room temperature and atmospheric pressure.

12. The semiconductor device of claim 8, wherein, The seed layer comprises a beryllium-magnesium oxide Be x Mg 1-x O, wherein 0 < x < 0.

5.

13. The semiconductor device of claim 8, wherein, each of the at least two high-k dielectric layers exhibits a dielectric constant k of 50 or more.

14. The semiconductor device of claim 8, wherein, ​ 15. The semiconductor device of claim 8, wherein, ​ 16. The semiconductor device of claim 8, further comprising an interface layer disposed between the second electrode and the multilayer stack.

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